if_ixl.c revision 292100
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixl/if_ixl.c 292100 2015-12-11 13:08:38Z smh $*/ 34 35#ifndef IXL_STANDALONE_BUILD 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#endif 39 40#include "ixl.h" 41#include "ixl_pf.h" 42 43#ifdef RSS 44#include <net/rss_config.h> 45#endif 46 47/********************************************************************* 48 * Driver version 49 *********************************************************************/ 50char ixl_driver_version[] = "1.4.3"; 51 52/********************************************************************* 53 * PCI Device ID Table 54 * 55 * Used by probe to select devices to load on 56 * Last field stores an index into ixl_strings 57 * Last entry must be all 0s 58 * 59 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 60 *********************************************************************/ 61 62static ixl_vendor_info_t ixl_vendor_info_array[] = 63{ 64 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0}, 65 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0}, 66 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0}, 67 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0}, 68 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0}, 69 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0}, 70 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0}, 71 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0}, 72 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4, 0, 0, 0}, 73 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2, 0, 0, 0}, 74 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A, 0, 0, 0}, 75#ifdef X722_SUPPORT 76 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722, 0, 0, 0}, 77 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722, 0, 0, 0}, 78 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722, 0, 0, 0}, 79#endif 80 /* required last entry */ 81 {0, 0, 0, 0, 0} 82}; 83 84/********************************************************************* 85 * Table of branding strings 86 *********************************************************************/ 87 88static char *ixl_strings[] = { 89 "Intel(R) Ethernet Connection XL710 Driver" 90}; 91 92 93/********************************************************************* 94 * Function prototypes 95 *********************************************************************/ 96static int ixl_probe(device_t); 97static int ixl_attach(device_t); 98static int ixl_detach(device_t); 99static int ixl_shutdown(device_t); 100static int ixl_get_hw_capabilities(struct ixl_pf *); 101static void ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int); 102static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 103static void ixl_init(void *); 104static void ixl_init_locked(struct ixl_pf *); 105static void ixl_stop(struct ixl_pf *); 106static void ixl_media_status(struct ifnet *, struct ifmediareq *); 107static int ixl_media_change(struct ifnet *); 108static void ixl_update_link_status(struct ixl_pf *); 109static int ixl_allocate_pci_resources(struct ixl_pf *); 110static u16 ixl_get_bus_info(struct i40e_hw *, device_t); 111static int ixl_setup_stations(struct ixl_pf *); 112static int ixl_switch_config(struct ixl_pf *); 113static int ixl_initialize_vsi(struct ixl_vsi *); 114static int ixl_assign_vsi_msix(struct ixl_pf *); 115static int ixl_assign_vsi_legacy(struct ixl_pf *); 116static int ixl_init_msix(struct ixl_pf *); 117static void ixl_configure_msix(struct ixl_pf *); 118static void ixl_configure_itr(struct ixl_pf *); 119static void ixl_configure_legacy(struct ixl_pf *); 120static void ixl_free_pci_resources(struct ixl_pf *); 121static void ixl_local_timer(void *); 122static int ixl_setup_interface(device_t, struct ixl_vsi *); 123static void ixl_link_event(struct ixl_pf *, struct i40e_arq_event_info *); 124static void ixl_config_rss(struct ixl_vsi *); 125static void ixl_set_queue_rx_itr(struct ixl_queue *); 126static void ixl_set_queue_tx_itr(struct ixl_queue *); 127static int ixl_set_advertised_speeds(struct ixl_pf *, int); 128 129static int ixl_enable_rings(struct ixl_vsi *); 130static int ixl_disable_rings(struct ixl_vsi *); 131static void ixl_enable_intr(struct ixl_vsi *); 132static void ixl_disable_intr(struct ixl_vsi *); 133static void ixl_disable_rings_intr(struct ixl_vsi *); 134 135static void ixl_enable_adminq(struct i40e_hw *); 136static void ixl_disable_adminq(struct i40e_hw *); 137static void ixl_enable_queue(struct i40e_hw *, int); 138static void ixl_disable_queue(struct i40e_hw *, int); 139static void ixl_enable_legacy(struct i40e_hw *); 140static void ixl_disable_legacy(struct i40e_hw *); 141 142static void ixl_set_promisc(struct ixl_vsi *); 143static void ixl_add_multi(struct ixl_vsi *); 144static void ixl_del_multi(struct ixl_vsi *); 145static void ixl_register_vlan(void *, struct ifnet *, u16); 146static void ixl_unregister_vlan(void *, struct ifnet *, u16); 147static void ixl_setup_vlan_filters(struct ixl_vsi *); 148 149static void ixl_init_filters(struct ixl_vsi *); 150static void ixl_reconfigure_filters(struct ixl_vsi *vsi); 151static void ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan); 152static void ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan); 153static void ixl_add_hw_filters(struct ixl_vsi *, int, int); 154static void ixl_del_hw_filters(struct ixl_vsi *, int); 155static struct ixl_mac_filter * 156 ixl_find_filter(struct ixl_vsi *, u8 *, s16); 157static void ixl_add_mc_filter(struct ixl_vsi *, u8 *); 158static void ixl_free_mac_filters(struct ixl_vsi *vsi); 159 160 161/* Sysctl debug interface */ 162static int ixl_debug_info(SYSCTL_HANDLER_ARGS); 163static void ixl_print_debug_info(struct ixl_pf *); 164 165/* The MSI/X Interrupt handlers */ 166static void ixl_intr(void *); 167static void ixl_msix_que(void *); 168static void ixl_msix_adminq(void *); 169static void ixl_handle_mdd_event(struct ixl_pf *); 170 171/* Deferred interrupt tasklets */ 172static void ixl_do_adminq(void *, int); 173 174/* Sysctl handlers */ 175static int ixl_set_flowcntl(SYSCTL_HANDLER_ARGS); 176static int ixl_set_advertise(SYSCTL_HANDLER_ARGS); 177static int ixl_current_speed(SYSCTL_HANDLER_ARGS); 178static int ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS); 179 180/* Statistics */ 181static void ixl_add_hw_stats(struct ixl_pf *); 182static void ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *, 183 struct sysctl_oid_list *, struct i40e_hw_port_stats *); 184static void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *, 185 struct sysctl_oid_list *, 186 struct i40e_eth_stats *); 187static void ixl_update_stats_counters(struct ixl_pf *); 188static void ixl_update_eth_stats(struct ixl_vsi *); 189static void ixl_update_vsi_stats(struct ixl_vsi *); 190static void ixl_pf_reset_stats(struct ixl_pf *); 191static void ixl_vsi_reset_stats(struct ixl_vsi *); 192static void ixl_stat_update48(struct i40e_hw *, u32, u32, bool, 193 u64 *, u64 *); 194static void ixl_stat_update32(struct i40e_hw *, u32, bool, 195 u64 *, u64 *); 196 197#ifdef IXL_DEBUG_SYSCTL 198static int ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS); 199static int ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS); 200static int ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS); 201static int ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS); 202static int ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS); 203#endif 204 205#ifdef PCI_IOV 206static int ixl_adminq_err_to_errno(enum i40e_admin_queue_err err); 207 208static int ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t*); 209static void ixl_uninit_iov(device_t dev); 210static int ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t*); 211 212static void ixl_handle_vf_msg(struct ixl_pf *, 213 struct i40e_arq_event_info *); 214static void ixl_handle_vflr(void *arg, int pending); 215 216static void ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf); 217static void ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf); 218#endif 219 220/********************************************************************* 221 * FreeBSD Device Interface Entry Points 222 *********************************************************************/ 223 224static device_method_t ixl_methods[] = { 225 /* Device interface */ 226 DEVMETHOD(device_probe, ixl_probe), 227 DEVMETHOD(device_attach, ixl_attach), 228 DEVMETHOD(device_detach, ixl_detach), 229 DEVMETHOD(device_shutdown, ixl_shutdown), 230#ifdef PCI_IOV 231 DEVMETHOD(pci_init_iov, ixl_init_iov), 232 DEVMETHOD(pci_uninit_iov, ixl_uninit_iov), 233 DEVMETHOD(pci_add_vf, ixl_add_vf), 234#endif 235 {0, 0} 236}; 237 238static driver_t ixl_driver = { 239 "ixl", ixl_methods, sizeof(struct ixl_pf), 240}; 241 242devclass_t ixl_devclass; 243DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0); 244 245MODULE_DEPEND(ixl, pci, 1, 1, 1); 246MODULE_DEPEND(ixl, ether, 1, 1, 1); 247#ifdef DEV_NETMAP 248MODULE_DEPEND(ixl, netmap, 1, 1, 1); 249#endif /* DEV_NETMAP */ 250 251/* 252** Global reset mutex 253*/ 254static struct mtx ixl_reset_mtx; 255 256/* 257** TUNEABLE PARAMETERS: 258*/ 259 260static SYSCTL_NODE(_hw, OID_AUTO, ixl, CTLFLAG_RD, 0, 261 "IXL driver parameters"); 262 263/* 264 * MSIX should be the default for best performance, 265 * but this allows it to be forced off for testing. 266 */ 267static int ixl_enable_msix = 1; 268TUNABLE_INT("hw.ixl.enable_msix", &ixl_enable_msix); 269SYSCTL_INT(_hw_ixl, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixl_enable_msix, 0, 270 "Enable MSI-X interrupts"); 271 272/* 273** Number of descriptors per ring: 274** - TX and RX are the same size 275*/ 276static int ixl_ringsz = DEFAULT_RING; 277TUNABLE_INT("hw.ixl.ringsz", &ixl_ringsz); 278SYSCTL_INT(_hw_ixl, OID_AUTO, ring_size, CTLFLAG_RDTUN, 279 &ixl_ringsz, 0, "Descriptor Ring Size"); 280 281/* 282** This can be set manually, if left as 0 the 283** number of queues will be calculated based 284** on cpus and msix vectors available. 285*/ 286int ixl_max_queues = 0; 287TUNABLE_INT("hw.ixl.max_queues", &ixl_max_queues); 288SYSCTL_INT(_hw_ixl, OID_AUTO, max_queues, CTLFLAG_RDTUN, 289 &ixl_max_queues, 0, "Number of Queues"); 290 291/* 292** Controls for Interrupt Throttling 293** - true/false for dynamic adjustment 294** - default values for static ITR 295*/ 296int ixl_dynamic_rx_itr = 0; 297TUNABLE_INT("hw.ixl.dynamic_rx_itr", &ixl_dynamic_rx_itr); 298SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN, 299 &ixl_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate"); 300 301int ixl_dynamic_tx_itr = 0; 302TUNABLE_INT("hw.ixl.dynamic_tx_itr", &ixl_dynamic_tx_itr); 303SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN, 304 &ixl_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate"); 305 306int ixl_rx_itr = IXL_ITR_8K; 307TUNABLE_INT("hw.ixl.rx_itr", &ixl_rx_itr); 308SYSCTL_INT(_hw_ixl, OID_AUTO, rx_itr, CTLFLAG_RDTUN, 309 &ixl_rx_itr, 0, "RX Interrupt Rate"); 310 311int ixl_tx_itr = IXL_ITR_4K; 312TUNABLE_INT("hw.ixl.tx_itr", &ixl_tx_itr); 313SYSCTL_INT(_hw_ixl, OID_AUTO, tx_itr, CTLFLAG_RDTUN, 314 &ixl_tx_itr, 0, "TX Interrupt Rate"); 315 316#ifdef IXL_FDIR 317static int ixl_enable_fdir = 1; 318TUNABLE_INT("hw.ixl.enable_fdir", &ixl_enable_fdir); 319/* Rate at which we sample */ 320int ixl_atr_rate = 20; 321TUNABLE_INT("hw.ixl.atr_rate", &ixl_atr_rate); 322#endif 323 324#ifdef DEV_NETMAP 325#define NETMAP_IXL_MAIN /* only bring in one part of the netmap code */ 326#include <dev/netmap/if_ixl_netmap.h> 327#endif /* DEV_NETMAP */ 328 329static char *ixl_fc_string[6] = { 330 "None", 331 "Rx", 332 "Tx", 333 "Full", 334 "Priority", 335 "Default" 336}; 337 338static MALLOC_DEFINE(M_IXL, "ixl", "ixl driver allocations"); 339 340static uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] = 341 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 342 343/********************************************************************* 344 * Device identification routine 345 * 346 * ixl_probe determines if the driver should be loaded on 347 * the hardware based on PCI vendor/device id of the device. 348 * 349 * return BUS_PROBE_DEFAULT on success, positive on failure 350 *********************************************************************/ 351 352static int 353ixl_probe(device_t dev) 354{ 355 ixl_vendor_info_t *ent; 356 357 u16 pci_vendor_id, pci_device_id; 358 u16 pci_subvendor_id, pci_subdevice_id; 359 char device_name[256]; 360 static bool lock_init = FALSE; 361 362 INIT_DEBUGOUT("ixl_probe: begin"); 363 364 pci_vendor_id = pci_get_vendor(dev); 365 if (pci_vendor_id != I40E_INTEL_VENDOR_ID) 366 return (ENXIO); 367 368 pci_device_id = pci_get_device(dev); 369 pci_subvendor_id = pci_get_subvendor(dev); 370 pci_subdevice_id = pci_get_subdevice(dev); 371 372 ent = ixl_vendor_info_array; 373 while (ent->vendor_id != 0) { 374 if ((pci_vendor_id == ent->vendor_id) && 375 (pci_device_id == ent->device_id) && 376 377 ((pci_subvendor_id == ent->subvendor_id) || 378 (ent->subvendor_id == 0)) && 379 380 ((pci_subdevice_id == ent->subdevice_id) || 381 (ent->subdevice_id == 0))) { 382 sprintf(device_name, "%s, Version - %s", 383 ixl_strings[ent->index], 384 ixl_driver_version); 385 device_set_desc_copy(dev, device_name); 386 /* One shot mutex init */ 387 if (lock_init == FALSE) { 388 lock_init = TRUE; 389 mtx_init(&ixl_reset_mtx, 390 "ixl_reset", 391 "IXL RESET Lock", MTX_DEF); 392 } 393 return (BUS_PROBE_DEFAULT); 394 } 395 ent++; 396 } 397 return (ENXIO); 398} 399 400/********************************************************************* 401 * Device initialization routine 402 * 403 * The attach entry point is called when the driver is being loaded. 404 * This routine identifies the type of hardware, allocates all resources 405 * and initializes the hardware. 406 * 407 * return 0 on success, positive on failure 408 *********************************************************************/ 409 410static int 411ixl_attach(device_t dev) 412{ 413 struct ixl_pf *pf; 414 struct i40e_hw *hw; 415 struct ixl_vsi *vsi; 416 u16 bus; 417 int error = 0; 418#ifdef PCI_IOV 419 nvlist_t *pf_schema, *vf_schema; 420 int iov_error; 421#endif 422 423 INIT_DEBUGOUT("ixl_attach: begin"); 424 425 /* Allocate, clear, and link in our primary soft structure */ 426 pf = device_get_softc(dev); 427 pf->dev = pf->osdep.dev = dev; 428 hw = &pf->hw; 429 430 /* 431 ** Note this assumes we have a single embedded VSI, 432 ** this could be enhanced later to allocate multiple 433 */ 434 vsi = &pf->vsi; 435 vsi->dev = pf->dev; 436 437 /* Core Lock Init*/ 438 IXL_PF_LOCK_INIT(pf, device_get_nameunit(dev)); 439 440 /* Set up the timer callout */ 441 callout_init_mtx(&pf->timer, &pf->pf_mtx, 0); 442 443 /* Set up sysctls */ 444 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 445 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 446 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW, 447 pf, 0, ixl_set_flowcntl, "I", "Flow Control"); 448 449 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 450 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 451 OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW, 452 pf, 0, ixl_set_advertise, "I", "Advertised Speed"); 453 454 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 455 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 456 OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD, 457 pf, 0, ixl_current_speed, "A", "Current Port Speed"); 458 459 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 460 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 461 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 462 pf, 0, ixl_sysctl_show_fw, "A", "Firmware version"); 463 464 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 465 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 466 OID_AUTO, "rx_itr", CTLFLAG_RW, 467 &ixl_rx_itr, IXL_ITR_8K, "RX ITR"); 468 469 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 470 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 471 OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW, 472 &ixl_dynamic_rx_itr, 0, "Dynamic RX ITR"); 473 474 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 476 OID_AUTO, "tx_itr", CTLFLAG_RW, 477 &ixl_tx_itr, IXL_ITR_4K, "TX ITR"); 478 479 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 480 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 481 OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW, 482 &ixl_dynamic_tx_itr, 0, "Dynamic TX ITR"); 483 484#ifdef IXL_DEBUG_SYSCTL 485 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 486 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 487 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0, 488 ixl_debug_info, "I", "Debug Information"); 489 490 /* Debug shared-code message level */ 491 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 492 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 493 OID_AUTO, "debug_mask", CTLFLAG_RW, 494 &pf->hw.debug_mask, 0, "Debug Message Level"); 495 496 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 497 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 498 OID_AUTO, "vc_debug_level", CTLFLAG_RW, &pf->vc_debug_lvl, 499 0, "PF/VF Virtual Channel debug level"); 500 501 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 502 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 503 OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD, 504 pf, 0, ixl_sysctl_link_status, "A", "Current Link Status"); 505 506 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 507 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 508 OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD, 509 pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities"); 510 511 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 513 OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD, 514 pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List"); 515 516 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 517 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 518 OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD, 519 pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation"); 520 521 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 522 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 523 OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD, 524 pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration"); 525#endif 526 527 /* Save off the PCI information */ 528 hw->vendor_id = pci_get_vendor(dev); 529 hw->device_id = pci_get_device(dev); 530 hw->revision_id = pci_read_config(dev, PCIR_REVID, 1); 531 hw->subsystem_vendor_id = 532 pci_read_config(dev, PCIR_SUBVEND_0, 2); 533 hw->subsystem_device_id = 534 pci_read_config(dev, PCIR_SUBDEV_0, 2); 535 536 hw->bus.device = pci_get_slot(dev); 537 hw->bus.func = pci_get_function(dev); 538 539 pf->vc_debug_lvl = 1; 540 541 /* Do PCI setup - map BAR0, etc */ 542 if (ixl_allocate_pci_resources(pf)) { 543 device_printf(dev, "Allocation of PCI resources failed\n"); 544 error = ENXIO; 545 goto err_out; 546 } 547 548 /* Establish a clean starting point */ 549 i40e_clear_hw(hw); 550 error = i40e_pf_reset(hw); 551 if (error) { 552 device_printf(dev,"PF reset failure %x\n", error); 553 error = EIO; 554 goto err_out; 555 } 556 557 /* Set admin queue parameters */ 558 hw->aq.num_arq_entries = IXL_AQ_LEN; 559 hw->aq.num_asq_entries = IXL_AQ_LEN; 560 hw->aq.arq_buf_size = IXL_AQ_BUFSZ; 561 hw->aq.asq_buf_size = IXL_AQ_BUFSZ; 562 563 /* Initialize the shared code */ 564 error = i40e_init_shared_code(hw); 565 if (error) { 566 device_printf(dev,"Unable to initialize the shared code\n"); 567 error = EIO; 568 goto err_out; 569 } 570 571 /* Set up the admin queue */ 572 error = i40e_init_adminq(hw); 573 if (error) { 574 device_printf(dev, "The driver for the device stopped " 575 "because the NVM image is newer than expected.\n" 576 "You must install the most recent version of " 577 " the network driver.\n"); 578 goto err_out; 579 } 580 device_printf(dev, "%s\n", ixl_fw_version_str(hw)); 581 582 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 583 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 584 device_printf(dev, "The driver for the device detected " 585 "a newer version of the NVM image than expected.\n" 586 "Please install the most recent version of the network driver.\n"); 587 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 588 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 589 device_printf(dev, "The driver for the device detected " 590 "an older version of the NVM image than expected.\n" 591 "Please update the NVM image.\n"); 592 593 /* Clear PXE mode */ 594 i40e_clear_pxe_mode(hw); 595 596 /* Get capabilities from the device */ 597 error = ixl_get_hw_capabilities(pf); 598 if (error) { 599 device_printf(dev, "HW capabilities failure!\n"); 600 goto err_get_cap; 601 } 602 603 /* Set up host memory cache */ 604 error = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 605 hw->func_caps.num_rx_qp, 0, 0); 606 if (error) { 607 device_printf(dev, "init_lan_hmc failed: %d\n", error); 608 goto err_get_cap; 609 } 610 611 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 612 if (error) { 613 device_printf(dev, "configure_lan_hmc failed: %d\n", error); 614 goto err_mac_hmc; 615 } 616 617 /* Disable LLDP from the firmware */ 618 i40e_aq_stop_lldp(hw, TRUE, NULL); 619 620 i40e_get_mac_addr(hw, hw->mac.addr); 621 error = i40e_validate_mac_addr(hw->mac.addr); 622 if (error) { 623 device_printf(dev, "validate_mac_addr failed: %d\n", error); 624 goto err_mac_hmc; 625 } 626 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN); 627 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 628 629 /* Set up VSI and queues */ 630 if (ixl_setup_stations(pf) != 0) { 631 device_printf(dev, "setup stations failed!\n"); 632 error = ENOMEM; 633 goto err_mac_hmc; 634 } 635 636 /* Initialize mac filter list for VSI */ 637 SLIST_INIT(&vsi->ftl); 638 639 /* Set up interrupt routing here */ 640 if (pf->msix > 1) 641 error = ixl_assign_vsi_msix(pf); 642 else 643 error = ixl_assign_vsi_legacy(pf); 644 if (error) 645 goto err_late; 646 647 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 648 (hw->aq.fw_maj_ver < 4)) { 649 i40e_msec_delay(75); 650 error = i40e_aq_set_link_restart_an(hw, TRUE, NULL); 651 if (error) 652 device_printf(dev, "link restart failed, aq_err=%d\n", 653 pf->hw.aq.asq_last_status); 654 } 655 656 /* Determine link state */ 657 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 658 i40e_get_link_status(hw, &pf->link_up); 659 660 /* Setup OS specific network interface */ 661 if (ixl_setup_interface(dev, vsi) != 0) { 662 device_printf(dev, "interface setup failed!\n"); 663 error = EIO; 664 goto err_late; 665 } 666 667 error = ixl_switch_config(pf); 668 if (error) { 669 device_printf(dev, "Initial switch config failed: %d\n", error); 670 goto err_mac_hmc; 671 } 672 673 /* Limit phy interrupts to link and modules failure */ 674 error = i40e_aq_set_phy_int_mask(hw, 675 I40E_AQ_EVENT_LINK_UPDOWN | I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL); 676 if (error) 677 device_printf(dev, "set phy mask failed: %d\n", error); 678 679 /* Get the bus configuration and set the shared code */ 680 bus = ixl_get_bus_info(hw, dev); 681 i40e_set_pci_config_data(hw, bus); 682 683 /* Initialize statistics */ 684 ixl_pf_reset_stats(pf); 685 ixl_update_stats_counters(pf); 686 ixl_add_hw_stats(pf); 687 688 /* Register for VLAN events */ 689 vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 690 ixl_register_vlan, vsi, EVENTHANDLER_PRI_FIRST); 691 vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 692 ixl_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST); 693 694#ifdef PCI_IOV 695 /* SR-IOV is only supported when MSI-X is in use. */ 696 if (pf->msix > 1) { 697 pf_schema = pci_iov_schema_alloc_node(); 698 vf_schema = pci_iov_schema_alloc_node(); 699 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 700 pci_iov_schema_add_bool(vf_schema, "mac-anti-spoof", 701 IOV_SCHEMA_HASDEFAULT, TRUE); 702 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 703 IOV_SCHEMA_HASDEFAULT, FALSE); 704 pci_iov_schema_add_bool(vf_schema, "allow-promisc", 705 IOV_SCHEMA_HASDEFAULT, FALSE); 706 707 iov_error = pci_iov_attach(dev, pf_schema, vf_schema); 708 if (iov_error != 0) 709 device_printf(dev, 710 "Failed to initialize SR-IOV (error=%d)\n", 711 iov_error); 712 } 713#endif 714 715#ifdef DEV_NETMAP 716 ixl_netmap_attach(vsi); 717#endif /* DEV_NETMAP */ 718 INIT_DEBUGOUT("ixl_attach: end"); 719 return (0); 720 721err_late: 722 if (vsi->ifp != NULL) 723 if_free(vsi->ifp); 724err_mac_hmc: 725 i40e_shutdown_lan_hmc(hw); 726err_get_cap: 727 i40e_shutdown_adminq(hw); 728err_out: 729 ixl_free_pci_resources(pf); 730 ixl_free_vsi(vsi); 731 IXL_PF_LOCK_DESTROY(pf); 732 return (error); 733} 734 735/********************************************************************* 736 * Device removal routine 737 * 738 * The detach entry point is called when the driver is being removed. 739 * This routine stops the adapter and deallocates all the resources 740 * that were allocated for driver operation. 741 * 742 * return 0 on success, positive on failure 743 *********************************************************************/ 744 745static int 746ixl_detach(device_t dev) 747{ 748 struct ixl_pf *pf = device_get_softc(dev); 749 struct i40e_hw *hw = &pf->hw; 750 struct ixl_vsi *vsi = &pf->vsi; 751 struct ixl_queue *que = vsi->queues; 752 i40e_status status; 753#ifdef PCI_IOV 754 int error; 755#endif 756 757 INIT_DEBUGOUT("ixl_detach: begin"); 758 759 /* Make sure VLANS are not using driver */ 760 if (vsi->ifp->if_vlantrunk != NULL) { 761 device_printf(dev,"Vlan in use, detach first\n"); 762 return (EBUSY); 763 } 764 765#ifdef PCI_IOV 766 error = pci_iov_detach(dev); 767 if (error != 0) { 768 device_printf(dev, "SR-IOV in use; detach first.\n"); 769 return (error); 770 } 771#endif 772 773 ether_ifdetach(vsi->ifp); 774 if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 775 IXL_PF_LOCK(pf); 776 ixl_stop(pf); 777 IXL_PF_UNLOCK(pf); 778 } 779 780 for (int i = 0; i < vsi->num_queues; i++, que++) { 781 if (que->tq) { 782 taskqueue_drain(que->tq, &que->task); 783 taskqueue_drain(que->tq, &que->tx_task); 784 taskqueue_free(que->tq); 785 } 786 } 787 788 /* Shutdown LAN HMC */ 789 status = i40e_shutdown_lan_hmc(hw); 790 if (status) 791 device_printf(dev, 792 "Shutdown LAN HMC failed with code %d\n", status); 793 794 /* Shutdown admin queue */ 795 status = i40e_shutdown_adminq(hw); 796 if (status) 797 device_printf(dev, 798 "Shutdown Admin queue failed with code %d\n", status); 799 800 /* Unregister VLAN events */ 801 if (vsi->vlan_attach != NULL) 802 EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach); 803 if (vsi->vlan_detach != NULL) 804 EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach); 805 806 callout_drain(&pf->timer); 807#ifdef DEV_NETMAP 808 netmap_detach(vsi->ifp); 809#endif /* DEV_NETMAP */ 810 ixl_free_pci_resources(pf); 811 bus_generic_detach(dev); 812 if_free(vsi->ifp); 813 ixl_free_vsi(vsi); 814 IXL_PF_LOCK_DESTROY(pf); 815 return (0); 816} 817 818/********************************************************************* 819 * 820 * Shutdown entry point 821 * 822 **********************************************************************/ 823 824static int 825ixl_shutdown(device_t dev) 826{ 827 struct ixl_pf *pf = device_get_softc(dev); 828 IXL_PF_LOCK(pf); 829 ixl_stop(pf); 830 IXL_PF_UNLOCK(pf); 831 return (0); 832} 833 834 835/********************************************************************* 836 * 837 * Get the hardware capabilities 838 * 839 **********************************************************************/ 840 841static int 842ixl_get_hw_capabilities(struct ixl_pf *pf) 843{ 844 struct i40e_aqc_list_capabilities_element_resp *buf; 845 struct i40e_hw *hw = &pf->hw; 846 device_t dev = pf->dev; 847 int error, len; 848 u16 needed; 849 bool again = TRUE; 850 851 len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 852retry: 853 if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *) 854 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) { 855 device_printf(dev, "Unable to allocate cap memory\n"); 856 return (ENOMEM); 857 } 858 859 /* This populates the hw struct */ 860 error = i40e_aq_discover_capabilities(hw, buf, len, 861 &needed, i40e_aqc_opc_list_func_capabilities, NULL); 862 free(buf, M_DEVBUF); 863 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) && 864 (again == TRUE)) { 865 /* retry once with a larger buffer */ 866 again = FALSE; 867 len = needed; 868 goto retry; 869 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 870 device_printf(dev, "capability discovery failed: %d\n", 871 pf->hw.aq.asq_last_status); 872 return (ENODEV); 873 } 874 875 /* Capture this PF's starting queue pair */ 876 pf->qbase = hw->func_caps.base_queue; 877 878#ifdef IXL_DEBUG 879 device_printf(dev,"pf_id=%d, num_vfs=%d, msix_pf=%d, " 880 "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n", 881 hw->pf_id, hw->func_caps.num_vfs, 882 hw->func_caps.num_msix_vectors, 883 hw->func_caps.num_msix_vectors_vf, 884 hw->func_caps.fd_filters_guaranteed, 885 hw->func_caps.fd_filters_best_effort, 886 hw->func_caps.num_tx_qp, 887 hw->func_caps.num_rx_qp, 888 hw->func_caps.base_queue); 889#endif 890 return (error); 891} 892 893static void 894ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask) 895{ 896 device_t dev = vsi->dev; 897 898 /* Enable/disable TXCSUM/TSO4 */ 899 if (!(ifp->if_capenable & IFCAP_TXCSUM) 900 && !(ifp->if_capenable & IFCAP_TSO4)) { 901 if (mask & IFCAP_TXCSUM) { 902 ifp->if_capenable |= IFCAP_TXCSUM; 903 /* enable TXCSUM, restore TSO if previously enabled */ 904 if (vsi->flags & IXL_FLAGS_KEEP_TSO4) { 905 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 906 ifp->if_capenable |= IFCAP_TSO4; 907 } 908 } 909 else if (mask & IFCAP_TSO4) { 910 ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4); 911 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 912 device_printf(dev, 913 "TSO4 requires txcsum, enabling both...\n"); 914 } 915 } else if((ifp->if_capenable & IFCAP_TXCSUM) 916 && !(ifp->if_capenable & IFCAP_TSO4)) { 917 if (mask & IFCAP_TXCSUM) 918 ifp->if_capenable &= ~IFCAP_TXCSUM; 919 else if (mask & IFCAP_TSO4) 920 ifp->if_capenable |= IFCAP_TSO4; 921 } else if((ifp->if_capenable & IFCAP_TXCSUM) 922 && (ifp->if_capenable & IFCAP_TSO4)) { 923 if (mask & IFCAP_TXCSUM) { 924 vsi->flags |= IXL_FLAGS_KEEP_TSO4; 925 ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4); 926 device_printf(dev, 927 "TSO4 requires txcsum, disabling both...\n"); 928 } else if (mask & IFCAP_TSO4) 929 ifp->if_capenable &= ~IFCAP_TSO4; 930 } 931 932 /* Enable/disable TXCSUM_IPV6/TSO6 */ 933 if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6) 934 && !(ifp->if_capenable & IFCAP_TSO6)) { 935 if (mask & IFCAP_TXCSUM_IPV6) { 936 ifp->if_capenable |= IFCAP_TXCSUM_IPV6; 937 if (vsi->flags & IXL_FLAGS_KEEP_TSO6) { 938 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 939 ifp->if_capenable |= IFCAP_TSO6; 940 } 941 } else if (mask & IFCAP_TSO6) { 942 ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 943 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 944 device_printf(dev, 945 "TSO6 requires txcsum6, enabling both...\n"); 946 } 947 } else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 948 && !(ifp->if_capenable & IFCAP_TSO6)) { 949 if (mask & IFCAP_TXCSUM_IPV6) 950 ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6; 951 else if (mask & IFCAP_TSO6) 952 ifp->if_capenable |= IFCAP_TSO6; 953 } else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 954 && (ifp->if_capenable & IFCAP_TSO6)) { 955 if (mask & IFCAP_TXCSUM_IPV6) { 956 vsi->flags |= IXL_FLAGS_KEEP_TSO6; 957 ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 958 device_printf(dev, 959 "TSO6 requires txcsum6, disabling both...\n"); 960 } else if (mask & IFCAP_TSO6) 961 ifp->if_capenable &= ~IFCAP_TSO6; 962 } 963} 964 965/********************************************************************* 966 * Ioctl entry point 967 * 968 * ixl_ioctl is called when the user wants to configure the 969 * interface. 970 * 971 * return 0 on success, positive on failure 972 **********************************************************************/ 973 974static int 975ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 976{ 977 struct ixl_vsi *vsi = ifp->if_softc; 978 struct ixl_pf *pf = vsi->back; 979 struct ifreq *ifr = (struct ifreq *) data; 980#if defined(INET) || defined(INET6) 981 struct ifaddr *ifa = (struct ifaddr *)data; 982 bool avoid_reset = FALSE; 983#endif 984 int error = 0; 985 986 switch (command) { 987 988 case SIOCSIFADDR: 989#ifdef INET 990 if (ifa->ifa_addr->sa_family == AF_INET) 991 avoid_reset = TRUE; 992#endif 993#ifdef INET6 994 if (ifa->ifa_addr->sa_family == AF_INET6) 995 avoid_reset = TRUE; 996#endif 997#if defined(INET) || defined(INET6) 998 /* 999 ** Calling init results in link renegotiation, 1000 ** so we avoid doing it when possible. 1001 */ 1002 if (avoid_reset) { 1003 ifp->if_flags |= IFF_UP; 1004 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1005 ixl_init(pf); 1006#ifdef INET 1007 if (!(ifp->if_flags & IFF_NOARP)) 1008 arp_ifinit(ifp, ifa); 1009#endif 1010 } else 1011 error = ether_ioctl(ifp, command, data); 1012 break; 1013#endif 1014 case SIOCSIFMTU: 1015 IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)"); 1016 if (ifr->ifr_mtu > IXL_MAX_FRAME - 1017 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) { 1018 error = EINVAL; 1019 } else { 1020 IXL_PF_LOCK(pf); 1021 ifp->if_mtu = ifr->ifr_mtu; 1022 vsi->max_frame_size = 1023 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 1024 + ETHER_VLAN_ENCAP_LEN; 1025 ixl_init_locked(pf); 1026 IXL_PF_UNLOCK(pf); 1027 } 1028 break; 1029 case SIOCSIFFLAGS: 1030 IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)"); 1031 IXL_PF_LOCK(pf); 1032 if (ifp->if_flags & IFF_UP) { 1033 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1034 if ((ifp->if_flags ^ pf->if_flags) & 1035 (IFF_PROMISC | IFF_ALLMULTI)) { 1036 ixl_set_promisc(vsi); 1037 } 1038 } else 1039 ixl_init_locked(pf); 1040 } else 1041 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1042 ixl_stop(pf); 1043 pf->if_flags = ifp->if_flags; 1044 IXL_PF_UNLOCK(pf); 1045 break; 1046 case SIOCADDMULTI: 1047 IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI"); 1048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1049 IXL_PF_LOCK(pf); 1050 ixl_disable_intr(vsi); 1051 ixl_add_multi(vsi); 1052 ixl_enable_intr(vsi); 1053 IXL_PF_UNLOCK(pf); 1054 } 1055 break; 1056 case SIOCDELMULTI: 1057 IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI"); 1058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1059 IXL_PF_LOCK(pf); 1060 ixl_disable_intr(vsi); 1061 ixl_del_multi(vsi); 1062 ixl_enable_intr(vsi); 1063 IXL_PF_UNLOCK(pf); 1064 } 1065 break; 1066 case SIOCSIFMEDIA: 1067 case SIOCGIFMEDIA: 1068#ifdef IFM_ETH_XTYPE 1069 case SIOCGIFXMEDIA: 1070#endif 1071 IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)"); 1072 error = ifmedia_ioctl(ifp, ifr, &vsi->media, command); 1073 break; 1074 case SIOCSIFCAP: 1075 { 1076 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1077 IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)"); 1078 1079 ixl_cap_txcsum_tso(vsi, ifp, mask); 1080 1081 if (mask & IFCAP_RXCSUM) 1082 ifp->if_capenable ^= IFCAP_RXCSUM; 1083 if (mask & IFCAP_RXCSUM_IPV6) 1084 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1085 if (mask & IFCAP_LRO) 1086 ifp->if_capenable ^= IFCAP_LRO; 1087 if (mask & IFCAP_VLAN_HWTAGGING) 1088 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1089 if (mask & IFCAP_VLAN_HWFILTER) 1090 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 1091 if (mask & IFCAP_VLAN_HWTSO) 1092 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1093 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1094 IXL_PF_LOCK(pf); 1095 ixl_init_locked(pf); 1096 IXL_PF_UNLOCK(pf); 1097 } 1098 VLAN_CAPABILITIES(ifp); 1099 1100 break; 1101 } 1102 1103 default: 1104 IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command); 1105 error = ether_ioctl(ifp, command, data); 1106 break; 1107 } 1108 1109 return (error); 1110} 1111 1112 1113/********************************************************************* 1114 * Init entry point 1115 * 1116 * This routine is used in two ways. It is used by the stack as 1117 * init entry point in network interface structure. It is also used 1118 * by the driver as a hw/sw initialization routine to get to a 1119 * consistent state. 1120 * 1121 * return 0 on success, positive on failure 1122 **********************************************************************/ 1123 1124static void 1125ixl_init_locked(struct ixl_pf *pf) 1126{ 1127 struct i40e_hw *hw = &pf->hw; 1128 struct ixl_vsi *vsi = &pf->vsi; 1129 struct ifnet *ifp = vsi->ifp; 1130 device_t dev = pf->dev; 1131 struct i40e_filter_control_settings filter; 1132 u8 tmpaddr[ETHER_ADDR_LEN]; 1133 int ret; 1134 1135 mtx_assert(&pf->pf_mtx, MA_OWNED); 1136 INIT_DEBUGOUT("ixl_init: begin"); 1137 ixl_stop(pf); 1138 1139 /* Get the latest mac address... User might use a LAA */ 1140 bcopy(IF_LLADDR(vsi->ifp), tmpaddr, 1141 I40E_ETH_LENGTH_OF_ADDRESS); 1142 if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && 1143 i40e_validate_mac_addr(tmpaddr)) { 1144 bcopy(tmpaddr, hw->mac.addr, 1145 I40E_ETH_LENGTH_OF_ADDRESS); 1146 ret = i40e_aq_mac_address_write(hw, 1147 I40E_AQC_WRITE_TYPE_LAA_ONLY, 1148 hw->mac.addr, NULL); 1149 if (ret) { 1150 device_printf(dev, "LLA address" 1151 "change failed!!\n"); 1152 return; 1153 } 1154 } 1155 1156 /* Set the various hardware offload abilities */ 1157 ifp->if_hwassist = 0; 1158 if (ifp->if_capenable & IFCAP_TSO) 1159 ifp->if_hwassist |= CSUM_TSO; 1160 if (ifp->if_capenable & IFCAP_TXCSUM) 1161 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1162 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 1163 ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); 1164 1165 /* Set up the device filtering */ 1166 bzero(&filter, sizeof(filter)); 1167 filter.enable_ethtype = TRUE; 1168 filter.enable_macvlan = TRUE; 1169#ifdef IXL_FDIR 1170 filter.enable_fdir = TRUE; 1171#endif 1172 if (i40e_set_filter_control(hw, &filter)) 1173 device_printf(dev, "set_filter_control() failed\n"); 1174 1175 /* Set up RSS */ 1176 ixl_config_rss(vsi); 1177 1178 /* 1179 ** Prepare the VSI: rings, hmc contexts, etc... 1180 */ 1181 if (ixl_initialize_vsi(vsi)) { 1182 device_printf(dev, "initialize vsi failed!!\n"); 1183 return; 1184 } 1185 1186 /* Add protocol filters to list */ 1187 ixl_init_filters(vsi); 1188 1189 /* Setup vlan's if needed */ 1190 ixl_setup_vlan_filters(vsi); 1191 1192 /* Start the local timer */ 1193 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1194 1195 /* Set up MSI/X routing and the ITR settings */ 1196 if (ixl_enable_msix) { 1197 ixl_configure_msix(pf); 1198 ixl_configure_itr(pf); 1199 } else 1200 ixl_configure_legacy(pf); 1201 1202 ixl_enable_rings(vsi); 1203 1204 i40e_aq_set_default_vsi(hw, vsi->seid, NULL); 1205 1206 ixl_reconfigure_filters(vsi); 1207 1208 /* Set MTU in hardware*/ 1209 int aq_error = i40e_aq_set_mac_config(hw, vsi->max_frame_size, 1210 TRUE, 0, NULL); 1211 if (aq_error) 1212 device_printf(vsi->dev, 1213 "aq_set_mac_config in init error, code %d\n", 1214 aq_error); 1215 1216 /* And now turn on interrupts */ 1217 ixl_enable_intr(vsi); 1218 1219 /* Now inform the stack we're ready */ 1220 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1221 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1222 1223 return; 1224} 1225 1226static void 1227ixl_init(void *arg) 1228{ 1229 struct ixl_pf *pf = arg; 1230 1231 IXL_PF_LOCK(pf); 1232 ixl_init_locked(pf); 1233 IXL_PF_UNLOCK(pf); 1234 return; 1235} 1236 1237/* 1238** 1239** MSIX Interrupt Handlers and Tasklets 1240** 1241*/ 1242static void 1243ixl_handle_que(void *context, int pending) 1244{ 1245 struct ixl_queue *que = context; 1246 struct ixl_vsi *vsi = que->vsi; 1247 struct i40e_hw *hw = vsi->hw; 1248 struct tx_ring *txr = &que->txr; 1249 struct ifnet *ifp = vsi->ifp; 1250 bool more; 1251 1252 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1253 more = ixl_rxeof(que, IXL_RX_LIMIT); 1254 IXL_TX_LOCK(txr); 1255 ixl_txeof(que); 1256 if (!drbr_empty(ifp, txr->br)) 1257 ixl_mq_start_locked(ifp, txr); 1258 IXL_TX_UNLOCK(txr); 1259 if (more) { 1260 taskqueue_enqueue(que->tq, &que->task); 1261 return; 1262 } 1263 } 1264 1265 /* Reenable this interrupt - hmmm */ 1266 ixl_enable_queue(hw, que->me); 1267 return; 1268} 1269 1270 1271/********************************************************************* 1272 * 1273 * Legacy Interrupt Service routine 1274 * 1275 **********************************************************************/ 1276void 1277ixl_intr(void *arg) 1278{ 1279 struct ixl_pf *pf = arg; 1280 struct i40e_hw *hw = &pf->hw; 1281 struct ixl_vsi *vsi = &pf->vsi; 1282 struct ixl_queue *que = vsi->queues; 1283 struct ifnet *ifp = vsi->ifp; 1284 struct tx_ring *txr = &que->txr; 1285 u32 reg, icr0, mask; 1286 bool more_tx, more_rx; 1287 1288 ++que->irqs; 1289 1290 /* Protect against spurious interrupts */ 1291 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1292 return; 1293 1294 icr0 = rd32(hw, I40E_PFINT_ICR0); 1295 1296 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1297 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1298 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1299 1300 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1301 1302#ifdef PCI_IOV 1303 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) 1304 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1305#endif 1306 1307 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 1308 taskqueue_enqueue(pf->tq, &pf->adminq); 1309 return; 1310 } 1311 1312 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1313 1314 IXL_TX_LOCK(txr); 1315 more_tx = ixl_txeof(que); 1316 if (!drbr_empty(vsi->ifp, txr->br)) 1317 more_tx = 1; 1318 IXL_TX_UNLOCK(txr); 1319 1320 /* re-enable other interrupt causes */ 1321 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 1322 1323 /* And now the queues */ 1324 reg = rd32(hw, I40E_QINT_RQCTL(0)); 1325 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1326 wr32(hw, I40E_QINT_RQCTL(0), reg); 1327 1328 reg = rd32(hw, I40E_QINT_TQCTL(0)); 1329 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1330 reg &= ~I40E_PFINT_ICR0_INTEVENT_MASK; 1331 wr32(hw, I40E_QINT_TQCTL(0), reg); 1332 1333 ixl_enable_legacy(hw); 1334 1335 return; 1336} 1337 1338 1339/********************************************************************* 1340 * 1341 * MSIX VSI Interrupt Service routine 1342 * 1343 **********************************************************************/ 1344void 1345ixl_msix_que(void *arg) 1346{ 1347 struct ixl_queue *que = arg; 1348 struct ixl_vsi *vsi = que->vsi; 1349 struct i40e_hw *hw = vsi->hw; 1350 struct tx_ring *txr = &que->txr; 1351 bool more_tx, more_rx; 1352 1353 /* Protect against spurious interrupts */ 1354 if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)) 1355 return; 1356 1357 ++que->irqs; 1358 1359 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1360 1361 IXL_TX_LOCK(txr); 1362 more_tx = ixl_txeof(que); 1363 /* 1364 ** Make certain that if the stack 1365 ** has anything queued the task gets 1366 ** scheduled to handle it. 1367 */ 1368 if (!drbr_empty(vsi->ifp, txr->br)) 1369 more_tx = 1; 1370 IXL_TX_UNLOCK(txr); 1371 1372 ixl_set_queue_rx_itr(que); 1373 ixl_set_queue_tx_itr(que); 1374 1375 if (more_tx || more_rx) 1376 taskqueue_enqueue(que->tq, &que->task); 1377 else 1378 ixl_enable_queue(hw, que->me); 1379 1380 return; 1381} 1382 1383 1384/********************************************************************* 1385 * 1386 * MSIX Admin Queue Interrupt Service routine 1387 * 1388 **********************************************************************/ 1389static void 1390ixl_msix_adminq(void *arg) 1391{ 1392 struct ixl_pf *pf = arg; 1393 struct i40e_hw *hw = &pf->hw; 1394 u32 reg, mask; 1395 1396 ++pf->admin_irq; 1397 1398 reg = rd32(hw, I40E_PFINT_ICR0); 1399 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1400 1401 /* Check on the cause */ 1402 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) 1403 mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 1404 1405 if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 1406 ixl_handle_mdd_event(pf); 1407 mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 1408 } 1409 1410#ifdef PCI_IOV 1411 if (reg & I40E_PFINT_ICR0_VFLR_MASK) { 1412 mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 1413 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1414 } 1415#endif 1416 1417 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1418 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1419 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1420 1421 taskqueue_enqueue(pf->tq, &pf->adminq); 1422 return; 1423} 1424 1425/********************************************************************* 1426 * 1427 * Media Ioctl callback 1428 * 1429 * This routine is called whenever the user queries the status of 1430 * the interface using ifconfig. 1431 * 1432 **********************************************************************/ 1433static void 1434ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) 1435{ 1436 struct ixl_vsi *vsi = ifp->if_softc; 1437 struct ixl_pf *pf = vsi->back; 1438 struct i40e_hw *hw = &pf->hw; 1439 1440 INIT_DEBUGOUT("ixl_media_status: begin"); 1441 IXL_PF_LOCK(pf); 1442 1443 hw->phy.get_link_info = TRUE; 1444 i40e_get_link_status(hw, &pf->link_up); 1445 ixl_update_link_status(pf); 1446 1447 ifmr->ifm_status = IFM_AVALID; 1448 ifmr->ifm_active = IFM_ETHER; 1449 1450 if (!pf->link_up) { 1451 IXL_PF_UNLOCK(pf); 1452 return; 1453 } 1454 1455 ifmr->ifm_status |= IFM_ACTIVE; 1456 /* Hardware is always full-duplex */ 1457 ifmr->ifm_active |= IFM_FDX; 1458 1459 switch (hw->phy.link_info.phy_type) { 1460 /* 100 M */ 1461 case I40E_PHY_TYPE_100BASE_TX: 1462 ifmr->ifm_active |= IFM_100_TX; 1463 break; 1464 /* 1 G */ 1465 case I40E_PHY_TYPE_1000BASE_T: 1466 ifmr->ifm_active |= IFM_1000_T; 1467 break; 1468 case I40E_PHY_TYPE_1000BASE_SX: 1469 ifmr->ifm_active |= IFM_1000_SX; 1470 break; 1471 case I40E_PHY_TYPE_1000BASE_LX: 1472 ifmr->ifm_active |= IFM_1000_LX; 1473 break; 1474 /* 10 G */ 1475 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1476 ifmr->ifm_active |= IFM_10G_TWINAX; 1477 break; 1478 case I40E_PHY_TYPE_10GBASE_SR: 1479 ifmr->ifm_active |= IFM_10G_SR; 1480 break; 1481 case I40E_PHY_TYPE_10GBASE_LR: 1482 ifmr->ifm_active |= IFM_10G_LR; 1483 break; 1484 case I40E_PHY_TYPE_10GBASE_T: 1485 ifmr->ifm_active |= IFM_10G_T; 1486 break; 1487 /* 40 G */ 1488 case I40E_PHY_TYPE_40GBASE_CR4: 1489 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1490 ifmr->ifm_active |= IFM_40G_CR4; 1491 break; 1492 case I40E_PHY_TYPE_40GBASE_SR4: 1493 ifmr->ifm_active |= IFM_40G_SR4; 1494 break; 1495 case I40E_PHY_TYPE_40GBASE_LR4: 1496 ifmr->ifm_active |= IFM_40G_LR4; 1497 break; 1498#ifndef IFM_ETH_XTYPE 1499 case I40E_PHY_TYPE_1000BASE_KX: 1500 ifmr->ifm_active |= IFM_1000_CX; 1501 break; 1502 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1503 case I40E_PHY_TYPE_10GBASE_CR1: 1504 ifmr->ifm_active |= IFM_10G_TWINAX; 1505 break; 1506 case I40E_PHY_TYPE_10GBASE_KX4: 1507 ifmr->ifm_active |= IFM_10G_CX4; 1508 break; 1509 case I40E_PHY_TYPE_10GBASE_KR: 1510 ifmr->ifm_active |= IFM_10G_SR; 1511 break; 1512 case I40E_PHY_TYPE_40GBASE_KR4: 1513 case I40E_PHY_TYPE_XLPPI: 1514 ifmr->ifm_active |= IFM_40G_SR4; 1515 break; 1516#else 1517 case I40E_PHY_TYPE_1000BASE_KX: 1518 ifmr->ifm_active |= IFM_1000_KX; 1519 break; 1520 /* ERJ: What's the difference between these? */ 1521 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1522 case I40E_PHY_TYPE_10GBASE_CR1: 1523 ifmr->ifm_active |= IFM_10G_CR1; 1524 break; 1525 case I40E_PHY_TYPE_10GBASE_KX4: 1526 ifmr->ifm_active |= IFM_10G_KX4; 1527 break; 1528 case I40E_PHY_TYPE_10GBASE_KR: 1529 ifmr->ifm_active |= IFM_10G_KR; 1530 break; 1531 case I40E_PHY_TYPE_20GBASE_KR2: 1532 ifmr->ifm_active |= IFM_20G_KR2; 1533 break; 1534 case I40E_PHY_TYPE_40GBASE_KR4: 1535 ifmr->ifm_active |= IFM_40G_KR4; 1536 break; 1537 case I40E_PHY_TYPE_XLPPI: 1538 ifmr->ifm_active |= IFM_40G_XLPPI; 1539 break; 1540#endif 1541 default: 1542 ifmr->ifm_active |= IFM_UNKNOWN; 1543 break; 1544 } 1545 /* Report flow control status as well */ 1546 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) 1547 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 1548 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) 1549 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 1550 1551 IXL_PF_UNLOCK(pf); 1552 1553 return; 1554} 1555 1556/********************************************************************* 1557 * 1558 * Media Ioctl callback 1559 * 1560 * This routine is called when the user changes speed/duplex using 1561 * media/mediopt option with ifconfig. 1562 * 1563 **********************************************************************/ 1564static int 1565ixl_media_change(struct ifnet * ifp) 1566{ 1567 struct ixl_vsi *vsi = ifp->if_softc; 1568 struct ifmedia *ifm = &vsi->media; 1569 1570 INIT_DEBUGOUT("ixl_media_change: begin"); 1571 1572 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1573 return (EINVAL); 1574 1575 if_printf(ifp, "Media change is currently not supported.\n"); 1576 1577 return (ENODEV); 1578} 1579 1580 1581#ifdef IXL_FDIR 1582/* 1583** ATR: Application Targetted Receive - creates a filter 1584** based on TX flow info that will keep the receive 1585** portion of the flow on the same queue. Based on the 1586** implementation this is only available for TCP connections 1587*/ 1588void 1589ixl_atr(struct ixl_queue *que, struct tcphdr *th, int etype) 1590{ 1591 struct ixl_vsi *vsi = que->vsi; 1592 struct tx_ring *txr = &que->txr; 1593 struct i40e_filter_program_desc *FDIR; 1594 u32 ptype, dtype; 1595 int idx; 1596 1597 /* check if ATR is enabled and sample rate */ 1598 if ((!ixl_enable_fdir) || (!txr->atr_rate)) 1599 return; 1600 /* 1601 ** We sample all TCP SYN/FIN packets, 1602 ** or at the selected sample rate 1603 */ 1604 txr->atr_count++; 1605 if (((th->th_flags & (TH_FIN | TH_SYN)) == 0) && 1606 (txr->atr_count < txr->atr_rate)) 1607 return; 1608 txr->atr_count = 0; 1609 1610 /* Get a descriptor to use */ 1611 idx = txr->next_avail; 1612 FDIR = (struct i40e_filter_program_desc *) &txr->base[idx]; 1613 if (++idx == que->num_desc) 1614 idx = 0; 1615 txr->avail--; 1616 txr->next_avail = idx; 1617 1618 ptype = (que->me << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1619 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1620 1621 ptype |= (etype == ETHERTYPE_IP) ? 1622 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1623 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1624 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1625 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1626 1627 ptype |= vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1628 1629 dtype = I40E_TX_DESC_DTYPE_FILTER_PROG; 1630 1631 /* 1632 ** We use the TCP TH_FIN as a trigger to remove 1633 ** the filter, otherwise its an update. 1634 */ 1635 dtype |= (th->th_flags & TH_FIN) ? 1636 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1637 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1638 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1639 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1640 1641 dtype |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1642 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1643 1644 dtype |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1645 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1646 1647 FDIR->qindex_flex_ptype_vsi = htole32(ptype); 1648 FDIR->dtype_cmd_cntindex = htole32(dtype); 1649 return; 1650} 1651#endif 1652 1653 1654static void 1655ixl_set_promisc(struct ixl_vsi *vsi) 1656{ 1657 struct ifnet *ifp = vsi->ifp; 1658 struct i40e_hw *hw = vsi->hw; 1659 int err, mcnt = 0; 1660 bool uni = FALSE, multi = FALSE; 1661 1662 if (ifp->if_flags & IFF_ALLMULTI) 1663 multi = TRUE; 1664 else { /* Need to count the multicast addresses */ 1665 struct ifmultiaddr *ifma; 1666 if_maddr_rlock(ifp); 1667 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1668 if (ifma->ifma_addr->sa_family != AF_LINK) 1669 continue; 1670 if (mcnt == MAX_MULTICAST_ADDR) 1671 break; 1672 mcnt++; 1673 } 1674 if_maddr_runlock(ifp); 1675 } 1676 1677 if (mcnt >= MAX_MULTICAST_ADDR) 1678 multi = TRUE; 1679 if (ifp->if_flags & IFF_PROMISC) 1680 uni = TRUE; 1681 1682 err = i40e_aq_set_vsi_unicast_promiscuous(hw, 1683 vsi->seid, uni, NULL); 1684 err = i40e_aq_set_vsi_multicast_promiscuous(hw, 1685 vsi->seid, multi, NULL); 1686 return; 1687} 1688 1689/********************************************************************* 1690 * Filter Routines 1691 * 1692 * Routines for multicast and vlan filter management. 1693 * 1694 *********************************************************************/ 1695static void 1696ixl_add_multi(struct ixl_vsi *vsi) 1697{ 1698 struct ifmultiaddr *ifma; 1699 struct ifnet *ifp = vsi->ifp; 1700 struct i40e_hw *hw = vsi->hw; 1701 int mcnt = 0, flags; 1702 1703 IOCTL_DEBUGOUT("ixl_add_multi: begin"); 1704 1705 if_maddr_rlock(ifp); 1706 /* 1707 ** First just get a count, to decide if we 1708 ** we simply use multicast promiscuous. 1709 */ 1710 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1711 if (ifma->ifma_addr->sa_family != AF_LINK) 1712 continue; 1713 mcnt++; 1714 } 1715 if_maddr_runlock(ifp); 1716 1717 if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) { 1718 /* delete existing MC filters */ 1719 ixl_del_hw_filters(vsi, mcnt); 1720 i40e_aq_set_vsi_multicast_promiscuous(hw, 1721 vsi->seid, TRUE, NULL); 1722 return; 1723 } 1724 1725 mcnt = 0; 1726 if_maddr_rlock(ifp); 1727 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1728 if (ifma->ifma_addr->sa_family != AF_LINK) 1729 continue; 1730 ixl_add_mc_filter(vsi, 1731 (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 1732 mcnt++; 1733 } 1734 if_maddr_runlock(ifp); 1735 if (mcnt > 0) { 1736 flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC); 1737 ixl_add_hw_filters(vsi, flags, mcnt); 1738 } 1739 1740 IOCTL_DEBUGOUT("ixl_add_multi: end"); 1741 return; 1742} 1743 1744static void 1745ixl_del_multi(struct ixl_vsi *vsi) 1746{ 1747 struct ifnet *ifp = vsi->ifp; 1748 struct ifmultiaddr *ifma; 1749 struct ixl_mac_filter *f; 1750 int mcnt = 0; 1751 bool match = FALSE; 1752 1753 IOCTL_DEBUGOUT("ixl_del_multi: begin"); 1754 1755 /* Search for removed multicast addresses */ 1756 if_maddr_rlock(ifp); 1757 SLIST_FOREACH(f, &vsi->ftl, next) { 1758 if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) { 1759 match = FALSE; 1760 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1761 if (ifma->ifma_addr->sa_family != AF_LINK) 1762 continue; 1763 u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1764 if (cmp_etheraddr(f->macaddr, mc_addr)) { 1765 match = TRUE; 1766 break; 1767 } 1768 } 1769 if (match == FALSE) { 1770 f->flags |= IXL_FILTER_DEL; 1771 mcnt++; 1772 } 1773 } 1774 } 1775 if_maddr_runlock(ifp); 1776 1777 if (mcnt > 0) 1778 ixl_del_hw_filters(vsi, mcnt); 1779} 1780 1781 1782/********************************************************************* 1783 * Timer routine 1784 * 1785 * This routine checks for link status,updates statistics, 1786 * and runs the watchdog check. 1787 * 1788 **********************************************************************/ 1789 1790static void 1791ixl_local_timer(void *arg) 1792{ 1793 struct ixl_pf *pf = arg; 1794 struct i40e_hw *hw = &pf->hw; 1795 struct ixl_vsi *vsi = &pf->vsi; 1796 struct ixl_queue *que = vsi->queues; 1797 device_t dev = pf->dev; 1798 int hung = 0; 1799 u32 mask; 1800 1801 mtx_assert(&pf->pf_mtx, MA_OWNED); 1802 1803 /* Fire off the adminq task */ 1804 taskqueue_enqueue(pf->tq, &pf->adminq); 1805 1806 /* Update stats */ 1807 ixl_update_stats_counters(pf); 1808 1809 /* 1810 ** Check status of the queues 1811 */ 1812 mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK | 1813 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK); 1814 1815 for (int i = 0; i < vsi->num_queues; i++,que++) { 1816 /* Any queues with outstanding work get a sw irq */ 1817 if (que->busy) 1818 wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask); 1819 /* 1820 ** Each time txeof runs without cleaning, but there 1821 ** are uncleaned descriptors it increments busy. If 1822 ** we get to 5 we declare it hung. 1823 */ 1824 if (que->busy == IXL_QUEUE_HUNG) { 1825 ++hung; 1826 /* Mark the queue as inactive */ 1827 vsi->active_queues &= ~((u64)1 << que->me); 1828 continue; 1829 } else { 1830 /* Check if we've come back from hung */ 1831 if ((vsi->active_queues & ((u64)1 << que->me)) == 0) 1832 vsi->active_queues |= ((u64)1 << que->me); 1833 } 1834 if (que->busy >= IXL_MAX_TX_BUSY) { 1835#ifdef IXL_DEBUG 1836 device_printf(dev,"Warning queue %d " 1837 "appears to be hung!\n", i); 1838#endif 1839 que->busy = IXL_QUEUE_HUNG; 1840 ++hung; 1841 } 1842 } 1843 /* Only reinit if all queues show hung */ 1844 if (hung == vsi->num_queues) 1845 goto hung; 1846 1847 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1848 return; 1849 1850hung: 1851 device_printf(dev, "Local Timer: HANG DETECT - Resetting!!\n"); 1852 ixl_init_locked(pf); 1853} 1854 1855/* 1856** Note: this routine updates the OS on the link state 1857** the real check of the hardware only happens with 1858** a link interrupt. 1859*/ 1860static void 1861ixl_update_link_status(struct ixl_pf *pf) 1862{ 1863 struct ixl_vsi *vsi = &pf->vsi; 1864 struct i40e_hw *hw = &pf->hw; 1865 struct ifnet *ifp = vsi->ifp; 1866 device_t dev = pf->dev; 1867 1868 if (pf->link_up){ 1869 if (vsi->link_active == FALSE) { 1870 pf->fc = hw->fc.current_mode; 1871 if (bootverbose) { 1872 device_printf(dev,"Link is up %d Gbps %s," 1873 " Flow Control: %s\n", 1874 ((pf->link_speed == 1875 I40E_LINK_SPEED_40GB)? 40:10), 1876 "Full Duplex", ixl_fc_string[pf->fc]); 1877 } 1878 vsi->link_active = TRUE; 1879 /* 1880 ** Warn user if link speed on NPAR enabled 1881 ** partition is not at least 10GB 1882 */ 1883 if (hw->func_caps.npar_enable && 1884 (hw->phy.link_info.link_speed == 1885 I40E_LINK_SPEED_1GB || 1886 hw->phy.link_info.link_speed == 1887 I40E_LINK_SPEED_100MB)) 1888 device_printf(dev, "The partition detected" 1889 "link speed that is less than 10Gbps\n"); 1890 if_link_state_change(ifp, LINK_STATE_UP); 1891 } 1892 } else { /* Link down */ 1893 if (vsi->link_active == TRUE) { 1894 if (bootverbose) 1895 device_printf(dev,"Link is Down\n"); 1896 if_link_state_change(ifp, LINK_STATE_DOWN); 1897 vsi->link_active = FALSE; 1898 } 1899 } 1900 1901 return; 1902} 1903 1904/********************************************************************* 1905 * 1906 * This routine disables all traffic on the adapter by issuing a 1907 * global reset on the MAC and deallocates TX/RX buffers. 1908 * 1909 **********************************************************************/ 1910 1911static void 1912ixl_stop(struct ixl_pf *pf) 1913{ 1914 struct ixl_vsi *vsi = &pf->vsi; 1915 struct ifnet *ifp = vsi->ifp; 1916 1917 mtx_assert(&pf->pf_mtx, MA_OWNED); 1918 1919 INIT_DEBUGOUT("ixl_stop: begin\n"); 1920 if (pf->num_vfs == 0) 1921 ixl_disable_intr(vsi); 1922 else 1923 ixl_disable_rings_intr(vsi); 1924 ixl_disable_rings(vsi); 1925 1926 /* Tell the stack that the interface is no longer active */ 1927 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1928 1929 /* Stop the local timer */ 1930 callout_stop(&pf->timer); 1931 1932 return; 1933} 1934 1935 1936/********************************************************************* 1937 * 1938 * Setup MSIX Interrupt resources and handlers for the VSI 1939 * 1940 **********************************************************************/ 1941static int 1942ixl_assign_vsi_legacy(struct ixl_pf *pf) 1943{ 1944 device_t dev = pf->dev; 1945 struct ixl_vsi *vsi = &pf->vsi; 1946 struct ixl_queue *que = vsi->queues; 1947 int error, rid = 0; 1948 1949 if (pf->msix == 1) 1950 rid = 1; 1951 pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1952 &rid, RF_SHAREABLE | RF_ACTIVE); 1953 if (pf->res == NULL) { 1954 device_printf(dev,"Unable to allocate" 1955 " bus resource: vsi legacy/msi interrupt\n"); 1956 return (ENXIO); 1957 } 1958 1959 /* Set the handler function */ 1960 error = bus_setup_intr(dev, pf->res, 1961 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1962 ixl_intr, pf, &pf->tag); 1963 if (error) { 1964 pf->res = NULL; 1965 device_printf(dev, "Failed to register legacy/msi handler"); 1966 return (error); 1967 } 1968 bus_describe_intr(dev, pf->res, pf->tag, "irq0"); 1969 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1970 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1971 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1972 taskqueue_thread_enqueue, &que->tq); 1973 taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que", 1974 device_get_nameunit(dev)); 1975 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1976 1977#ifdef PCI_IOV 1978 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 1979#endif 1980 1981 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1982 taskqueue_thread_enqueue, &pf->tq); 1983 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1984 device_get_nameunit(dev)); 1985 1986 return (0); 1987} 1988 1989 1990/********************************************************************* 1991 * 1992 * Setup MSIX Interrupt resources and handlers for the VSI 1993 * 1994 **********************************************************************/ 1995static int 1996ixl_assign_vsi_msix(struct ixl_pf *pf) 1997{ 1998 device_t dev = pf->dev; 1999 struct ixl_vsi *vsi = &pf->vsi; 2000 struct ixl_queue *que = vsi->queues; 2001 struct tx_ring *txr; 2002 int error, rid, vector = 0; 2003 2004 /* Admin Que is vector 0*/ 2005 rid = vector + 1; 2006 pf->res = bus_alloc_resource_any(dev, 2007 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2008 if (!pf->res) { 2009 device_printf(dev,"Unable to allocate" 2010 " bus resource: Adminq interrupt [%d]\n", rid); 2011 return (ENXIO); 2012 } 2013 /* Set the adminq vector and handler */ 2014 error = bus_setup_intr(dev, pf->res, 2015 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2016 ixl_msix_adminq, pf, &pf->tag); 2017 if (error) { 2018 pf->res = NULL; 2019 device_printf(dev, "Failed to register Admin que handler"); 2020 return (error); 2021 } 2022 bus_describe_intr(dev, pf->res, pf->tag, "aq"); 2023 pf->admvec = vector; 2024 /* Tasklet for Admin Queue */ 2025 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 2026 2027#ifdef PCI_IOV 2028 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 2029#endif 2030 2031 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 2032 taskqueue_thread_enqueue, &pf->tq); 2033 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 2034 device_get_nameunit(pf->dev)); 2035 ++vector; 2036 2037 /* Now set up the stations */ 2038 for (int i = 0; i < vsi->num_queues; i++, vector++, que++) { 2039 int cpu_id = i; 2040 rid = vector + 1; 2041 txr = &que->txr; 2042 que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2043 RF_SHAREABLE | RF_ACTIVE); 2044 if (que->res == NULL) { 2045 device_printf(dev,"Unable to allocate" 2046 " bus resource: que interrupt [%d]\n", vector); 2047 return (ENXIO); 2048 } 2049 /* Set the handler function */ 2050 error = bus_setup_intr(dev, que->res, 2051 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2052 ixl_msix_que, que, &que->tag); 2053 if (error) { 2054 que->res = NULL; 2055 device_printf(dev, "Failed to register que handler"); 2056 return (error); 2057 } 2058 bus_describe_intr(dev, que->res, que->tag, "q%d", i); 2059 /* Bind the vector to a CPU */ 2060#ifdef RSS 2061 cpu_id = rss_getcpu(i % rss_getnumbuckets()); 2062#endif 2063 bus_bind_intr(dev, que->res, cpu_id); 2064 que->msix = vector; 2065 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 2066 TASK_INIT(&que->task, 0, ixl_handle_que, que); 2067 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 2068 taskqueue_thread_enqueue, &que->tq); 2069#ifdef RSS 2070 taskqueue_start_threads_pinned(&que->tq, 1, PI_NET, 2071 cpu_id, "%s (bucket %d)", 2072 device_get_nameunit(dev), cpu_id); 2073#else 2074 taskqueue_start_threads(&que->tq, 1, PI_NET, 2075 "%s que", device_get_nameunit(dev)); 2076#endif 2077 } 2078 2079 return (0); 2080} 2081 2082 2083/* 2084 * Allocate MSI/X vectors 2085 */ 2086static int 2087ixl_init_msix(struct ixl_pf *pf) 2088{ 2089 device_t dev = pf->dev; 2090 int rid, want, vectors, queues, available; 2091 2092 /* Override by tuneable */ 2093 if (ixl_enable_msix == 0) 2094 goto msi; 2095 2096 /* 2097 ** When used in a virtualized environment 2098 ** PCI BUSMASTER capability may not be set 2099 ** so explicity set it here and rewrite 2100 ** the ENABLE in the MSIX control register 2101 ** at this point to cause the host to 2102 ** successfully initialize us. 2103 */ 2104 { 2105 u16 pci_cmd_word; 2106 int msix_ctrl; 2107 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2108 pci_cmd_word |= PCIM_CMD_BUSMASTEREN; 2109 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); 2110 pci_find_cap(dev, PCIY_MSIX, &rid); 2111 rid += PCIR_MSIX_CTRL; 2112 msix_ctrl = pci_read_config(dev, rid, 2); 2113 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 2114 pci_write_config(dev, rid, msix_ctrl, 2); 2115 } 2116 2117 /* First try MSI/X */ 2118 rid = PCIR_BAR(IXL_BAR); 2119 pf->msix_mem = bus_alloc_resource_any(dev, 2120 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2121 if (!pf->msix_mem) { 2122 /* May not be enabled */ 2123 device_printf(pf->dev, 2124 "Unable to map MSIX table \n"); 2125 goto msi; 2126 } 2127 2128 available = pci_msix_count(dev); 2129 if (available == 0) { /* system has msix disabled */ 2130 bus_release_resource(dev, SYS_RES_MEMORY, 2131 rid, pf->msix_mem); 2132 pf->msix_mem = NULL; 2133 goto msi; 2134 } 2135 2136 /* Figure out a reasonable auto config value */ 2137 queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus; 2138 2139 /* Override with hardcoded value if sane */ 2140 if ((ixl_max_queues != 0) && (ixl_max_queues <= queues)) 2141 queues = ixl_max_queues; 2142 2143#ifdef RSS 2144 /* If we're doing RSS, clamp at the number of RSS buckets */ 2145 if (queues > rss_getnumbuckets()) 2146 queues = rss_getnumbuckets(); 2147#endif 2148 2149 /* 2150 ** Want one vector (RX/TX pair) per queue 2151 ** plus an additional for the admin queue. 2152 */ 2153 want = queues + 1; 2154 if (want <= available) /* Have enough */ 2155 vectors = want; 2156 else { 2157 device_printf(pf->dev, 2158 "MSIX Configuration Problem, " 2159 "%d vectors available but %d wanted!\n", 2160 available, want); 2161 return (0); /* Will go to Legacy setup */ 2162 } 2163 2164 if (pci_alloc_msix(dev, &vectors) == 0) { 2165 device_printf(pf->dev, 2166 "Using MSIX interrupts with %d vectors\n", vectors); 2167 pf->msix = vectors; 2168 pf->vsi.num_queues = queues; 2169#ifdef RSS 2170 /* 2171 * If we're doing RSS, the number of queues needs to 2172 * match the number of RSS buckets that are configured. 2173 * 2174 * + If there's more queues than RSS buckets, we'll end 2175 * up with queues that get no traffic. 2176 * 2177 * + If there's more RSS buckets than queues, we'll end 2178 * up having multiple RSS buckets map to the same queue, 2179 * so there'll be some contention. 2180 */ 2181 if (queues != rss_getnumbuckets()) { 2182 device_printf(dev, 2183 "%s: queues (%d) != RSS buckets (%d)" 2184 "; performance will be impacted.\n", 2185 __func__, queues, rss_getnumbuckets()); 2186 } 2187#endif 2188 return (vectors); 2189 } 2190msi: 2191 vectors = pci_msi_count(dev); 2192 pf->vsi.num_queues = 1; 2193 pf->msix = 1; 2194 ixl_max_queues = 1; 2195 ixl_enable_msix = 0; 2196 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) 2197 device_printf(pf->dev,"Using an MSI interrupt\n"); 2198 else { 2199 pf->msix = 0; 2200 device_printf(pf->dev,"Using a Legacy interrupt\n"); 2201 } 2202 return (vectors); 2203} 2204 2205 2206/* 2207 * Plumb MSI/X vectors 2208 */ 2209static void 2210ixl_configure_msix(struct ixl_pf *pf) 2211{ 2212 struct i40e_hw *hw = &pf->hw; 2213 struct ixl_vsi *vsi = &pf->vsi; 2214 u32 reg; 2215 u16 vector = 1; 2216 2217 /* First set up the adminq - vector 0 */ 2218 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 2219 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 2220 2221 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 2222 I40E_PFINT_ICR0_ENA_GRST_MASK | 2223 I40E_PFINT_ICR0_HMC_ERR_MASK | 2224 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 2225 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 2226 I40E_PFINT_ICR0_ENA_VFLR_MASK | 2227 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK; 2228 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2229 2230 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 2231 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x003E); 2232 2233 wr32(hw, I40E_PFINT_DYN_CTL0, 2234 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 2235 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 2236 2237 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2238 2239 /* Next configure the queues */ 2240 for (int i = 0; i < vsi->num_queues; i++, vector++) { 2241 wr32(hw, I40E_PFINT_DYN_CTLN(i), i); 2242 wr32(hw, I40E_PFINT_LNKLSTN(i), i); 2243 2244 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 2245 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2246 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2247 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2248 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 2249 wr32(hw, I40E_QINT_RQCTL(i), reg); 2250 2251 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 2252 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2253 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2254 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2255 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2256 if (i == (vsi->num_queues - 1)) 2257 reg |= (IXL_QUEUE_EOL 2258 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2259 wr32(hw, I40E_QINT_TQCTL(i), reg); 2260 } 2261} 2262 2263/* 2264 * Configure for MSI single vector operation 2265 */ 2266static void 2267ixl_configure_legacy(struct ixl_pf *pf) 2268{ 2269 struct i40e_hw *hw = &pf->hw; 2270 u32 reg; 2271 2272 2273 wr32(hw, I40E_PFINT_ITR0(0), 0); 2274 wr32(hw, I40E_PFINT_ITR0(1), 0); 2275 2276 2277 /* Setup "other" causes */ 2278 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK 2279 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK 2280 | I40E_PFINT_ICR0_ENA_GRST_MASK 2281 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK 2282 | I40E_PFINT_ICR0_ENA_GPIO_MASK 2283 | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK 2284 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK 2285 | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK 2286 | I40E_PFINT_ICR0_ENA_VFLR_MASK 2287 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK 2288 ; 2289 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2290 2291 /* SW_ITR_IDX = 0, but don't change INTENA */ 2292 wr32(hw, I40E_PFINT_DYN_CTL0, 2293 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | 2294 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK); 2295 /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ 2296 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2297 2298 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 2299 wr32(hw, I40E_PFINT_LNKLST0, 0); 2300 2301 /* Associate the queue pair to the vector and enable the q int */ 2302 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK 2303 | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 2304 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2305 wr32(hw, I40E_QINT_RQCTL(0), reg); 2306 2307 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK 2308 | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 2309 | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2310 wr32(hw, I40E_QINT_TQCTL(0), reg); 2311 2312 /* Next enable the queue pair */ 2313 reg = rd32(hw, I40E_QTX_ENA(0)); 2314 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 2315 wr32(hw, I40E_QTX_ENA(0), reg); 2316 2317 reg = rd32(hw, I40E_QRX_ENA(0)); 2318 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 2319 wr32(hw, I40E_QRX_ENA(0), reg); 2320} 2321 2322 2323/* 2324 * Set the Initial ITR state 2325 */ 2326static void 2327ixl_configure_itr(struct ixl_pf *pf) 2328{ 2329 struct i40e_hw *hw = &pf->hw; 2330 struct ixl_vsi *vsi = &pf->vsi; 2331 struct ixl_queue *que = vsi->queues; 2332 2333 vsi->rx_itr_setting = ixl_rx_itr; 2334 if (ixl_dynamic_rx_itr) 2335 vsi->rx_itr_setting |= IXL_ITR_DYNAMIC; 2336 vsi->tx_itr_setting = ixl_tx_itr; 2337 if (ixl_dynamic_tx_itr) 2338 vsi->tx_itr_setting |= IXL_ITR_DYNAMIC; 2339 2340 for (int i = 0; i < vsi->num_queues; i++, que++) { 2341 struct tx_ring *txr = &que->txr; 2342 struct rx_ring *rxr = &que->rxr; 2343 2344 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 2345 vsi->rx_itr_setting); 2346 rxr->itr = vsi->rx_itr_setting; 2347 rxr->latency = IXL_AVE_LATENCY; 2348 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 2349 vsi->tx_itr_setting); 2350 txr->itr = vsi->tx_itr_setting; 2351 txr->latency = IXL_AVE_LATENCY; 2352 } 2353} 2354 2355 2356static int 2357ixl_allocate_pci_resources(struct ixl_pf *pf) 2358{ 2359 int rid; 2360 device_t dev = pf->dev; 2361 2362 rid = PCIR_BAR(0); 2363 pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2364 &rid, RF_ACTIVE); 2365 2366 if (!(pf->pci_mem)) { 2367 device_printf(dev,"Unable to allocate bus resource: memory\n"); 2368 return (ENXIO); 2369 } 2370 2371 pf->osdep.mem_bus_space_tag = 2372 rman_get_bustag(pf->pci_mem); 2373 pf->osdep.mem_bus_space_handle = 2374 rman_get_bushandle(pf->pci_mem); 2375 pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem); 2376 pf->osdep.flush_reg = I40E_GLGEN_STAT; 2377 pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle; 2378 2379 pf->hw.back = &pf->osdep; 2380 2381 /* 2382 ** Now setup MSI or MSI/X, should 2383 ** return us the number of supported 2384 ** vectors. (Will be 1 for MSI) 2385 */ 2386 pf->msix = ixl_init_msix(pf); 2387 return (0); 2388} 2389 2390static void 2391ixl_free_pci_resources(struct ixl_pf * pf) 2392{ 2393 struct ixl_vsi *vsi = &pf->vsi; 2394 struct ixl_queue *que = vsi->queues; 2395 device_t dev = pf->dev; 2396 int rid, memrid; 2397 2398 memrid = PCIR_BAR(IXL_BAR); 2399 2400 /* We may get here before stations are setup */ 2401 if ((!ixl_enable_msix) || (que == NULL)) 2402 goto early; 2403 2404 /* 2405 ** Release all msix VSI resources: 2406 */ 2407 for (int i = 0; i < vsi->num_queues; i++, que++) { 2408 rid = que->msix + 1; 2409 if (que->tag != NULL) { 2410 bus_teardown_intr(dev, que->res, que->tag); 2411 que->tag = NULL; 2412 } 2413 if (que->res != NULL) 2414 bus_release_resource(dev, SYS_RES_IRQ, rid, que->res); 2415 } 2416 2417early: 2418 /* Clean the AdminQ interrupt last */ 2419 if (pf->admvec) /* we are doing MSIX */ 2420 rid = pf->admvec + 1; 2421 else 2422 (pf->msix != 0) ? (rid = 1):(rid = 0); 2423 2424 if (pf->tag != NULL) { 2425 bus_teardown_intr(dev, pf->res, pf->tag); 2426 pf->tag = NULL; 2427 } 2428 if (pf->res != NULL) 2429 bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res); 2430 2431 if (pf->msix) 2432 pci_release_msi(dev); 2433 2434 if (pf->msix_mem != NULL) 2435 bus_release_resource(dev, SYS_RES_MEMORY, 2436 memrid, pf->msix_mem); 2437 2438 if (pf->pci_mem != NULL) 2439 bus_release_resource(dev, SYS_RES_MEMORY, 2440 PCIR_BAR(0), pf->pci_mem); 2441 2442 return; 2443} 2444 2445static void 2446ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type) 2447{ 2448 /* Display supported media types */ 2449 if (phy_type & (1 << I40E_PHY_TYPE_100BASE_TX)) 2450 ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2451 2452 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_T)) 2453 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2454 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_SX)) 2455 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 2456 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_LX)) 2457 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_LX, 0, NULL); 2458 2459 if (phy_type & (1 << I40E_PHY_TYPE_XAUI) || 2460 phy_type & (1 << I40E_PHY_TYPE_XFI) || 2461 phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU)) 2462 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2463 2464 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_SR)) 2465 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2466 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_LR)) 2467 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 2468 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_T)) 2469 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL); 2470 2471 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4) || 2472 phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) || 2473 phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) || 2474 phy_type & (1 << I40E_PHY_TYPE_XLAUI) || 2475 phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2476 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2477 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4)) 2478 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2479 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4)) 2480 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL); 2481 2482#ifndef IFM_ETH_XTYPE 2483 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2484 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 2485 2486 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) || 2487 phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1) || 2488 phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) || 2489 phy_type & (1 << I40E_PHY_TYPE_SFI)) 2490 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2491 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2492 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 2493 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2494 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2495 2496 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2497 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2498 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2499 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2500#else 2501 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2502 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 2503 2504 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) 2505 || phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1)) 2506 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CR1, 0, NULL); 2507 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC)) 2508 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX_LONG, 0, NULL); 2509 if (phy_type & (1 << I40E_PHY_TYPE_SFI)) 2510 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SFI, 0, NULL); 2511 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2512 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 2513 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2514 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 2515 2516 if (phy_type & (1 << I40E_PHY_TYPE_20GBASE_KR2)) 2517 ifmedia_add(&vsi->media, IFM_ETHER | IFM_20G_KR2, 0, NULL); 2518 2519 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2520 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_KR4, 0, NULL); 2521 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2522 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_XLPPI, 0, NULL); 2523#endif 2524} 2525 2526/********************************************************************* 2527 * 2528 * Setup networking device structure and register an interface. 2529 * 2530 **********************************************************************/ 2531static int 2532ixl_setup_interface(device_t dev, struct ixl_vsi *vsi) 2533{ 2534 struct ifnet *ifp; 2535 struct i40e_hw *hw = vsi->hw; 2536 struct ixl_queue *que = vsi->queues; 2537 struct i40e_aq_get_phy_abilities_resp abilities; 2538 enum i40e_status_code aq_error = 0; 2539 2540 INIT_DEBUGOUT("ixl_setup_interface: begin"); 2541 2542 ifp = vsi->ifp = if_alloc(IFT_ETHER); 2543 if (ifp == NULL) { 2544 device_printf(dev, "can not allocate ifnet structure\n"); 2545 return (-1); 2546 } 2547 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2548 ifp->if_mtu = ETHERMTU; 2549 if_initbaudrate(ifp, IF_Gbps(40)); 2550 ifp->if_init = ixl_init; 2551 ifp->if_softc = vsi; 2552 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2553 ifp->if_ioctl = ixl_ioctl; 2554 2555#if __FreeBSD_version >= 1100036 2556 if_setgetcounterfn(ifp, ixl_get_counter); 2557#endif 2558 2559 ifp->if_transmit = ixl_mq_start; 2560 2561 ifp->if_qflush = ixl_qflush; 2562 2563 ifp->if_snd.ifq_maxlen = que->num_desc - 2; 2564 2565 vsi->max_frame_size = 2566 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 2567 + ETHER_VLAN_ENCAP_LEN; 2568 2569 /* 2570 * Tell the upper layer(s) we support long frames. 2571 */ 2572 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2573 2574 ifp->if_capabilities |= IFCAP_HWCSUM; 2575 ifp->if_capabilities |= IFCAP_HWCSUM_IPV6; 2576 ifp->if_capabilities |= IFCAP_TSO; 2577 ifp->if_capabilities |= IFCAP_JUMBO_MTU; 2578 ifp->if_capabilities |= IFCAP_LRO; 2579 2580 /* VLAN capabilties */ 2581 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING 2582 | IFCAP_VLAN_HWTSO 2583 | IFCAP_VLAN_MTU 2584 | IFCAP_VLAN_HWCSUM; 2585 ifp->if_capenable = ifp->if_capabilities; 2586 2587 /* 2588 ** Don't turn this on by default, if vlans are 2589 ** created on another pseudo device (eg. lagg) 2590 ** then vlan events are not passed thru, breaking 2591 ** operation, but with HW FILTER off it works. If 2592 ** using vlans directly on the ixl driver you can 2593 ** enable this and get full hardware tag filtering. 2594 */ 2595 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 2596 2597 /* 2598 * Specify the media types supported by this adapter and register 2599 * callbacks to update media and link information 2600 */ 2601 ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change, 2602 ixl_media_status); 2603 2604 aq_error = i40e_aq_get_phy_capabilities(hw, 2605 FALSE, TRUE, &abilities, NULL); 2606 /* May need delay to detect fiber correctly */ 2607 if (aq_error == I40E_ERR_UNKNOWN_PHY) { 2608 i40e_msec_delay(200); 2609 aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, 2610 TRUE, &abilities, NULL); 2611 } 2612 if (aq_error) { 2613 if (aq_error == I40E_ERR_UNKNOWN_PHY) 2614 device_printf(dev, "Unknown PHY type detected!\n"); 2615 else 2616 device_printf(dev, 2617 "Error getting supported media types, err %d," 2618 " AQ error %d\n", aq_error, hw->aq.asq_last_status); 2619 return (0); 2620 } 2621 2622 ixl_add_ifmedia(vsi, abilities.phy_type); 2623 2624 /* Use autoselect media by default */ 2625 ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2626 ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO); 2627 2628 ether_ifattach(ifp, hw->mac.addr); 2629 2630 return (0); 2631} 2632 2633/* 2634** Run when the Admin Queue gets a 2635** link transition interrupt. 2636*/ 2637static void 2638ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e) 2639{ 2640 struct i40e_hw *hw = &pf->hw; 2641 struct i40e_aqc_get_link_status *status = 2642 (struct i40e_aqc_get_link_status *)&e->desc.params.raw; 2643 bool check; 2644 2645 hw->phy.get_link_info = TRUE; 2646 i40e_get_link_status(hw, &check); 2647 pf->link_up = check; 2648#ifdef IXL_DEBUG 2649 printf("Link is %s\n", check ? "up":"down"); 2650#endif 2651 /* Report if Unqualified modules are found */ 2652 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && 2653 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && 2654 (!(status->link_info & I40E_AQ_LINK_UP))) 2655 device_printf(pf->dev, "Link failed because " 2656 "an unqualified module was detected\n"); 2657 2658 return; 2659} 2660 2661/********************************************************************* 2662 * 2663 * Get Firmware Switch configuration 2664 * - this will need to be more robust when more complex 2665 * switch configurations are enabled. 2666 * 2667 **********************************************************************/ 2668static int 2669ixl_switch_config(struct ixl_pf *pf) 2670{ 2671 struct i40e_hw *hw = &pf->hw; 2672 struct ixl_vsi *vsi = &pf->vsi; 2673 device_t dev = vsi->dev; 2674 struct i40e_aqc_get_switch_config_resp *sw_config; 2675 u8 aq_buf[I40E_AQ_LARGE_BUF]; 2676 int ret; 2677 u16 next = 0; 2678 2679 memset(&aq_buf, 0, sizeof(aq_buf)); 2680 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 2681 ret = i40e_aq_get_switch_config(hw, sw_config, 2682 sizeof(aq_buf), &next, NULL); 2683 if (ret) { 2684 device_printf(dev,"aq_get_switch_config failed (ret=%d)!!\n", 2685 ret); 2686 return (ret); 2687 } 2688#ifdef IXL_DEBUG 2689 device_printf(dev, 2690 "Switch config: header reported: %d in structure, %d total\n", 2691 sw_config->header.num_reported, sw_config->header.num_total); 2692 for (int i = 0; i < sw_config->header.num_reported; i++) { 2693 device_printf(dev, 2694 "%d: type=%d seid=%d uplink=%d downlink=%d\n", i, 2695 sw_config->element[i].element_type, 2696 sw_config->element[i].seid, 2697 sw_config->element[i].uplink_seid, 2698 sw_config->element[i].downlink_seid); 2699 } 2700#endif 2701 /* Simplified due to a single VSI at the moment */ 2702 vsi->uplink_seid = sw_config->element[0].uplink_seid; 2703 vsi->downlink_seid = sw_config->element[0].downlink_seid; 2704 vsi->seid = sw_config->element[0].seid; 2705 return (ret); 2706} 2707 2708/********************************************************************* 2709 * 2710 * Initialize the VSI: this handles contexts, which means things 2711 * like the number of descriptors, buffer size, 2712 * plus we init the rings thru this function. 2713 * 2714 **********************************************************************/ 2715static int 2716ixl_initialize_vsi(struct ixl_vsi *vsi) 2717{ 2718 struct ixl_pf *pf = vsi->back; 2719 struct ixl_queue *que = vsi->queues; 2720 device_t dev = vsi->dev; 2721 struct i40e_hw *hw = vsi->hw; 2722 struct i40e_vsi_context ctxt; 2723 int err = 0; 2724 2725 memset(&ctxt, 0, sizeof(ctxt)); 2726 ctxt.seid = vsi->seid; 2727 if (pf->veb_seid != 0) 2728 ctxt.uplink_seid = pf->veb_seid; 2729 ctxt.pf_num = hw->pf_id; 2730 err = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 2731 if (err) { 2732 device_printf(dev,"get vsi params failed %x!!\n", err); 2733 return (err); 2734 } 2735#ifdef IXL_DEBUG 2736 printf("get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, " 2737 "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, " 2738 "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid, 2739 ctxt.uplink_seid, ctxt.vsi_number, 2740 ctxt.vsis_allocated, ctxt.vsis_unallocated, 2741 ctxt.flags, ctxt.pf_num, ctxt.vf_num, 2742 ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits); 2743#endif 2744 /* 2745 ** Set the queue and traffic class bits 2746 ** - when multiple traffic classes are supported 2747 ** this will need to be more robust. 2748 */ 2749 ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 2750 ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG; 2751 ctxt.info.queue_mapping[0] = 0; 2752 ctxt.info.tc_mapping[0] = 0x0800; 2753 2754 /* Set VLAN receive stripping mode */ 2755 ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID; 2756 ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL; 2757 if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2758 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2759 else 2760 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2761 2762 /* Keep copy of VSI info in VSI for statistic counters */ 2763 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 2764 2765 /* Reset VSI statistics */ 2766 ixl_vsi_reset_stats(vsi); 2767 vsi->hw_filters_add = 0; 2768 vsi->hw_filters_del = 0; 2769 2770 ctxt.flags = htole16(I40E_AQ_VSI_TYPE_PF); 2771 2772 err = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 2773 if (err) { 2774 device_printf(dev,"update vsi params failed %x!!\n", 2775 hw->aq.asq_last_status); 2776 return (err); 2777 } 2778 2779 for (int i = 0; i < vsi->num_queues; i++, que++) { 2780 struct tx_ring *txr = &que->txr; 2781 struct rx_ring *rxr = &que->rxr; 2782 struct i40e_hmc_obj_txq tctx; 2783 struct i40e_hmc_obj_rxq rctx; 2784 u32 txctl; 2785 u16 size; 2786 2787 2788 /* Setup the HMC TX Context */ 2789 size = que->num_desc * sizeof(struct i40e_tx_desc); 2790 memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq)); 2791 tctx.new_context = 1; 2792 tctx.base = (txr->dma.pa/IXL_TX_CTX_BASE_UNITS); 2793 tctx.qlen = que->num_desc; 2794 tctx.fc_ena = 0; 2795 tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */ 2796 /* Enable HEAD writeback */ 2797 tctx.head_wb_ena = 1; 2798 tctx.head_wb_addr = txr->dma.pa + 2799 (que->num_desc * sizeof(struct i40e_tx_desc)); 2800 tctx.rdylist_act = 0; 2801 err = i40e_clear_lan_tx_queue_context(hw, i); 2802 if (err) { 2803 device_printf(dev, "Unable to clear TX context\n"); 2804 break; 2805 } 2806 err = i40e_set_lan_tx_queue_context(hw, i, &tctx); 2807 if (err) { 2808 device_printf(dev, "Unable to set TX context\n"); 2809 break; 2810 } 2811 /* Associate the ring with this PF */ 2812 txctl = I40E_QTX_CTL_PF_QUEUE; 2813 txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2814 I40E_QTX_CTL_PF_INDX_MASK); 2815 wr32(hw, I40E_QTX_CTL(i), txctl); 2816 ixl_flush(hw); 2817 2818 /* Do ring (re)init */ 2819 ixl_init_tx_ring(que); 2820 2821 /* Next setup the HMC RX Context */ 2822 if (vsi->max_frame_size <= MCLBYTES) 2823 rxr->mbuf_sz = MCLBYTES; 2824 else 2825 rxr->mbuf_sz = MJUMPAGESIZE; 2826 2827 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len; 2828 2829 /* Set up an RX context for the HMC */ 2830 memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq)); 2831 rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT; 2832 /* ignore header split for now */ 2833 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT; 2834 rctx.rxmax = (vsi->max_frame_size < max_rxmax) ? 2835 vsi->max_frame_size : max_rxmax; 2836 rctx.dtype = 0; 2837 rctx.dsize = 1; /* do 32byte descriptors */ 2838 rctx.hsplit_0 = 0; /* no HDR split initially */ 2839 rctx.base = (rxr->dma.pa/IXL_RX_CTX_BASE_UNITS); 2840 rctx.qlen = que->num_desc; 2841 rctx.tphrdesc_ena = 1; 2842 rctx.tphwdesc_ena = 1; 2843 rctx.tphdata_ena = 0; 2844 rctx.tphhead_ena = 0; 2845 rctx.lrxqthresh = 2; 2846 rctx.crcstrip = 1; 2847 rctx.l2tsel = 1; 2848 rctx.showiv = 1; 2849 rctx.fc_ena = 0; 2850 rctx.prefena = 1; 2851 2852 err = i40e_clear_lan_rx_queue_context(hw, i); 2853 if (err) { 2854 device_printf(dev, 2855 "Unable to clear RX context %d\n", i); 2856 break; 2857 } 2858 err = i40e_set_lan_rx_queue_context(hw, i, &rctx); 2859 if (err) { 2860 device_printf(dev, "Unable to set RX context %d\n", i); 2861 break; 2862 } 2863 err = ixl_init_rx_ring(que); 2864 if (err) { 2865 device_printf(dev, "Fail in init_rx_ring %d\n", i); 2866 break; 2867 } 2868 wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0); 2869#ifdef DEV_NETMAP 2870 /* preserve queue */ 2871 if (vsi->ifp->if_capenable & IFCAP_NETMAP) { 2872 struct netmap_adapter *na = NA(vsi->ifp); 2873 struct netmap_kring *kring = &na->rx_rings[i]; 2874 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 2875 wr32(vsi->hw, I40E_QRX_TAIL(que->me), t); 2876 } else 2877#endif /* DEV_NETMAP */ 2878 wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1); 2879 } 2880 return (err); 2881} 2882 2883 2884/********************************************************************* 2885 * 2886 * Free all VSI structs. 2887 * 2888 **********************************************************************/ 2889void 2890ixl_free_vsi(struct ixl_vsi *vsi) 2891{ 2892 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 2893 struct ixl_queue *que = vsi->queues; 2894 2895 /* Free station queues */ 2896 for (int i = 0; i < vsi->num_queues; i++, que++) { 2897 struct tx_ring *txr = &que->txr; 2898 struct rx_ring *rxr = &que->rxr; 2899 2900 if (!mtx_initialized(&txr->mtx)) /* uninitialized */ 2901 continue; 2902 IXL_TX_LOCK(txr); 2903 ixl_free_que_tx(que); 2904 if (txr->base) 2905 i40e_free_dma_mem(&pf->hw, &txr->dma); 2906 IXL_TX_UNLOCK(txr); 2907 IXL_TX_LOCK_DESTROY(txr); 2908 2909 if (!mtx_initialized(&rxr->mtx)) /* uninitialized */ 2910 continue; 2911 IXL_RX_LOCK(rxr); 2912 ixl_free_que_rx(que); 2913 if (rxr->base) 2914 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2915 IXL_RX_UNLOCK(rxr); 2916 IXL_RX_LOCK_DESTROY(rxr); 2917 2918 } 2919 free(vsi->queues, M_DEVBUF); 2920 2921 /* Free VSI filter list */ 2922 ixl_free_mac_filters(vsi); 2923} 2924 2925static void 2926ixl_free_mac_filters(struct ixl_vsi *vsi) 2927{ 2928 struct ixl_mac_filter *f; 2929 2930 while (!SLIST_EMPTY(&vsi->ftl)) { 2931 f = SLIST_FIRST(&vsi->ftl); 2932 SLIST_REMOVE_HEAD(&vsi->ftl, next); 2933 free(f, M_DEVBUF); 2934 } 2935} 2936 2937 2938/********************************************************************* 2939 * 2940 * Allocate memory for the VSI (virtual station interface) and their 2941 * associated queues, rings and the descriptors associated with each, 2942 * called only once at attach. 2943 * 2944 **********************************************************************/ 2945static int 2946ixl_setup_stations(struct ixl_pf *pf) 2947{ 2948 device_t dev = pf->dev; 2949 struct ixl_vsi *vsi; 2950 struct ixl_queue *que; 2951 struct tx_ring *txr; 2952 struct rx_ring *rxr; 2953 int rsize, tsize; 2954 int error = I40E_SUCCESS; 2955 2956 vsi = &pf->vsi; 2957 vsi->back = (void *)pf; 2958 vsi->hw = &pf->hw; 2959 vsi->id = 0; 2960 vsi->num_vlans = 0; 2961 vsi->back = pf; 2962 2963 /* Get memory for the station queues */ 2964 if (!(vsi->queues = 2965 (struct ixl_queue *) malloc(sizeof(struct ixl_queue) * 2966 vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2967 device_printf(dev, "Unable to allocate queue memory\n"); 2968 error = ENOMEM; 2969 goto early; 2970 } 2971 2972 for (int i = 0; i < vsi->num_queues; i++) { 2973 que = &vsi->queues[i]; 2974 que->num_desc = ixl_ringsz; 2975 que->me = i; 2976 que->vsi = vsi; 2977 /* mark the queue as active */ 2978 vsi->active_queues |= (u64)1 << que->me; 2979 txr = &que->txr; 2980 txr->que = que; 2981 txr->tail = I40E_QTX_TAIL(que->me); 2982 2983 /* Initialize the TX lock */ 2984 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 2985 device_get_nameunit(dev), que->me); 2986 mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF); 2987 /* Create the TX descriptor ring */ 2988 tsize = roundup2((que->num_desc * 2989 sizeof(struct i40e_tx_desc)) + 2990 sizeof(u32), DBA_ALIGN); 2991 if (i40e_allocate_dma_mem(&pf->hw, 2992 &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) { 2993 device_printf(dev, 2994 "Unable to allocate TX Descriptor memory\n"); 2995 error = ENOMEM; 2996 goto fail; 2997 } 2998 txr->base = (struct i40e_tx_desc *)txr->dma.va; 2999 bzero((void *)txr->base, tsize); 3000 /* Now allocate transmit soft structs for the ring */ 3001 if (ixl_allocate_tx_data(que)) { 3002 device_printf(dev, 3003 "Critical Failure setting up TX structures\n"); 3004 error = ENOMEM; 3005 goto fail; 3006 } 3007 /* Allocate a buf ring */ 3008 txr->br = buf_ring_alloc(4096, M_DEVBUF, 3009 M_WAITOK, &txr->mtx); 3010 if (txr->br == NULL) { 3011 device_printf(dev, 3012 "Critical Failure setting up TX buf ring\n"); 3013 error = ENOMEM; 3014 goto fail; 3015 } 3016 3017 /* 3018 * Next the RX queues... 3019 */ 3020 rsize = roundup2(que->num_desc * 3021 sizeof(union i40e_rx_desc), DBA_ALIGN); 3022 rxr = &que->rxr; 3023 rxr->que = que; 3024 rxr->tail = I40E_QRX_TAIL(que->me); 3025 3026 /* Initialize the RX side lock */ 3027 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 3028 device_get_nameunit(dev), que->me); 3029 mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF); 3030 3031 if (i40e_allocate_dma_mem(&pf->hw, 3032 &rxr->dma, i40e_mem_reserved, rsize, 4096)) { 3033 device_printf(dev, 3034 "Unable to allocate RX Descriptor memory\n"); 3035 error = ENOMEM; 3036 goto fail; 3037 } 3038 rxr->base = (union i40e_rx_desc *)rxr->dma.va; 3039 bzero((void *)rxr->base, rsize); 3040 3041 /* Allocate receive soft structs for the ring*/ 3042 if (ixl_allocate_rx_data(que)) { 3043 device_printf(dev, 3044 "Critical Failure setting up receive structs\n"); 3045 error = ENOMEM; 3046 goto fail; 3047 } 3048 } 3049 3050 return (0); 3051 3052fail: 3053 for (int i = 0; i < vsi->num_queues; i++) { 3054 que = &vsi->queues[i]; 3055 rxr = &que->rxr; 3056 txr = &que->txr; 3057 if (rxr->base) 3058 i40e_free_dma_mem(&pf->hw, &rxr->dma); 3059 if (txr->base) 3060 i40e_free_dma_mem(&pf->hw, &txr->dma); 3061 } 3062 3063early: 3064 return (error); 3065} 3066 3067/* 3068** Provide a update to the queue RX 3069** interrupt moderation value. 3070*/ 3071static void 3072ixl_set_queue_rx_itr(struct ixl_queue *que) 3073{ 3074 struct ixl_vsi *vsi = que->vsi; 3075 struct i40e_hw *hw = vsi->hw; 3076 struct rx_ring *rxr = &que->rxr; 3077 u16 rx_itr; 3078 u16 rx_latency = 0; 3079 int rx_bytes; 3080 3081 3082 /* Idle, do nothing */ 3083 if (rxr->bytes == 0) 3084 return; 3085 3086 if (ixl_dynamic_rx_itr) { 3087 rx_bytes = rxr->bytes/rxr->itr; 3088 rx_itr = rxr->itr; 3089 3090 /* Adjust latency range */ 3091 switch (rxr->latency) { 3092 case IXL_LOW_LATENCY: 3093 if (rx_bytes > 10) { 3094 rx_latency = IXL_AVE_LATENCY; 3095 rx_itr = IXL_ITR_20K; 3096 } 3097 break; 3098 case IXL_AVE_LATENCY: 3099 if (rx_bytes > 20) { 3100 rx_latency = IXL_BULK_LATENCY; 3101 rx_itr = IXL_ITR_8K; 3102 } else if (rx_bytes <= 10) { 3103 rx_latency = IXL_LOW_LATENCY; 3104 rx_itr = IXL_ITR_100K; 3105 } 3106 break; 3107 case IXL_BULK_LATENCY: 3108 if (rx_bytes <= 20) { 3109 rx_latency = IXL_AVE_LATENCY; 3110 rx_itr = IXL_ITR_20K; 3111 } 3112 break; 3113 } 3114 3115 rxr->latency = rx_latency; 3116 3117 if (rx_itr != rxr->itr) { 3118 /* do an exponential smoothing */ 3119 rx_itr = (10 * rx_itr * rxr->itr) / 3120 ((9 * rx_itr) + rxr->itr); 3121 rxr->itr = rx_itr & IXL_MAX_ITR; 3122 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3123 que->me), rxr->itr); 3124 } 3125 } else { /* We may have have toggled to non-dynamic */ 3126 if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC) 3127 vsi->rx_itr_setting = ixl_rx_itr; 3128 /* Update the hardware if needed */ 3129 if (rxr->itr != vsi->rx_itr_setting) { 3130 rxr->itr = vsi->rx_itr_setting; 3131 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3132 que->me), rxr->itr); 3133 } 3134 } 3135 rxr->bytes = 0; 3136 rxr->packets = 0; 3137 return; 3138} 3139 3140 3141/* 3142** Provide a update to the queue TX 3143** interrupt moderation value. 3144*/ 3145static void 3146ixl_set_queue_tx_itr(struct ixl_queue *que) 3147{ 3148 struct ixl_vsi *vsi = que->vsi; 3149 struct i40e_hw *hw = vsi->hw; 3150 struct tx_ring *txr = &que->txr; 3151 u16 tx_itr; 3152 u16 tx_latency = 0; 3153 int tx_bytes; 3154 3155 3156 /* Idle, do nothing */ 3157 if (txr->bytes == 0) 3158 return; 3159 3160 if (ixl_dynamic_tx_itr) { 3161 tx_bytes = txr->bytes/txr->itr; 3162 tx_itr = txr->itr; 3163 3164 switch (txr->latency) { 3165 case IXL_LOW_LATENCY: 3166 if (tx_bytes > 10) { 3167 tx_latency = IXL_AVE_LATENCY; 3168 tx_itr = IXL_ITR_20K; 3169 } 3170 break; 3171 case IXL_AVE_LATENCY: 3172 if (tx_bytes > 20) { 3173 tx_latency = IXL_BULK_LATENCY; 3174 tx_itr = IXL_ITR_8K; 3175 } else if (tx_bytes <= 10) { 3176 tx_latency = IXL_LOW_LATENCY; 3177 tx_itr = IXL_ITR_100K; 3178 } 3179 break; 3180 case IXL_BULK_LATENCY: 3181 if (tx_bytes <= 20) { 3182 tx_latency = IXL_AVE_LATENCY; 3183 tx_itr = IXL_ITR_20K; 3184 } 3185 break; 3186 } 3187 3188 txr->latency = tx_latency; 3189 3190 if (tx_itr != txr->itr) { 3191 /* do an exponential smoothing */ 3192 tx_itr = (10 * tx_itr * txr->itr) / 3193 ((9 * tx_itr) + txr->itr); 3194 txr->itr = tx_itr & IXL_MAX_ITR; 3195 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3196 que->me), txr->itr); 3197 } 3198 3199 } else { /* We may have have toggled to non-dynamic */ 3200 if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC) 3201 vsi->tx_itr_setting = ixl_tx_itr; 3202 /* Update the hardware if needed */ 3203 if (txr->itr != vsi->tx_itr_setting) { 3204 txr->itr = vsi->tx_itr_setting; 3205 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3206 que->me), txr->itr); 3207 } 3208 } 3209 txr->bytes = 0; 3210 txr->packets = 0; 3211 return; 3212} 3213 3214#define QUEUE_NAME_LEN 32 3215 3216static void 3217ixl_add_vsi_sysctls(struct ixl_pf *pf, struct ixl_vsi *vsi, 3218 struct sysctl_ctx_list *ctx, const char *sysctl_name) 3219{ 3220 struct sysctl_oid *tree; 3221 struct sysctl_oid_list *child; 3222 struct sysctl_oid_list *vsi_list; 3223 3224 tree = device_get_sysctl_tree(pf->dev); 3225 child = SYSCTL_CHILDREN(tree); 3226 vsi->vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, sysctl_name, 3227 CTLFLAG_RD, NULL, "VSI Number"); 3228 vsi_list = SYSCTL_CHILDREN(vsi->vsi_node); 3229 3230 ixl_add_sysctls_eth_stats(ctx, vsi_list, &vsi->eth_stats); 3231} 3232 3233static void 3234ixl_add_hw_stats(struct ixl_pf *pf) 3235{ 3236 device_t dev = pf->dev; 3237 struct ixl_vsi *vsi = &pf->vsi; 3238 struct ixl_queue *queues = vsi->queues; 3239 struct i40e_hw_port_stats *pf_stats = &pf->stats; 3240 3241 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3242 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3243 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3244 struct sysctl_oid_list *vsi_list; 3245 3246 struct sysctl_oid *queue_node; 3247 struct sysctl_oid_list *queue_list; 3248 3249 struct tx_ring *txr; 3250 struct rx_ring *rxr; 3251 char queue_namebuf[QUEUE_NAME_LEN]; 3252 3253 /* Driver statistics */ 3254 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 3255 CTLFLAG_RD, &pf->watchdog_events, 3256 "Watchdog timeouts"); 3257 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq", 3258 CTLFLAG_RD, &pf->admin_irq, 3259 "Admin Queue IRQ Handled"); 3260 3261 ixl_add_vsi_sysctls(pf, &pf->vsi, ctx, "pf"); 3262 vsi_list = SYSCTL_CHILDREN(pf->vsi.vsi_node); 3263 3264 /* Queue statistics */ 3265 for (int q = 0; q < vsi->num_queues; q++) { 3266 snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q); 3267 queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, 3268 OID_AUTO, queue_namebuf, CTLFLAG_RD, NULL, "Queue #"); 3269 queue_list = SYSCTL_CHILDREN(queue_node); 3270 3271 txr = &(queues[q].txr); 3272 rxr = &(queues[q].rxr); 3273 3274 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed", 3275 CTLFLAG_RD, &(queues[q].mbuf_defrag_failed), 3276 "m_defrag() failed"); 3277 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped", 3278 CTLFLAG_RD, &(queues[q].dropped_pkts), 3279 "Driver dropped packets"); 3280 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 3281 CTLFLAG_RD, &(queues[q].irqs), 3282 "irqs on this queue"); 3283 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 3284 CTLFLAG_RD, &(queues[q].tso), 3285 "TSO"); 3286 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup", 3287 CTLFLAG_RD, &(queues[q].tx_dma_setup), 3288 "Driver tx dma failure in xmit"); 3289 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail", 3290 CTLFLAG_RD, &(txr->no_desc), 3291 "Queue No Descriptor Available"); 3292 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 3293 CTLFLAG_RD, &(txr->total_packets), 3294 "Queue Packets Transmitted"); 3295 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes", 3296 CTLFLAG_RD, &(txr->tx_bytes), 3297 "Queue Bytes Transmitted"); 3298 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 3299 CTLFLAG_RD, &(rxr->rx_packets), 3300 "Queue Packets Received"); 3301 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 3302 CTLFLAG_RD, &(rxr->rx_bytes), 3303 "Queue Bytes Received"); 3304 } 3305 3306 /* MAC stats */ 3307 ixl_add_sysctls_mac_stats(ctx, child, pf_stats); 3308} 3309 3310static void 3311ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 3312 struct sysctl_oid_list *child, 3313 struct i40e_eth_stats *eth_stats) 3314{ 3315 struct ixl_sysctl_info ctls[] = 3316 { 3317 {ð_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"}, 3318 {ð_stats->rx_unicast, "ucast_pkts_rcvd", 3319 "Unicast Packets Received"}, 3320 {ð_stats->rx_multicast, "mcast_pkts_rcvd", 3321 "Multicast Packets Received"}, 3322 {ð_stats->rx_broadcast, "bcast_pkts_rcvd", 3323 "Broadcast Packets Received"}, 3324 {ð_stats->rx_discards, "rx_discards", "Discarded RX packets"}, 3325 {ð_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"}, 3326 {ð_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"}, 3327 {ð_stats->tx_multicast, "mcast_pkts_txd", 3328 "Multicast Packets Transmitted"}, 3329 {ð_stats->tx_broadcast, "bcast_pkts_txd", 3330 "Broadcast Packets Transmitted"}, 3331 // end 3332 {0,0,0} 3333 }; 3334 3335 struct ixl_sysctl_info *entry = ctls; 3336 while (entry->stat != 0) 3337 { 3338 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name, 3339 CTLFLAG_RD, entry->stat, 3340 entry->description); 3341 entry++; 3342 } 3343} 3344 3345static void 3346ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, 3347 struct sysctl_oid_list *child, 3348 struct i40e_hw_port_stats *stats) 3349{ 3350 struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac", 3351 CTLFLAG_RD, NULL, "Mac Statistics"); 3352 struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node); 3353 3354 struct i40e_eth_stats *eth_stats = &stats->eth; 3355 ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats); 3356 3357 struct ixl_sysctl_info ctls[] = 3358 { 3359 {&stats->crc_errors, "crc_errors", "CRC Errors"}, 3360 {&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"}, 3361 {&stats->mac_local_faults, "local_faults", "MAC Local Faults"}, 3362 {&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"}, 3363 {&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"}, 3364 /* Packet Reception Stats */ 3365 {&stats->rx_size_64, "rx_frames_64", "64 byte frames received"}, 3366 {&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"}, 3367 {&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"}, 3368 {&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"}, 3369 {&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"}, 3370 {&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"}, 3371 {&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"}, 3372 {&stats->rx_undersize, "rx_undersize", "Undersized packets received"}, 3373 {&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"}, 3374 {&stats->rx_oversize, "rx_oversized", "Oversized packets received"}, 3375 {&stats->rx_jabber, "rx_jabber", "Received Jabber"}, 3376 {&stats->checksum_error, "checksum_errors", "Checksum Errors"}, 3377 /* Packet Transmission Stats */ 3378 {&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"}, 3379 {&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"}, 3380 {&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"}, 3381 {&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"}, 3382 {&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"}, 3383 {&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"}, 3384 {&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"}, 3385 /* Flow control */ 3386 {&stats->link_xon_tx, "xon_txd", "Link XON transmitted"}, 3387 {&stats->link_xon_rx, "xon_recvd", "Link XON received"}, 3388 {&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"}, 3389 {&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"}, 3390 /* End */ 3391 {0,0,0} 3392 }; 3393 3394 struct ixl_sysctl_info *entry = ctls; 3395 while (entry->stat != 0) 3396 { 3397 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name, 3398 CTLFLAG_RD, entry->stat, 3399 entry->description); 3400 entry++; 3401 } 3402} 3403 3404 3405/* 3406** ixl_config_rss - setup RSS 3407** - note this is done for the single vsi 3408*/ 3409static void ixl_config_rss(struct ixl_vsi *vsi) 3410{ 3411 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3412 struct i40e_hw *hw = vsi->hw; 3413 u32 lut = 0; 3414 u64 set_hena = 0, hena; 3415 int i, j, que_id; 3416#ifdef RSS 3417 u32 rss_hash_config; 3418 u32 rss_seed[IXL_KEYSZ]; 3419#else 3420 u32 rss_seed[IXL_KEYSZ] = {0x41b01687, 3421 0x183cfd8c, 0xce880440, 0x580cbc3c, 3422 0x35897377, 0x328b25e1, 0x4fa98922, 3423 0xb7d90c14, 0xd5bad70d, 0xcd15a2c1}; 3424#endif 3425 3426#ifdef RSS 3427 /* Fetch the configured RSS key */ 3428 rss_getkey((uint8_t *) &rss_seed); 3429#endif 3430 3431 /* Fill out hash function seed */ 3432 for (i = 0; i < IXL_KEYSZ; i++) 3433 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]); 3434 3435 /* Enable PCTYPES for RSS: */ 3436#ifdef RSS 3437 rss_hash_config = rss_gethashconfig(); 3438 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 3439 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER); 3440 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 3441 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 3442 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 3443 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 3444 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 3445 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER); 3446 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 3447 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6); 3448 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 3449 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 3450 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 3451 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 3452#else 3453 set_hena = 3454 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | 3455 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | 3456 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | 3457 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | 3458 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | 3459 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | 3460 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | 3461 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | 3462 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | 3463 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | 3464 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD); 3465#endif 3466 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | 3467 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); 3468 hena |= set_hena; 3469 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 3470 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 3471 3472 /* Populate the LUT with max no. of queues in round robin fashion */ 3473 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 3474 if (j == vsi->num_queues) 3475 j = 0; 3476#ifdef RSS 3477 /* 3478 * Fetch the RSS bucket id for the given indirection entry. 3479 * Cap it at the number of configured buckets (which is 3480 * num_queues.) 3481 */ 3482 que_id = rss_get_indirection_to_bucket(i); 3483 que_id = que_id % vsi->num_queues; 3484#else 3485 que_id = j; 3486#endif 3487 /* lut = 4-byte sliding window of 4 lut entries */ 3488 lut = (lut << 8) | (que_id & 3489 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1)); 3490 /* On i = 3, we have 4 entries in lut; write to the register */ 3491 if ((i & 3) == 3) 3492 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut); 3493 } 3494 ixl_flush(hw); 3495} 3496 3497 3498/* 3499** This routine is run via an vlan config EVENT, 3500** it enables us to use the HW Filter table since 3501** we can get the vlan id. This just creates the 3502** entry in the soft version of the VFTA, init will 3503** repopulate the real table. 3504*/ 3505static void 3506ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3507{ 3508 struct ixl_vsi *vsi = ifp->if_softc; 3509 struct i40e_hw *hw = vsi->hw; 3510 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3511 3512 if (ifp->if_softc != arg) /* Not our event */ 3513 return; 3514 3515 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3516 return; 3517 3518 IXL_PF_LOCK(pf); 3519 ++vsi->num_vlans; 3520 ixl_add_filter(vsi, hw->mac.addr, vtag); 3521 IXL_PF_UNLOCK(pf); 3522} 3523 3524/* 3525** This routine is run via an vlan 3526** unconfig EVENT, remove our entry 3527** in the soft vfta. 3528*/ 3529static void 3530ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3531{ 3532 struct ixl_vsi *vsi = ifp->if_softc; 3533 struct i40e_hw *hw = vsi->hw; 3534 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3535 3536 if (ifp->if_softc != arg) 3537 return; 3538 3539 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3540 return; 3541 3542 IXL_PF_LOCK(pf); 3543 --vsi->num_vlans; 3544 ixl_del_filter(vsi, hw->mac.addr, vtag); 3545 IXL_PF_UNLOCK(pf); 3546} 3547 3548/* 3549** This routine updates vlan filters, called by init 3550** it scans the filter table and then updates the hw 3551** after a soft reset. 3552*/ 3553static void 3554ixl_setup_vlan_filters(struct ixl_vsi *vsi) 3555{ 3556 struct ixl_mac_filter *f; 3557 int cnt = 0, flags; 3558 3559 if (vsi->num_vlans == 0) 3560 return; 3561 /* 3562 ** Scan the filter list for vlan entries, 3563 ** mark them for addition and then call 3564 ** for the AQ update. 3565 */ 3566 SLIST_FOREACH(f, &vsi->ftl, next) { 3567 if (f->flags & IXL_FILTER_VLAN) { 3568 f->flags |= 3569 (IXL_FILTER_ADD | 3570 IXL_FILTER_USED); 3571 cnt++; 3572 } 3573 } 3574 if (cnt == 0) { 3575 printf("setup vlan: no filters found!\n"); 3576 return; 3577 } 3578 flags = IXL_FILTER_VLAN; 3579 flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3580 ixl_add_hw_filters(vsi, flags, cnt); 3581 return; 3582} 3583 3584/* 3585** Initialize filter list and add filters that the hardware 3586** needs to know about. 3587*/ 3588static void 3589ixl_init_filters(struct ixl_vsi *vsi) 3590{ 3591 /* Add broadcast address */ 3592 ixl_add_filter(vsi, ixl_bcast_addr, IXL_VLAN_ANY); 3593} 3594 3595/* 3596** This routine adds mulicast filters 3597*/ 3598static void 3599ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr) 3600{ 3601 struct ixl_mac_filter *f; 3602 3603 /* Does one already exist */ 3604 f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3605 if (f != NULL) 3606 return; 3607 3608 f = ixl_get_filter(vsi); 3609 if (f == NULL) { 3610 printf("WARNING: no filter available!!\n"); 3611 return; 3612 } 3613 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3614 f->vlan = IXL_VLAN_ANY; 3615 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED 3616 | IXL_FILTER_MC); 3617 3618 return; 3619} 3620 3621static void 3622ixl_reconfigure_filters(struct ixl_vsi *vsi) 3623{ 3624 3625 ixl_add_hw_filters(vsi, IXL_FILTER_USED, vsi->num_macs); 3626} 3627 3628/* 3629** This routine adds macvlan filters 3630*/ 3631static void 3632ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3633{ 3634 struct ixl_mac_filter *f, *tmp; 3635 struct ixl_pf *pf; 3636 device_t dev; 3637 3638 DEBUGOUT("ixl_add_filter: begin"); 3639 3640 pf = vsi->back; 3641 dev = pf->dev; 3642 3643 /* Does one already exist */ 3644 f = ixl_find_filter(vsi, macaddr, vlan); 3645 if (f != NULL) 3646 return; 3647 /* 3648 ** Is this the first vlan being registered, if so we 3649 ** need to remove the ANY filter that indicates we are 3650 ** not in a vlan, and replace that with a 0 filter. 3651 */ 3652 if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) { 3653 tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3654 if (tmp != NULL) { 3655 ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY); 3656 ixl_add_filter(vsi, macaddr, 0); 3657 } 3658 } 3659 3660 f = ixl_get_filter(vsi); 3661 if (f == NULL) { 3662 device_printf(dev, "WARNING: no filter available!!\n"); 3663 return; 3664 } 3665 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3666 f->vlan = vlan; 3667 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3668 if (f->vlan != IXL_VLAN_ANY) 3669 f->flags |= IXL_FILTER_VLAN; 3670 else 3671 vsi->num_macs++; 3672 3673 ixl_add_hw_filters(vsi, f->flags, 1); 3674 return; 3675} 3676 3677static void 3678ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3679{ 3680 struct ixl_mac_filter *f; 3681 3682 f = ixl_find_filter(vsi, macaddr, vlan); 3683 if (f == NULL) 3684 return; 3685 3686 f->flags |= IXL_FILTER_DEL; 3687 ixl_del_hw_filters(vsi, 1); 3688 vsi->num_macs--; 3689 3690 /* Check if this is the last vlan removal */ 3691 if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) { 3692 /* Switch back to a non-vlan filter */ 3693 ixl_del_filter(vsi, macaddr, 0); 3694 ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY); 3695 } 3696 return; 3697} 3698 3699/* 3700** Find the filter with both matching mac addr and vlan id 3701*/ 3702static struct ixl_mac_filter * 3703ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3704{ 3705 struct ixl_mac_filter *f; 3706 bool match = FALSE; 3707 3708 SLIST_FOREACH(f, &vsi->ftl, next) { 3709 if (!cmp_etheraddr(f->macaddr, macaddr)) 3710 continue; 3711 if (f->vlan == vlan) { 3712 match = TRUE; 3713 break; 3714 } 3715 } 3716 3717 if (!match) 3718 f = NULL; 3719 return (f); 3720} 3721 3722/* 3723** This routine takes additions to the vsi filter 3724** table and creates an Admin Queue call to create 3725** the filters in the hardware. 3726*/ 3727static void 3728ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt) 3729{ 3730 struct i40e_aqc_add_macvlan_element_data *a, *b; 3731 struct ixl_mac_filter *f; 3732 struct ixl_pf *pf; 3733 struct i40e_hw *hw; 3734 device_t dev; 3735 int err, j = 0; 3736 3737 pf = vsi->back; 3738 dev = pf->dev; 3739 hw = &pf->hw; 3740 IXL_PF_LOCK_ASSERT(pf); 3741 3742 a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt, 3743 M_DEVBUF, M_NOWAIT | M_ZERO); 3744 if (a == NULL) { 3745 device_printf(dev, "add_hw_filters failed to get memory\n"); 3746 return; 3747 } 3748 3749 /* 3750 ** Scan the filter list, each time we find one 3751 ** we add it to the admin queue array and turn off 3752 ** the add bit. 3753 */ 3754 SLIST_FOREACH(f, &vsi->ftl, next) { 3755 if (f->flags == flags) { 3756 b = &a[j]; // a pox on fvl long names :) 3757 bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN); 3758 if (f->vlan == IXL_VLAN_ANY) { 3759 b->vlan_tag = 0; 3760 b->flags = I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 3761 } else { 3762 b->vlan_tag = f->vlan; 3763 b->flags = 0; 3764 } 3765 b->flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 3766 f->flags &= ~IXL_FILTER_ADD; 3767 j++; 3768 } 3769 if (j == cnt) 3770 break; 3771 } 3772 if (j > 0) { 3773 err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL); 3774 if (err) 3775 device_printf(dev, "aq_add_macvlan err %d, " 3776 "aq_error %d\n", err, hw->aq.asq_last_status); 3777 else 3778 vsi->hw_filters_add += j; 3779 } 3780 free(a, M_DEVBUF); 3781 return; 3782} 3783 3784/* 3785** This routine takes removals in the vsi filter 3786** table and creates an Admin Queue call to delete 3787** the filters in the hardware. 3788*/ 3789static void 3790ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt) 3791{ 3792 struct i40e_aqc_remove_macvlan_element_data *d, *e; 3793 struct ixl_pf *pf; 3794 struct i40e_hw *hw; 3795 device_t dev; 3796 struct ixl_mac_filter *f, *f_temp; 3797 int err, j = 0; 3798 3799 DEBUGOUT("ixl_del_hw_filters: begin\n"); 3800 3801 pf = vsi->back; 3802 hw = &pf->hw; 3803 dev = pf->dev; 3804 3805 d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt, 3806 M_DEVBUF, M_NOWAIT | M_ZERO); 3807 if (d == NULL) { 3808 printf("del hw filter failed to get memory\n"); 3809 return; 3810 } 3811 3812 SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) { 3813 if (f->flags & IXL_FILTER_DEL) { 3814 e = &d[j]; // a pox on fvl long names :) 3815 bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN); 3816 e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3817 e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 3818 /* delete entry from vsi list */ 3819 SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next); 3820 free(f, M_DEVBUF); 3821 j++; 3822 } 3823 if (j == cnt) 3824 break; 3825 } 3826 if (j > 0) { 3827 err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL); 3828 /* NOTE: returns ENOENT every time but seems to work fine, 3829 so we'll ignore that specific error. */ 3830 // TODO: Does this still occur on current firmwares? 3831 if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) { 3832 int sc = 0; 3833 for (int i = 0; i < j; i++) 3834 sc += (!d[i].error_code); 3835 vsi->hw_filters_del += sc; 3836 device_printf(dev, 3837 "Failed to remove %d/%d filters, aq error %d\n", 3838 j - sc, j, hw->aq.asq_last_status); 3839 } else 3840 vsi->hw_filters_del += j; 3841 } 3842 free(d, M_DEVBUF); 3843 3844 DEBUGOUT("ixl_del_hw_filters: end\n"); 3845 return; 3846} 3847 3848static int 3849ixl_enable_rings(struct ixl_vsi *vsi) 3850{ 3851 struct ixl_pf *pf = vsi->back; 3852 struct i40e_hw *hw = &pf->hw; 3853 int index, error; 3854 u32 reg; 3855 3856 error = 0; 3857 for (int i = 0; i < vsi->num_queues; i++) { 3858 index = vsi->first_queue + i; 3859 i40e_pre_tx_queue_cfg(hw, index, TRUE); 3860 3861 reg = rd32(hw, I40E_QTX_ENA(index)); 3862 reg |= I40E_QTX_ENA_QENA_REQ_MASK | 3863 I40E_QTX_ENA_QENA_STAT_MASK; 3864 wr32(hw, I40E_QTX_ENA(index), reg); 3865 /* Verify the enable took */ 3866 for (int j = 0; j < 10; j++) { 3867 reg = rd32(hw, I40E_QTX_ENA(index)); 3868 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3869 break; 3870 i40e_msec_delay(10); 3871 } 3872 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) { 3873 device_printf(pf->dev, "TX queue %d disabled!\n", 3874 index); 3875 error = ETIMEDOUT; 3876 } 3877 3878 reg = rd32(hw, I40E_QRX_ENA(index)); 3879 reg |= I40E_QRX_ENA_QENA_REQ_MASK | 3880 I40E_QRX_ENA_QENA_STAT_MASK; 3881 wr32(hw, I40E_QRX_ENA(index), reg); 3882 /* Verify the enable took */ 3883 for (int j = 0; j < 10; j++) { 3884 reg = rd32(hw, I40E_QRX_ENA(index)); 3885 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3886 break; 3887 i40e_msec_delay(10); 3888 } 3889 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) { 3890 device_printf(pf->dev, "RX queue %d disabled!\n", 3891 index); 3892 error = ETIMEDOUT; 3893 } 3894 } 3895 3896 return (error); 3897} 3898 3899static int 3900ixl_disable_rings(struct ixl_vsi *vsi) 3901{ 3902 struct ixl_pf *pf = vsi->back; 3903 struct i40e_hw *hw = &pf->hw; 3904 int index, error; 3905 u32 reg; 3906 3907 error = 0; 3908 for (int i = 0; i < vsi->num_queues; i++) { 3909 index = vsi->first_queue + i; 3910 3911 i40e_pre_tx_queue_cfg(hw, index, FALSE); 3912 i40e_usec_delay(500); 3913 3914 reg = rd32(hw, I40E_QTX_ENA(index)); 3915 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3916 wr32(hw, I40E_QTX_ENA(index), reg); 3917 /* Verify the disable took */ 3918 for (int j = 0; j < 10; j++) { 3919 reg = rd32(hw, I40E_QTX_ENA(index)); 3920 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3921 break; 3922 i40e_msec_delay(10); 3923 } 3924 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) { 3925 device_printf(pf->dev, "TX queue %d still enabled!\n", 3926 index); 3927 error = ETIMEDOUT; 3928 } 3929 3930 reg = rd32(hw, I40E_QRX_ENA(index)); 3931 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3932 wr32(hw, I40E_QRX_ENA(index), reg); 3933 /* Verify the disable took */ 3934 for (int j = 0; j < 10; j++) { 3935 reg = rd32(hw, I40E_QRX_ENA(index)); 3936 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3937 break; 3938 i40e_msec_delay(10); 3939 } 3940 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) { 3941 device_printf(pf->dev, "RX queue %d still enabled!\n", 3942 index); 3943 error = ETIMEDOUT; 3944 } 3945 } 3946 3947 return (error); 3948} 3949 3950/** 3951 * ixl_handle_mdd_event 3952 * 3953 * Called from interrupt handler to identify possibly malicious vfs 3954 * (But also detects events from the PF, as well) 3955 **/ 3956static void ixl_handle_mdd_event(struct ixl_pf *pf) 3957{ 3958 struct i40e_hw *hw = &pf->hw; 3959 device_t dev = pf->dev; 3960 bool mdd_detected = false; 3961 bool pf_mdd_detected = false; 3962 u32 reg; 3963 3964 /* find what triggered the MDD event */ 3965 reg = rd32(hw, I40E_GL_MDET_TX); 3966 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 3967 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 3968 I40E_GL_MDET_TX_PF_NUM_SHIFT; 3969 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 3970 I40E_GL_MDET_TX_EVENT_SHIFT; 3971 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 3972 I40E_GL_MDET_TX_QUEUE_SHIFT; 3973 device_printf(dev, 3974 "Malicious Driver Detection event 0x%02x" 3975 " on TX queue %d pf number 0x%02x\n", 3976 event, queue, pf_num); 3977 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 3978 mdd_detected = true; 3979 } 3980 reg = rd32(hw, I40E_GL_MDET_RX); 3981 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 3982 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 3983 I40E_GL_MDET_RX_FUNCTION_SHIFT; 3984 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 3985 I40E_GL_MDET_RX_EVENT_SHIFT; 3986 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 3987 I40E_GL_MDET_RX_QUEUE_SHIFT; 3988 device_printf(dev, 3989 "Malicious Driver Detection event 0x%02x" 3990 " on RX queue %d of function 0x%02x\n", 3991 event, queue, func); 3992 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 3993 mdd_detected = true; 3994 } 3995 3996 if (mdd_detected) { 3997 reg = rd32(hw, I40E_PF_MDET_TX); 3998 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 3999 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 4000 device_printf(dev, 4001 "MDD TX event is for this function 0x%08x", 4002 reg); 4003 pf_mdd_detected = true; 4004 } 4005 reg = rd32(hw, I40E_PF_MDET_RX); 4006 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 4007 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 4008 device_printf(dev, 4009 "MDD RX event is for this function 0x%08x", 4010 reg); 4011 pf_mdd_detected = true; 4012 } 4013 } 4014 4015 /* re-enable mdd interrupt cause */ 4016 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4017 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 4018 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4019 ixl_flush(hw); 4020} 4021 4022static void 4023ixl_enable_intr(struct ixl_vsi *vsi) 4024{ 4025 struct i40e_hw *hw = vsi->hw; 4026 struct ixl_queue *que = vsi->queues; 4027 4028 if (ixl_enable_msix) { 4029 ixl_enable_adminq(hw); 4030 for (int i = 0; i < vsi->num_queues; i++, que++) 4031 ixl_enable_queue(hw, que->me); 4032 } else 4033 ixl_enable_legacy(hw); 4034} 4035 4036static void 4037ixl_disable_rings_intr(struct ixl_vsi *vsi) 4038{ 4039 struct i40e_hw *hw = vsi->hw; 4040 struct ixl_queue *que = vsi->queues; 4041 4042 for (int i = 0; i < vsi->num_queues; i++, que++) 4043 ixl_disable_queue(hw, que->me); 4044} 4045 4046static void 4047ixl_disable_intr(struct ixl_vsi *vsi) 4048{ 4049 struct i40e_hw *hw = vsi->hw; 4050 4051 if (ixl_enable_msix) 4052 ixl_disable_adminq(hw); 4053 else 4054 ixl_disable_legacy(hw); 4055} 4056 4057static void 4058ixl_enable_adminq(struct i40e_hw *hw) 4059{ 4060 u32 reg; 4061 4062 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4063 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4064 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4065 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4066 ixl_flush(hw); 4067 return; 4068} 4069 4070static void 4071ixl_disable_adminq(struct i40e_hw *hw) 4072{ 4073 u32 reg; 4074 4075 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4076 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4077 4078 return; 4079} 4080 4081static void 4082ixl_enable_queue(struct i40e_hw *hw, int id) 4083{ 4084 u32 reg; 4085 4086 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | 4087 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 4088 (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 4089 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4090} 4091 4092static void 4093ixl_disable_queue(struct i40e_hw *hw, int id) 4094{ 4095 u32 reg; 4096 4097 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4098 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4099 4100 return; 4101} 4102 4103static void 4104ixl_enable_legacy(struct i40e_hw *hw) 4105{ 4106 u32 reg; 4107 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4108 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4109 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4110 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4111} 4112 4113static void 4114ixl_disable_legacy(struct i40e_hw *hw) 4115{ 4116 u32 reg; 4117 4118 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4119 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4120 4121 return; 4122} 4123 4124static void 4125ixl_update_stats_counters(struct ixl_pf *pf) 4126{ 4127 struct i40e_hw *hw = &pf->hw; 4128 struct ixl_vsi *vsi = &pf->vsi; 4129 struct ixl_vf *vf; 4130 4131 struct i40e_hw_port_stats *nsd = &pf->stats; 4132 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 4133 4134 /* Update hw stats */ 4135 ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 4136 pf->stat_offsets_loaded, 4137 &osd->crc_errors, &nsd->crc_errors); 4138 ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 4139 pf->stat_offsets_loaded, 4140 &osd->illegal_bytes, &nsd->illegal_bytes); 4141 ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 4142 I40E_GLPRT_GORCL(hw->port), 4143 pf->stat_offsets_loaded, 4144 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 4145 ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 4146 I40E_GLPRT_GOTCL(hw->port), 4147 pf->stat_offsets_loaded, 4148 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 4149 ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 4150 pf->stat_offsets_loaded, 4151 &osd->eth.rx_discards, 4152 &nsd->eth.rx_discards); 4153 ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 4154 I40E_GLPRT_UPRCL(hw->port), 4155 pf->stat_offsets_loaded, 4156 &osd->eth.rx_unicast, 4157 &nsd->eth.rx_unicast); 4158 ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 4159 I40E_GLPRT_UPTCL(hw->port), 4160 pf->stat_offsets_loaded, 4161 &osd->eth.tx_unicast, 4162 &nsd->eth.tx_unicast); 4163 ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 4164 I40E_GLPRT_MPRCL(hw->port), 4165 pf->stat_offsets_loaded, 4166 &osd->eth.rx_multicast, 4167 &nsd->eth.rx_multicast); 4168 ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 4169 I40E_GLPRT_MPTCL(hw->port), 4170 pf->stat_offsets_loaded, 4171 &osd->eth.tx_multicast, 4172 &nsd->eth.tx_multicast); 4173 ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 4174 I40E_GLPRT_BPRCL(hw->port), 4175 pf->stat_offsets_loaded, 4176 &osd->eth.rx_broadcast, 4177 &nsd->eth.rx_broadcast); 4178 ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 4179 I40E_GLPRT_BPTCL(hw->port), 4180 pf->stat_offsets_loaded, 4181 &osd->eth.tx_broadcast, 4182 &nsd->eth.tx_broadcast); 4183 4184 ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 4185 pf->stat_offsets_loaded, 4186 &osd->tx_dropped_link_down, 4187 &nsd->tx_dropped_link_down); 4188 ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 4189 pf->stat_offsets_loaded, 4190 &osd->mac_local_faults, 4191 &nsd->mac_local_faults); 4192 ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 4193 pf->stat_offsets_loaded, 4194 &osd->mac_remote_faults, 4195 &nsd->mac_remote_faults); 4196 ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 4197 pf->stat_offsets_loaded, 4198 &osd->rx_length_errors, 4199 &nsd->rx_length_errors); 4200 4201 /* Flow control (LFC) stats */ 4202 ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 4203 pf->stat_offsets_loaded, 4204 &osd->link_xon_rx, &nsd->link_xon_rx); 4205 ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 4206 pf->stat_offsets_loaded, 4207 &osd->link_xon_tx, &nsd->link_xon_tx); 4208 ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 4209 pf->stat_offsets_loaded, 4210 &osd->link_xoff_rx, &nsd->link_xoff_rx); 4211 ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 4212 pf->stat_offsets_loaded, 4213 &osd->link_xoff_tx, &nsd->link_xoff_tx); 4214 4215 /* Packet size stats rx */ 4216 ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 4217 I40E_GLPRT_PRC64L(hw->port), 4218 pf->stat_offsets_loaded, 4219 &osd->rx_size_64, &nsd->rx_size_64); 4220 ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 4221 I40E_GLPRT_PRC127L(hw->port), 4222 pf->stat_offsets_loaded, 4223 &osd->rx_size_127, &nsd->rx_size_127); 4224 ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 4225 I40E_GLPRT_PRC255L(hw->port), 4226 pf->stat_offsets_loaded, 4227 &osd->rx_size_255, &nsd->rx_size_255); 4228 ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 4229 I40E_GLPRT_PRC511L(hw->port), 4230 pf->stat_offsets_loaded, 4231 &osd->rx_size_511, &nsd->rx_size_511); 4232 ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 4233 I40E_GLPRT_PRC1023L(hw->port), 4234 pf->stat_offsets_loaded, 4235 &osd->rx_size_1023, &nsd->rx_size_1023); 4236 ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 4237 I40E_GLPRT_PRC1522L(hw->port), 4238 pf->stat_offsets_loaded, 4239 &osd->rx_size_1522, &nsd->rx_size_1522); 4240 ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 4241 I40E_GLPRT_PRC9522L(hw->port), 4242 pf->stat_offsets_loaded, 4243 &osd->rx_size_big, &nsd->rx_size_big); 4244 4245 /* Packet size stats tx */ 4246 ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 4247 I40E_GLPRT_PTC64L(hw->port), 4248 pf->stat_offsets_loaded, 4249 &osd->tx_size_64, &nsd->tx_size_64); 4250 ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 4251 I40E_GLPRT_PTC127L(hw->port), 4252 pf->stat_offsets_loaded, 4253 &osd->tx_size_127, &nsd->tx_size_127); 4254 ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 4255 I40E_GLPRT_PTC255L(hw->port), 4256 pf->stat_offsets_loaded, 4257 &osd->tx_size_255, &nsd->tx_size_255); 4258 ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 4259 I40E_GLPRT_PTC511L(hw->port), 4260 pf->stat_offsets_loaded, 4261 &osd->tx_size_511, &nsd->tx_size_511); 4262 ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 4263 I40E_GLPRT_PTC1023L(hw->port), 4264 pf->stat_offsets_loaded, 4265 &osd->tx_size_1023, &nsd->tx_size_1023); 4266 ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 4267 I40E_GLPRT_PTC1522L(hw->port), 4268 pf->stat_offsets_loaded, 4269 &osd->tx_size_1522, &nsd->tx_size_1522); 4270 ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 4271 I40E_GLPRT_PTC9522L(hw->port), 4272 pf->stat_offsets_loaded, 4273 &osd->tx_size_big, &nsd->tx_size_big); 4274 4275 ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 4276 pf->stat_offsets_loaded, 4277 &osd->rx_undersize, &nsd->rx_undersize); 4278 ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 4279 pf->stat_offsets_loaded, 4280 &osd->rx_fragments, &nsd->rx_fragments); 4281 ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 4282 pf->stat_offsets_loaded, 4283 &osd->rx_oversize, &nsd->rx_oversize); 4284 ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 4285 pf->stat_offsets_loaded, 4286 &osd->rx_jabber, &nsd->rx_jabber); 4287 pf->stat_offsets_loaded = true; 4288 /* End hw stats */ 4289 4290 /* Update vsi stats */ 4291 ixl_update_vsi_stats(vsi); 4292 4293 for (int i = 0; i < pf->num_vfs; i++) { 4294 vf = &pf->vfs[i]; 4295 if (vf->vf_flags & VF_FLAG_ENABLED) 4296 ixl_update_eth_stats(&pf->vfs[i].vsi); 4297 } 4298} 4299 4300/* 4301** Tasklet handler for MSIX Adminq interrupts 4302** - do outside interrupt since it might sleep 4303*/ 4304static void 4305ixl_do_adminq(void *context, int pending) 4306{ 4307 struct ixl_pf *pf = context; 4308 struct i40e_hw *hw = &pf->hw; 4309 struct ixl_vsi *vsi = &pf->vsi; 4310 struct i40e_arq_event_info event; 4311 i40e_status ret; 4312 u32 reg, loop = 0; 4313 u16 opcode, result; 4314 4315 event.buf_len = IXL_AQ_BUF_SZ; 4316 event.msg_buf = malloc(event.buf_len, 4317 M_DEVBUF, M_NOWAIT | M_ZERO); 4318 if (!event.msg_buf) { 4319 printf("Unable to allocate adminq memory\n"); 4320 return; 4321 } 4322 4323 IXL_PF_LOCK(pf); 4324 /* clean and process any events */ 4325 do { 4326 ret = i40e_clean_arq_element(hw, &event, &result); 4327 if (ret) 4328 break; 4329 opcode = LE16_TO_CPU(event.desc.opcode); 4330 switch (opcode) { 4331 case i40e_aqc_opc_get_link_status: 4332 ixl_link_event(pf, &event); 4333 ixl_update_link_status(pf); 4334 break; 4335 case i40e_aqc_opc_send_msg_to_pf: 4336#ifdef PCI_IOV 4337 ixl_handle_vf_msg(pf, &event); 4338#endif 4339 break; 4340 case i40e_aqc_opc_event_lan_overflow: 4341 break; 4342 default: 4343#ifdef IXL_DEBUG 4344 printf("AdminQ unknown event %x\n", opcode); 4345#endif 4346 break; 4347 } 4348 4349 } while (result && (loop++ < IXL_ADM_LIMIT)); 4350 4351 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4352 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 4353 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4354 free(event.msg_buf, M_DEVBUF); 4355 4356 /* 4357 * If there are still messages to process, reschedule ourselves. 4358 * Otherwise, re-enable our interrupt and go to sleep. 4359 */ 4360 if (result > 0) 4361 taskqueue_enqueue(pf->tq, &pf->adminq); 4362 else 4363 ixl_enable_intr(vsi); 4364 4365 IXL_PF_UNLOCK(pf); 4366} 4367 4368static int 4369ixl_debug_info(SYSCTL_HANDLER_ARGS) 4370{ 4371 struct ixl_pf *pf; 4372 int error, input = 0; 4373 4374 error = sysctl_handle_int(oidp, &input, 0, req); 4375 4376 if (error || !req->newptr) 4377 return (error); 4378 4379 if (input == 1) { 4380 pf = (struct ixl_pf *)arg1; 4381 ixl_print_debug_info(pf); 4382 } 4383 4384 return (error); 4385} 4386 4387static void 4388ixl_print_debug_info(struct ixl_pf *pf) 4389{ 4390 struct i40e_hw *hw = &pf->hw; 4391 struct ixl_vsi *vsi = &pf->vsi; 4392 struct ixl_queue *que = vsi->queues; 4393 struct rx_ring *rxr = &que->rxr; 4394 struct tx_ring *txr = &que->txr; 4395 u32 reg; 4396 4397 4398 printf("Queue irqs = %jx\n", (uintmax_t)que->irqs); 4399 printf("AdminQ irqs = %jx\n", (uintmax_t)pf->admin_irq); 4400 printf("RX next check = %x\n", rxr->next_check); 4401 printf("RX not ready = %jx\n", (uintmax_t)rxr->not_done); 4402 printf("RX packets = %jx\n", (uintmax_t)rxr->rx_packets); 4403 printf("TX desc avail = %x\n", txr->avail); 4404 4405 reg = rd32(hw, I40E_GLV_GORCL(0xc)); 4406 printf("RX Bytes = %x\n", reg); 4407 reg = rd32(hw, I40E_GLPRT_GORCL(hw->port)); 4408 printf("Port RX Bytes = %x\n", reg); 4409 reg = rd32(hw, I40E_GLV_RDPC(0xc)); 4410 printf("RX discard = %x\n", reg); 4411 reg = rd32(hw, I40E_GLPRT_RDPC(hw->port)); 4412 printf("Port RX discard = %x\n", reg); 4413 4414 reg = rd32(hw, I40E_GLV_TEPC(0xc)); 4415 printf("TX errors = %x\n", reg); 4416 reg = rd32(hw, I40E_GLV_GOTCL(0xc)); 4417 printf("TX Bytes = %x\n", reg); 4418 4419 reg = rd32(hw, I40E_GLPRT_RUC(hw->port)); 4420 printf("RX undersize = %x\n", reg); 4421 reg = rd32(hw, I40E_GLPRT_RFC(hw->port)); 4422 printf("RX fragments = %x\n", reg); 4423 reg = rd32(hw, I40E_GLPRT_ROC(hw->port)); 4424 printf("RX oversize = %x\n", reg); 4425 reg = rd32(hw, I40E_GLPRT_RLEC(hw->port)); 4426 printf("RX length error = %x\n", reg); 4427 reg = rd32(hw, I40E_GLPRT_MRFC(hw->port)); 4428 printf("mac remote fault = %x\n", reg); 4429 reg = rd32(hw, I40E_GLPRT_MLFC(hw->port)); 4430 printf("mac local fault = %x\n", reg); 4431} 4432 4433/** 4434 * Update VSI-specific ethernet statistics counters. 4435 **/ 4436void ixl_update_eth_stats(struct ixl_vsi *vsi) 4437{ 4438 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 4439 struct i40e_hw *hw = &pf->hw; 4440 struct i40e_eth_stats *es; 4441 struct i40e_eth_stats *oes; 4442 struct i40e_hw_port_stats *nsd; 4443 u16 stat_idx = vsi->info.stat_counter_idx; 4444 4445 es = &vsi->eth_stats; 4446 oes = &vsi->eth_stats_offsets; 4447 nsd = &pf->stats; 4448 4449 /* Gather up the stats that the hw collects */ 4450 ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 4451 vsi->stat_offsets_loaded, 4452 &oes->tx_errors, &es->tx_errors); 4453 ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 4454 vsi->stat_offsets_loaded, 4455 &oes->rx_discards, &es->rx_discards); 4456 4457 ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 4458 I40E_GLV_GORCL(stat_idx), 4459 vsi->stat_offsets_loaded, 4460 &oes->rx_bytes, &es->rx_bytes); 4461 ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 4462 I40E_GLV_UPRCL(stat_idx), 4463 vsi->stat_offsets_loaded, 4464 &oes->rx_unicast, &es->rx_unicast); 4465 ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 4466 I40E_GLV_MPRCL(stat_idx), 4467 vsi->stat_offsets_loaded, 4468 &oes->rx_multicast, &es->rx_multicast); 4469 ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 4470 I40E_GLV_BPRCL(stat_idx), 4471 vsi->stat_offsets_loaded, 4472 &oes->rx_broadcast, &es->rx_broadcast); 4473 4474 ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 4475 I40E_GLV_GOTCL(stat_idx), 4476 vsi->stat_offsets_loaded, 4477 &oes->tx_bytes, &es->tx_bytes); 4478 ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 4479 I40E_GLV_UPTCL(stat_idx), 4480 vsi->stat_offsets_loaded, 4481 &oes->tx_unicast, &es->tx_unicast); 4482 ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 4483 I40E_GLV_MPTCL(stat_idx), 4484 vsi->stat_offsets_loaded, 4485 &oes->tx_multicast, &es->tx_multicast); 4486 ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 4487 I40E_GLV_BPTCL(stat_idx), 4488 vsi->stat_offsets_loaded, 4489 &oes->tx_broadcast, &es->tx_broadcast); 4490 vsi->stat_offsets_loaded = true; 4491} 4492 4493static void 4494ixl_update_vsi_stats(struct ixl_vsi *vsi) 4495{ 4496 struct ixl_pf *pf; 4497 struct ifnet *ifp; 4498 struct i40e_eth_stats *es; 4499 u64 tx_discards; 4500 4501 struct i40e_hw_port_stats *nsd; 4502 4503 pf = vsi->back; 4504 ifp = vsi->ifp; 4505 es = &vsi->eth_stats; 4506 nsd = &pf->stats; 4507 4508 ixl_update_eth_stats(vsi); 4509 4510 tx_discards = es->tx_discards + nsd->tx_dropped_link_down; 4511 for (int i = 0; i < vsi->num_queues; i++) 4512 tx_discards += vsi->queues[i].txr.br->br_drops; 4513 4514 /* Update ifnet stats */ 4515 IXL_SET_IPACKETS(vsi, es->rx_unicast + 4516 es->rx_multicast + 4517 es->rx_broadcast); 4518 IXL_SET_OPACKETS(vsi, es->tx_unicast + 4519 es->tx_multicast + 4520 es->tx_broadcast); 4521 IXL_SET_IBYTES(vsi, es->rx_bytes); 4522 IXL_SET_OBYTES(vsi, es->tx_bytes); 4523 IXL_SET_IMCASTS(vsi, es->rx_multicast); 4524 IXL_SET_OMCASTS(vsi, es->tx_multicast); 4525 4526 IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes + 4527 nsd->rx_undersize + nsd->rx_oversize + nsd->rx_fragments + 4528 nsd->rx_jabber); 4529 IXL_SET_OERRORS(vsi, es->tx_errors); 4530 IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards); 4531 IXL_SET_OQDROPS(vsi, tx_discards); 4532 IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol); 4533 IXL_SET_COLLISIONS(vsi, 0); 4534} 4535 4536/** 4537 * Reset all of the stats for the given pf 4538 **/ 4539void ixl_pf_reset_stats(struct ixl_pf *pf) 4540{ 4541 bzero(&pf->stats, sizeof(struct i40e_hw_port_stats)); 4542 bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats)); 4543 pf->stat_offsets_loaded = false; 4544} 4545 4546/** 4547 * Resets all stats of the given vsi 4548 **/ 4549void ixl_vsi_reset_stats(struct ixl_vsi *vsi) 4550{ 4551 bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats)); 4552 bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats)); 4553 vsi->stat_offsets_loaded = false; 4554} 4555 4556/** 4557 * Read and update a 48 bit stat from the hw 4558 * 4559 * Since the device stats are not reset at PFReset, they likely will not 4560 * be zeroed when the driver starts. We'll save the first values read 4561 * and use them as offsets to be subtracted from the raw values in order 4562 * to report stats that count from zero. 4563 **/ 4564static void 4565ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 4566 bool offset_loaded, u64 *offset, u64 *stat) 4567{ 4568 u64 new_data; 4569 4570#if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__) 4571 new_data = rd64(hw, loreg); 4572#else 4573 /* 4574 * Use two rd32's instead of one rd64; FreeBSD versions before 4575 * 10 don't support 8 byte bus reads/writes. 4576 */ 4577 new_data = rd32(hw, loreg); 4578 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 4579#endif 4580 4581 if (!offset_loaded) 4582 *offset = new_data; 4583 if (new_data >= *offset) 4584 *stat = new_data - *offset; 4585 else 4586 *stat = (new_data + ((u64)1 << 48)) - *offset; 4587 *stat &= 0xFFFFFFFFFFFFULL; 4588} 4589 4590/** 4591 * Read and update a 32 bit stat from the hw 4592 **/ 4593static void 4594ixl_stat_update32(struct i40e_hw *hw, u32 reg, 4595 bool offset_loaded, u64 *offset, u64 *stat) 4596{ 4597 u32 new_data; 4598 4599 new_data = rd32(hw, reg); 4600 if (!offset_loaded) 4601 *offset = new_data; 4602 if (new_data >= *offset) 4603 *stat = (u32)(new_data - *offset); 4604 else 4605 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset); 4606} 4607 4608/* 4609** Set flow control using sysctl: 4610** 0 - off 4611** 1 - rx pause 4612** 2 - tx pause 4613** 3 - full 4614*/ 4615static int 4616ixl_set_flowcntl(SYSCTL_HANDLER_ARGS) 4617{ 4618 /* 4619 * TODO: ensure flow control is disabled if 4620 * priority flow control is enabled 4621 * 4622 * TODO: ensure tx CRC by hardware should be enabled 4623 * if tx flow control is enabled. 4624 */ 4625 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4626 struct i40e_hw *hw = &pf->hw; 4627 device_t dev = pf->dev; 4628 int error = 0; 4629 enum i40e_status_code aq_error = 0; 4630 u8 fc_aq_err = 0; 4631 4632 /* Get request */ 4633 error = sysctl_handle_int(oidp, &pf->fc, 0, req); 4634 if ((error) || (req->newptr == NULL)) 4635 return (error); 4636 if (pf->fc < 0 || pf->fc > 3) { 4637 device_printf(dev, 4638 "Invalid fc mode; valid modes are 0 through 3\n"); 4639 return (EINVAL); 4640 } 4641 4642 /* 4643 ** Changing flow control mode currently does not work on 4644 ** 40GBASE-CR4 PHYs 4645 */ 4646 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4 4647 || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) { 4648 device_printf(dev, "Changing flow control mode unsupported" 4649 " on 40GBase-CR4 media.\n"); 4650 return (ENODEV); 4651 } 4652 4653 /* Set fc ability for port */ 4654 hw->fc.requested_mode = pf->fc; 4655 aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE); 4656 if (aq_error) { 4657 device_printf(dev, 4658 "%s: Error setting new fc mode %d; fc_err %#x\n", 4659 __func__, aq_error, fc_aq_err); 4660 return (EAGAIN); 4661 } 4662 4663 return (0); 4664} 4665 4666static int 4667ixl_current_speed(SYSCTL_HANDLER_ARGS) 4668{ 4669 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4670 struct i40e_hw *hw = &pf->hw; 4671 int error = 0, index = 0; 4672 4673 char *speeds[] = { 4674 "Unknown", 4675 "100M", 4676 "1G", 4677 "10G", 4678 "40G", 4679 "20G" 4680 }; 4681 4682 ixl_update_link_status(pf); 4683 4684 switch (hw->phy.link_info.link_speed) { 4685 case I40E_LINK_SPEED_100MB: 4686 index = 1; 4687 break; 4688 case I40E_LINK_SPEED_1GB: 4689 index = 2; 4690 break; 4691 case I40E_LINK_SPEED_10GB: 4692 index = 3; 4693 break; 4694 case I40E_LINK_SPEED_40GB: 4695 index = 4; 4696 break; 4697 case I40E_LINK_SPEED_20GB: 4698 index = 5; 4699 break; 4700 case I40E_LINK_SPEED_UNKNOWN: 4701 default: 4702 index = 0; 4703 break; 4704 } 4705 4706 error = sysctl_handle_string(oidp, speeds[index], 4707 strlen(speeds[index]), req); 4708 return (error); 4709} 4710 4711static int 4712ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds) 4713{ 4714 struct i40e_hw *hw = &pf->hw; 4715 device_t dev = pf->dev; 4716 struct i40e_aq_get_phy_abilities_resp abilities; 4717 struct i40e_aq_set_phy_config config; 4718 enum i40e_status_code aq_error = 0; 4719 4720 /* Get current capability information */ 4721 aq_error = i40e_aq_get_phy_capabilities(hw, 4722 FALSE, FALSE, &abilities, NULL); 4723 if (aq_error) { 4724 device_printf(dev, 4725 "%s: Error getting phy capabilities %d," 4726 " aq error: %d\n", __func__, aq_error, 4727 hw->aq.asq_last_status); 4728 return (EAGAIN); 4729 } 4730 4731 /* Prepare new config */ 4732 bzero(&config, sizeof(config)); 4733 config.phy_type = abilities.phy_type; 4734 config.abilities = abilities.abilities 4735 | I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 4736 config.eee_capability = abilities.eee_capability; 4737 config.eeer = abilities.eeer_val; 4738 config.low_power_ctrl = abilities.d3_lpan; 4739 /* Translate into aq cmd link_speed */ 4740 if (speeds & 0x8) 4741 config.link_speed |= I40E_LINK_SPEED_20GB; 4742 if (speeds & 0x4) 4743 config.link_speed |= I40E_LINK_SPEED_10GB; 4744 if (speeds & 0x2) 4745 config.link_speed |= I40E_LINK_SPEED_1GB; 4746 if (speeds & 0x1) 4747 config.link_speed |= I40E_LINK_SPEED_100MB; 4748 4749 /* Do aq command & restart link */ 4750 aq_error = i40e_aq_set_phy_config(hw, &config, NULL); 4751 if (aq_error) { 4752 device_printf(dev, 4753 "%s: Error setting new phy config %d," 4754 " aq error: %d\n", __func__, aq_error, 4755 hw->aq.asq_last_status); 4756 return (EAGAIN); 4757 } 4758 4759 /* 4760 ** This seems a bit heavy handed, but we 4761 ** need to get a reinit on some devices 4762 */ 4763 IXL_PF_LOCK(pf); 4764 ixl_stop(pf); 4765 ixl_init_locked(pf); 4766 IXL_PF_UNLOCK(pf); 4767 4768 return (0); 4769} 4770 4771/* 4772** Control link advertise speed: 4773** Flags: 4774** 0x1 - advertise 100 Mb 4775** 0x2 - advertise 1G 4776** 0x4 - advertise 10G 4777** 0x8 - advertise 20G 4778** 4779** Does not work on 40G devices. 4780*/ 4781static int 4782ixl_set_advertise(SYSCTL_HANDLER_ARGS) 4783{ 4784 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4785 struct i40e_hw *hw = &pf->hw; 4786 device_t dev = pf->dev; 4787 int requested_ls = 0; 4788 int error = 0; 4789 4790 /* 4791 ** FW doesn't support changing advertised speed 4792 ** for 40G devices; speed is always 40G. 4793 */ 4794 if (i40e_is_40G_device(hw->device_id)) 4795 return (ENODEV); 4796 4797 /* Read in new mode */ 4798 requested_ls = pf->advertised_speed; 4799 error = sysctl_handle_int(oidp, &requested_ls, 0, req); 4800 if ((error) || (req->newptr == NULL)) 4801 return (error); 4802 /* Check for sane value */ 4803 if (requested_ls < 0x1 || requested_ls > 0xE) { 4804 device_printf(dev, "Invalid advertised speed; " 4805 "valid modes are 0x1 through 0xE\n"); 4806 return (EINVAL); 4807 } 4808 /* Then check for validity based on adapter type */ 4809 switch (hw->device_id) { 4810 case I40E_DEV_ID_10G_BASE_T: 4811 if (requested_ls & 0x8) { 4812 device_printf(dev, 4813 "20Gbs speed not supported on this device.\n"); 4814 return (EINVAL); 4815 } 4816 break; 4817 case I40E_DEV_ID_20G_KR2: 4818 if (requested_ls & 0x1) { 4819 device_printf(dev, 4820 "100Mbs speed not supported on this device.\n"); 4821 return (EINVAL); 4822 } 4823 break; 4824 default: 4825 if (requested_ls & ~0x6) { 4826 device_printf(dev, 4827 "Only 1/10Gbs speeds are supported on this device.\n"); 4828 return (EINVAL); 4829 } 4830 break; 4831 } 4832 4833 /* Exit if no change */ 4834 if (pf->advertised_speed == requested_ls) 4835 return (0); 4836 4837 error = ixl_set_advertised_speeds(pf, requested_ls); 4838 if (error) 4839 return (error); 4840 4841 pf->advertised_speed = requested_ls; 4842 ixl_update_link_status(pf); 4843 return (0); 4844} 4845 4846/* 4847** Get the width and transaction speed of 4848** the bus this adapter is plugged into. 4849*/ 4850static u16 4851ixl_get_bus_info(struct i40e_hw *hw, device_t dev) 4852{ 4853 u16 link; 4854 u32 offset; 4855 4856 4857 /* Get the PCI Express Capabilities offset */ 4858 pci_find_cap(dev, PCIY_EXPRESS, &offset); 4859 4860 /* ...and read the Link Status Register */ 4861 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 4862 4863 switch (link & I40E_PCI_LINK_WIDTH) { 4864 case I40E_PCI_LINK_WIDTH_1: 4865 hw->bus.width = i40e_bus_width_pcie_x1; 4866 break; 4867 case I40E_PCI_LINK_WIDTH_2: 4868 hw->bus.width = i40e_bus_width_pcie_x2; 4869 break; 4870 case I40E_PCI_LINK_WIDTH_4: 4871 hw->bus.width = i40e_bus_width_pcie_x4; 4872 break; 4873 case I40E_PCI_LINK_WIDTH_8: 4874 hw->bus.width = i40e_bus_width_pcie_x8; 4875 break; 4876 default: 4877 hw->bus.width = i40e_bus_width_unknown; 4878 break; 4879 } 4880 4881 switch (link & I40E_PCI_LINK_SPEED) { 4882 case I40E_PCI_LINK_SPEED_2500: 4883 hw->bus.speed = i40e_bus_speed_2500; 4884 break; 4885 case I40E_PCI_LINK_SPEED_5000: 4886 hw->bus.speed = i40e_bus_speed_5000; 4887 break; 4888 case I40E_PCI_LINK_SPEED_8000: 4889 hw->bus.speed = i40e_bus_speed_8000; 4890 break; 4891 default: 4892 hw->bus.speed = i40e_bus_speed_unknown; 4893 break; 4894 } 4895 4896 4897 device_printf(dev,"PCI Express Bus: Speed %s %s\n", 4898 ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s": 4899 (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s": 4900 (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"), 4901 (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" : 4902 (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" : 4903 (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" : 4904 ("Unknown")); 4905 4906 if ((hw->bus.width <= i40e_bus_width_pcie_x8) && 4907 (hw->bus.speed < i40e_bus_speed_8000)) { 4908 device_printf(dev, "PCI-Express bandwidth available" 4909 " for this device\n may be insufficient for" 4910 " optimal performance.\n"); 4911 device_printf(dev, "For expected performance a x8 " 4912 "PCIE Gen3 slot is required.\n"); 4913 } 4914 4915 return (link); 4916} 4917 4918static int 4919ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS) 4920{ 4921 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4922 struct i40e_hw *hw = &pf->hw; 4923 char buf[32]; 4924 4925 snprintf(buf, sizeof(buf), 4926 "f%d.%d a%d.%d n%02x.%02x e%08x", 4927 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 4928 hw->aq.api_maj_ver, hw->aq.api_min_ver, 4929 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 4930 IXL_NVM_VERSION_HI_SHIFT, 4931 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 4932 IXL_NVM_VERSION_LO_SHIFT, 4933 hw->nvm.eetrack); 4934 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4935} 4936 4937 4938#ifdef IXL_DEBUG_SYSCTL 4939static int 4940ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS) 4941{ 4942 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4943 struct i40e_hw *hw = &pf->hw; 4944 struct i40e_link_status link_status; 4945 char buf[512]; 4946 4947 enum i40e_status_code aq_error = 0; 4948 4949 aq_error = i40e_aq_get_link_info(hw, TRUE, &link_status, NULL); 4950 if (aq_error) { 4951 printf("i40e_aq_get_link_info() error %d\n", aq_error); 4952 return (EPERM); 4953 } 4954 4955 sprintf(buf, "\n" 4956 "PHY Type : %#04x\n" 4957 "Speed : %#04x\n" 4958 "Link info: %#04x\n" 4959 "AN info : %#04x\n" 4960 "Ext info : %#04x", 4961 link_status.phy_type, link_status.link_speed, 4962 link_status.link_info, link_status.an_info, 4963 link_status.ext_info); 4964 4965 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4966} 4967 4968static int 4969ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS) 4970{ 4971 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4972 struct i40e_hw *hw = &pf->hw; 4973 char buf[512]; 4974 enum i40e_status_code aq_error = 0; 4975 4976 struct i40e_aq_get_phy_abilities_resp abilities; 4977 4978 aq_error = i40e_aq_get_phy_capabilities(hw, 4979 TRUE, FALSE, &abilities, NULL); 4980 if (aq_error) { 4981 printf("i40e_aq_get_phy_capabilities() error %d\n", aq_error); 4982 return (EPERM); 4983 } 4984 4985 sprintf(buf, "\n" 4986 "PHY Type : %#010x\n" 4987 "Speed : %#04x\n" 4988 "Abilities: %#04x\n" 4989 "EEE cap : %#06x\n" 4990 "EEER reg : %#010x\n" 4991 "D3 Lpan : %#04x", 4992 abilities.phy_type, abilities.link_speed, 4993 abilities.abilities, abilities.eee_capability, 4994 abilities.eeer_val, abilities.d3_lpan); 4995 4996 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4997} 4998 4999static int 5000ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS) 5001{ 5002 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5003 struct ixl_vsi *vsi = &pf->vsi; 5004 struct ixl_mac_filter *f; 5005 char *buf, *buf_i; 5006 5007 int error = 0; 5008 int ftl_len = 0; 5009 int ftl_counter = 0; 5010 int buf_len = 0; 5011 int entry_len = 42; 5012 5013 SLIST_FOREACH(f, &vsi->ftl, next) { 5014 ftl_len++; 5015 } 5016 5017 if (ftl_len < 1) { 5018 sysctl_handle_string(oidp, "(none)", 6, req); 5019 return (0); 5020 } 5021 5022 buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2; 5023 buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT); 5024 5025 sprintf(buf_i++, "\n"); 5026 SLIST_FOREACH(f, &vsi->ftl, next) { 5027 sprintf(buf_i, 5028 MAC_FORMAT ", vlan %4d, flags %#06x", 5029 MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags); 5030 buf_i += entry_len; 5031 /* don't print '\n' for last entry */ 5032 if (++ftl_counter != ftl_len) { 5033 sprintf(buf_i, "\n"); 5034 buf_i++; 5035 } 5036 } 5037 5038 error = sysctl_handle_string(oidp, buf, strlen(buf), req); 5039 if (error) 5040 printf("sysctl error: %d\n", error); 5041 free(buf, M_DEVBUF); 5042 return error; 5043} 5044 5045#define IXL_SW_RES_SIZE 0x14 5046static int 5047ixl_res_alloc_cmp(const void *a, const void *b) 5048{ 5049 const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two; 5050 one = (const struct i40e_aqc_switch_resource_alloc_element_resp *)a; 5051 two = (const struct i40e_aqc_switch_resource_alloc_element_resp *)b; 5052 5053 return ((int)one->resource_type - (int)two->resource_type); 5054} 5055 5056static int 5057ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS) 5058{ 5059 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5060 struct i40e_hw *hw = &pf->hw; 5061 device_t dev = pf->dev; 5062 struct sbuf *buf; 5063 int error = 0; 5064 5065 u8 num_entries; 5066 struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE]; 5067 5068 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 5069 if (!buf) { 5070 device_printf(dev, "Could not allocate sbuf for output.\n"); 5071 return (ENOMEM); 5072 } 5073 5074 bzero(resp, sizeof(resp)); 5075 error = i40e_aq_get_switch_resource_alloc(hw, &num_entries, 5076 resp, 5077 IXL_SW_RES_SIZE, 5078 NULL); 5079 if (error) { 5080 device_printf(dev, 5081 "%s: get_switch_resource_alloc() error %d, aq error %d\n", 5082 __func__, error, hw->aq.asq_last_status); 5083 sbuf_delete(buf); 5084 return error; 5085 } 5086 5087 /* Sort entries by type for display */ 5088 qsort(resp, num_entries, 5089 sizeof(struct i40e_aqc_switch_resource_alloc_element_resp), 5090 &ixl_res_alloc_cmp); 5091 5092 sbuf_cat(buf, "\n"); 5093 sbuf_printf(buf, "# of entries: %d\n", num_entries); 5094 sbuf_printf(buf, 5095 "Type | Guaranteed | Total | Used | Un-allocated\n" 5096 " | (this) | (all) | (this) | (all) \n"); 5097 for (int i = 0; i < num_entries; i++) { 5098 sbuf_printf(buf, 5099 "%#4x | %10d %5d %6d %12d", 5100 resp[i].resource_type, 5101 resp[i].guaranteed, 5102 resp[i].total, 5103 resp[i].used, 5104 resp[i].total_unalloced); 5105 if (i < num_entries - 1) 5106 sbuf_cat(buf, "\n"); 5107 } 5108 5109 error = sbuf_finish(buf); 5110 if (error) { 5111 device_printf(dev, "Error finishing sbuf: %d\n", error); 5112 sbuf_delete(buf); 5113 return error; 5114 } 5115 5116 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 5117 if (error) 5118 device_printf(dev, "sysctl error: %d\n", error); 5119 sbuf_delete(buf); 5120 5121 return (error); 5122} 5123 5124/* 5125** Caller must init and delete sbuf; this function will clear and 5126** finish it for caller. 5127*/ 5128static char * 5129ixl_switch_element_string(struct sbuf *s, u16 seid, bool uplink) 5130{ 5131 sbuf_clear(s); 5132 5133 if (seid == 0 && uplink) 5134 sbuf_cat(s, "Network"); 5135 else if (seid == 0) 5136 sbuf_cat(s, "Host"); 5137 else if (seid == 1) 5138 sbuf_cat(s, "EMP"); 5139 else if (seid <= 5) 5140 sbuf_printf(s, "MAC %d", seid - 2); 5141 else if (seid <= 15) 5142 sbuf_cat(s, "Reserved"); 5143 else if (seid <= 31) 5144 sbuf_printf(s, "PF %d", seid - 16); 5145 else if (seid <= 159) 5146 sbuf_printf(s, "VF %d", seid - 32); 5147 else if (seid <= 287) 5148 sbuf_cat(s, "Reserved"); 5149 else if (seid <= 511) 5150 sbuf_cat(s, "Other"); // for other structures 5151 else if (seid <= 895) 5152 sbuf_printf(s, "VSI %d", seid - 512); 5153 else if (seid <= 1023) 5154 sbuf_printf(s, "Reserved"); 5155 else 5156 sbuf_cat(s, "Invalid"); 5157 5158 sbuf_finish(s); 5159 return sbuf_data(s); 5160} 5161 5162static int 5163ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS) 5164{ 5165 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5166 struct i40e_hw *hw = &pf->hw; 5167 device_t dev = pf->dev; 5168 struct sbuf *buf; 5169 struct sbuf *nmbuf; 5170 int error = 0; 5171 u8 aq_buf[I40E_AQ_LARGE_BUF]; 5172 5173 u16 next = 0; 5174 struct i40e_aqc_get_switch_config_resp *sw_config; 5175 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 5176 5177 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 5178 if (!buf) { 5179 device_printf(dev, "Could not allocate sbuf for sysctl output.\n"); 5180 return (ENOMEM); 5181 } 5182 5183 error = i40e_aq_get_switch_config(hw, sw_config, 5184 sizeof(aq_buf), &next, NULL); 5185 if (error) { 5186 device_printf(dev, 5187 "%s: aq_get_switch_config() error %d, aq error %d\n", 5188 __func__, error, hw->aq.asq_last_status); 5189 sbuf_delete(buf); 5190 return error; 5191 } 5192 5193 nmbuf = sbuf_new_auto(); 5194 if (!nmbuf) { 5195 device_printf(dev, "Could not allocate sbuf for name output.\n"); 5196 return (ENOMEM); 5197 } 5198 5199 sbuf_cat(buf, "\n"); 5200 // Assuming <= 255 elements in switch 5201 sbuf_printf(buf, "# of elements: %d\n", sw_config->header.num_reported); 5202 /* Exclude: 5203 ** Revision -- all elements are revision 1 for now 5204 */ 5205 sbuf_printf(buf, 5206 "SEID ( Name ) | Uplink | Downlink | Conn Type\n" 5207 " | | | (uplink)\n"); 5208 for (int i = 0; i < sw_config->header.num_reported; i++) { 5209 // "%4d (%8s) | %8s %8s %#8x", 5210 sbuf_printf(buf, "%4d", sw_config->element[i].seid); 5211 sbuf_cat(buf, " "); 5212 sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf, 5213 sw_config->element[i].seid, false)); 5214 sbuf_cat(buf, " | "); 5215 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5216 sw_config->element[i].uplink_seid, true)); 5217 sbuf_cat(buf, " "); 5218 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5219 sw_config->element[i].downlink_seid, false)); 5220 sbuf_cat(buf, " "); 5221 sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type); 5222 if (i < sw_config->header.num_reported - 1) 5223 sbuf_cat(buf, "\n"); 5224 } 5225 sbuf_delete(nmbuf); 5226 5227 error = sbuf_finish(buf); 5228 if (error) { 5229 device_printf(dev, "Error finishing sbuf: %d\n", error); 5230 sbuf_delete(buf); 5231 return error; 5232 } 5233 5234 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 5235 if (error) 5236 device_printf(dev, "sysctl error: %d\n", error); 5237 sbuf_delete(buf); 5238 5239 return (error); 5240} 5241#endif /* IXL_DEBUG_SYSCTL */ 5242 5243 5244#ifdef PCI_IOV 5245static int 5246ixl_vf_alloc_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5247{ 5248 struct i40e_hw *hw; 5249 struct ixl_vsi *vsi; 5250 struct i40e_vsi_context vsi_ctx; 5251 int i; 5252 uint16_t first_queue; 5253 enum i40e_status_code code; 5254 5255 hw = &pf->hw; 5256 vsi = &pf->vsi; 5257 5258 vsi_ctx.pf_num = hw->pf_id; 5259 vsi_ctx.uplink_seid = pf->veb_seid; 5260 vsi_ctx.connection_type = IXL_VSI_DATA_PORT; 5261 vsi_ctx.vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5262 vsi_ctx.flags = I40E_AQ_VSI_TYPE_VF; 5263 5264 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 5265 5266 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5267 vsi_ctx.info.switch_id = htole16(0); 5268 5269 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_SECURITY_VALID); 5270 vsi_ctx.info.sec_flags = 0; 5271 if (vf->vf_flags & VF_FLAG_MAC_ANTI_SPOOF) 5272 vsi_ctx.info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK; 5273 5274 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 5275 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5276 I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 5277 5278 vsi_ctx.info.valid_sections |= 5279 htole16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5280 vsi_ctx.info.mapping_flags = htole16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5281 first_queue = vsi->num_queues + vf->vf_num * IXLV_MAX_QUEUES; 5282 for (i = 0; i < IXLV_MAX_QUEUES; i++) 5283 vsi_ctx.info.queue_mapping[i] = htole16(first_queue + i); 5284 for (; i < nitems(vsi_ctx.info.queue_mapping); i++) 5285 vsi_ctx.info.queue_mapping[i] = htole16(I40E_AQ_VSI_QUEUE_MASK); 5286 5287 vsi_ctx.info.tc_mapping[0] = htole16( 5288 (0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5289 (1 << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5290 5291 code = i40e_aq_add_vsi(hw, &vsi_ctx, NULL); 5292 if (code != I40E_SUCCESS) 5293 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5294 vf->vsi.seid = vsi_ctx.seid; 5295 vf->vsi.vsi_num = vsi_ctx.vsi_number; 5296 vf->vsi.first_queue = first_queue; 5297 vf->vsi.num_queues = IXLV_MAX_QUEUES; 5298 5299 code = i40e_aq_get_vsi_params(hw, &vsi_ctx, NULL); 5300 if (code != I40E_SUCCESS) 5301 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5302 5303 code = i40e_aq_config_vsi_bw_limit(hw, vf->vsi.seid, 0, 0, NULL); 5304 if (code != I40E_SUCCESS) { 5305 device_printf(pf->dev, "Failed to disable BW limit: %d\n", 5306 ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5307 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5308 } 5309 5310 memcpy(&vf->vsi.info, &vsi_ctx.info, sizeof(vf->vsi.info)); 5311 return (0); 5312} 5313 5314static int 5315ixl_vf_setup_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5316{ 5317 struct i40e_hw *hw; 5318 int error; 5319 5320 hw = &pf->hw; 5321 5322 error = ixl_vf_alloc_vsi(pf, vf); 5323 if (error != 0) 5324 return (error); 5325 5326 vf->vsi.hw_filters_add = 0; 5327 vf->vsi.hw_filters_del = 0; 5328 ixl_add_filter(&vf->vsi, ixl_bcast_addr, IXL_VLAN_ANY); 5329 ixl_reconfigure_filters(&vf->vsi); 5330 5331 return (0); 5332} 5333 5334static void 5335ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum, 5336 uint32_t val) 5337{ 5338 uint32_t qtable; 5339 int index, shift; 5340 5341 /* 5342 * Two queues are mapped in a single register, so we have to do some 5343 * gymnastics to convert the queue number into a register index and 5344 * shift. 5345 */ 5346 index = qnum / 2; 5347 shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT; 5348 5349 qtable = rd32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num)); 5350 qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift); 5351 qtable |= val << shift; 5352 wr32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable); 5353} 5354 5355static void 5356ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf) 5357{ 5358 struct i40e_hw *hw; 5359 uint32_t qtable; 5360 int i; 5361 5362 hw = &pf->hw; 5363 5364 /* 5365 * Contiguous mappings aren't actually supported by the hardware, 5366 * so we have to use non-contiguous mappings. 5367 */ 5368 wr32(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num), 5369 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK); 5370 5371 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num), 5372 I40E_VPLAN_MAPENA_TXRX_ENA_MASK); 5373 5374 for (i = 0; i < vf->vsi.num_queues; i++) { 5375 qtable = (vf->vsi.first_queue + i) << 5376 I40E_VPLAN_QTABLE_QINDEX_SHIFT; 5377 5378 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), qtable); 5379 } 5380 5381 /* Map queues allocated to VF to its VSI. */ 5382 for (i = 0; i < vf->vsi.num_queues; i++) 5383 ixl_vf_map_vsi_queue(hw, vf, i, vf->vsi.first_queue + i); 5384 5385 /* Set rest of VSI queues as unused. */ 5386 for (; i < IXL_MAX_VSI_QUEUES; i++) 5387 ixl_vf_map_vsi_queue(hw, vf, i, 5388 I40E_VSILAN_QTABLE_QINDEX_0_MASK); 5389 5390 ixl_flush(hw); 5391} 5392 5393static void 5394ixl_vf_vsi_release(struct ixl_pf *pf, struct ixl_vsi *vsi) 5395{ 5396 struct i40e_hw *hw; 5397 5398 hw = &pf->hw; 5399 5400 if (vsi->seid == 0) 5401 return; 5402 5403 i40e_aq_delete_element(hw, vsi->seid, NULL); 5404} 5405 5406static void 5407ixl_vf_disable_queue_intr(struct i40e_hw *hw, uint32_t vfint_reg) 5408{ 5409 5410 wr32(hw, vfint_reg, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); 5411 ixl_flush(hw); 5412} 5413 5414static void 5415ixl_vf_unregister_intr(struct i40e_hw *hw, uint32_t vpint_reg) 5416{ 5417 5418 wr32(hw, vpint_reg, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | 5419 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 5420 ixl_flush(hw); 5421} 5422 5423static void 5424ixl_vf_release_resources(struct ixl_pf *pf, struct ixl_vf *vf) 5425{ 5426 struct i40e_hw *hw; 5427 uint32_t vfint_reg, vpint_reg; 5428 int i; 5429 5430 hw = &pf->hw; 5431 5432 ixl_vf_vsi_release(pf, &vf->vsi); 5433 5434 /* Index 0 has a special register. */ 5435 ixl_vf_disable_queue_intr(hw, I40E_VFINT_DYN_CTL0(vf->vf_num)); 5436 5437 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5438 vfint_reg = IXL_VFINT_DYN_CTLN_REG(hw, i , vf->vf_num); 5439 ixl_vf_disable_queue_intr(hw, vfint_reg); 5440 } 5441 5442 /* Index 0 has a special register. */ 5443 ixl_vf_unregister_intr(hw, I40E_VPINT_LNKLST0(vf->vf_num)); 5444 5445 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5446 vpint_reg = IXL_VPINT_LNKLSTN_REG(hw, i, vf->vf_num); 5447 ixl_vf_unregister_intr(hw, vpint_reg); 5448 } 5449 5450 vf->vsi.num_queues = 0; 5451} 5452 5453static int 5454ixl_flush_pcie(struct ixl_pf *pf, struct ixl_vf *vf) 5455{ 5456 struct i40e_hw *hw; 5457 int i; 5458 uint16_t global_vf_num; 5459 uint32_t ciad; 5460 5461 hw = &pf->hw; 5462 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5463 5464 wr32(hw, I40E_PF_PCI_CIAA, IXL_PF_PCI_CIAA_VF_DEVICE_STATUS | 5465 (global_vf_num << I40E_PF_PCI_CIAA_VF_NUM_SHIFT)); 5466 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5467 ciad = rd32(hw, I40E_PF_PCI_CIAD); 5468 if ((ciad & IXL_PF_PCI_CIAD_VF_TRANS_PENDING_MASK) == 0) 5469 return (0); 5470 DELAY(1); 5471 } 5472 5473 return (ETIMEDOUT); 5474} 5475 5476static void 5477ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5478{ 5479 struct i40e_hw *hw; 5480 uint32_t vfrtrig; 5481 5482 hw = &pf->hw; 5483 5484 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5485 vfrtrig |= I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5486 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5487 ixl_flush(hw); 5488 5489 ixl_reinit_vf(pf, vf); 5490} 5491 5492static void 5493ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5494{ 5495 struct i40e_hw *hw; 5496 uint32_t vfrstat, vfrtrig; 5497 int i, error; 5498 5499 hw = &pf->hw; 5500 5501 error = ixl_flush_pcie(pf, vf); 5502 if (error != 0) 5503 device_printf(pf->dev, 5504 "Timed out waiting for PCIe activity to stop on VF-%d\n", 5505 vf->vf_num); 5506 5507 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5508 DELAY(10); 5509 5510 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num)); 5511 if (vfrstat & I40E_VPGEN_VFRSTAT_VFRD_MASK) 5512 break; 5513 } 5514 5515 if (i == IXL_VF_RESET_TIMEOUT) 5516 device_printf(pf->dev, "VF %d failed to reset\n", vf->vf_num); 5517 5518 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_COMPLETED); 5519 5520 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5521 vfrtrig &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5522 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5523 5524 if (vf->vsi.seid != 0) 5525 ixl_disable_rings(&vf->vsi); 5526 5527 ixl_vf_release_resources(pf, vf); 5528 ixl_vf_setup_vsi(pf, vf); 5529 ixl_vf_map_queues(pf, vf); 5530 5531 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_VFACTIVE); 5532 ixl_flush(hw); 5533} 5534 5535static const char * 5536ixl_vc_opcode_str(uint16_t op) 5537{ 5538 5539 switch (op) { 5540 case I40E_VIRTCHNL_OP_VERSION: 5541 return ("VERSION"); 5542 case I40E_VIRTCHNL_OP_RESET_VF: 5543 return ("RESET_VF"); 5544 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 5545 return ("GET_VF_RESOURCES"); 5546 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 5547 return ("CONFIG_TX_QUEUE"); 5548 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 5549 return ("CONFIG_RX_QUEUE"); 5550 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 5551 return ("CONFIG_VSI_QUEUES"); 5552 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 5553 return ("CONFIG_IRQ_MAP"); 5554 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 5555 return ("ENABLE_QUEUES"); 5556 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 5557 return ("DISABLE_QUEUES"); 5558 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 5559 return ("ADD_ETHER_ADDRESS"); 5560 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 5561 return ("DEL_ETHER_ADDRESS"); 5562 case I40E_VIRTCHNL_OP_ADD_VLAN: 5563 return ("ADD_VLAN"); 5564 case I40E_VIRTCHNL_OP_DEL_VLAN: 5565 return ("DEL_VLAN"); 5566 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 5567 return ("CONFIG_PROMISCUOUS_MODE"); 5568 case I40E_VIRTCHNL_OP_GET_STATS: 5569 return ("GET_STATS"); 5570 case I40E_VIRTCHNL_OP_FCOE: 5571 return ("FCOE"); 5572 case I40E_VIRTCHNL_OP_EVENT: 5573 return ("EVENT"); 5574 default: 5575 return ("UNKNOWN"); 5576 } 5577} 5578 5579static int 5580ixl_vc_opcode_level(uint16_t opcode) 5581{ 5582 5583 switch (opcode) { 5584 case I40E_VIRTCHNL_OP_GET_STATS: 5585 return (10); 5586 default: 5587 return (5); 5588 } 5589} 5590 5591static void 5592ixl_send_vf_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5593 enum i40e_status_code status, void *msg, uint16_t len) 5594{ 5595 struct i40e_hw *hw; 5596 int global_vf_id; 5597 5598 hw = &pf->hw; 5599 global_vf_id = hw->func_caps.vf_base_id + vf->vf_num; 5600 5601 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(op), 5602 "Sending msg (op=%s[%d], status=%d) to VF-%d\n", 5603 ixl_vc_opcode_str(op), op, status, vf->vf_num); 5604 5605 i40e_aq_send_msg_to_vf(hw, global_vf_id, op, status, msg, len, NULL); 5606} 5607 5608static void 5609ixl_send_vf_ack(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op) 5610{ 5611 5612 ixl_send_vf_msg(pf, vf, op, I40E_SUCCESS, NULL, 0); 5613} 5614 5615static void 5616ixl_send_vf_nack_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5617 enum i40e_status_code status, const char *file, int line) 5618{ 5619 5620 I40E_VC_DEBUG(pf, 1, 5621 "Sending NACK (op=%s[%d], err=%d) to VF-%d from %s:%d\n", 5622 ixl_vc_opcode_str(op), op, status, vf->vf_num, file, line); 5623 ixl_send_vf_msg(pf, vf, op, status, NULL, 0); 5624} 5625 5626static void 5627ixl_vf_version_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5628 uint16_t msg_size) 5629{ 5630 struct i40e_virtchnl_version_info reply; 5631 5632 if (msg_size != sizeof(struct i40e_virtchnl_version_info)) { 5633 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_VERSION, 5634 I40E_ERR_PARAM); 5635 return; 5636 } 5637 5638 reply.major = I40E_VIRTCHNL_VERSION_MAJOR; 5639 reply.minor = I40E_VIRTCHNL_VERSION_MINOR; 5640 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_VERSION, I40E_SUCCESS, &reply, 5641 sizeof(reply)); 5642} 5643 5644static void 5645ixl_vf_reset_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5646 uint16_t msg_size) 5647{ 5648 5649 if (msg_size != 0) { 5650 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_RESET_VF, 5651 I40E_ERR_PARAM); 5652 return; 5653 } 5654 5655 ixl_reset_vf(pf, vf); 5656 5657 /* No response to a reset message. */ 5658} 5659 5660static void 5661ixl_vf_get_resources_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5662 uint16_t msg_size) 5663{ 5664 struct i40e_virtchnl_vf_resource reply; 5665 5666 if (msg_size != 0) { 5667 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5668 I40E_ERR_PARAM); 5669 return; 5670 } 5671 5672 bzero(&reply, sizeof(reply)); 5673 5674 reply.vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2; 5675 5676 reply.num_vsis = 1; 5677 reply.num_queue_pairs = vf->vsi.num_queues; 5678 reply.max_vectors = pf->hw.func_caps.num_msix_vectors_vf; 5679 reply.vsi_res[0].vsi_id = vf->vsi.vsi_num; 5680 reply.vsi_res[0].vsi_type = I40E_VSI_SRIOV; 5681 reply.vsi_res[0].num_queue_pairs = vf->vsi.num_queues; 5682 memcpy(reply.vsi_res[0].default_mac_addr, vf->mac, ETHER_ADDR_LEN); 5683 5684 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5685 I40E_SUCCESS, &reply, sizeof(reply)); 5686} 5687 5688static int 5689ixl_vf_config_tx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5690 struct i40e_virtchnl_txq_info *info) 5691{ 5692 struct i40e_hw *hw; 5693 struct i40e_hmc_obj_txq txq; 5694 uint16_t global_queue_num, global_vf_num; 5695 enum i40e_status_code status; 5696 uint32_t qtx_ctl; 5697 5698 hw = &pf->hw; 5699 global_queue_num = vf->vsi.first_queue + info->queue_id; 5700 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5701 bzero(&txq, sizeof(txq)); 5702 5703 status = i40e_clear_lan_tx_queue_context(hw, global_queue_num); 5704 if (status != I40E_SUCCESS) 5705 return (EINVAL); 5706 5707 txq.base = info->dma_ring_addr / IXL_TX_CTX_BASE_UNITS; 5708 5709 txq.head_wb_ena = info->headwb_enabled; 5710 txq.head_wb_addr = info->dma_headwb_addr; 5711 txq.qlen = info->ring_len; 5712 txq.rdylist = le16_to_cpu(vf->vsi.info.qs_handle[0]); 5713 txq.rdylist_act = 0; 5714 5715 status = i40e_set_lan_tx_queue_context(hw, global_queue_num, &txq); 5716 if (status != I40E_SUCCESS) 5717 return (EINVAL); 5718 5719 qtx_ctl = I40E_QTX_CTL_VF_QUEUE | 5720 (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) | 5721 (global_vf_num << I40E_QTX_CTL_VFVM_INDX_SHIFT); 5722 wr32(hw, I40E_QTX_CTL(global_queue_num), qtx_ctl); 5723 ixl_flush(hw); 5724 5725 return (0); 5726} 5727 5728static int 5729ixl_vf_config_rx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5730 struct i40e_virtchnl_rxq_info *info) 5731{ 5732 struct i40e_hw *hw; 5733 struct i40e_hmc_obj_rxq rxq; 5734 uint16_t global_queue_num; 5735 enum i40e_status_code status; 5736 5737 hw = &pf->hw; 5738 global_queue_num = vf->vsi.first_queue + info->queue_id; 5739 bzero(&rxq, sizeof(rxq)); 5740 5741 if (info->databuffer_size > IXL_VF_MAX_BUFFER) 5742 return (EINVAL); 5743 5744 if (info->max_pkt_size > IXL_VF_MAX_FRAME || 5745 info->max_pkt_size < ETHER_MIN_LEN) 5746 return (EINVAL); 5747 5748 if (info->splithdr_enabled) { 5749 if (info->hdr_size > IXL_VF_MAX_HDR_BUFFER) 5750 return (EINVAL); 5751 5752 rxq.hsplit_0 = info->rx_split_pos & 5753 (I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 | 5754 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP | 5755 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP | 5756 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP); 5757 rxq.hbuff = info->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT; 5758 5759 rxq.dtype = 2; 5760 } 5761 5762 status = i40e_clear_lan_rx_queue_context(hw, global_queue_num); 5763 if (status != I40E_SUCCESS) 5764 return (EINVAL); 5765 5766 rxq.base = info->dma_ring_addr / IXL_RX_CTX_BASE_UNITS; 5767 rxq.qlen = info->ring_len; 5768 5769 rxq.dbuff = info->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT; 5770 5771 rxq.dsize = 1; 5772 rxq.crcstrip = 1; 5773 rxq.l2tsel = 1; 5774 5775 rxq.rxmax = info->max_pkt_size; 5776 rxq.tphrdesc_ena = 1; 5777 rxq.tphwdesc_ena = 1; 5778 rxq.tphdata_ena = 1; 5779 rxq.tphhead_ena = 1; 5780 rxq.lrxqthresh = 2; 5781 rxq.prefena = 1; 5782 5783 status = i40e_set_lan_rx_queue_context(hw, global_queue_num, &rxq); 5784 if (status != I40E_SUCCESS) 5785 return (EINVAL); 5786 5787 return (0); 5788} 5789 5790static void 5791ixl_vf_config_vsi_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5792 uint16_t msg_size) 5793{ 5794 struct i40e_virtchnl_vsi_queue_config_info *info; 5795 struct i40e_virtchnl_queue_pair_info *pair; 5796 int i; 5797 5798 if (msg_size < sizeof(*info)) { 5799 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5800 I40E_ERR_PARAM); 5801 return; 5802 } 5803 5804 info = msg; 5805 if (info->num_queue_pairs == 0) { 5806 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5807 I40E_ERR_PARAM); 5808 return; 5809 } 5810 5811 if (msg_size != sizeof(*info) + info->num_queue_pairs * sizeof(*pair)) { 5812 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5813 I40E_ERR_PARAM); 5814 return; 5815 } 5816 5817 if (info->vsi_id != vf->vsi.vsi_num) { 5818 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5819 I40E_ERR_PARAM); 5820 return; 5821 } 5822 5823 for (i = 0; i < info->num_queue_pairs; i++) { 5824 pair = &info->qpair[i]; 5825 5826 if (pair->txq.vsi_id != vf->vsi.vsi_num || 5827 pair->rxq.vsi_id != vf->vsi.vsi_num || 5828 pair->txq.queue_id != pair->rxq.queue_id || 5829 pair->txq.queue_id >= vf->vsi.num_queues) { 5830 5831 i40e_send_vf_nack(pf, vf, 5832 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5833 return; 5834 } 5835 5836 if (ixl_vf_config_tx_queue(pf, vf, &pair->txq) != 0) { 5837 i40e_send_vf_nack(pf, vf, 5838 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5839 return; 5840 } 5841 5842 if (ixl_vf_config_rx_queue(pf, vf, &pair->rxq) != 0) { 5843 i40e_send_vf_nack(pf, vf, 5844 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5845 return; 5846 } 5847 } 5848 5849 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES); 5850} 5851 5852static void 5853ixl_vf_set_qctl(struct ixl_pf *pf, 5854 const struct i40e_virtchnl_vector_map *vector, 5855 enum i40e_queue_type cur_type, uint16_t cur_queue, 5856 enum i40e_queue_type *last_type, uint16_t *last_queue) 5857{ 5858 uint32_t offset, qctl; 5859 uint16_t itr_indx; 5860 5861 if (cur_type == I40E_QUEUE_TYPE_RX) { 5862 offset = I40E_QINT_RQCTL(cur_queue); 5863 itr_indx = vector->rxitr_idx; 5864 } else { 5865 offset = I40E_QINT_TQCTL(cur_queue); 5866 itr_indx = vector->txitr_idx; 5867 } 5868 5869 qctl = htole32((vector->vector_id << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5870 (*last_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5871 (*last_queue << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5872 I40E_QINT_RQCTL_CAUSE_ENA_MASK | 5873 (itr_indx << I40E_QINT_RQCTL_ITR_INDX_SHIFT)); 5874 5875 wr32(&pf->hw, offset, qctl); 5876 5877 *last_type = cur_type; 5878 *last_queue = cur_queue; 5879} 5880 5881static void 5882ixl_vf_config_vector(struct ixl_pf *pf, struct ixl_vf *vf, 5883 const struct i40e_virtchnl_vector_map *vector) 5884{ 5885 struct i40e_hw *hw; 5886 u_int qindex; 5887 enum i40e_queue_type type, last_type; 5888 uint32_t lnklst_reg; 5889 uint16_t rxq_map, txq_map, cur_queue, last_queue; 5890 5891 hw = &pf->hw; 5892 5893 rxq_map = vector->rxq_map; 5894 txq_map = vector->txq_map; 5895 5896 last_queue = IXL_END_OF_INTR_LNKLST; 5897 last_type = I40E_QUEUE_TYPE_RX; 5898 5899 /* 5900 * The datasheet says to optimize performance, RX queues and TX queues 5901 * should be interleaved in the interrupt linked list, so we process 5902 * both at once here. 5903 */ 5904 while ((rxq_map != 0) || (txq_map != 0)) { 5905 if (txq_map != 0) { 5906 qindex = ffs(txq_map) - 1; 5907 type = I40E_QUEUE_TYPE_TX; 5908 cur_queue = vf->vsi.first_queue + qindex; 5909 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5910 &last_type, &last_queue); 5911 txq_map &= ~(1 << qindex); 5912 } 5913 5914 if (rxq_map != 0) { 5915 qindex = ffs(rxq_map) - 1; 5916 type = I40E_QUEUE_TYPE_RX; 5917 cur_queue = vf->vsi.first_queue + qindex; 5918 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5919 &last_type, &last_queue); 5920 rxq_map &= ~(1 << qindex); 5921 } 5922 } 5923 5924 if (vector->vector_id == 0) 5925 lnklst_reg = I40E_VPINT_LNKLST0(vf->vf_num); 5926 else 5927 lnklst_reg = IXL_VPINT_LNKLSTN_REG(hw, vector->vector_id, 5928 vf->vf_num); 5929 wr32(hw, lnklst_reg, 5930 (last_queue << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5931 (last_type << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 5932 5933 ixl_flush(hw); 5934} 5935 5936static void 5937ixl_vf_config_irq_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5938 uint16_t msg_size) 5939{ 5940 struct i40e_virtchnl_irq_map_info *map; 5941 struct i40e_virtchnl_vector_map *vector; 5942 struct i40e_hw *hw; 5943 int i, largest_txq, largest_rxq; 5944 5945 hw = &pf->hw; 5946 5947 if (msg_size < sizeof(*map)) { 5948 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5949 I40E_ERR_PARAM); 5950 return; 5951 } 5952 5953 map = msg; 5954 if (map->num_vectors == 0) { 5955 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5956 I40E_ERR_PARAM); 5957 return; 5958 } 5959 5960 if (msg_size != sizeof(*map) + map->num_vectors * sizeof(*vector)) { 5961 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5962 I40E_ERR_PARAM); 5963 return; 5964 } 5965 5966 for (i = 0; i < map->num_vectors; i++) { 5967 vector = &map->vecmap[i]; 5968 5969 if ((vector->vector_id >= hw->func_caps.num_msix_vectors_vf) || 5970 vector->vsi_id != vf->vsi.vsi_num) { 5971 i40e_send_vf_nack(pf, vf, 5972 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, I40E_ERR_PARAM); 5973 return; 5974 } 5975 5976 if (vector->rxq_map != 0) { 5977 largest_rxq = fls(vector->rxq_map) - 1; 5978 if (largest_rxq >= vf->vsi.num_queues) { 5979 i40e_send_vf_nack(pf, vf, 5980 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5981 I40E_ERR_PARAM); 5982 return; 5983 } 5984 } 5985 5986 if (vector->txq_map != 0) { 5987 largest_txq = fls(vector->txq_map) - 1; 5988 if (largest_txq >= vf->vsi.num_queues) { 5989 i40e_send_vf_nack(pf, vf, 5990 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5991 I40E_ERR_PARAM); 5992 return; 5993 } 5994 } 5995 5996 if (vector->rxitr_idx > IXL_MAX_ITR_IDX || 5997 vector->txitr_idx > IXL_MAX_ITR_IDX) { 5998 i40e_send_vf_nack(pf, vf, 5999 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 6000 I40E_ERR_PARAM); 6001 return; 6002 } 6003 6004 ixl_vf_config_vector(pf, vf, vector); 6005 } 6006 6007 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP); 6008} 6009 6010static void 6011ixl_vf_enable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6012 uint16_t msg_size) 6013{ 6014 struct i40e_virtchnl_queue_select *select; 6015 int error; 6016 6017 if (msg_size != sizeof(*select)) { 6018 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6019 I40E_ERR_PARAM); 6020 return; 6021 } 6022 6023 select = msg; 6024 if (select->vsi_id != vf->vsi.vsi_num || 6025 select->rx_queues == 0 || select->tx_queues == 0) { 6026 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6027 I40E_ERR_PARAM); 6028 return; 6029 } 6030 6031 error = ixl_enable_rings(&vf->vsi); 6032 if (error) { 6033 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6034 I40E_ERR_TIMEOUT); 6035 return; 6036 } 6037 6038 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES); 6039} 6040 6041static void 6042ixl_vf_disable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6043 void *msg, uint16_t msg_size) 6044{ 6045 struct i40e_virtchnl_queue_select *select; 6046 int error; 6047 6048 if (msg_size != sizeof(*select)) { 6049 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6050 I40E_ERR_PARAM); 6051 return; 6052 } 6053 6054 select = msg; 6055 if (select->vsi_id != vf->vsi.vsi_num || 6056 select->rx_queues == 0 || select->tx_queues == 0) { 6057 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6058 I40E_ERR_PARAM); 6059 return; 6060 } 6061 6062 error = ixl_disable_rings(&vf->vsi); 6063 if (error) { 6064 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6065 I40E_ERR_TIMEOUT); 6066 return; 6067 } 6068 6069 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES); 6070} 6071 6072static boolean_t 6073ixl_zero_mac(const uint8_t *addr) 6074{ 6075 uint8_t zero[ETHER_ADDR_LEN] = {0, 0, 0, 0, 0, 0}; 6076 6077 return (cmp_etheraddr(addr, zero)); 6078} 6079 6080static boolean_t 6081ixl_bcast_mac(const uint8_t *addr) 6082{ 6083 6084 return (cmp_etheraddr(addr, ixl_bcast_addr)); 6085} 6086 6087static int 6088ixl_vf_mac_valid(struct ixl_vf *vf, const uint8_t *addr) 6089{ 6090 6091 if (ixl_zero_mac(addr) || ixl_bcast_mac(addr)) 6092 return (EINVAL); 6093 6094 /* 6095 * If the VF is not allowed to change its MAC address, don't let it 6096 * set a MAC filter for an address that is not a multicast address and 6097 * is not its assigned MAC. 6098 */ 6099 if (!(vf->vf_flags & VF_FLAG_SET_MAC_CAP) && 6100 !(ETHER_IS_MULTICAST(addr) || cmp_etheraddr(addr, vf->mac))) 6101 return (EPERM); 6102 6103 return (0); 6104} 6105 6106static void 6107ixl_vf_add_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6108 uint16_t msg_size) 6109{ 6110 struct i40e_virtchnl_ether_addr_list *addr_list; 6111 struct i40e_virtchnl_ether_addr *addr; 6112 struct ixl_vsi *vsi; 6113 int i; 6114 size_t expected_size; 6115 6116 vsi = &vf->vsi; 6117 6118 if (msg_size < sizeof(*addr_list)) { 6119 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6120 I40E_ERR_PARAM); 6121 return; 6122 } 6123 6124 addr_list = msg; 6125 expected_size = sizeof(*addr_list) + 6126 addr_list->num_elements * sizeof(*addr); 6127 6128 if (addr_list->num_elements == 0 || 6129 addr_list->vsi_id != vsi->vsi_num || 6130 msg_size != expected_size) { 6131 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6132 I40E_ERR_PARAM); 6133 return; 6134 } 6135 6136 for (i = 0; i < addr_list->num_elements; i++) { 6137 if (ixl_vf_mac_valid(vf, addr_list->list[i].addr) != 0) { 6138 i40e_send_vf_nack(pf, vf, 6139 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6140 return; 6141 } 6142 } 6143 6144 for (i = 0; i < addr_list->num_elements; i++) { 6145 addr = &addr_list->list[i]; 6146 ixl_add_filter(vsi, addr->addr, IXL_VLAN_ANY); 6147 } 6148 6149 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS); 6150} 6151 6152static void 6153ixl_vf_del_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6154 uint16_t msg_size) 6155{ 6156 struct i40e_virtchnl_ether_addr_list *addr_list; 6157 struct i40e_virtchnl_ether_addr *addr; 6158 size_t expected_size; 6159 int i; 6160 6161 if (msg_size < sizeof(*addr_list)) { 6162 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6163 I40E_ERR_PARAM); 6164 return; 6165 } 6166 6167 addr_list = msg; 6168 expected_size = sizeof(*addr_list) + 6169 addr_list->num_elements * sizeof(*addr); 6170 6171 if (addr_list->num_elements == 0 || 6172 addr_list->vsi_id != vf->vsi.vsi_num || 6173 msg_size != expected_size) { 6174 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6175 I40E_ERR_PARAM); 6176 return; 6177 } 6178 6179 for (i = 0; i < addr_list->num_elements; i++) { 6180 addr = &addr_list->list[i]; 6181 if (ixl_zero_mac(addr->addr) || ixl_bcast_mac(addr->addr)) { 6182 i40e_send_vf_nack(pf, vf, 6183 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6184 return; 6185 } 6186 } 6187 6188 for (i = 0; i < addr_list->num_elements; i++) { 6189 addr = &addr_list->list[i]; 6190 ixl_del_filter(&vf->vsi, addr->addr, IXL_VLAN_ANY); 6191 } 6192 6193 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS); 6194} 6195 6196static enum i40e_status_code 6197ixl_vf_enable_vlan_strip(struct ixl_pf *pf, struct ixl_vf *vf) 6198{ 6199 struct i40e_vsi_context vsi_ctx; 6200 6201 vsi_ctx.seid = vf->vsi.seid; 6202 6203 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 6204 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 6205 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 6206 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 6207 return (i40e_aq_update_vsi_params(&pf->hw, &vsi_ctx, NULL)); 6208} 6209 6210static void 6211ixl_vf_add_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6212 uint16_t msg_size) 6213{ 6214 struct i40e_virtchnl_vlan_filter_list *filter_list; 6215 enum i40e_status_code code; 6216 size_t expected_size; 6217 int i; 6218 6219 if (msg_size < sizeof(*filter_list)) { 6220 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6221 I40E_ERR_PARAM); 6222 return; 6223 } 6224 6225 filter_list = msg; 6226 expected_size = sizeof(*filter_list) + 6227 filter_list->num_elements * sizeof(uint16_t); 6228 if (filter_list->num_elements == 0 || 6229 filter_list->vsi_id != vf->vsi.vsi_num || 6230 msg_size != expected_size) { 6231 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6232 I40E_ERR_PARAM); 6233 return; 6234 } 6235 6236 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6237 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6238 I40E_ERR_PARAM); 6239 return; 6240 } 6241 6242 for (i = 0; i < filter_list->num_elements; i++) { 6243 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6244 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6245 I40E_ERR_PARAM); 6246 return; 6247 } 6248 } 6249 6250 code = ixl_vf_enable_vlan_strip(pf, vf); 6251 if (code != I40E_SUCCESS) { 6252 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6253 I40E_ERR_PARAM); 6254 } 6255 6256 for (i = 0; i < filter_list->num_elements; i++) 6257 ixl_add_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6258 6259 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN); 6260} 6261 6262static void 6263ixl_vf_del_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6264 uint16_t msg_size) 6265{ 6266 struct i40e_virtchnl_vlan_filter_list *filter_list; 6267 int i; 6268 size_t expected_size; 6269 6270 if (msg_size < sizeof(*filter_list)) { 6271 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6272 I40E_ERR_PARAM); 6273 return; 6274 } 6275 6276 filter_list = msg; 6277 expected_size = sizeof(*filter_list) + 6278 filter_list->num_elements * sizeof(uint16_t); 6279 if (filter_list->num_elements == 0 || 6280 filter_list->vsi_id != vf->vsi.vsi_num || 6281 msg_size != expected_size) { 6282 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6283 I40E_ERR_PARAM); 6284 return; 6285 } 6286 6287 for (i = 0; i < filter_list->num_elements; i++) { 6288 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6289 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6290 I40E_ERR_PARAM); 6291 return; 6292 } 6293 } 6294 6295 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6296 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6297 I40E_ERR_PARAM); 6298 return; 6299 } 6300 6301 for (i = 0; i < filter_list->num_elements; i++) 6302 ixl_del_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6303 6304 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN); 6305} 6306 6307static void 6308ixl_vf_config_promisc_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6309 void *msg, uint16_t msg_size) 6310{ 6311 struct i40e_virtchnl_promisc_info *info; 6312 enum i40e_status_code code; 6313 6314 if (msg_size != sizeof(*info)) { 6315 i40e_send_vf_nack(pf, vf, 6316 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6317 return; 6318 } 6319 6320 if (!vf->vf_flags & VF_FLAG_PROMISC_CAP) { 6321 i40e_send_vf_nack(pf, vf, 6322 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6323 return; 6324 } 6325 6326 info = msg; 6327 if (info->vsi_id != vf->vsi.vsi_num) { 6328 i40e_send_vf_nack(pf, vf, 6329 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6330 return; 6331 } 6332 6333 code = i40e_aq_set_vsi_unicast_promiscuous(&pf->hw, info->vsi_id, 6334 info->flags & I40E_FLAG_VF_UNICAST_PROMISC, NULL); 6335 if (code != I40E_SUCCESS) { 6336 i40e_send_vf_nack(pf, vf, 6337 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6338 return; 6339 } 6340 6341 code = i40e_aq_set_vsi_multicast_promiscuous(&pf->hw, info->vsi_id, 6342 info->flags & I40E_FLAG_VF_MULTICAST_PROMISC, NULL); 6343 if (code != I40E_SUCCESS) { 6344 i40e_send_vf_nack(pf, vf, 6345 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6346 return; 6347 } 6348 6349 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE); 6350} 6351 6352static void 6353ixl_vf_get_stats_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6354 uint16_t msg_size) 6355{ 6356 struct i40e_virtchnl_queue_select *queue; 6357 6358 if (msg_size != sizeof(*queue)) { 6359 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6360 I40E_ERR_PARAM); 6361 return; 6362 } 6363 6364 queue = msg; 6365 if (queue->vsi_id != vf->vsi.vsi_num) { 6366 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6367 I40E_ERR_PARAM); 6368 return; 6369 } 6370 6371 ixl_update_eth_stats(&vf->vsi); 6372 6373 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6374 I40E_SUCCESS, &vf->vsi.eth_stats, sizeof(vf->vsi.eth_stats)); 6375} 6376 6377static void 6378ixl_handle_vf_msg(struct ixl_pf *pf, struct i40e_arq_event_info *event) 6379{ 6380 struct ixl_vf *vf; 6381 void *msg; 6382 uint16_t vf_num, msg_size; 6383 uint32_t opcode; 6384 6385 vf_num = le16toh(event->desc.retval) - pf->hw.func_caps.vf_base_id; 6386 opcode = le32toh(event->desc.cookie_high); 6387 6388 if (vf_num >= pf->num_vfs) { 6389 device_printf(pf->dev, "Got msg from illegal VF: %d\n", vf_num); 6390 return; 6391 } 6392 6393 vf = &pf->vfs[vf_num]; 6394 msg = event->msg_buf; 6395 msg_size = event->msg_len; 6396 6397 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(opcode), 6398 "Got msg %s(%d) from VF-%d of size %d\n", 6399 ixl_vc_opcode_str(opcode), opcode, vf_num, msg_size); 6400 6401 switch (opcode) { 6402 case I40E_VIRTCHNL_OP_VERSION: 6403 ixl_vf_version_msg(pf, vf, msg, msg_size); 6404 break; 6405 case I40E_VIRTCHNL_OP_RESET_VF: 6406 ixl_vf_reset_msg(pf, vf, msg, msg_size); 6407 break; 6408 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 6409 ixl_vf_get_resources_msg(pf, vf, msg, msg_size); 6410 break; 6411 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 6412 ixl_vf_config_vsi_msg(pf, vf, msg, msg_size); 6413 break; 6414 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 6415 ixl_vf_config_irq_msg(pf, vf, msg, msg_size); 6416 break; 6417 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 6418 ixl_vf_enable_queues_msg(pf, vf, msg, msg_size); 6419 break; 6420 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 6421 ixl_vf_disable_queues_msg(pf, vf, msg, msg_size); 6422 break; 6423 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 6424 ixl_vf_add_mac_msg(pf, vf, msg, msg_size); 6425 break; 6426 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 6427 ixl_vf_del_mac_msg(pf, vf, msg, msg_size); 6428 break; 6429 case I40E_VIRTCHNL_OP_ADD_VLAN: 6430 ixl_vf_add_vlan_msg(pf, vf, msg, msg_size); 6431 break; 6432 case I40E_VIRTCHNL_OP_DEL_VLAN: 6433 ixl_vf_del_vlan_msg(pf, vf, msg, msg_size); 6434 break; 6435 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 6436 ixl_vf_config_promisc_msg(pf, vf, msg, msg_size); 6437 break; 6438 case I40E_VIRTCHNL_OP_GET_STATS: 6439 ixl_vf_get_stats_msg(pf, vf, msg, msg_size); 6440 break; 6441 6442 /* These two opcodes have been superseded by CONFIG_VSI_QUEUES. */ 6443 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 6444 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 6445 default: 6446 i40e_send_vf_nack(pf, vf, opcode, I40E_ERR_NOT_IMPLEMENTED); 6447 break; 6448 } 6449} 6450 6451/* Handle any VFs that have reset themselves via a Function Level Reset(FLR). */ 6452static void 6453ixl_handle_vflr(void *arg, int pending) 6454{ 6455 struct ixl_pf *pf; 6456 struct i40e_hw *hw; 6457 uint16_t global_vf_num; 6458 uint32_t vflrstat_index, vflrstat_mask, vflrstat, icr0; 6459 int i; 6460 6461 pf = arg; 6462 hw = &pf->hw; 6463 6464 IXL_PF_LOCK(pf); 6465 for (i = 0; i < pf->num_vfs; i++) { 6466 global_vf_num = hw->func_caps.vf_base_id + i; 6467 6468 vflrstat_index = IXL_GLGEN_VFLRSTAT_INDEX(global_vf_num); 6469 vflrstat_mask = IXL_GLGEN_VFLRSTAT_MASK(global_vf_num); 6470 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index)); 6471 if (vflrstat & vflrstat_mask) { 6472 wr32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index), 6473 vflrstat_mask); 6474 6475 ixl_reinit_vf(pf, &pf->vfs[i]); 6476 } 6477 } 6478 6479 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA); 6480 icr0 |= I40E_PFINT_ICR0_ENA_VFLR_MASK; 6481 wr32(hw, I40E_PFINT_ICR0_ENA, icr0); 6482 ixl_flush(hw); 6483 6484 IXL_PF_UNLOCK(pf); 6485} 6486 6487static int 6488ixl_adminq_err_to_errno(enum i40e_admin_queue_err err) 6489{ 6490 6491 switch (err) { 6492 case I40E_AQ_RC_EPERM: 6493 return (EPERM); 6494 case I40E_AQ_RC_ENOENT: 6495 return (ENOENT); 6496 case I40E_AQ_RC_ESRCH: 6497 return (ESRCH); 6498 case I40E_AQ_RC_EINTR: 6499 return (EINTR); 6500 case I40E_AQ_RC_EIO: 6501 return (EIO); 6502 case I40E_AQ_RC_ENXIO: 6503 return (ENXIO); 6504 case I40E_AQ_RC_E2BIG: 6505 return (E2BIG); 6506 case I40E_AQ_RC_EAGAIN: 6507 return (EAGAIN); 6508 case I40E_AQ_RC_ENOMEM: 6509 return (ENOMEM); 6510 case I40E_AQ_RC_EACCES: 6511 return (EACCES); 6512 case I40E_AQ_RC_EFAULT: 6513 return (EFAULT); 6514 case I40E_AQ_RC_EBUSY: 6515 return (EBUSY); 6516 case I40E_AQ_RC_EEXIST: 6517 return (EEXIST); 6518 case I40E_AQ_RC_EINVAL: 6519 return (EINVAL); 6520 case I40E_AQ_RC_ENOTTY: 6521 return (ENOTTY); 6522 case I40E_AQ_RC_ENOSPC: 6523 return (ENOSPC); 6524 case I40E_AQ_RC_ENOSYS: 6525 return (ENOSYS); 6526 case I40E_AQ_RC_ERANGE: 6527 return (ERANGE); 6528 case I40E_AQ_RC_EFLUSHED: 6529 return (EINVAL); /* No exact equivalent in errno.h */ 6530 case I40E_AQ_RC_BAD_ADDR: 6531 return (EFAULT); 6532 case I40E_AQ_RC_EMODE: 6533 return (EPERM); 6534 case I40E_AQ_RC_EFBIG: 6535 return (EFBIG); 6536 default: 6537 return (EINVAL); 6538 } 6539} 6540 6541static int 6542ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t *params) 6543{ 6544 struct ixl_pf *pf; 6545 struct i40e_hw *hw; 6546 struct ixl_vsi *pf_vsi; 6547 enum i40e_status_code ret; 6548 int i, error; 6549 6550 pf = device_get_softc(dev); 6551 hw = &pf->hw; 6552 pf_vsi = &pf->vsi; 6553 6554 IXL_PF_LOCK(pf); 6555 pf->vfs = malloc(sizeof(struct ixl_vf) * num_vfs, M_IXL, M_NOWAIT | 6556 M_ZERO); 6557 6558 if (pf->vfs == NULL) { 6559 error = ENOMEM; 6560 goto fail; 6561 } 6562 6563 for (i = 0; i < num_vfs; i++) 6564 sysctl_ctx_init(&pf->vfs[i].ctx); 6565 6566 ret = i40e_aq_add_veb(hw, pf_vsi->uplink_seid, pf_vsi->seid, 6567 1, FALSE, FALSE, &pf->veb_seid, NULL); 6568 if (ret != I40E_SUCCESS) { 6569 error = ixl_adminq_err_to_errno(hw->aq.asq_last_status); 6570 device_printf(dev, "add_veb failed; code=%d error=%d", ret, 6571 error); 6572 goto fail; 6573 } 6574 6575 ixl_configure_msix(pf); 6576 ixl_enable_adminq(hw); 6577 6578 pf->num_vfs = num_vfs; 6579 IXL_PF_UNLOCK(pf); 6580 return (0); 6581 6582fail: 6583 free(pf->vfs, M_IXL); 6584 pf->vfs = NULL; 6585 IXL_PF_UNLOCK(pf); 6586 return (error); 6587} 6588 6589static void 6590ixl_uninit_iov(device_t dev) 6591{ 6592 struct ixl_pf *pf; 6593 struct i40e_hw *hw; 6594 struct ixl_vsi *vsi; 6595 struct ifnet *ifp; 6596 struct ixl_vf *vfs; 6597 int i, num_vfs; 6598 6599 pf = device_get_softc(dev); 6600 hw = &pf->hw; 6601 vsi = &pf->vsi; 6602 ifp = vsi->ifp; 6603 6604 IXL_PF_LOCK(pf); 6605 for (i = 0; i < pf->num_vfs; i++) { 6606 if (pf->vfs[i].vsi.seid != 0) 6607 i40e_aq_delete_element(hw, pf->vfs[i].vsi.seid, NULL); 6608 } 6609 6610 if (pf->veb_seid != 0) { 6611 i40e_aq_delete_element(hw, pf->veb_seid, NULL); 6612 pf->veb_seid = 0; 6613 } 6614 6615 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 6616 ixl_disable_intr(vsi); 6617 6618 vfs = pf->vfs; 6619 num_vfs = pf->num_vfs; 6620 6621 pf->vfs = NULL; 6622 pf->num_vfs = 0; 6623 IXL_PF_UNLOCK(pf); 6624 6625 /* Do this after the unlock as sysctl_ctx_free might sleep. */ 6626 for (i = 0; i < num_vfs; i++) 6627 sysctl_ctx_free(&vfs[i].ctx); 6628 free(vfs, M_IXL); 6629} 6630 6631static int 6632ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 6633{ 6634 char sysctl_name[QUEUE_NAME_LEN]; 6635 struct ixl_pf *pf; 6636 struct ixl_vf *vf; 6637 const void *mac; 6638 size_t size; 6639 int error; 6640 6641 pf = device_get_softc(dev); 6642 vf = &pf->vfs[vfnum]; 6643 6644 IXL_PF_LOCK(pf); 6645 vf->vf_num = vfnum; 6646 6647 vf->vsi.back = pf; 6648 vf->vf_flags = VF_FLAG_ENABLED; 6649 SLIST_INIT(&vf->vsi.ftl); 6650 6651 error = ixl_vf_setup_vsi(pf, vf); 6652 if (error != 0) 6653 goto out; 6654 6655 if (nvlist_exists_binary(params, "mac-addr")) { 6656 mac = nvlist_get_binary(params, "mac-addr", &size); 6657 bcopy(mac, vf->mac, ETHER_ADDR_LEN); 6658 6659 if (nvlist_get_bool(params, "allow-set-mac")) 6660 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6661 } else 6662 /* 6663 * If the administrator has not specified a MAC address then 6664 * we must allow the VF to choose one. 6665 */ 6666 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6667 6668 if (nvlist_get_bool(params, "mac-anti-spoof")) 6669 vf->vf_flags |= VF_FLAG_MAC_ANTI_SPOOF; 6670 6671 if (nvlist_get_bool(params, "allow-promisc")) 6672 vf->vf_flags |= VF_FLAG_PROMISC_CAP; 6673 6674 vf->vf_flags |= VF_FLAG_VLAN_CAP; 6675 6676 ixl_reset_vf(pf, vf); 6677out: 6678 IXL_PF_UNLOCK(pf); 6679 if (error == 0) { 6680 snprintf(sysctl_name, sizeof(sysctl_name), "vf%d", vfnum); 6681 ixl_add_vsi_sysctls(pf, &vf->vsi, &vf->ctx, sysctl_name); 6682 } 6683 6684 return (error); 6685} 6686#endif /* PCI_IOV */ 6687