ixgbe_osdep.h revision 283620
1127664Sbms/****************************************************************************** 2127664Sbms 3127664Sbms Copyright (c) 2001-2015, Intel Corporation 4127664Sbms All rights reserved. 5127664Sbms 6127664Sbms Redistribution and use in source and binary forms, with or without 7127664Sbms modification, are permitted provided that the following conditions are met: 8127664Sbms 9127664Sbms 1. Redistributions of source code must retain the above copyright notice, 10127664Sbms this list of conditions and the following disclaimer. 11127664Sbms 12127664Sbms 2. Redistributions in binary form must reproduce the above copyright 13127664Sbms notice, this list of conditions and the following disclaimer in the 14127664Sbms documentation and/or other materials provided with the distribution. 15127664Sbms 16127664Sbms 3. Neither the name of the Intel Corporation nor the names of its 17127664Sbms contributors may be used to endorse or promote products derived from 18127664Sbms this software without specific prior written permission. 19127664Sbms 20127664Sbms THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21127664Sbms AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22127664Sbms IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23127664Sbms ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24127664Sbms LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25127664Sbms CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26127664Sbms SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27127664Sbms INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28127664Sbms CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29127664Sbms ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30127664Sbms POSSIBILITY OF SUCH DAMAGE. 31127664Sbms 32127664Sbms******************************************************************************/ 33127664Sbms/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_osdep.h 283620 2015-05-27 17:44:11Z erj $*/ 34127664Sbms 35127664Sbms#ifndef _IXGBE_OS_H_ 36127664Sbms#define _IXGBE_OS_H_ 37214518Srpaulo 38127664Sbms#include <sys/types.h> 39127664Sbms#include <sys/param.h> 40127664Sbms#include <sys/endian.h> 41127664Sbms#include <sys/systm.h> 42127664Sbms#include <sys/mbuf.h> 43127664Sbms#include <sys/protosw.h> 44127664Sbms#include <sys/socket.h> 45127664Sbms#include <sys/malloc.h> 46127664Sbms#include <sys/kernel.h> 47127664Sbms#include <sys/bus.h> 48127664Sbms#include <machine/bus.h> 49127664Sbms#include <sys/rman.h> 50127664Sbms#include <machine/resource.h> 51127664Sbms#include <vm/vm.h> 52127664Sbms#include <vm/pmap.h> 53127664Sbms#include <machine/clock.h> 54127664Sbms#include <dev/pci/pcivar.h> 55127664Sbms#include <dev/pci/pcireg.h> 56127664Sbms 57127664Sbms#define ASSERT(x) if(!(x)) panic("IXGBE: x") 58127664Sbms#define EWARN(H, W, S) printf(W) 59127664Sbms 60127664Sbms/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */ 61127664Sbms#define usec_delay(x) DELAY(x) 62127664Sbms#define msec_delay(x) DELAY(1000*(x)) 63127664Sbms 64127664Sbms#define DBG 0 65127664Sbms#define MSGOUT(S, A, B) printf(S "\n", A, B) 66#define DEBUGFUNC(F) DEBUGOUT(F); 67#if DBG 68 #define DEBUGOUT(S) printf(S "\n") 69 #define DEBUGOUT1(S,A) printf(S "\n",A) 70 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B) 71 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C) 72 #define DEBUGOUT4(S,A,B,C,D) printf(S "\n",A,B,C,D) 73 #define DEBUGOUT5(S,A,B,C,D,E) printf(S "\n",A,B,C,D,E) 74 #define DEBUGOUT6(S,A,B,C,D,E,F) printf(S "\n",A,B,C,D,E,F) 75 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G) 76 #define ERROR_REPORT1(S,A) printf(S "\n",A) 77 #define ERROR_REPORT2(S,A,B) printf(S "\n",A,B) 78 #define ERROR_REPORT3(S,A,B,C) printf(S "\n",A,B,C) 79#else 80 #define DEBUGOUT(S) 81 #define DEBUGOUT1(S,A) 82 #define DEBUGOUT2(S,A,B) 83 #define DEBUGOUT3(S,A,B,C) 84 #define DEBUGOUT4(S,A,B,C,D) 85 #define DEBUGOUT5(S,A,B,C,D,E) 86 #define DEBUGOUT6(S,A,B,C,D,E,F) 87 #define DEBUGOUT7(S,A,B,C,D,E,F,G) 88 89 #define ERROR_REPORT1(S,A) 90 #define ERROR_REPORT2(S,A,B) 91 #define ERROR_REPORT3(S,A,B,C) 92#endif 93 94#define FALSE 0 95#define false 0 /* shared code requires this */ 96#define TRUE 1 97#define true 1 98#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 99#define PCI_COMMAND_REGISTER PCIR_COMMAND 100 101/* Shared code dropped this define.. */ 102#define IXGBE_INTEL_VENDOR_ID 0x8086 103 104/* Bunch of defines for shared code bogosity */ 105#define UNREFERENCED_PARAMETER(_p) 106#define UNREFERENCED_1PARAMETER(_p) 107#define UNREFERENCED_2PARAMETER(_p, _q) 108#define UNREFERENCED_3PARAMETER(_p, _q, _r) 109#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) 110 111#define IXGBE_NTOHL(_i) ntohl(_i) 112#define IXGBE_NTOHS(_i) ntohs(_i) 113 114/* XXX these need to be revisited */ 115#define IXGBE_CPU_TO_LE32 htole32 116#define IXGBE_LE32_TO_CPUS(x) 117#define IXGBE_CPU_TO_BE16 htobe16 118#define IXGBE_CPU_TO_BE32 htobe32 119 120typedef uint8_t u8; 121typedef int8_t s8; 122typedef uint16_t u16; 123typedef int16_t s16; 124typedef uint32_t u32; 125typedef int32_t s32; 126typedef uint64_t u64; 127#ifndef __bool_true_false_are_defined 128typedef boolean_t bool; 129#endif 130 131/* shared code requires this */ 132#define __le16 u16 133#define __le32 u32 134#define __le64 u64 135#define __be16 u16 136#define __be32 u32 137#define __be64 u64 138 139#define le16_to_cpu 140 141#if __FreeBSD_version < 800000 142#if defined(__i386__) || defined(__amd64__) 143#define mb() __asm volatile("mfence" ::: "memory") 144#define wmb() __asm volatile("sfence" ::: "memory") 145#define rmb() __asm volatile("lfence" ::: "memory") 146#else 147#define mb() 148#define rmb() 149#define wmb() 150#endif 151#endif 152 153#if defined(__i386__) || defined(__amd64__) 154static __inline 155void prefetch(void *x) 156{ 157 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 158} 159#else 160#define prefetch(x) 161#endif 162 163/* 164 * Optimized bcopy thanks to Luigi Rizzo's investigative work. Assumes 165 * non-overlapping regions and 32-byte padding on both src and dst. 166 */ 167static __inline int 168ixgbe_bcopy(void *_src, void *_dst, int l) 169{ 170 uint64_t *src = _src; 171 uint64_t *dst = _dst; 172 173 for (; l > 0; l -= 32) { 174 *dst++ = *src++; 175 *dst++ = *src++; 176 *dst++ = *src++; 177 *dst++ = *src++; 178 } 179 return (0); 180} 181 182struct ixgbe_osdep 183{ 184 bus_space_tag_t mem_bus_space_tag; 185 bus_space_handle_t mem_bus_space_handle; 186 struct device *dev; 187}; 188 189/* These routines are needed by the shared code */ 190struct ixgbe_hw; 191extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32); 192#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg 193 194extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16); 195#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg 196 197#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) 198 199#define IXGBE_READ_REG(a, reg) (\ 200 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \ 201 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \ 202 reg)) 203 204#define IXGBE_WRITE_REG(a, reg, value) (\ 205 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \ 206 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \ 207 reg, value)) 208 209 210#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\ 211 bus_space_read_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \ 212 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \ 213 (reg + ((offset) << 2)))) 214 215#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\ 216 bus_space_write_4( ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_tag, \ 217 ((struct ixgbe_osdep *)(a)->back)->mem_bus_space_handle, \ 218 (reg + ((offset) << 2)), value)) 219 220 221#endif /* _IXGBE_OS_H_ */ 222