1179055Sjfv/****************************************************************************** 2171384Sjfv 3315333Serj Copyright (c) 2001-2017, Intel Corporation 4171384Sjfv All rights reserved. 5315333Serj 6315333Serj Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8315333Serj 9315333Serj 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11315333Serj 12315333Serj 2. Redistributions in binary form must reproduce the above copyright 13315333Serj notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15315333Serj 16315333Serj 3. Neither the name of the Intel Corporation nor the names of its 17315333Serj contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19315333Serj 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21315333Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22315333Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23315333Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24315333Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25315333Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26315333Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27315333Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28315333Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_common.c 315333 2017-03-15 21:20:17Z erj $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_common.h" 36215911Sjfv#include "ixgbe_phy.h" 37251964Sjfv#include "ixgbe_dcb.h" 38251964Sjfv#include "ixgbe_dcb_82599.h" 39171384Sjfv#include "ixgbe_api.h" 40171384Sjfv 41171384Sjfvstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42171384Sjfvstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43171384Sjfvstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44171384Sjfvstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45171384Sjfvstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46171384Sjfvstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47230775Sjfv u16 count); 48171384Sjfvstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49171384Sjfvstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50171384Sjfvstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51171384Sjfvstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52171384Sjfv 53171384Sjfvstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54200239Sjfvstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55230775Sjfv u16 *san_mac_offset); 56230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57230775Sjfv u16 words, u16 *data); 58230775Sjfvstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59230775Sjfv u16 words, u16 *data); 60230775Sjfvstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61230775Sjfv u16 offset); 62215911Sjfv 63171384Sjfv/** 64179055Sjfv * ixgbe_init_ops_generic - Inits function ptrs 65179055Sjfv * @hw: pointer to the hardware structure 66171384Sjfv * 67179055Sjfv * Initialize the function pointers. 68171384Sjfv **/ 69179055Sjfvs32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70171384Sjfv{ 71179055Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72179055Sjfv struct ixgbe_mac_info *mac = &hw->mac; 73295524Ssbruno u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 74171384Sjfv 75200239Sjfv DEBUGFUNC("ixgbe_init_ops_generic"); 76200239Sjfv 77171384Sjfv /* EEPROM */ 78283620Serj eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 79179055Sjfv /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80230775Sjfv if (eec & IXGBE_EEC_PRES) { 81283620Serj eeprom->ops.read = ixgbe_read_eerd_generic; 82283620Serj eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 83230775Sjfv } else { 84283620Serj eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 85230775Sjfv eeprom->ops.read_buffer = 86283620Serj ixgbe_read_eeprom_buffer_bit_bang_generic; 87230775Sjfv } 88283620Serj eeprom->ops.write = ixgbe_write_eeprom_generic; 89283620Serj eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 90179055Sjfv eeprom->ops.validate_checksum = 91283620Serj ixgbe_validate_eeprom_checksum_generic; 92283620Serj eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 93283620Serj eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 94179055Sjfv 95179055Sjfv /* MAC */ 96283620Serj mac->ops.init_hw = ixgbe_init_hw_generic; 97179055Sjfv mac->ops.reset_hw = NULL; 98283620Serj mac->ops.start_hw = ixgbe_start_hw_generic; 99283620Serj mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 100179055Sjfv mac->ops.get_media_type = NULL; 101185352Sjfv mac->ops.get_supported_physical_layer = NULL; 102283620Serj mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 103283620Serj mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 104283620Serj mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 105283620Serj mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 106283620Serj mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 107283620Serj mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 108283620Serj mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 109283620Serj mac->ops.prot_autoc_read = prot_autoc_read_generic; 110283620Serj mac->ops.prot_autoc_write = prot_autoc_write_generic; 111179055Sjfv 112179055Sjfv /* LEDs */ 113283620Serj mac->ops.led_on = ixgbe_led_on_generic; 114283620Serj mac->ops.led_off = ixgbe_led_off_generic; 115283620Serj mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 116283620Serj mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 117315333Serj mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 118179055Sjfv 119171384Sjfv /* RAR, Multicast, VLAN */ 120283620Serj mac->ops.set_rar = ixgbe_set_rar_generic; 121283620Serj mac->ops.clear_rar = ixgbe_clear_rar_generic; 122190873Sjfv mac->ops.insert_mac_addr = NULL; 123179055Sjfv mac->ops.set_vmdq = NULL; 124181003Sjfv mac->ops.clear_vmdq = NULL; 125283620Serj mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 126283620Serj mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 127283620Serj mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 128283620Serj mac->ops.enable_mc = ixgbe_enable_mc_generic; 129283620Serj mac->ops.disable_mc = ixgbe_disable_mc_generic; 130181003Sjfv mac->ops.clear_vfta = NULL; 131181003Sjfv mac->ops.set_vfta = NULL; 132230775Sjfv mac->ops.set_vlvf = NULL; 133181003Sjfv mac->ops.init_uta_tables = NULL; 134283620Serj mac->ops.enable_rx = ixgbe_enable_rx_generic; 135283620Serj mac->ops.disable_rx = ixgbe_disable_rx_generic; 136171384Sjfv 137190873Sjfv /* Flow Control */ 138283620Serj mac->ops.fc_enable = ixgbe_fc_enable_generic; 139283620Serj mac->ops.setup_fc = ixgbe_setup_fc_generic; 140315333Serj mac->ops.fc_autoneg = ixgbe_fc_autoneg; 141179055Sjfv 142179055Sjfv /* Link */ 143179055Sjfv mac->ops.get_link_capabilities = NULL; 144179055Sjfv mac->ops.setup_link = NULL; 145179055Sjfv mac->ops.check_link = NULL; 146251964Sjfv mac->ops.dmac_config = NULL; 147251964Sjfv mac->ops.dmac_update_tcs = NULL; 148251964Sjfv mac->ops.dmac_config_tcs = NULL; 149179055Sjfv 150171384Sjfv return IXGBE_SUCCESS; 151171384Sjfv} 152171384Sjfv 153171384Sjfv/** 154251964Sjfv * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 155251964Sjfv * of flow control 156251964Sjfv * @hw: pointer to hardware structure 157238149Sjfv * 158251964Sjfv * This function returns TRUE if the device supports flow control 159251964Sjfv * autonegotiation, and FALSE if it does not. 160251964Sjfv * 161238149Sjfv **/ 162251964Sjfvbool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 163238149Sjfv{ 164251964Sjfv bool supported = FALSE; 165251964Sjfv ixgbe_link_speed speed; 166251964Sjfv bool link_up; 167238149Sjfv 168238149Sjfv DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 169238149Sjfv 170251964Sjfv switch (hw->phy.media_type) { 171251964Sjfv case ixgbe_media_type_fiber_fixed: 172283620Serj case ixgbe_media_type_fiber_qsfp: 173251964Sjfv case ixgbe_media_type_fiber: 174315333Serj /* flow control autoneg black list */ 175315333Serj switch (hw->device_id) { 176315333Serj case IXGBE_DEV_ID_X550EM_A_SFP: 177315333Serj case IXGBE_DEV_ID_X550EM_A_SFP_N: 178315333Serj case IXGBE_DEV_ID_X550EM_A_QSFP: 179315333Serj case IXGBE_DEV_ID_X550EM_A_QSFP_N: 180315333Serj supported = FALSE; 181315333Serj break; 182315333Serj default: 183315333Serj hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 184315333Serj /* if link is down, assume supported */ 185315333Serj if (link_up) 186315333Serj supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 187251964Sjfv TRUE : FALSE; 188315333Serj else 189315333Serj supported = TRUE; 190315333Serj } 191315333Serj 192251964Sjfv break; 193251964Sjfv case ixgbe_media_type_backplane: 194251964Sjfv supported = TRUE; 195251964Sjfv break; 196251964Sjfv case ixgbe_media_type_copper: 197251964Sjfv /* only some copper devices support flow control autoneg */ 198251964Sjfv switch (hw->device_id) { 199251964Sjfv case IXGBE_DEV_ID_82599_T3_LOM: 200251964Sjfv case IXGBE_DEV_ID_X540T: 201283620Serj case IXGBE_DEV_ID_X540T1: 202251964Sjfv case IXGBE_DEV_ID_X540_BYPASS: 203283620Serj case IXGBE_DEV_ID_X550T: 204295524Ssbruno case IXGBE_DEV_ID_X550T1: 205283620Serj case IXGBE_DEV_ID_X550EM_X_10G_T: 206315333Serj case IXGBE_DEV_ID_X550EM_A_10G_T: 207315333Serj case IXGBE_DEV_ID_X550EM_A_1G_T: 208315333Serj case IXGBE_DEV_ID_X550EM_A_1G_T_L: 209251964Sjfv supported = TRUE; 210251964Sjfv break; 211251964Sjfv default: 212251964Sjfv supported = FALSE; 213251964Sjfv } 214238149Sjfv default: 215251964Sjfv break; 216238149Sjfv } 217251964Sjfv 218315333Serj if (!supported) 219295528Ssmh ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 220315333Serj "Device %x does not support flow control autoneg", 221315333Serj hw->device_id); 222251964Sjfv return supported; 223238149Sjfv} 224238149Sjfv 225238149Sjfv/** 226283620Serj * ixgbe_setup_fc_generic - Set up flow control 227238149Sjfv * @hw: pointer to hardware structure 228238149Sjfv * 229238149Sjfv * Called at init time to set up flow control. 230238149Sjfv **/ 231283620Serjs32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 232238149Sjfv{ 233238149Sjfv s32 ret_val = IXGBE_SUCCESS; 234238149Sjfv u32 reg = 0, reg_bp = 0; 235238149Sjfv u16 reg_cu = 0; 236283620Serj bool locked = FALSE; 237238149Sjfv 238283620Serj DEBUGFUNC("ixgbe_setup_fc_generic"); 239238149Sjfv 240283620Serj /* Validate the requested mode */ 241238149Sjfv if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 242251964Sjfv ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 243251964Sjfv "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 244238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 245238149Sjfv goto out; 246238149Sjfv } 247238149Sjfv 248238149Sjfv /* 249238149Sjfv * 10gig parts do not have a word in the EEPROM to determine the 250238149Sjfv * default flow control setting, so we explicitly set it to full. 251238149Sjfv */ 252238149Sjfv if (hw->fc.requested_mode == ixgbe_fc_default) 253238149Sjfv hw->fc.requested_mode = ixgbe_fc_full; 254238149Sjfv 255238149Sjfv /* 256238149Sjfv * Set up the 1G and 10G flow control advertisement registers so the 257238149Sjfv * HW will be able to do fc autoneg once the cable is plugged in. If 258238149Sjfv * we link at 10G, the 1G advertisement is harmless and vice versa. 259238149Sjfv */ 260238149Sjfv switch (hw->phy.media_type) { 261283620Serj case ixgbe_media_type_backplane: 262283620Serj /* some MAC's need RMW protection on AUTOC */ 263283620Serj ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 264283620Serj if (ret_val != IXGBE_SUCCESS) 265283620Serj goto out; 266283620Serj 267283620Serj /* only backplane uses autoc so fall though */ 268247822Sjfv case ixgbe_media_type_fiber_fixed: 269283620Serj case ixgbe_media_type_fiber_qsfp: 270238149Sjfv case ixgbe_media_type_fiber: 271238149Sjfv reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 272283620Serj 273238149Sjfv break; 274238149Sjfv case ixgbe_media_type_copper: 275238149Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 276238149Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 277238149Sjfv break; 278238149Sjfv default: 279238149Sjfv break; 280238149Sjfv } 281238149Sjfv 282238149Sjfv /* 283238149Sjfv * The possible values of fc.requested_mode are: 284238149Sjfv * 0: Flow control is completely disabled 285238149Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 286238149Sjfv * but not send pause frames). 287238149Sjfv * 2: Tx flow control is enabled (we can send pause frames but 288238149Sjfv * we do not support receiving pause frames). 289238149Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 290238149Sjfv * other: Invalid. 291238149Sjfv */ 292238149Sjfv switch (hw->fc.requested_mode) { 293238149Sjfv case ixgbe_fc_none: 294238149Sjfv /* Flow control completely disabled by software override. */ 295238149Sjfv reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 296238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) 297238149Sjfv reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 298238149Sjfv IXGBE_AUTOC_ASM_PAUSE); 299238149Sjfv else if (hw->phy.media_type == ixgbe_media_type_copper) 300238149Sjfv reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 301238149Sjfv break; 302238149Sjfv case ixgbe_fc_tx_pause: 303238149Sjfv /* 304238149Sjfv * Tx Flow control is enabled, and Rx Flow control is 305238149Sjfv * disabled by software override. 306238149Sjfv */ 307238149Sjfv reg |= IXGBE_PCS1GANA_ASM_PAUSE; 308238149Sjfv reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 309238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) { 310238149Sjfv reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 311238149Sjfv reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 312238149Sjfv } else if (hw->phy.media_type == ixgbe_media_type_copper) { 313238149Sjfv reg_cu |= IXGBE_TAF_ASM_PAUSE; 314238149Sjfv reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 315238149Sjfv } 316238149Sjfv break; 317238149Sjfv case ixgbe_fc_rx_pause: 318238149Sjfv /* 319238149Sjfv * Rx Flow control is enabled and Tx Flow control is 320238149Sjfv * disabled by software override. Since there really 321238149Sjfv * isn't a way to advertise that we are capable of RX 322238149Sjfv * Pause ONLY, we will advertise that we support both 323238149Sjfv * symmetric and asymmetric Rx PAUSE, as such we fall 324238149Sjfv * through to the fc_full statement. Later, we will 325238149Sjfv * disable the adapter's ability to send PAUSE frames. 326238149Sjfv */ 327238149Sjfv case ixgbe_fc_full: 328238149Sjfv /* Flow control (both Rx and Tx) is enabled by SW override. */ 329238149Sjfv reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 330238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) 331238149Sjfv reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 332238149Sjfv IXGBE_AUTOC_ASM_PAUSE; 333238149Sjfv else if (hw->phy.media_type == ixgbe_media_type_copper) 334238149Sjfv reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 335238149Sjfv break; 336238149Sjfv default: 337251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 338251964Sjfv "Flow control param set incorrectly\n"); 339238149Sjfv ret_val = IXGBE_ERR_CONFIG; 340238149Sjfv goto out; 341238149Sjfv break; 342238149Sjfv } 343238149Sjfv 344283620Serj if (hw->mac.type < ixgbe_mac_X540) { 345238149Sjfv /* 346238149Sjfv * Enable auto-negotiation between the MAC & PHY; 347238149Sjfv * the MAC will advertise clause 37 flow control. 348238149Sjfv */ 349238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 350238149Sjfv reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 351238149Sjfv 352238149Sjfv /* Disable AN timeout */ 353238149Sjfv if (hw->fc.strict_ieee) 354238149Sjfv reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 355238149Sjfv 356238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 357238149Sjfv DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 358238149Sjfv } 359238149Sjfv 360238149Sjfv /* 361238149Sjfv * AUTOC restart handles negotiation of 1G and 10G on backplane 362238149Sjfv * and copper. There is no need to set the PCS1GCTL register. 363238149Sjfv * 364238149Sjfv */ 365238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) { 366238149Sjfv reg_bp |= IXGBE_AUTOC_AN_RESTART; 367283620Serj ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 368283620Serj if (ret_val) 369283620Serj goto out; 370238149Sjfv } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 371251964Sjfv (ixgbe_device_supports_autoneg_fc(hw))) { 372238149Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 373238149Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 374238149Sjfv } 375238149Sjfv 376283620Serj DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 377238149Sjfvout: 378238149Sjfv return ret_val; 379238149Sjfv} 380238149Sjfv 381238149Sjfv/** 382179055Sjfv * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 383171384Sjfv * @hw: pointer to hardware structure 384171384Sjfv * 385171384Sjfv * Starts the hardware by filling the bus info structure and media type, clears 386171384Sjfv * all on chip counters, initializes receive address registers, multicast 387171384Sjfv * table, VLAN filter table, calls routine to set up link and flow control 388171384Sjfv * settings, and leaves transmit and receive units disabled and uninitialized 389171384Sjfv **/ 390171384Sjfvs32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 391171384Sjfv{ 392238149Sjfv s32 ret_val; 393171384Sjfv u32 ctrl_ext; 394315333Serj u16 device_caps; 395171384Sjfv 396200239Sjfv DEBUGFUNC("ixgbe_start_hw_generic"); 397200239Sjfv 398171384Sjfv /* Set the media type */ 399179055Sjfv hw->phy.media_type = hw->mac.ops.get_media_type(hw); 400171384Sjfv 401190873Sjfv /* PHY ops initialization must be done in reset_hw() */ 402171384Sjfv 403171384Sjfv /* Clear the VLAN filter table */ 404179055Sjfv hw->mac.ops.clear_vfta(hw); 405171384Sjfv 406171384Sjfv /* Clear statistics registers */ 407179055Sjfv hw->mac.ops.clear_hw_cntrs(hw); 408171384Sjfv 409171384Sjfv /* Set No Snoop Disable */ 410171384Sjfv ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 411171384Sjfv ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 412171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 413179055Sjfv IXGBE_WRITE_FLUSH(hw); 414171384Sjfv 415190873Sjfv /* Setup flow control */ 416238149Sjfv ret_val = ixgbe_setup_fc(hw); 417315333Serj if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 418315333Serj DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 419315333Serj return ret_val; 420315333Serj } 421190873Sjfv 422315333Serj /* Cache bit indicating need for crosstalk fix */ 423315333Serj switch (hw->mac.type) { 424315333Serj case ixgbe_mac_82599EB: 425315333Serj case ixgbe_mac_X550EM_x: 426315333Serj case ixgbe_mac_X550EM_a: 427315333Serj hw->mac.ops.get_device_caps(hw, &device_caps); 428315333Serj if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 429315333Serj hw->need_crosstalk_fix = FALSE; 430315333Serj else 431315333Serj hw->need_crosstalk_fix = TRUE; 432315333Serj break; 433315333Serj default: 434315333Serj hw->need_crosstalk_fix = FALSE; 435315333Serj break; 436315333Serj } 437315333Serj 438171384Sjfv /* Clear adapter stopped flag */ 439171384Sjfv hw->adapter_stopped = FALSE; 440171384Sjfv 441315333Serj return IXGBE_SUCCESS; 442171384Sjfv} 443171384Sjfv 444171384Sjfv/** 445215911Sjfv * ixgbe_start_hw_gen2 - Init sequence for common device family 446215911Sjfv * @hw: pointer to hw structure 447215911Sjfv * 448215911Sjfv * Performs the init sequence common to the second generation 449215911Sjfv * of 10 GbE devices. 450215911Sjfv * Devices in the second generation: 451215911Sjfv * 82599 452217593Sjfv * X540 453215911Sjfv **/ 454215911Sjfvs32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 455215911Sjfv{ 456215911Sjfv u32 i; 457215911Sjfv u32 regval; 458215911Sjfv 459215911Sjfv /* Clear the rate limiters */ 460215911Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 461215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 462215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 463215911Sjfv } 464215911Sjfv IXGBE_WRITE_FLUSH(hw); 465215911Sjfv 466215911Sjfv /* Disable relaxed ordering */ 467215911Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 468215911Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 469238149Sjfv regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 470215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 471215911Sjfv } 472215911Sjfv 473215911Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 474215911Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 475238149Sjfv regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 476238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 477215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 478215911Sjfv } 479215911Sjfv 480215911Sjfv return IXGBE_SUCCESS; 481215911Sjfv} 482215911Sjfv 483215911Sjfv/** 484171384Sjfv * ixgbe_init_hw_generic - Generic hardware initialization 485171384Sjfv * @hw: pointer to hardware structure 486171384Sjfv * 487179055Sjfv * Initialize the hardware by resetting the hardware, filling the bus info 488171384Sjfv * structure and media type, clears all on chip counters, initializes receive 489171384Sjfv * address registers, multicast table, VLAN filter table, calls routine to set 490171384Sjfv * up link and flow control settings, and leaves transmit and receive units 491171384Sjfv * disabled and uninitialized 492171384Sjfv **/ 493171384Sjfvs32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 494171384Sjfv{ 495215911Sjfv s32 status; 496190873Sjfv 497200239Sjfv DEBUGFUNC("ixgbe_init_hw_generic"); 498200239Sjfv 499171384Sjfv /* Reset the hardware */ 500190873Sjfv status = hw->mac.ops.reset_hw(hw); 501171384Sjfv 502190873Sjfv if (status == IXGBE_SUCCESS) { 503190873Sjfv /* Start the HW */ 504190873Sjfv status = hw->mac.ops.start_hw(hw); 505190873Sjfv } 506171384Sjfv 507315333Serj /* Initialize the LED link active for LED blink support */ 508315333Serj hw->mac.ops.init_led_link_act(hw); 509315333Serj 510315333Serj if (status != IXGBE_SUCCESS) 511315333Serj DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 512315333Serj 513190873Sjfv return status; 514171384Sjfv} 515171384Sjfv 516171384Sjfv/** 517171384Sjfv * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 518171384Sjfv * @hw: pointer to hardware structure 519171384Sjfv * 520171384Sjfv * Clears all hardware statistics counters by reading them from the hardware 521171384Sjfv * Statistics counters are clear on read. 522171384Sjfv **/ 523171384Sjfvs32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 524171384Sjfv{ 525171384Sjfv u16 i = 0; 526171384Sjfv 527200239Sjfv DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 528200239Sjfv 529171384Sjfv IXGBE_READ_REG(hw, IXGBE_CRCERRS); 530171384Sjfv IXGBE_READ_REG(hw, IXGBE_ILLERRC); 531171384Sjfv IXGBE_READ_REG(hw, IXGBE_ERRBC); 532171384Sjfv IXGBE_READ_REG(hw, IXGBE_MSPDC); 533171384Sjfv for (i = 0; i < 8; i++) 534171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPC(i)); 535171384Sjfv 536171384Sjfv IXGBE_READ_REG(hw, IXGBE_MLFC); 537171384Sjfv IXGBE_READ_REG(hw, IXGBE_MRFC); 538171384Sjfv IXGBE_READ_REG(hw, IXGBE_RLEC); 539171384Sjfv IXGBE_READ_REG(hw, IXGBE_LXONTXC); 540185352Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 541190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 542190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 543190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 544190873Sjfv } else { 545190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXONRXC); 546190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 547190873Sjfv } 548171384Sjfv 549171384Sjfv for (i = 0; i < 8; i++) { 550171384Sjfv IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 551185352Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 552190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 553190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 554190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 555190873Sjfv } else { 556190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 557190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 558190873Sjfv } 559171384Sjfv } 560190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) 561190873Sjfv for (i = 0; i < 8; i++) 562190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 563171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC64); 564171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC127); 565171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC255); 566171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC511); 567171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC1023); 568171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC1522); 569171384Sjfv IXGBE_READ_REG(hw, IXGBE_GPRC); 570171384Sjfv IXGBE_READ_REG(hw, IXGBE_BPRC); 571171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPRC); 572171384Sjfv IXGBE_READ_REG(hw, IXGBE_GPTC); 573171384Sjfv IXGBE_READ_REG(hw, IXGBE_GORCL); 574171384Sjfv IXGBE_READ_REG(hw, IXGBE_GORCH); 575171384Sjfv IXGBE_READ_REG(hw, IXGBE_GOTCL); 576171384Sjfv IXGBE_READ_REG(hw, IXGBE_GOTCH); 577230775Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 578230775Sjfv for (i = 0; i < 8; i++) 579230775Sjfv IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 580171384Sjfv IXGBE_READ_REG(hw, IXGBE_RUC); 581171384Sjfv IXGBE_READ_REG(hw, IXGBE_RFC); 582171384Sjfv IXGBE_READ_REG(hw, IXGBE_ROC); 583171384Sjfv IXGBE_READ_REG(hw, IXGBE_RJC); 584171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPRC); 585171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPDC); 586171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPTC); 587171384Sjfv IXGBE_READ_REG(hw, IXGBE_TORL); 588171384Sjfv IXGBE_READ_REG(hw, IXGBE_TORH); 589171384Sjfv IXGBE_READ_REG(hw, IXGBE_TPR); 590171384Sjfv IXGBE_READ_REG(hw, IXGBE_TPT); 591171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC64); 592171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC127); 593171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC255); 594171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC511); 595171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC1023); 596171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC1522); 597171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPTC); 598171384Sjfv IXGBE_READ_REG(hw, IXGBE_BPTC); 599171384Sjfv for (i = 0; i < 16; i++) { 600171384Sjfv IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 601171384Sjfv IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 602215911Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 603215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 604215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 605215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 606215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 607215911Sjfv IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 608215911Sjfv } else { 609215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 610215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 611215911Sjfv } 612171384Sjfv } 613171384Sjfv 614283620Serj if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 615230775Sjfv if (hw->phy.id == 0) 616230775Sjfv ixgbe_identify_phy(hw); 617230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 618230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 619230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 620230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 621230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 622230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 623230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 624230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 625230775Sjfv } 626230775Sjfv 627171384Sjfv return IXGBE_SUCCESS; 628171384Sjfv} 629171384Sjfv 630171384Sjfv/** 631215911Sjfv * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 632215911Sjfv * @hw: pointer to hardware structure 633215911Sjfv * @pba_num: stores the part number string from the EEPROM 634215911Sjfv * @pba_num_size: part number string buffer length 635215911Sjfv * 636215911Sjfv * Reads the part number string from the EEPROM. 637215911Sjfv **/ 638215911Sjfvs32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 639230775Sjfv u32 pba_num_size) 640215911Sjfv{ 641215911Sjfv s32 ret_val; 642215911Sjfv u16 data; 643215911Sjfv u16 pba_ptr; 644215911Sjfv u16 offset; 645215911Sjfv u16 length; 646215911Sjfv 647215911Sjfv DEBUGFUNC("ixgbe_read_pba_string_generic"); 648215911Sjfv 649215911Sjfv if (pba_num == NULL) { 650215911Sjfv DEBUGOUT("PBA string buffer was null\n"); 651215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 652215911Sjfv } 653215911Sjfv 654215911Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 655215911Sjfv if (ret_val) { 656215911Sjfv DEBUGOUT("NVM Read Error\n"); 657215911Sjfv return ret_val; 658215911Sjfv } 659215911Sjfv 660215911Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 661215911Sjfv if (ret_val) { 662215911Sjfv DEBUGOUT("NVM Read Error\n"); 663215911Sjfv return ret_val; 664215911Sjfv } 665215911Sjfv 666215911Sjfv /* 667215911Sjfv * if data is not ptr guard the PBA must be in legacy format which 668215911Sjfv * means pba_ptr is actually our second data word for the PBA number 669215911Sjfv * and we can decode it into an ascii string 670215911Sjfv */ 671215911Sjfv if (data != IXGBE_PBANUM_PTR_GUARD) { 672215911Sjfv DEBUGOUT("NVM PBA number is not stored as string\n"); 673215911Sjfv 674215911Sjfv /* we will need 11 characters to store the PBA */ 675215911Sjfv if (pba_num_size < 11) { 676215911Sjfv DEBUGOUT("PBA string buffer too small\n"); 677215911Sjfv return IXGBE_ERR_NO_SPACE; 678215911Sjfv } 679215911Sjfv 680215911Sjfv /* extract hex string from data and pba_ptr */ 681215911Sjfv pba_num[0] = (data >> 12) & 0xF; 682215911Sjfv pba_num[1] = (data >> 8) & 0xF; 683215911Sjfv pba_num[2] = (data >> 4) & 0xF; 684215911Sjfv pba_num[3] = data & 0xF; 685215911Sjfv pba_num[4] = (pba_ptr >> 12) & 0xF; 686215911Sjfv pba_num[5] = (pba_ptr >> 8) & 0xF; 687215911Sjfv pba_num[6] = '-'; 688215911Sjfv pba_num[7] = 0; 689215911Sjfv pba_num[8] = (pba_ptr >> 4) & 0xF; 690215911Sjfv pba_num[9] = pba_ptr & 0xF; 691215911Sjfv 692215911Sjfv /* put a null character on the end of our string */ 693215911Sjfv pba_num[10] = '\0'; 694215911Sjfv 695215911Sjfv /* switch all the data but the '-' to hex char */ 696215911Sjfv for (offset = 0; offset < 10; offset++) { 697215911Sjfv if (pba_num[offset] < 0xA) 698215911Sjfv pba_num[offset] += '0'; 699215911Sjfv else if (pba_num[offset] < 0x10) 700215911Sjfv pba_num[offset] += 'A' - 0xA; 701215911Sjfv } 702215911Sjfv 703215911Sjfv return IXGBE_SUCCESS; 704215911Sjfv } 705215911Sjfv 706215911Sjfv ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 707215911Sjfv if (ret_val) { 708215911Sjfv DEBUGOUT("NVM Read Error\n"); 709215911Sjfv return ret_val; 710215911Sjfv } 711215911Sjfv 712215911Sjfv if (length == 0xFFFF || length == 0) { 713215911Sjfv DEBUGOUT("NVM PBA number section invalid length\n"); 714215911Sjfv return IXGBE_ERR_PBA_SECTION; 715215911Sjfv } 716215911Sjfv 717215911Sjfv /* check if pba_num buffer is big enough */ 718215911Sjfv if (pba_num_size < (((u32)length * 2) - 1)) { 719215911Sjfv DEBUGOUT("PBA string buffer too small\n"); 720215911Sjfv return IXGBE_ERR_NO_SPACE; 721215911Sjfv } 722215911Sjfv 723215911Sjfv /* trim pba length from start of string */ 724215911Sjfv pba_ptr++; 725215911Sjfv length--; 726215911Sjfv 727215911Sjfv for (offset = 0; offset < length; offset++) { 728215911Sjfv ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 729215911Sjfv if (ret_val) { 730215911Sjfv DEBUGOUT("NVM Read Error\n"); 731215911Sjfv return ret_val; 732215911Sjfv } 733215911Sjfv pba_num[offset * 2] = (u8)(data >> 8); 734215911Sjfv pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 735215911Sjfv } 736215911Sjfv pba_num[offset * 2] = '\0'; 737215911Sjfv 738215911Sjfv return IXGBE_SUCCESS; 739215911Sjfv} 740215911Sjfv 741215911Sjfv/** 742185352Sjfv * ixgbe_read_pba_num_generic - Reads part number from EEPROM 743179055Sjfv * @hw: pointer to hardware structure 744179055Sjfv * @pba_num: stores the part number from the EEPROM 745179055Sjfv * 746179055Sjfv * Reads the part number from the EEPROM. 747179055Sjfv **/ 748179055Sjfvs32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 749179055Sjfv{ 750179055Sjfv s32 ret_val; 751179055Sjfv u16 data; 752179055Sjfv 753179055Sjfv DEBUGFUNC("ixgbe_read_pba_num_generic"); 754179055Sjfv 755179055Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 756179055Sjfv if (ret_val) { 757179055Sjfv DEBUGOUT("NVM Read Error\n"); 758179055Sjfv return ret_val; 759215911Sjfv } else if (data == IXGBE_PBANUM_PTR_GUARD) { 760215911Sjfv DEBUGOUT("NVM Not supported\n"); 761215911Sjfv return IXGBE_NOT_IMPLEMENTED; 762179055Sjfv } 763179055Sjfv *pba_num = (u32)(data << 16); 764179055Sjfv 765179055Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 766179055Sjfv if (ret_val) { 767179055Sjfv DEBUGOUT("NVM Read Error\n"); 768179055Sjfv return ret_val; 769179055Sjfv } 770179055Sjfv *pba_num |= data; 771179055Sjfv 772179055Sjfv return IXGBE_SUCCESS; 773179055Sjfv} 774179055Sjfv 775179055Sjfv/** 776247822Sjfv * ixgbe_read_pba_raw 777247822Sjfv * @hw: pointer to the HW structure 778247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 779247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 780247822Sjfv * @max_pba_block_size: PBA block size limit 781247822Sjfv * @pba: pointer to output PBA structure 782247822Sjfv * 783247822Sjfv * Reads PBA from EEPROM image when eeprom_buf is not NULL. 784247822Sjfv * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 785247822Sjfv * 786247822Sjfv **/ 787247822Sjfvs32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 788247822Sjfv u32 eeprom_buf_size, u16 max_pba_block_size, 789247822Sjfv struct ixgbe_pba *pba) 790247822Sjfv{ 791247822Sjfv s32 ret_val; 792247822Sjfv u16 pba_block_size; 793247822Sjfv 794247822Sjfv if (pba == NULL) 795247822Sjfv return IXGBE_ERR_PARAM; 796247822Sjfv 797247822Sjfv if (eeprom_buf == NULL) { 798247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 799247822Sjfv &pba->word[0]); 800247822Sjfv if (ret_val) 801247822Sjfv return ret_val; 802247822Sjfv } else { 803247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 804247822Sjfv pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 805247822Sjfv pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 806247822Sjfv } else { 807247822Sjfv return IXGBE_ERR_PARAM; 808247822Sjfv } 809247822Sjfv } 810247822Sjfv 811247822Sjfv if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 812247822Sjfv if (pba->pba_block == NULL) 813247822Sjfv return IXGBE_ERR_PARAM; 814247822Sjfv 815247822Sjfv ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 816247822Sjfv eeprom_buf_size, 817247822Sjfv &pba_block_size); 818247822Sjfv if (ret_val) 819247822Sjfv return ret_val; 820247822Sjfv 821247822Sjfv if (pba_block_size > max_pba_block_size) 822247822Sjfv return IXGBE_ERR_PARAM; 823247822Sjfv 824247822Sjfv if (eeprom_buf == NULL) { 825247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 826247822Sjfv pba_block_size, 827247822Sjfv pba->pba_block); 828247822Sjfv if (ret_val) 829247822Sjfv return ret_val; 830247822Sjfv } else { 831247822Sjfv if (eeprom_buf_size > (u32)(pba->word[1] + 832283620Serj pba_block_size)) { 833247822Sjfv memcpy(pba->pba_block, 834247822Sjfv &eeprom_buf[pba->word[1]], 835247822Sjfv pba_block_size * sizeof(u16)); 836247822Sjfv } else { 837247822Sjfv return IXGBE_ERR_PARAM; 838247822Sjfv } 839247822Sjfv } 840247822Sjfv } 841247822Sjfv 842247822Sjfv return IXGBE_SUCCESS; 843247822Sjfv} 844247822Sjfv 845247822Sjfv/** 846247822Sjfv * ixgbe_write_pba_raw 847247822Sjfv * @hw: pointer to the HW structure 848247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 849247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 850247822Sjfv * @pba: pointer to PBA structure 851247822Sjfv * 852247822Sjfv * Writes PBA to EEPROM image when eeprom_buf is not NULL. 853247822Sjfv * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 854247822Sjfv * 855247822Sjfv **/ 856247822Sjfvs32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 857247822Sjfv u32 eeprom_buf_size, struct ixgbe_pba *pba) 858247822Sjfv{ 859247822Sjfv s32 ret_val; 860247822Sjfv 861247822Sjfv if (pba == NULL) 862247822Sjfv return IXGBE_ERR_PARAM; 863247822Sjfv 864247822Sjfv if (eeprom_buf == NULL) { 865247822Sjfv ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 866247822Sjfv &pba->word[0]); 867247822Sjfv if (ret_val) 868247822Sjfv return ret_val; 869247822Sjfv } else { 870247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 871247822Sjfv eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 872247822Sjfv eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 873247822Sjfv } else { 874247822Sjfv return IXGBE_ERR_PARAM; 875247822Sjfv } 876247822Sjfv } 877247822Sjfv 878247822Sjfv if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 879247822Sjfv if (pba->pba_block == NULL) 880247822Sjfv return IXGBE_ERR_PARAM; 881247822Sjfv 882247822Sjfv if (eeprom_buf == NULL) { 883247822Sjfv ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 884247822Sjfv pba->pba_block[0], 885247822Sjfv pba->pba_block); 886247822Sjfv if (ret_val) 887247822Sjfv return ret_val; 888247822Sjfv } else { 889247822Sjfv if (eeprom_buf_size > (u32)(pba->word[1] + 890247822Sjfv pba->pba_block[0])) { 891247822Sjfv memcpy(&eeprom_buf[pba->word[1]], 892247822Sjfv pba->pba_block, 893247822Sjfv pba->pba_block[0] * sizeof(u16)); 894247822Sjfv } else { 895247822Sjfv return IXGBE_ERR_PARAM; 896247822Sjfv } 897247822Sjfv } 898247822Sjfv } 899247822Sjfv 900247822Sjfv return IXGBE_SUCCESS; 901247822Sjfv} 902247822Sjfv 903247822Sjfv/** 904247822Sjfv * ixgbe_get_pba_block_size 905247822Sjfv * @hw: pointer to the HW structure 906247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 907247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 908247822Sjfv * @pba_data_size: pointer to output variable 909247822Sjfv * 910247822Sjfv * Returns the size of the PBA block in words. Function operates on EEPROM 911247822Sjfv * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 912247822Sjfv * EEPROM device. 913247822Sjfv * 914247822Sjfv **/ 915247822Sjfvs32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 916247822Sjfv u32 eeprom_buf_size, u16 *pba_block_size) 917247822Sjfv{ 918247822Sjfv s32 ret_val; 919247822Sjfv u16 pba_word[2]; 920247822Sjfv u16 length; 921247822Sjfv 922247822Sjfv DEBUGFUNC("ixgbe_get_pba_block_size"); 923247822Sjfv 924247822Sjfv if (eeprom_buf == NULL) { 925247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 926247822Sjfv &pba_word[0]); 927247822Sjfv if (ret_val) 928247822Sjfv return ret_val; 929247822Sjfv } else { 930247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 931247822Sjfv pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 932247822Sjfv pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 933247822Sjfv } else { 934247822Sjfv return IXGBE_ERR_PARAM; 935247822Sjfv } 936247822Sjfv } 937247822Sjfv 938247822Sjfv if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 939247822Sjfv if (eeprom_buf == NULL) { 940247822Sjfv ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 941247822Sjfv &length); 942247822Sjfv if (ret_val) 943247822Sjfv return ret_val; 944247822Sjfv } else { 945247822Sjfv if (eeprom_buf_size > pba_word[1]) 946247822Sjfv length = eeprom_buf[pba_word[1] + 0]; 947247822Sjfv else 948247822Sjfv return IXGBE_ERR_PARAM; 949247822Sjfv } 950247822Sjfv 951247822Sjfv if (length == 0xFFFF || length == 0) 952247822Sjfv return IXGBE_ERR_PBA_SECTION; 953247822Sjfv } else { 954247822Sjfv /* PBA number in legacy format, there is no PBA Block. */ 955247822Sjfv length = 0; 956247822Sjfv } 957247822Sjfv 958247822Sjfv if (pba_block_size != NULL) 959247822Sjfv *pba_block_size = length; 960247822Sjfv 961247822Sjfv return IXGBE_SUCCESS; 962247822Sjfv} 963247822Sjfv 964247822Sjfv/** 965171384Sjfv * ixgbe_get_mac_addr_generic - Generic get MAC address 966171384Sjfv * @hw: pointer to hardware structure 967171384Sjfv * @mac_addr: Adapter MAC address 968171384Sjfv * 969171384Sjfv * Reads the adapter's MAC address from first Receive Address Register (RAR0) 970171384Sjfv * A reset of the adapter must be performed prior to calling this function 971171384Sjfv * in order for the MAC address to have been loaded from the EEPROM into RAR0 972171384Sjfv **/ 973171384Sjfvs32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 974171384Sjfv{ 975171384Sjfv u32 rar_high; 976171384Sjfv u32 rar_low; 977171384Sjfv u16 i; 978171384Sjfv 979200239Sjfv DEBUGFUNC("ixgbe_get_mac_addr_generic"); 980200239Sjfv 981171384Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 982171384Sjfv rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 983171384Sjfv 984171384Sjfv for (i = 0; i < 4; i++) 985171384Sjfv mac_addr[i] = (u8)(rar_low >> (i*8)); 986171384Sjfv 987171384Sjfv for (i = 0; i < 2; i++) 988171384Sjfv mac_addr[i+4] = (u8)(rar_high >> (i*8)); 989171384Sjfv 990171384Sjfv return IXGBE_SUCCESS; 991171384Sjfv} 992171384Sjfv 993171384Sjfv/** 994251964Sjfv * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 995171384Sjfv * @hw: pointer to hardware structure 996251964Sjfv * @link_status: the link status returned by the PCI config space 997171384Sjfv * 998251964Sjfv * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 999171384Sjfv **/ 1000251964Sjfvvoid ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1001171384Sjfv{ 1002185352Sjfv struct ixgbe_mac_info *mac = &hw->mac; 1003171384Sjfv 1004283620Serj if (hw->bus.type == ixgbe_bus_type_unknown) 1005283620Serj hw->bus.type = ixgbe_bus_type_pci_express; 1006171384Sjfv 1007171384Sjfv switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1008171384Sjfv case IXGBE_PCI_LINK_WIDTH_1: 1009171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x1; 1010171384Sjfv break; 1011171384Sjfv case IXGBE_PCI_LINK_WIDTH_2: 1012171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x2; 1013171384Sjfv break; 1014171384Sjfv case IXGBE_PCI_LINK_WIDTH_4: 1015171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x4; 1016171384Sjfv break; 1017171384Sjfv case IXGBE_PCI_LINK_WIDTH_8: 1018171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x8; 1019171384Sjfv break; 1020171384Sjfv default: 1021171384Sjfv hw->bus.width = ixgbe_bus_width_unknown; 1022171384Sjfv break; 1023171384Sjfv } 1024171384Sjfv 1025171384Sjfv switch (link_status & IXGBE_PCI_LINK_SPEED) { 1026171384Sjfv case IXGBE_PCI_LINK_SPEED_2500: 1027171384Sjfv hw->bus.speed = ixgbe_bus_speed_2500; 1028171384Sjfv break; 1029171384Sjfv case IXGBE_PCI_LINK_SPEED_5000: 1030171384Sjfv hw->bus.speed = ixgbe_bus_speed_5000; 1031171384Sjfv break; 1032238149Sjfv case IXGBE_PCI_LINK_SPEED_8000: 1033238149Sjfv hw->bus.speed = ixgbe_bus_speed_8000; 1034238149Sjfv break; 1035171384Sjfv default: 1036171384Sjfv hw->bus.speed = ixgbe_bus_speed_unknown; 1037171384Sjfv break; 1038171384Sjfv } 1039171384Sjfv 1040185352Sjfv mac->ops.set_lan_id(hw); 1041251964Sjfv} 1042185352Sjfv 1043251964Sjfv/** 1044251964Sjfv * ixgbe_get_bus_info_generic - Generic set PCI bus info 1045251964Sjfv * @hw: pointer to hardware structure 1046251964Sjfv * 1047251964Sjfv * Gets the PCI bus info (speed, width, type) then calls helper function to 1048251964Sjfv * store this data within the ixgbe_hw structure. 1049251964Sjfv **/ 1050251964Sjfvs32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1051251964Sjfv{ 1052251964Sjfv u16 link_status; 1053251964Sjfv 1054251964Sjfv DEBUGFUNC("ixgbe_get_bus_info_generic"); 1055251964Sjfv 1056251964Sjfv /* Get the negotiated link width and speed from PCI config space */ 1057251964Sjfv link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1058251964Sjfv 1059251964Sjfv ixgbe_set_pci_config_data_generic(hw, link_status); 1060251964Sjfv 1061171384Sjfv return IXGBE_SUCCESS; 1062171384Sjfv} 1063171384Sjfv 1064171384Sjfv/** 1065185352Sjfv * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1066185352Sjfv * @hw: pointer to the HW structure 1067185352Sjfv * 1068315333Serj * Determines the LAN function id by reading memory-mapped registers and swaps 1069315333Serj * the port value if requested, and set MAC instance for devices that share 1070315333Serj * CS4227. 1071185352Sjfv **/ 1072185352Sjfvvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1073185352Sjfv{ 1074185352Sjfv struct ixgbe_bus_info *bus = &hw->bus; 1075185352Sjfv u32 reg; 1076315333Serj u16 ee_ctrl_4; 1077185352Sjfv 1078200239Sjfv DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1079200239Sjfv 1080185352Sjfv reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1081185352Sjfv bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1082315333Serj bus->lan_id = (u8)bus->func; 1083185352Sjfv 1084185352Sjfv /* check for a port swap */ 1085295524Ssbruno reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1086185352Sjfv if (reg & IXGBE_FACTPS_LFS) 1087185352Sjfv bus->func ^= 0x1; 1088315333Serj 1089315333Serj /* Get MAC instance from EEPROM for configuring CS4227 */ 1090315333Serj if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1091315333Serj hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1092315333Serj bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1093315333Serj IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1094315333Serj } 1095185352Sjfv} 1096185352Sjfv 1097185352Sjfv/** 1098179055Sjfv * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1099171384Sjfv * @hw: pointer to hardware structure 1100171384Sjfv * 1101171384Sjfv * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1102171384Sjfv * disables transmit and receive units. The adapter_stopped flag is used by 1103171384Sjfv * the shared code and drivers to determine if the adapter is in a stopped 1104171384Sjfv * state and should not touch the hardware. 1105171384Sjfv **/ 1106171384Sjfvs32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1107171384Sjfv{ 1108171384Sjfv u32 reg_val; 1109171384Sjfv u16 i; 1110171384Sjfv 1111200239Sjfv DEBUGFUNC("ixgbe_stop_adapter_generic"); 1112200239Sjfv 1113171384Sjfv /* 1114171384Sjfv * Set the adapter_stopped flag so other driver functions stop touching 1115171384Sjfv * the hardware 1116171384Sjfv */ 1117171384Sjfv hw->adapter_stopped = TRUE; 1118171384Sjfv 1119171384Sjfv /* Disable the receive unit */ 1120283620Serj ixgbe_disable_rx(hw); 1121171384Sjfv 1122230775Sjfv /* Clear interrupt mask to stop interrupts from being generated */ 1123171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1124171384Sjfv 1125230775Sjfv /* Clear any pending interrupts, flush previous writes */ 1126171384Sjfv IXGBE_READ_REG(hw, IXGBE_EICR); 1127171384Sjfv 1128171384Sjfv /* Disable the transmit unit. Each queue must be disabled. */ 1129230775Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) 1130230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1131230775Sjfv 1132230775Sjfv /* Disable the receive unit by stopping each queue */ 1133230775Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 1134230775Sjfv reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1135230775Sjfv reg_val &= ~IXGBE_RXDCTL_ENABLE; 1136230775Sjfv reg_val |= IXGBE_RXDCTL_SWFLSH; 1137230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1138171384Sjfv } 1139171384Sjfv 1140230775Sjfv /* flush all queues disables */ 1141230775Sjfv IXGBE_WRITE_FLUSH(hw); 1142230775Sjfv msec_delay(2); 1143230775Sjfv 1144179055Sjfv /* 1145283620Serj * Prevent the PCI-E bus from hanging by disabling PCI-E master 1146179055Sjfv * access and verify no pending requests 1147179055Sjfv */ 1148230775Sjfv return ixgbe_disable_pcie_master(hw); 1149171384Sjfv} 1150171384Sjfv 1151171384Sjfv/** 1152315333Serj * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1153315333Serj * @hw: pointer to hardware structure 1154315333Serj * 1155315333Serj * Store the index for the link active LED. This will be used to support 1156315333Serj * blinking the LED. 1157315333Serj **/ 1158315333Serjs32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1159315333Serj{ 1160315333Serj struct ixgbe_mac_info *mac = &hw->mac; 1161315333Serj u32 led_reg, led_mode; 1162315333Serj u8 i; 1163315333Serj 1164315333Serj led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1165315333Serj 1166315333Serj /* Get LED link active from the LEDCTL register */ 1167315333Serj for (i = 0; i < 4; i++) { 1168315333Serj led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1169315333Serj 1170315333Serj if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1171315333Serj IXGBE_LED_LINK_ACTIVE) { 1172315333Serj mac->led_link_act = i; 1173315333Serj return IXGBE_SUCCESS; 1174315333Serj } 1175315333Serj } 1176315333Serj 1177315333Serj /* 1178315333Serj * If LEDCTL register does not have the LED link active set, then use 1179315333Serj * known MAC defaults. 1180315333Serj */ 1181315333Serj switch (hw->mac.type) { 1182315333Serj case ixgbe_mac_X550EM_a: 1183315333Serj case ixgbe_mac_X550EM_x: 1184315333Serj mac->led_link_act = 1; 1185315333Serj break; 1186315333Serj default: 1187315333Serj mac->led_link_act = 2; 1188315333Serj } 1189315333Serj return IXGBE_SUCCESS; 1190315333Serj} 1191315333Serj 1192315333Serj/** 1193171384Sjfv * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1194171384Sjfv * @hw: pointer to hardware structure 1195171384Sjfv * @index: led number to turn on 1196171384Sjfv **/ 1197171384Sjfvs32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1198171384Sjfv{ 1199171384Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1200171384Sjfv 1201200239Sjfv DEBUGFUNC("ixgbe_led_on_generic"); 1202200239Sjfv 1203315333Serj if (index > 3) 1204315333Serj return IXGBE_ERR_PARAM; 1205315333Serj 1206171384Sjfv /* To turn on the LED, set mode to ON. */ 1207171384Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 1208171384Sjfv led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1209171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1210179055Sjfv IXGBE_WRITE_FLUSH(hw); 1211171384Sjfv 1212171384Sjfv return IXGBE_SUCCESS; 1213171384Sjfv} 1214171384Sjfv 1215171384Sjfv/** 1216171384Sjfv * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1217171384Sjfv * @hw: pointer to hardware structure 1218171384Sjfv * @index: led number to turn off 1219171384Sjfv **/ 1220171384Sjfvs32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1221171384Sjfv{ 1222171384Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1223171384Sjfv 1224200239Sjfv DEBUGFUNC("ixgbe_led_off_generic"); 1225200239Sjfv 1226315333Serj if (index > 3) 1227315333Serj return IXGBE_ERR_PARAM; 1228315333Serj 1229171384Sjfv /* To turn off the LED, set mode to OFF. */ 1230171384Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 1231171384Sjfv led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1232171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1233179055Sjfv IXGBE_WRITE_FLUSH(hw); 1234171384Sjfv 1235171384Sjfv return IXGBE_SUCCESS; 1236171384Sjfv} 1237171384Sjfv 1238171384Sjfv/** 1239171384Sjfv * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1240171384Sjfv * @hw: pointer to hardware structure 1241171384Sjfv * 1242171384Sjfv * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1243171384Sjfv * ixgbe_hw struct in order to set up EEPROM access. 1244171384Sjfv **/ 1245171384Sjfvs32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1246171384Sjfv{ 1247171384Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1248171384Sjfv u32 eec; 1249171384Sjfv u16 eeprom_size; 1250171384Sjfv 1251200239Sjfv DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1252200239Sjfv 1253171384Sjfv if (eeprom->type == ixgbe_eeprom_uninitialized) { 1254171384Sjfv eeprom->type = ixgbe_eeprom_none; 1255181003Sjfv /* Set default semaphore delay to 10ms which is a well 1256181003Sjfv * tested value */ 1257181003Sjfv eeprom->semaphore_delay = 10; 1258230775Sjfv /* Clear EEPROM page size, it will be initialized as needed */ 1259230775Sjfv eeprom->word_page_size = 0; 1260171384Sjfv 1261171384Sjfv /* 1262171384Sjfv * Check for EEPROM present first. 1263171384Sjfv * If not present leave as none 1264171384Sjfv */ 1265295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1266171384Sjfv if (eec & IXGBE_EEC_PRES) { 1267171384Sjfv eeprom->type = ixgbe_eeprom_spi; 1268171384Sjfv 1269171384Sjfv /* 1270171384Sjfv * SPI EEPROM is assumed here. This code would need to 1271171384Sjfv * change if a future EEPROM is not SPI. 1272171384Sjfv */ 1273171384Sjfv eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1274230775Sjfv IXGBE_EEC_SIZE_SHIFT); 1275171384Sjfv eeprom->word_size = 1 << (eeprom_size + 1276230775Sjfv IXGBE_EEPROM_WORD_SIZE_SHIFT); 1277171384Sjfv } 1278171384Sjfv 1279171384Sjfv if (eec & IXGBE_EEC_ADDR_SIZE) 1280171384Sjfv eeprom->address_bits = 16; 1281171384Sjfv else 1282171384Sjfv eeprom->address_bits = 8; 1283171384Sjfv DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1284230775Sjfv "%d\n", eeprom->type, eeprom->word_size, 1285230775Sjfv eeprom->address_bits); 1286171384Sjfv } 1287171384Sjfv 1288171384Sjfv return IXGBE_SUCCESS; 1289171384Sjfv} 1290171384Sjfv 1291171384Sjfv/** 1292230775Sjfv * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1293171384Sjfv * @hw: pointer to hardware structure 1294230775Sjfv * @offset: offset within the EEPROM to write 1295230775Sjfv * @words: number of word(s) 1296230775Sjfv * @data: 16 bit word(s) to write to EEPROM 1297171384Sjfv * 1298230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1299171384Sjfv **/ 1300230775Sjfvs32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1301230775Sjfv u16 words, u16 *data) 1302171384Sjfv{ 1303230775Sjfv s32 status = IXGBE_SUCCESS; 1304230775Sjfv u16 i, count; 1305171384Sjfv 1306230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1307200239Sjfv 1308179055Sjfv hw->eeprom.ops.init_params(hw); 1309179055Sjfv 1310230775Sjfv if (words == 0) { 1311230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1312230775Sjfv goto out; 1313230775Sjfv } 1314230775Sjfv 1315230775Sjfv if (offset + words > hw->eeprom.word_size) { 1316179055Sjfv status = IXGBE_ERR_EEPROM; 1317179055Sjfv goto out; 1318179055Sjfv } 1319179055Sjfv 1320230775Sjfv /* 1321230775Sjfv * The EEPROM page size cannot be queried from the chip. We do lazy 1322230775Sjfv * initialization. It is worth to do that when we write large buffer. 1323230775Sjfv */ 1324230775Sjfv if ((hw->eeprom.word_page_size == 0) && 1325230775Sjfv (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1326230775Sjfv ixgbe_detect_eeprom_page_size_generic(hw, offset); 1327230775Sjfv 1328230775Sjfv /* 1329230775Sjfv * We cannot hold synchronization semaphores for too long 1330230775Sjfv * to avoid other entity starvation. However it is more efficient 1331230775Sjfv * to read in bursts than synchronizing access for each word. 1332230775Sjfv */ 1333230775Sjfv for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1334230775Sjfv count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1335230775Sjfv IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1336230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1337230775Sjfv count, &data[i]); 1338230775Sjfv 1339230775Sjfv if (status != IXGBE_SUCCESS) 1340230775Sjfv break; 1341230775Sjfv } 1342230775Sjfv 1343230775Sjfvout: 1344230775Sjfv return status; 1345230775Sjfv} 1346230775Sjfv 1347230775Sjfv/** 1348230775Sjfv * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1349230775Sjfv * @hw: pointer to hardware structure 1350230775Sjfv * @offset: offset within the EEPROM to be written to 1351230775Sjfv * @words: number of word(s) 1352230775Sjfv * @data: 16 bit word(s) to be written to the EEPROM 1353230775Sjfv * 1354230775Sjfv * If ixgbe_eeprom_update_checksum is not called after this function, the 1355230775Sjfv * EEPROM will most likely contain an invalid checksum. 1356230775Sjfv **/ 1357230775Sjfvstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1358230775Sjfv u16 words, u16 *data) 1359230775Sjfv{ 1360230775Sjfv s32 status; 1361230775Sjfv u16 word; 1362230775Sjfv u16 page_size; 1363230775Sjfv u16 i; 1364230775Sjfv u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1365230775Sjfv 1366230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1367230775Sjfv 1368171384Sjfv /* Prepare the EEPROM for writing */ 1369171384Sjfv status = ixgbe_acquire_eeprom(hw); 1370171384Sjfv 1371171384Sjfv if (status == IXGBE_SUCCESS) { 1372171384Sjfv if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1373171384Sjfv ixgbe_release_eeprom(hw); 1374171384Sjfv status = IXGBE_ERR_EEPROM; 1375171384Sjfv } 1376171384Sjfv } 1377171384Sjfv 1378171384Sjfv if (status == IXGBE_SUCCESS) { 1379230775Sjfv for (i = 0; i < words; i++) { 1380230775Sjfv ixgbe_standby_eeprom(hw); 1381171384Sjfv 1382230775Sjfv /* Send the WRITE ENABLE command (8 bit opcode ) */ 1383230775Sjfv ixgbe_shift_out_eeprom_bits(hw, 1384230775Sjfv IXGBE_EEPROM_WREN_OPCODE_SPI, 1385230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1386171384Sjfv 1387230775Sjfv ixgbe_standby_eeprom(hw); 1388171384Sjfv 1389230775Sjfv /* 1390230775Sjfv * Some SPI eeproms use the 8th address bit embedded 1391230775Sjfv * in the opcode 1392230775Sjfv */ 1393230775Sjfv if ((hw->eeprom.address_bits == 8) && 1394230775Sjfv ((offset + i) >= 128)) 1395230775Sjfv write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1396171384Sjfv 1397230775Sjfv /* Send the Write command (8-bit opcode + addr) */ 1398230775Sjfv ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1399230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1400230775Sjfv ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1401230775Sjfv hw->eeprom.address_bits); 1402171384Sjfv 1403230775Sjfv page_size = hw->eeprom.word_page_size; 1404171384Sjfv 1405230775Sjfv /* Send the data in burst via SPI*/ 1406230775Sjfv do { 1407230775Sjfv word = data[i]; 1408230775Sjfv word = (word >> 8) | (word << 8); 1409230775Sjfv ixgbe_shift_out_eeprom_bits(hw, word, 16); 1410230775Sjfv 1411230775Sjfv if (page_size == 0) 1412230775Sjfv break; 1413230775Sjfv 1414230775Sjfv /* do not wrap around page */ 1415230775Sjfv if (((offset + i) & (page_size - 1)) == 1416230775Sjfv (page_size - 1)) 1417230775Sjfv break; 1418230775Sjfv } while (++i < words); 1419230775Sjfv 1420230775Sjfv ixgbe_standby_eeprom(hw); 1421230775Sjfv msec_delay(10); 1422230775Sjfv } 1423171384Sjfv /* Done with writing - release the EEPROM */ 1424171384Sjfv ixgbe_release_eeprom(hw); 1425171384Sjfv } 1426171384Sjfv 1427171384Sjfv return status; 1428171384Sjfv} 1429171384Sjfv 1430171384Sjfv/** 1431230775Sjfv * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1432171384Sjfv * @hw: pointer to hardware structure 1433230775Sjfv * @offset: offset within the EEPROM to be written to 1434230775Sjfv * @data: 16 bit word to be written to the EEPROM 1435171384Sjfv * 1436230775Sjfv * If ixgbe_eeprom_update_checksum is not called after this function, the 1437230775Sjfv * EEPROM will most likely contain an invalid checksum. 1438171384Sjfv **/ 1439230775Sjfvs32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1440171384Sjfv{ 1441171384Sjfv s32 status; 1442171384Sjfv 1443230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_generic"); 1444200239Sjfv 1445179055Sjfv hw->eeprom.ops.init_params(hw); 1446179055Sjfv 1447179055Sjfv if (offset >= hw->eeprom.word_size) { 1448179055Sjfv status = IXGBE_ERR_EEPROM; 1449179055Sjfv goto out; 1450179055Sjfv } 1451179055Sjfv 1452230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1453230775Sjfv 1454230775Sjfvout: 1455230775Sjfv return status; 1456230775Sjfv} 1457230775Sjfv 1458230775Sjfv/** 1459230775Sjfv * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1460230775Sjfv * @hw: pointer to hardware structure 1461230775Sjfv * @offset: offset within the EEPROM to be read 1462230775Sjfv * @data: read 16 bit words(s) from EEPROM 1463230775Sjfv * @words: number of word(s) 1464230775Sjfv * 1465230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1466230775Sjfv **/ 1467230775Sjfvs32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1468230775Sjfv u16 words, u16 *data) 1469230775Sjfv{ 1470230775Sjfv s32 status = IXGBE_SUCCESS; 1471230775Sjfv u16 i, count; 1472230775Sjfv 1473230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1474230775Sjfv 1475230775Sjfv hw->eeprom.ops.init_params(hw); 1476230775Sjfv 1477230775Sjfv if (words == 0) { 1478230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1479230775Sjfv goto out; 1480230775Sjfv } 1481230775Sjfv 1482230775Sjfv if (offset + words > hw->eeprom.word_size) { 1483230775Sjfv status = IXGBE_ERR_EEPROM; 1484230775Sjfv goto out; 1485230775Sjfv } 1486230775Sjfv 1487230775Sjfv /* 1488230775Sjfv * We cannot hold synchronization semaphores for too long 1489230775Sjfv * to avoid other entity starvation. However it is more efficient 1490230775Sjfv * to read in bursts than synchronizing access for each word. 1491230775Sjfv */ 1492230775Sjfv for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1493230775Sjfv count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1494230775Sjfv IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1495230775Sjfv 1496230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1497230775Sjfv count, &data[i]); 1498230775Sjfv 1499230775Sjfv if (status != IXGBE_SUCCESS) 1500230775Sjfv break; 1501230775Sjfv } 1502230775Sjfv 1503230775Sjfvout: 1504230775Sjfv return status; 1505230775Sjfv} 1506230775Sjfv 1507230775Sjfv/** 1508230775Sjfv * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1509230775Sjfv * @hw: pointer to hardware structure 1510230775Sjfv * @offset: offset within the EEPROM to be read 1511230775Sjfv * @words: number of word(s) 1512230775Sjfv * @data: read 16 bit word(s) from EEPROM 1513230775Sjfv * 1514230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1515230775Sjfv **/ 1516230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1517230775Sjfv u16 words, u16 *data) 1518230775Sjfv{ 1519230775Sjfv s32 status; 1520230775Sjfv u16 word_in; 1521230775Sjfv u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1522230775Sjfv u16 i; 1523230775Sjfv 1524230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1525230775Sjfv 1526171384Sjfv /* Prepare the EEPROM for reading */ 1527171384Sjfv status = ixgbe_acquire_eeprom(hw); 1528171384Sjfv 1529171384Sjfv if (status == IXGBE_SUCCESS) { 1530171384Sjfv if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1531171384Sjfv ixgbe_release_eeprom(hw); 1532171384Sjfv status = IXGBE_ERR_EEPROM; 1533171384Sjfv } 1534171384Sjfv } 1535171384Sjfv 1536171384Sjfv if (status == IXGBE_SUCCESS) { 1537230775Sjfv for (i = 0; i < words; i++) { 1538230775Sjfv ixgbe_standby_eeprom(hw); 1539230775Sjfv /* 1540230775Sjfv * Some SPI eeproms use the 8th address bit embedded 1541230775Sjfv * in the opcode 1542230775Sjfv */ 1543230775Sjfv if ((hw->eeprom.address_bits == 8) && 1544230775Sjfv ((offset + i) >= 128)) 1545230775Sjfv read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1546171384Sjfv 1547230775Sjfv /* Send the READ command (opcode + addr) */ 1548230775Sjfv ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1549230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1550230775Sjfv ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1551230775Sjfv hw->eeprom.address_bits); 1552171384Sjfv 1553230775Sjfv /* Read the data. */ 1554230775Sjfv word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1555230775Sjfv data[i] = (word_in >> 8) | (word_in << 8); 1556230775Sjfv } 1557171384Sjfv 1558171384Sjfv /* End this read operation */ 1559171384Sjfv ixgbe_release_eeprom(hw); 1560171384Sjfv } 1561171384Sjfv 1562230775Sjfv return status; 1563230775Sjfv} 1564230775Sjfv 1565230775Sjfv/** 1566230775Sjfv * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1567230775Sjfv * @hw: pointer to hardware structure 1568230775Sjfv * @offset: offset within the EEPROM to be read 1569230775Sjfv * @data: read 16 bit value from EEPROM 1570230775Sjfv * 1571230775Sjfv * Reads 16 bit value from EEPROM through bit-bang method 1572230775Sjfv **/ 1573230775Sjfvs32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1574230775Sjfv u16 *data) 1575230775Sjfv{ 1576230775Sjfv s32 status; 1577230775Sjfv 1578230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1579230775Sjfv 1580230775Sjfv hw->eeprom.ops.init_params(hw); 1581230775Sjfv 1582230775Sjfv if (offset >= hw->eeprom.word_size) { 1583230775Sjfv status = IXGBE_ERR_EEPROM; 1584230775Sjfv goto out; 1585230775Sjfv } 1586230775Sjfv 1587230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1588230775Sjfv 1589179055Sjfvout: 1590171384Sjfv return status; 1591171384Sjfv} 1592171384Sjfv 1593171384Sjfv/** 1594230775Sjfv * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1595171384Sjfv * @hw: pointer to hardware structure 1596230775Sjfv * @offset: offset of word in the EEPROM to read 1597230775Sjfv * @words: number of word(s) 1598230775Sjfv * @data: 16 bit word(s) from the EEPROM 1599171384Sjfv * 1600230775Sjfv * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1601171384Sjfv **/ 1602230775Sjfvs32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1603230775Sjfv u16 words, u16 *data) 1604171384Sjfv{ 1605171384Sjfv u32 eerd; 1606230775Sjfv s32 status = IXGBE_SUCCESS; 1607230775Sjfv u32 i; 1608171384Sjfv 1609230775Sjfv DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1610200239Sjfv 1611179055Sjfv hw->eeprom.ops.init_params(hw); 1612179055Sjfv 1613230775Sjfv if (words == 0) { 1614230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1615251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1616230775Sjfv goto out; 1617230775Sjfv } 1618230775Sjfv 1619179055Sjfv if (offset >= hw->eeprom.word_size) { 1620179055Sjfv status = IXGBE_ERR_EEPROM; 1621251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1622179055Sjfv goto out; 1623179055Sjfv } 1624179055Sjfv 1625230775Sjfv for (i = 0; i < words; i++) { 1626247822Sjfv eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1627230775Sjfv IXGBE_EEPROM_RW_REG_START; 1628171384Sjfv 1629230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1630230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1631171384Sjfv 1632230775Sjfv if (status == IXGBE_SUCCESS) { 1633230775Sjfv data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1634230775Sjfv IXGBE_EEPROM_RW_REG_DATA); 1635230775Sjfv } else { 1636230775Sjfv DEBUGOUT("Eeprom read timed out\n"); 1637230775Sjfv goto out; 1638230775Sjfv } 1639230775Sjfv } 1640230775Sjfvout: 1641230775Sjfv return status; 1642230775Sjfv} 1643171384Sjfv 1644230775Sjfv/** 1645230775Sjfv * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1646230775Sjfv * @hw: pointer to hardware structure 1647230775Sjfv * @offset: offset within the EEPROM to be used as a scratch pad 1648230775Sjfv * 1649230775Sjfv * Discover EEPROM page size by writing marching data at given offset. 1650230775Sjfv * This function is called only when we are writing a new large buffer 1651230775Sjfv * at given offset so the data would be overwritten anyway. 1652230775Sjfv **/ 1653230775Sjfvstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1654230775Sjfv u16 offset) 1655230775Sjfv{ 1656230775Sjfv u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1657230775Sjfv s32 status = IXGBE_SUCCESS; 1658230775Sjfv u16 i; 1659230775Sjfv 1660230775Sjfv DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1661230775Sjfv 1662230775Sjfv for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1663230775Sjfv data[i] = i; 1664230775Sjfv 1665230775Sjfv hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1666230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1667230775Sjfv IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1668230775Sjfv hw->eeprom.word_page_size = 0; 1669230775Sjfv if (status != IXGBE_SUCCESS) 1670230775Sjfv goto out; 1671230775Sjfv 1672230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1673230775Sjfv if (status != IXGBE_SUCCESS) 1674230775Sjfv goto out; 1675230775Sjfv 1676230775Sjfv /* 1677230775Sjfv * When writing in burst more than the actual page size 1678230775Sjfv * EEPROM address wraps around current page. 1679230775Sjfv */ 1680230775Sjfv hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1681230775Sjfv 1682230775Sjfv DEBUGOUT1("Detected EEPROM page size = %d words.", 1683230775Sjfv hw->eeprom.word_page_size); 1684179055Sjfvout: 1685171384Sjfv return status; 1686171384Sjfv} 1687171384Sjfv 1688171384Sjfv/** 1689230775Sjfv * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1690215911Sjfv * @hw: pointer to hardware structure 1691230775Sjfv * @offset: offset of word in the EEPROM to read 1692230775Sjfv * @data: word read from the EEPROM 1693230775Sjfv * 1694230775Sjfv * Reads a 16 bit word from the EEPROM using the EERD register. 1695230775Sjfv **/ 1696230775Sjfvs32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1697230775Sjfv{ 1698230775Sjfv return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1699230775Sjfv} 1700230775Sjfv 1701230775Sjfv/** 1702230775Sjfv * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1703230775Sjfv * @hw: pointer to hardware structure 1704215911Sjfv * @offset: offset of word in the EEPROM to write 1705230775Sjfv * @words: number of word(s) 1706230775Sjfv * @data: word(s) write to the EEPROM 1707215911Sjfv * 1708230775Sjfv * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1709215911Sjfv **/ 1710230775Sjfvs32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1711230775Sjfv u16 words, u16 *data) 1712215911Sjfv{ 1713215911Sjfv u32 eewr; 1714230775Sjfv s32 status = IXGBE_SUCCESS; 1715230775Sjfv u16 i; 1716215911Sjfv 1717215911Sjfv DEBUGFUNC("ixgbe_write_eewr_generic"); 1718215911Sjfv 1719215911Sjfv hw->eeprom.ops.init_params(hw); 1720215911Sjfv 1721230775Sjfv if (words == 0) { 1722230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1723251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1724230775Sjfv goto out; 1725230775Sjfv } 1726230775Sjfv 1727215911Sjfv if (offset >= hw->eeprom.word_size) { 1728215911Sjfv status = IXGBE_ERR_EEPROM; 1729251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1730215911Sjfv goto out; 1731215911Sjfv } 1732215911Sjfv 1733230775Sjfv for (i = 0; i < words; i++) { 1734230775Sjfv eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1735230775Sjfv (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1736230775Sjfv IXGBE_EEPROM_RW_REG_START; 1737215911Sjfv 1738230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1739230775Sjfv if (status != IXGBE_SUCCESS) { 1740230775Sjfv DEBUGOUT("Eeprom write EEWR timed out\n"); 1741230775Sjfv goto out; 1742230775Sjfv } 1743215911Sjfv 1744230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1745215911Sjfv 1746230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1747230775Sjfv if (status != IXGBE_SUCCESS) { 1748230775Sjfv DEBUGOUT("Eeprom write EEWR timed out\n"); 1749230775Sjfv goto out; 1750230775Sjfv } 1751215911Sjfv } 1752215911Sjfv 1753215911Sjfvout: 1754215911Sjfv return status; 1755215911Sjfv} 1756215911Sjfv 1757215911Sjfv/** 1758230775Sjfv * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1759230775Sjfv * @hw: pointer to hardware structure 1760230775Sjfv * @offset: offset of word in the EEPROM to write 1761230775Sjfv * @data: word write to the EEPROM 1762230775Sjfv * 1763230775Sjfv * Write a 16 bit word to the EEPROM using the EEWR register. 1764230775Sjfv **/ 1765230775Sjfvs32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1766230775Sjfv{ 1767230775Sjfv return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1768230775Sjfv} 1769230775Sjfv 1770230775Sjfv/** 1771200239Sjfv * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1772171384Sjfv * @hw: pointer to hardware structure 1773200239Sjfv * @ee_reg: EEPROM flag for polling 1774171384Sjfv * 1775200239Sjfv * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1776200239Sjfv * read or write is done respectively. 1777171384Sjfv **/ 1778200239Sjfvs32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1779171384Sjfv{ 1780171384Sjfv u32 i; 1781171384Sjfv u32 reg; 1782171384Sjfv s32 status = IXGBE_ERR_EEPROM; 1783171384Sjfv 1784200239Sjfv DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1785200239Sjfv 1786200239Sjfv for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1787200239Sjfv if (ee_reg == IXGBE_NVM_POLL_READ) 1788200239Sjfv reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1789200239Sjfv else 1790200239Sjfv reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1791200239Sjfv 1792200239Sjfv if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1793171384Sjfv status = IXGBE_SUCCESS; 1794171384Sjfv break; 1795171384Sjfv } 1796171384Sjfv usec_delay(5); 1797171384Sjfv } 1798251964Sjfv 1799251964Sjfv if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1800251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1801251964Sjfv "EEPROM read/write done polling timed out"); 1802251964Sjfv 1803171384Sjfv return status; 1804171384Sjfv} 1805171384Sjfv 1806171384Sjfv/** 1807171384Sjfv * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1808171384Sjfv * @hw: pointer to hardware structure 1809171384Sjfv * 1810171384Sjfv * Prepares EEPROM for access using bit-bang method. This function should 1811171384Sjfv * be called before issuing a command to the EEPROM. 1812171384Sjfv **/ 1813171384Sjfvstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1814171384Sjfv{ 1815171384Sjfv s32 status = IXGBE_SUCCESS; 1816171384Sjfv u32 eec; 1817171384Sjfv u32 i; 1818171384Sjfv 1819200239Sjfv DEBUGFUNC("ixgbe_acquire_eeprom"); 1820200239Sjfv 1821230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1822230775Sjfv != IXGBE_SUCCESS) 1823171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 1824171384Sjfv 1825171384Sjfv if (status == IXGBE_SUCCESS) { 1826295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1827171384Sjfv 1828171384Sjfv /* Request EEPROM Access */ 1829171384Sjfv eec |= IXGBE_EEC_REQ; 1830295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1831171384Sjfv 1832171384Sjfv for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1833295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1834171384Sjfv if (eec & IXGBE_EEC_GNT) 1835171384Sjfv break; 1836171384Sjfv usec_delay(5); 1837171384Sjfv } 1838171384Sjfv 1839179055Sjfv /* Release if grant not acquired */ 1840171384Sjfv if (!(eec & IXGBE_EEC_GNT)) { 1841171384Sjfv eec &= ~IXGBE_EEC_REQ; 1842295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1843171384Sjfv DEBUGOUT("Could not acquire EEPROM grant\n"); 1844171384Sjfv 1845230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1846171384Sjfv status = IXGBE_ERR_EEPROM; 1847171384Sjfv } 1848171384Sjfv 1849215911Sjfv /* Setup EEPROM for Read/Write */ 1850215911Sjfv if (status == IXGBE_SUCCESS) { 1851215911Sjfv /* Clear CS and SK */ 1852215911Sjfv eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1853295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1854215911Sjfv IXGBE_WRITE_FLUSH(hw); 1855215911Sjfv usec_delay(1); 1856215911Sjfv } 1857171384Sjfv } 1858171384Sjfv return status; 1859171384Sjfv} 1860171384Sjfv 1861171384Sjfv/** 1862171384Sjfv * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1863171384Sjfv * @hw: pointer to hardware structure 1864171384Sjfv * 1865171384Sjfv * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1866171384Sjfv **/ 1867171384Sjfvstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1868171384Sjfv{ 1869171384Sjfv s32 status = IXGBE_ERR_EEPROM; 1870194875Sjfv u32 timeout = 2000; 1871171384Sjfv u32 i; 1872171384Sjfv u32 swsm; 1873171384Sjfv 1874200239Sjfv DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1875200239Sjfv 1876215911Sjfv 1877171384Sjfv /* Get SMBI software semaphore between device drivers first */ 1878171384Sjfv for (i = 0; i < timeout; i++) { 1879171384Sjfv /* 1880171384Sjfv * If the SMBI bit is 0 when we read it, then the bit will be 1881171384Sjfv * set and we have the semaphore 1882171384Sjfv */ 1883295524Ssbruno swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1884171384Sjfv if (!(swsm & IXGBE_SWSM_SMBI)) { 1885171384Sjfv status = IXGBE_SUCCESS; 1886171384Sjfv break; 1887171384Sjfv } 1888190873Sjfv usec_delay(50); 1889171384Sjfv } 1890171384Sjfv 1891230775Sjfv if (i == timeout) { 1892230775Sjfv DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1893230775Sjfv "not granted.\n"); 1894230775Sjfv /* 1895230775Sjfv * this release is particularly important because our attempts 1896230775Sjfv * above to get the semaphore may have succeeded, and if there 1897230775Sjfv * was a timeout, we should unconditionally clear the semaphore 1898230775Sjfv * bits to free the driver to make progress 1899230775Sjfv */ 1900230775Sjfv ixgbe_release_eeprom_semaphore(hw); 1901230775Sjfv 1902230775Sjfv usec_delay(50); 1903230775Sjfv /* 1904230775Sjfv * one last try 1905230775Sjfv * If the SMBI bit is 0 when we read it, then the bit will be 1906230775Sjfv * set and we have the semaphore 1907230775Sjfv */ 1908295524Ssbruno swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1909230775Sjfv if (!(swsm & IXGBE_SWSM_SMBI)) 1910230775Sjfv status = IXGBE_SUCCESS; 1911230775Sjfv } 1912230775Sjfv 1913171384Sjfv /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1914171384Sjfv if (status == IXGBE_SUCCESS) { 1915171384Sjfv for (i = 0; i < timeout; i++) { 1916295524Ssbruno swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1917171384Sjfv 1918171384Sjfv /* Set the SW EEPROM semaphore bit to request access */ 1919171384Sjfv swsm |= IXGBE_SWSM_SWESMBI; 1920295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1921171384Sjfv 1922171384Sjfv /* 1923171384Sjfv * If we set the bit successfully then we got the 1924171384Sjfv * semaphore. 1925171384Sjfv */ 1926295524Ssbruno swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1927171384Sjfv if (swsm & IXGBE_SWSM_SWESMBI) 1928171384Sjfv break; 1929171384Sjfv 1930171384Sjfv usec_delay(50); 1931171384Sjfv } 1932171384Sjfv 1933171384Sjfv /* 1934171384Sjfv * Release semaphores and return error if SW EEPROM semaphore 1935171384Sjfv * was not granted because we don't have access to the EEPROM 1936171384Sjfv */ 1937171384Sjfv if (i >= timeout) { 1938251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1939251964Sjfv "SWESMBI Software EEPROM semaphore not granted.\n"); 1940171384Sjfv ixgbe_release_eeprom_semaphore(hw); 1941171384Sjfv status = IXGBE_ERR_EEPROM; 1942171384Sjfv } 1943190873Sjfv } else { 1944251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1945251964Sjfv "Software semaphore SMBI between device drivers " 1946251964Sjfv "not granted.\n"); 1947171384Sjfv } 1948171384Sjfv 1949171384Sjfv return status; 1950171384Sjfv} 1951171384Sjfv 1952171384Sjfv/** 1953171384Sjfv * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1954171384Sjfv * @hw: pointer to hardware structure 1955171384Sjfv * 1956171384Sjfv * This function clears hardware semaphore bits. 1957171384Sjfv **/ 1958171384Sjfvstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1959171384Sjfv{ 1960171384Sjfv u32 swsm; 1961171384Sjfv 1962200239Sjfv DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1963200239Sjfv 1964171384Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1965171384Sjfv 1966171384Sjfv /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1967171384Sjfv swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1968171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1969179055Sjfv IXGBE_WRITE_FLUSH(hw); 1970171384Sjfv} 1971171384Sjfv 1972171384Sjfv/** 1973171384Sjfv * ixgbe_ready_eeprom - Polls for EEPROM ready 1974171384Sjfv * @hw: pointer to hardware structure 1975171384Sjfv **/ 1976171384Sjfvstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1977171384Sjfv{ 1978171384Sjfv s32 status = IXGBE_SUCCESS; 1979171384Sjfv u16 i; 1980171384Sjfv u8 spi_stat_reg; 1981171384Sjfv 1982200239Sjfv DEBUGFUNC("ixgbe_ready_eeprom"); 1983200239Sjfv 1984171384Sjfv /* 1985171384Sjfv * Read "Status Register" repeatedly until the LSB is cleared. The 1986171384Sjfv * EEPROM will signal that the command has been completed by clearing 1987171384Sjfv * bit 0 of the internal status register. If it's not cleared within 1988171384Sjfv * 5 milliseconds, then error out. 1989171384Sjfv */ 1990171384Sjfv for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1991171384Sjfv ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1992230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1993171384Sjfv spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1994171384Sjfv if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1995171384Sjfv break; 1996171384Sjfv 1997171384Sjfv usec_delay(5); 1998171384Sjfv ixgbe_standby_eeprom(hw); 1999171384Sjfv }; 2000171384Sjfv 2001171384Sjfv /* 2002171384Sjfv * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2003171384Sjfv * devices (and only 0-5mSec on 5V devices) 2004171384Sjfv */ 2005171384Sjfv if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2006171384Sjfv DEBUGOUT("SPI EEPROM Status error\n"); 2007171384Sjfv status = IXGBE_ERR_EEPROM; 2008171384Sjfv } 2009171384Sjfv 2010171384Sjfv return status; 2011171384Sjfv} 2012171384Sjfv 2013171384Sjfv/** 2014171384Sjfv * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2015171384Sjfv * @hw: pointer to hardware structure 2016171384Sjfv **/ 2017171384Sjfvstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2018171384Sjfv{ 2019171384Sjfv u32 eec; 2020171384Sjfv 2021200239Sjfv DEBUGFUNC("ixgbe_standby_eeprom"); 2022200239Sjfv 2023295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2024171384Sjfv 2025171384Sjfv /* Toggle CS to flush commands */ 2026171384Sjfv eec |= IXGBE_EEC_CS; 2027295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2028171384Sjfv IXGBE_WRITE_FLUSH(hw); 2029171384Sjfv usec_delay(1); 2030171384Sjfv eec &= ~IXGBE_EEC_CS; 2031295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2032171384Sjfv IXGBE_WRITE_FLUSH(hw); 2033171384Sjfv usec_delay(1); 2034171384Sjfv} 2035171384Sjfv 2036171384Sjfv/** 2037171384Sjfv * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2038171384Sjfv * @hw: pointer to hardware structure 2039171384Sjfv * @data: data to send to the EEPROM 2040171384Sjfv * @count: number of bits to shift out 2041171384Sjfv **/ 2042171384Sjfvstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2043230775Sjfv u16 count) 2044171384Sjfv{ 2045171384Sjfv u32 eec; 2046171384Sjfv u32 mask; 2047171384Sjfv u32 i; 2048171384Sjfv 2049200239Sjfv DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2050200239Sjfv 2051295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2052171384Sjfv 2053171384Sjfv /* 2054171384Sjfv * Mask is used to shift "count" bits of "data" out to the EEPROM 2055171384Sjfv * one bit at a time. Determine the starting bit based on count 2056171384Sjfv */ 2057171384Sjfv mask = 0x01 << (count - 1); 2058171384Sjfv 2059171384Sjfv for (i = 0; i < count; i++) { 2060171384Sjfv /* 2061171384Sjfv * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2062171384Sjfv * "1", and then raising and then lowering the clock (the SK 2063171384Sjfv * bit controls the clock input to the EEPROM). A "0" is 2064171384Sjfv * shifted out to the EEPROM by setting "DI" to "0" and then 2065171384Sjfv * raising and then lowering the clock. 2066171384Sjfv */ 2067171384Sjfv if (data & mask) 2068171384Sjfv eec |= IXGBE_EEC_DI; 2069171384Sjfv else 2070171384Sjfv eec &= ~IXGBE_EEC_DI; 2071171384Sjfv 2072295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2073171384Sjfv IXGBE_WRITE_FLUSH(hw); 2074171384Sjfv 2075171384Sjfv usec_delay(1); 2076171384Sjfv 2077171384Sjfv ixgbe_raise_eeprom_clk(hw, &eec); 2078171384Sjfv ixgbe_lower_eeprom_clk(hw, &eec); 2079171384Sjfv 2080171384Sjfv /* 2081171384Sjfv * Shift mask to signify next bit of data to shift in to the 2082171384Sjfv * EEPROM 2083171384Sjfv */ 2084171384Sjfv mask = mask >> 1; 2085171384Sjfv }; 2086171384Sjfv 2087171384Sjfv /* We leave the "DI" bit set to "0" when we leave this routine. */ 2088171384Sjfv eec &= ~IXGBE_EEC_DI; 2089295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2090171384Sjfv IXGBE_WRITE_FLUSH(hw); 2091171384Sjfv} 2092171384Sjfv 2093171384Sjfv/** 2094171384Sjfv * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2095171384Sjfv * @hw: pointer to hardware structure 2096171384Sjfv **/ 2097171384Sjfvstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2098171384Sjfv{ 2099171384Sjfv u32 eec; 2100171384Sjfv u32 i; 2101171384Sjfv u16 data = 0; 2102171384Sjfv 2103200239Sjfv DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2104200239Sjfv 2105171384Sjfv /* 2106171384Sjfv * In order to read a register from the EEPROM, we need to shift 2107171384Sjfv * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2108171384Sjfv * the clock input to the EEPROM (setting the SK bit), and then reading 2109171384Sjfv * the value of the "DO" bit. During this "shifting in" process the 2110171384Sjfv * "DI" bit should always be clear. 2111171384Sjfv */ 2112295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2113171384Sjfv 2114171384Sjfv eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2115171384Sjfv 2116171384Sjfv for (i = 0; i < count; i++) { 2117171384Sjfv data = data << 1; 2118171384Sjfv ixgbe_raise_eeprom_clk(hw, &eec); 2119171384Sjfv 2120295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2121171384Sjfv 2122171384Sjfv eec &= ~(IXGBE_EEC_DI); 2123171384Sjfv if (eec & IXGBE_EEC_DO) 2124171384Sjfv data |= 1; 2125171384Sjfv 2126171384Sjfv ixgbe_lower_eeprom_clk(hw, &eec); 2127171384Sjfv } 2128171384Sjfv 2129171384Sjfv return data; 2130171384Sjfv} 2131171384Sjfv 2132171384Sjfv/** 2133171384Sjfv * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2134171384Sjfv * @hw: pointer to hardware structure 2135171384Sjfv * @eec: EEC register's current value 2136171384Sjfv **/ 2137171384Sjfvstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2138171384Sjfv{ 2139200239Sjfv DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2140200239Sjfv 2141171384Sjfv /* 2142171384Sjfv * Raise the clock input to the EEPROM 2143171384Sjfv * (setting the SK bit), then delay 2144171384Sjfv */ 2145171384Sjfv *eec = *eec | IXGBE_EEC_SK; 2146295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2147171384Sjfv IXGBE_WRITE_FLUSH(hw); 2148171384Sjfv usec_delay(1); 2149171384Sjfv} 2150171384Sjfv 2151171384Sjfv/** 2152171384Sjfv * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2153171384Sjfv * @hw: pointer to hardware structure 2154171384Sjfv * @eecd: EECD's current value 2155171384Sjfv **/ 2156171384Sjfvstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2157171384Sjfv{ 2158200239Sjfv DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2159200239Sjfv 2160171384Sjfv /* 2161171384Sjfv * Lower the clock input to the EEPROM (clearing the SK bit), then 2162171384Sjfv * delay 2163171384Sjfv */ 2164171384Sjfv *eec = *eec & ~IXGBE_EEC_SK; 2165295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2166171384Sjfv IXGBE_WRITE_FLUSH(hw); 2167171384Sjfv usec_delay(1); 2168171384Sjfv} 2169171384Sjfv 2170171384Sjfv/** 2171171384Sjfv * ixgbe_release_eeprom - Release EEPROM, release semaphores 2172171384Sjfv * @hw: pointer to hardware structure 2173171384Sjfv **/ 2174171384Sjfvstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2175171384Sjfv{ 2176171384Sjfv u32 eec; 2177171384Sjfv 2178200239Sjfv DEBUGFUNC("ixgbe_release_eeprom"); 2179200239Sjfv 2180295524Ssbruno eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2181171384Sjfv 2182171384Sjfv eec |= IXGBE_EEC_CS; /* Pull CS high */ 2183171384Sjfv eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2184171384Sjfv 2185295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2186171384Sjfv IXGBE_WRITE_FLUSH(hw); 2187171384Sjfv 2188171384Sjfv usec_delay(1); 2189171384Sjfv 2190171384Sjfv /* Stop requesting EEPROM access */ 2191171384Sjfv eec &= ~IXGBE_EEC_REQ; 2192295524Ssbruno IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2193171384Sjfv 2194230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2195194875Sjfv 2196194875Sjfv /* Delay before attempt to obtain semaphore again to allow FW access */ 2197194875Sjfv msec_delay(hw->eeprom.semaphore_delay); 2198171384Sjfv} 2199171384Sjfv 2200171384Sjfv/** 2201200239Sjfv * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2202171384Sjfv * @hw: pointer to hardware structure 2203283620Serj * 2204283620Serj * Returns a negative error code on error, or the 16-bit checksum 2205171384Sjfv **/ 2206283620Serjs32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2207171384Sjfv{ 2208171384Sjfv u16 i; 2209171384Sjfv u16 j; 2210171384Sjfv u16 checksum = 0; 2211171384Sjfv u16 length = 0; 2212171384Sjfv u16 pointer = 0; 2213171384Sjfv u16 word = 0; 2214171384Sjfv 2215200239Sjfv DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2216200239Sjfv 2217171384Sjfv /* Include 0x0-0x3F in the checksum */ 2218171384Sjfv for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2219283620Serj if (hw->eeprom.ops.read(hw, i, &word)) { 2220171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2221283620Serj return IXGBE_ERR_EEPROM; 2222171384Sjfv } 2223171384Sjfv checksum += word; 2224171384Sjfv } 2225171384Sjfv 2226171384Sjfv /* Include all data from pointers except for the fw pointer */ 2227171384Sjfv for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2228283620Serj if (hw->eeprom.ops.read(hw, i, &pointer)) { 2229283620Serj DEBUGOUT("EEPROM read failed\n"); 2230283620Serj return IXGBE_ERR_EEPROM; 2231283620Serj } 2232171384Sjfv 2233283620Serj /* If the pointer seems invalid */ 2234283620Serj if (pointer == 0xFFFF || pointer == 0) 2235283620Serj continue; 2236171384Sjfv 2237283620Serj if (hw->eeprom.ops.read(hw, pointer, &length)) { 2238283620Serj DEBUGOUT("EEPROM read failed\n"); 2239283620Serj return IXGBE_ERR_EEPROM; 2240283620Serj } 2241283620Serj 2242283620Serj if (length == 0xFFFF || length == 0) 2243283620Serj continue; 2244283620Serj 2245283620Serj for (j = pointer + 1; j <= pointer + length; j++) { 2246283620Serj if (hw->eeprom.ops.read(hw, j, &word)) { 2247283620Serj DEBUGOUT("EEPROM read failed\n"); 2248283620Serj return IXGBE_ERR_EEPROM; 2249171384Sjfv } 2250283620Serj checksum += word; 2251171384Sjfv } 2252171384Sjfv } 2253171384Sjfv 2254171384Sjfv checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2255171384Sjfv 2256283620Serj return (s32)checksum; 2257171384Sjfv} 2258171384Sjfv 2259171384Sjfv/** 2260171384Sjfv * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2261171384Sjfv * @hw: pointer to hardware structure 2262171384Sjfv * @checksum_val: calculated checksum 2263171384Sjfv * 2264171384Sjfv * Performs checksum calculation and validates the EEPROM checksum. If the 2265171384Sjfv * caller does not need checksum_val, the value can be NULL. 2266171384Sjfv **/ 2267171384Sjfvs32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2268230775Sjfv u16 *checksum_val) 2269171384Sjfv{ 2270171384Sjfv s32 status; 2271171384Sjfv u16 checksum; 2272171384Sjfv u16 read_checksum = 0; 2273171384Sjfv 2274200239Sjfv DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2275200239Sjfv 2276283620Serj /* Read the first word from the EEPROM. If this times out or fails, do 2277171384Sjfv * not continue or we could be in for a very long wait while every 2278171384Sjfv * EEPROM read fails 2279171384Sjfv */ 2280179055Sjfv status = hw->eeprom.ops.read(hw, 0, &checksum); 2281283620Serj if (status) { 2282283620Serj DEBUGOUT("EEPROM read failed\n"); 2283283620Serj return status; 2284283620Serj } 2285171384Sjfv 2286283620Serj status = hw->eeprom.ops.calc_checksum(hw); 2287283620Serj if (status < 0) 2288283620Serj return status; 2289171384Sjfv 2290283620Serj checksum = (u16)(status & 0xffff); 2291171384Sjfv 2292283620Serj status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2293283620Serj if (status) { 2294171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2295283620Serj return status; 2296171384Sjfv } 2297171384Sjfv 2298283620Serj /* Verify read checksum from EEPROM is the same as 2299283620Serj * calculated checksum 2300283620Serj */ 2301283620Serj if (read_checksum != checksum) 2302283620Serj status = IXGBE_ERR_EEPROM_CHECKSUM; 2303283620Serj 2304283620Serj /* If the user cares, return the calculated checksum */ 2305283620Serj if (checksum_val) 2306283620Serj *checksum_val = checksum; 2307283620Serj 2308171384Sjfv return status; 2309171384Sjfv} 2310171384Sjfv 2311171384Sjfv/** 2312179055Sjfv * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2313171384Sjfv * @hw: pointer to hardware structure 2314171384Sjfv **/ 2315171384Sjfvs32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2316171384Sjfv{ 2317171384Sjfv s32 status; 2318171384Sjfv u16 checksum; 2319171384Sjfv 2320200239Sjfv DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2321200239Sjfv 2322283620Serj /* Read the first word from the EEPROM. If this times out or fails, do 2323171384Sjfv * not continue or we could be in for a very long wait while every 2324171384Sjfv * EEPROM read fails 2325171384Sjfv */ 2326179055Sjfv status = hw->eeprom.ops.read(hw, 0, &checksum); 2327283620Serj if (status) { 2328171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2329283620Serj return status; 2330171384Sjfv } 2331171384Sjfv 2332283620Serj status = hw->eeprom.ops.calc_checksum(hw); 2333283620Serj if (status < 0) 2334283620Serj return status; 2335283620Serj 2336283620Serj checksum = (u16)(status & 0xffff); 2337283620Serj 2338283620Serj status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2339283620Serj 2340171384Sjfv return status; 2341171384Sjfv} 2342171384Sjfv 2343171384Sjfv/** 2344171384Sjfv * ixgbe_validate_mac_addr - Validate MAC address 2345171384Sjfv * @mac_addr: pointer to MAC address. 2346171384Sjfv * 2347315333Serj * Tests a MAC address to ensure it is a valid Individual Address. 2348171384Sjfv **/ 2349171384Sjfvs32 ixgbe_validate_mac_addr(u8 *mac_addr) 2350171384Sjfv{ 2351171384Sjfv s32 status = IXGBE_SUCCESS; 2352171384Sjfv 2353200239Sjfv DEBUGFUNC("ixgbe_validate_mac_addr"); 2354200239Sjfv 2355171384Sjfv /* Make sure it is not a multicast address */ 2356171384Sjfv if (IXGBE_IS_MULTICAST(mac_addr)) { 2357171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2358171384Sjfv /* Not a broadcast address */ 2359171384Sjfv } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2360171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2361171384Sjfv /* Reject the zero address */ 2362171384Sjfv } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2363230775Sjfv mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2364171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2365171384Sjfv } 2366171384Sjfv return status; 2367171384Sjfv} 2368171384Sjfv 2369171384Sjfv/** 2370179055Sjfv * ixgbe_set_rar_generic - Set Rx address register 2371171384Sjfv * @hw: pointer to hardware structure 2372179055Sjfv * @index: Receive address register to write 2373171384Sjfv * @addr: Address to put into receive address register 2374179055Sjfv * @vmdq: VMDq "set" or "pool" index 2375171384Sjfv * @enable_addr: set flag that address is active 2376171384Sjfv * 2377171384Sjfv * Puts an ethernet address into a receive address register. 2378171384Sjfv **/ 2379179055Sjfvs32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2380230775Sjfv u32 enable_addr) 2381171384Sjfv{ 2382171384Sjfv u32 rar_low, rar_high; 2383179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2384171384Sjfv 2385200239Sjfv DEBUGFUNC("ixgbe_set_rar_generic"); 2386200239Sjfv 2387215911Sjfv /* Make sure we are using a valid rar index range */ 2388215911Sjfv if (index >= rar_entries) { 2389251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2390251964Sjfv "RAR index %d is out of range.\n", index); 2391215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 2392215911Sjfv } 2393215911Sjfv 2394179055Sjfv /* setup VMDq pool selection before this RAR gets enabled */ 2395179055Sjfv hw->mac.ops.set_vmdq(hw, index, vmdq); 2396171384Sjfv 2397215911Sjfv /* 2398215911Sjfv * HW expects these in little endian so we reverse the byte 2399215911Sjfv * order from network order (big endian) to little endian 2400215911Sjfv */ 2401215911Sjfv rar_low = ((u32)addr[0] | 2402230775Sjfv ((u32)addr[1] << 8) | 2403230775Sjfv ((u32)addr[2] << 16) | 2404230775Sjfv ((u32)addr[3] << 24)); 2405215911Sjfv /* 2406215911Sjfv * Some parts put the VMDq setting in the extra RAH bits, 2407215911Sjfv * so save everything except the lower 16 bits that hold part 2408215911Sjfv * of the address and the address valid bit. 2409215911Sjfv */ 2410215911Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2411215911Sjfv rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2412215911Sjfv rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2413171384Sjfv 2414215911Sjfv if (enable_addr != 0) 2415215911Sjfv rar_high |= IXGBE_RAH_AV; 2416171384Sjfv 2417215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2418215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2419171384Sjfv 2420171384Sjfv return IXGBE_SUCCESS; 2421171384Sjfv} 2422171384Sjfv 2423171384Sjfv/** 2424181003Sjfv * ixgbe_clear_rar_generic - Remove Rx address register 2425181003Sjfv * @hw: pointer to hardware structure 2426181003Sjfv * @index: Receive address register to write 2427181003Sjfv * 2428181003Sjfv * Clears an ethernet address from a receive address register. 2429181003Sjfv **/ 2430181003Sjfvs32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2431181003Sjfv{ 2432181003Sjfv u32 rar_high; 2433181003Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2434181003Sjfv 2435200239Sjfv DEBUGFUNC("ixgbe_clear_rar_generic"); 2436200239Sjfv 2437181003Sjfv /* Make sure we are using a valid rar index range */ 2438215911Sjfv if (index >= rar_entries) { 2439251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2440251964Sjfv "RAR index %d is out of range.\n", index); 2441215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 2442181003Sjfv } 2443181003Sjfv 2444215911Sjfv /* 2445215911Sjfv * Some parts put the VMDq setting in the extra RAH bits, 2446215911Sjfv * so save everything except the lower 16 bits that hold part 2447215911Sjfv * of the address and the address valid bit. 2448215911Sjfv */ 2449215911Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2450215911Sjfv rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2451215911Sjfv 2452215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2453215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2454215911Sjfv 2455181003Sjfv /* clear VMDq pool/queue selection for this RAR */ 2456181003Sjfv hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2457181003Sjfv 2458181003Sjfv return IXGBE_SUCCESS; 2459181003Sjfv} 2460181003Sjfv 2461181003Sjfv/** 2462171384Sjfv * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2463171384Sjfv * @hw: pointer to hardware structure 2464171384Sjfv * 2465171384Sjfv * Places the MAC address in receive address register 0 and clears the rest 2466179055Sjfv * of the receive address registers. Clears the multicast table. Assumes 2467171384Sjfv * the receiver is in reset when the routine is called. 2468171384Sjfv **/ 2469171384Sjfvs32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2470171384Sjfv{ 2471171384Sjfv u32 i; 2472179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2473171384Sjfv 2474200239Sjfv DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2475200239Sjfv 2476171384Sjfv /* 2477171384Sjfv * If the current mac address is valid, assume it is a software override 2478171384Sjfv * to the permanent address. 2479171384Sjfv * Otherwise, use the permanent address from the eeprom. 2480171384Sjfv */ 2481171384Sjfv if (ixgbe_validate_mac_addr(hw->mac.addr) == 2482171384Sjfv IXGBE_ERR_INVALID_MAC_ADDR) { 2483171384Sjfv /* Get the MAC address from the RAR0 for later reference */ 2484179055Sjfv hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2485171384Sjfv 2486171384Sjfv DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2487230775Sjfv hw->mac.addr[0], hw->mac.addr[1], 2488230775Sjfv hw->mac.addr[2]); 2489171384Sjfv DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2490230775Sjfv hw->mac.addr[4], hw->mac.addr[5]); 2491171384Sjfv } else { 2492171384Sjfv /* Setup the receive address. */ 2493171384Sjfv DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2494171384Sjfv DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2495230775Sjfv hw->mac.addr[0], hw->mac.addr[1], 2496230775Sjfv hw->mac.addr[2]); 2497171384Sjfv DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2498230775Sjfv hw->mac.addr[4], hw->mac.addr[5]); 2499171384Sjfv 2500179055Sjfv hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2501315333Serj } 2502217593Sjfv 2503315333Serj /* clear VMDq pool/queue selection for RAR 0 */ 2504315333Serj hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2505315333Serj 2506179055Sjfv hw->addr_ctrl.overflow_promisc = 0; 2507171384Sjfv 2508171384Sjfv hw->addr_ctrl.rar_used_count = 1; 2509171384Sjfv 2510171384Sjfv /* Zero out the other receive addresses. */ 2511179055Sjfv DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2512171384Sjfv for (i = 1; i < rar_entries; i++) { 2513171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2514171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2515171384Sjfv } 2516171384Sjfv 2517171384Sjfv /* Clear the MTA */ 2518171384Sjfv hw->addr_ctrl.mta_in_use = 0; 2519171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2520171384Sjfv 2521171384Sjfv DEBUGOUT(" Clearing MTA\n"); 2522179055Sjfv for (i = 0; i < hw->mac.mcft_size; i++) 2523171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2524171384Sjfv 2525181003Sjfv ixgbe_init_uta_tables(hw); 2526181003Sjfv 2527171384Sjfv return IXGBE_SUCCESS; 2528171384Sjfv} 2529171384Sjfv 2530171384Sjfv/** 2531179055Sjfv * ixgbe_add_uc_addr - Adds a secondary unicast address. 2532179055Sjfv * @hw: pointer to hardware structure 2533179055Sjfv * @addr: new address 2534179055Sjfv * 2535179055Sjfv * Adds it to unused receive address register or goes into promiscuous mode. 2536179055Sjfv **/ 2537179055Sjfvvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2538179055Sjfv{ 2539179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2540179055Sjfv u32 rar; 2541179055Sjfv 2542200239Sjfv DEBUGFUNC("ixgbe_add_uc_addr"); 2543200239Sjfv 2544179055Sjfv DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2545230775Sjfv addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2546179055Sjfv 2547179055Sjfv /* 2548179055Sjfv * Place this address in the RAR if there is room, 2549179055Sjfv * else put the controller into promiscuous mode 2550179055Sjfv */ 2551179055Sjfv if (hw->addr_ctrl.rar_used_count < rar_entries) { 2552190873Sjfv rar = hw->addr_ctrl.rar_used_count; 2553179055Sjfv hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2554179055Sjfv DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2555179055Sjfv hw->addr_ctrl.rar_used_count++; 2556179055Sjfv } else { 2557179055Sjfv hw->addr_ctrl.overflow_promisc++; 2558179055Sjfv } 2559179055Sjfv 2560179055Sjfv DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2561179055Sjfv} 2562179055Sjfv 2563179055Sjfv/** 2564179055Sjfv * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2565179055Sjfv * @hw: pointer to hardware structure 2566179055Sjfv * @addr_list: the list of new addresses 2567179055Sjfv * @addr_count: number of addresses 2568179055Sjfv * @next: iterator function to walk the address list 2569179055Sjfv * 2570179055Sjfv * The given list replaces any existing list. Clears the secondary addrs from 2571179055Sjfv * receive address registers. Uses unused receive address registers for the 2572179055Sjfv * first secondary addresses, and falls back to promiscuous mode as needed. 2573179055Sjfv * 2574179055Sjfv * Drivers using secondary unicast addresses must set user_set_promisc when 2575179055Sjfv * manually putting the device into promiscuous mode. 2576179055Sjfv **/ 2577179055Sjfvs32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2578230775Sjfv u32 addr_count, ixgbe_mc_addr_itr next) 2579179055Sjfv{ 2580179055Sjfv u8 *addr; 2581179055Sjfv u32 i; 2582179055Sjfv u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2583179055Sjfv u32 uc_addr_in_use; 2584179055Sjfv u32 fctrl; 2585179055Sjfv u32 vmdq; 2586179055Sjfv 2587200239Sjfv DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2588200239Sjfv 2589179055Sjfv /* 2590179055Sjfv * Clear accounting of old secondary address list, 2591179055Sjfv * don't count RAR[0] 2592179055Sjfv */ 2593190873Sjfv uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2594179055Sjfv hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2595179055Sjfv hw->addr_ctrl.overflow_promisc = 0; 2596179055Sjfv 2597179055Sjfv /* Zero out the other receive addresses */ 2598200239Sjfv DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2599200239Sjfv for (i = 0; i < uc_addr_in_use; i++) { 2600200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2601200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2602179055Sjfv } 2603179055Sjfv 2604179055Sjfv /* Add the new addresses */ 2605179055Sjfv for (i = 0; i < addr_count; i++) { 2606179055Sjfv DEBUGOUT(" Adding the secondary addresses:\n"); 2607179055Sjfv addr = next(hw, &addr_list, &vmdq); 2608179055Sjfv ixgbe_add_uc_addr(hw, addr, vmdq); 2609179055Sjfv } 2610179055Sjfv 2611179055Sjfv if (hw->addr_ctrl.overflow_promisc) { 2612179055Sjfv /* enable promisc if not already in overflow or set by user */ 2613179055Sjfv if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2614185352Sjfv DEBUGOUT(" Entering address overflow promisc mode\n"); 2615179055Sjfv fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2616179055Sjfv fctrl |= IXGBE_FCTRL_UPE; 2617179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2618179055Sjfv } 2619179055Sjfv } else { 2620179055Sjfv /* only disable if set by overflow, not by user */ 2621179055Sjfv if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2622179055Sjfv DEBUGOUT(" Leaving address overflow promisc mode\n"); 2623179055Sjfv fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2624179055Sjfv fctrl &= ~IXGBE_FCTRL_UPE; 2625179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2626179055Sjfv } 2627179055Sjfv } 2628179055Sjfv 2629179055Sjfv DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2630179055Sjfv return IXGBE_SUCCESS; 2631179055Sjfv} 2632179055Sjfv 2633179055Sjfv/** 2634171384Sjfv * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2635171384Sjfv * @hw: pointer to hardware structure 2636171384Sjfv * @mc_addr: the multicast address 2637171384Sjfv * 2638171384Sjfv * Extracts the 12 bits, from a multicast address, to determine which 2639171384Sjfv * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2640171384Sjfv * incoming rx multicast addresses, to determine the bit-vector to check in 2641171384Sjfv * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2642179055Sjfv * by the MO field of the MCSTCTRL. The MO field is set during initialization 2643171384Sjfv * to mc_filter_type. 2644171384Sjfv **/ 2645171384Sjfvstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2646171384Sjfv{ 2647171384Sjfv u32 vector = 0; 2648171384Sjfv 2649200239Sjfv DEBUGFUNC("ixgbe_mta_vector"); 2650200239Sjfv 2651171384Sjfv switch (hw->mac.mc_filter_type) { 2652179055Sjfv case 0: /* use bits [47:36] of the address */ 2653171384Sjfv vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2654171384Sjfv break; 2655179055Sjfv case 1: /* use bits [46:35] of the address */ 2656171384Sjfv vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2657171384Sjfv break; 2658179055Sjfv case 2: /* use bits [45:34] of the address */ 2659171384Sjfv vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2660171384Sjfv break; 2661179055Sjfv case 3: /* use bits [43:32] of the address */ 2662171384Sjfv vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2663171384Sjfv break; 2664179055Sjfv default: /* Invalid mc_filter_type */ 2665171384Sjfv DEBUGOUT("MC filter type param set incorrectly\n"); 2666171384Sjfv ASSERT(0); 2667171384Sjfv break; 2668171384Sjfv } 2669171384Sjfv 2670171384Sjfv /* vector can only be 12-bits or boundary will be exceeded */ 2671171384Sjfv vector &= 0xFFF; 2672171384Sjfv return vector; 2673171384Sjfv} 2674171384Sjfv 2675171384Sjfv/** 2676171384Sjfv * ixgbe_set_mta - Set bit-vector in multicast table 2677171384Sjfv * @hw: pointer to hardware structure 2678171384Sjfv * @hash_value: Multicast address hash value 2679171384Sjfv * 2680171384Sjfv * Sets the bit-vector in the multicast table. 2681171384Sjfv **/ 2682171384Sjfvvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2683171384Sjfv{ 2684171384Sjfv u32 vector; 2685171384Sjfv u32 vector_bit; 2686171384Sjfv u32 vector_reg; 2687171384Sjfv 2688200239Sjfv DEBUGFUNC("ixgbe_set_mta"); 2689200239Sjfv 2690171384Sjfv hw->addr_ctrl.mta_in_use++; 2691171384Sjfv 2692171384Sjfv vector = ixgbe_mta_vector(hw, mc_addr); 2693171384Sjfv DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2694171384Sjfv 2695171384Sjfv /* 2696171384Sjfv * The MTA is a register array of 128 32-bit registers. It is treated 2697171384Sjfv * like an array of 4096 bits. We want to set bit 2698171384Sjfv * BitArray[vector_value]. So we figure out what register the bit is 2699171384Sjfv * in, read it, OR in the new bit, then write back the new value. The 2700171384Sjfv * register is determined by the upper 7 bits of the vector value and 2701171384Sjfv * the bit within that register are determined by the lower 5 bits of 2702171384Sjfv * the value. 2703171384Sjfv */ 2704171384Sjfv vector_reg = (vector >> 5) & 0x7F; 2705171384Sjfv vector_bit = vector & 0x1F; 2706215911Sjfv hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2707171384Sjfv} 2708171384Sjfv 2709171384Sjfv/** 2710171384Sjfv * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2711171384Sjfv * @hw: pointer to hardware structure 2712171384Sjfv * @mc_addr_list: the list of new multicast addresses 2713171384Sjfv * @mc_addr_count: number of addresses 2714179055Sjfv * @next: iterator function to walk the multicast address list 2715230775Sjfv * @clear: flag, when set clears the table beforehand 2716171384Sjfv * 2717230775Sjfv * When the clear flag is set, the given list replaces any existing list. 2718230775Sjfv * Hashes the given addresses into the multicast table. 2719171384Sjfv **/ 2720171384Sjfvs32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2721230775Sjfv u32 mc_addr_count, ixgbe_mc_addr_itr next, 2722230775Sjfv bool clear) 2723171384Sjfv{ 2724171384Sjfv u32 i; 2725179055Sjfv u32 vmdq; 2726171384Sjfv 2727200239Sjfv DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2728200239Sjfv 2729171384Sjfv /* 2730171384Sjfv * Set the new number of MC addresses that we are being requested to 2731171384Sjfv * use. 2732171384Sjfv */ 2733171384Sjfv hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2734171384Sjfv hw->addr_ctrl.mta_in_use = 0; 2735171384Sjfv 2736215911Sjfv /* Clear mta_shadow */ 2737230775Sjfv if (clear) { 2738230775Sjfv DEBUGOUT(" Clearing MTA\n"); 2739230775Sjfv memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2740230775Sjfv } 2741171384Sjfv 2742215911Sjfv /* Update mta_shadow */ 2743171384Sjfv for (i = 0; i < mc_addr_count; i++) { 2744171384Sjfv DEBUGOUT(" Adding the multicast addresses:\n"); 2745190873Sjfv ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2746171384Sjfv } 2747171384Sjfv 2748171384Sjfv /* Enable mta */ 2749215911Sjfv for (i = 0; i < hw->mac.mcft_size; i++) 2750215911Sjfv IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2751215911Sjfv hw->mac.mta_shadow[i]); 2752215911Sjfv 2753171384Sjfv if (hw->addr_ctrl.mta_in_use > 0) 2754171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2755230775Sjfv IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2756171384Sjfv 2757171384Sjfv DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2758171384Sjfv return IXGBE_SUCCESS; 2759171384Sjfv} 2760171384Sjfv 2761171384Sjfv/** 2762171384Sjfv * ixgbe_enable_mc_generic - Enable multicast address in RAR 2763171384Sjfv * @hw: pointer to hardware structure 2764171384Sjfv * 2765171384Sjfv * Enables multicast address in RAR and the use of the multicast hash table. 2766171384Sjfv **/ 2767171384Sjfvs32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2768171384Sjfv{ 2769171384Sjfv struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2770171384Sjfv 2771200239Sjfv DEBUGFUNC("ixgbe_enable_mc_generic"); 2772200239Sjfv 2773171384Sjfv if (a->mta_in_use > 0) 2774171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2775230775Sjfv hw->mac.mc_filter_type); 2776171384Sjfv 2777171384Sjfv return IXGBE_SUCCESS; 2778171384Sjfv} 2779171384Sjfv 2780171384Sjfv/** 2781179055Sjfv * ixgbe_disable_mc_generic - Disable multicast address in RAR 2782171384Sjfv * @hw: pointer to hardware structure 2783171384Sjfv * 2784171384Sjfv * Disables multicast address in RAR and the use of the multicast hash table. 2785171384Sjfv **/ 2786171384Sjfvs32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2787171384Sjfv{ 2788171384Sjfv struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2789171384Sjfv 2790200239Sjfv DEBUGFUNC("ixgbe_disable_mc_generic"); 2791200239Sjfv 2792171384Sjfv if (a->mta_in_use > 0) 2793171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2794171384Sjfv 2795171384Sjfv return IXGBE_SUCCESS; 2796171384Sjfv} 2797171384Sjfv 2798171384Sjfv/** 2799190873Sjfv * ixgbe_fc_enable_generic - Enable flow control 2800185352Sjfv * @hw: pointer to hardware structure 2801185352Sjfv * 2802190873Sjfv * Enable flow control according to the current settings. 2803185352Sjfv **/ 2804238149Sjfvs32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2805185352Sjfv{ 2806185352Sjfv s32 ret_val = IXGBE_SUCCESS; 2807190873Sjfv u32 mflcn_reg, fccfg_reg; 2808190873Sjfv u32 reg; 2809215911Sjfv u32 fcrtl, fcrth; 2810238149Sjfv int i; 2811185352Sjfv 2812190873Sjfv DEBUGFUNC("ixgbe_fc_enable_generic"); 2813185352Sjfv 2814238149Sjfv /* Validate the water mark configuration */ 2815238149Sjfv if (!hw->fc.pause_time) { 2816238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2817190873Sjfv goto out; 2818238149Sjfv } 2819185352Sjfv 2820238149Sjfv /* Low water mark of zero causes XOFF floods */ 2821238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2822238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2823238149Sjfv hw->fc.high_water[i]) { 2824238149Sjfv if (!hw->fc.low_water[i] || 2825238149Sjfv hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2826238149Sjfv DEBUGOUT("Invalid water mark configuration\n"); 2827238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2828238149Sjfv goto out; 2829238149Sjfv } 2830238149Sjfv } 2831238149Sjfv } 2832238149Sjfv 2833238149Sjfv /* Negotiate the fc mode to use */ 2834315333Serj hw->mac.ops.fc_autoneg(hw); 2835238149Sjfv 2836190873Sjfv /* Disable any previous flow control settings */ 2837190873Sjfv mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2838238149Sjfv mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2839190873Sjfv 2840190873Sjfv fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2841190873Sjfv fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2842190873Sjfv 2843185352Sjfv /* 2844185352Sjfv * The possible values of fc.current_mode are: 2845190873Sjfv * 0: Flow control is completely disabled 2846190873Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 2847190873Sjfv * but not send pause frames). 2848190873Sjfv * 2: Tx flow control is enabled (we can send pause frames but 2849190873Sjfv * we do not support receiving pause frames). 2850190873Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 2851185352Sjfv * other: Invalid. 2852185352Sjfv */ 2853185352Sjfv switch (hw->fc.current_mode) { 2854185352Sjfv case ixgbe_fc_none: 2855215911Sjfv /* 2856215911Sjfv * Flow control is disabled by software override or autoneg. 2857190873Sjfv * The code below will actually disable it in the HW. 2858190873Sjfv */ 2859185352Sjfv break; 2860185352Sjfv case ixgbe_fc_rx_pause: 2861185352Sjfv /* 2862185352Sjfv * Rx Flow control is enabled and Tx Flow control is 2863185352Sjfv * disabled by software override. Since there really 2864185352Sjfv * isn't a way to advertise that we are capable of RX 2865185352Sjfv * Pause ONLY, we will advertise that we support both 2866185352Sjfv * symmetric and asymmetric Rx PAUSE. Later, we will 2867185352Sjfv * disable the adapter's ability to send PAUSE frames. 2868185352Sjfv */ 2869190873Sjfv mflcn_reg |= IXGBE_MFLCN_RFCE; 2870185352Sjfv break; 2871185352Sjfv case ixgbe_fc_tx_pause: 2872185352Sjfv /* 2873185352Sjfv * Tx Flow control is enabled, and Rx Flow control is 2874185352Sjfv * disabled by software override. 2875185352Sjfv */ 2876190873Sjfv fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2877185352Sjfv break; 2878185352Sjfv case ixgbe_fc_full: 2879185352Sjfv /* Flow control (both Rx and Tx) is enabled by SW override. */ 2880190873Sjfv mflcn_reg |= IXGBE_MFLCN_RFCE; 2881190873Sjfv fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2882185352Sjfv break; 2883185352Sjfv default: 2884251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2885251964Sjfv "Flow control param set incorrectly\n"); 2886200239Sjfv ret_val = IXGBE_ERR_CONFIG; 2887185352Sjfv goto out; 2888185352Sjfv break; 2889185352Sjfv } 2890185352Sjfv 2891190873Sjfv /* Set 802.3x based flow control settings. */ 2892190873Sjfv mflcn_reg |= IXGBE_MFLCN_DPF; 2893190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2894190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2895185352Sjfv 2896194875Sjfv 2897238149Sjfv /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2898238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2899238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2900238149Sjfv hw->fc.high_water[i]) { 2901238149Sjfv fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2902238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2903238149Sjfv fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2904238149Sjfv } else { 2905238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2906238149Sjfv /* 2907238149Sjfv * In order to prevent Tx hangs when the internal Tx 2908238149Sjfv * switch is enabled we must set the high water mark 2909283620Serj * to the Rx packet buffer size - 24KB. This allows 2910283620Serj * the Tx switch to function even under heavy Rx 2911283620Serj * workloads. 2912238149Sjfv */ 2913283620Serj fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2914238149Sjfv } 2915238149Sjfv 2916238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2917190873Sjfv } 2918185352Sjfv 2919190873Sjfv /* Configure pause time (2 TCs per register) */ 2920238149Sjfv reg = hw->fc.pause_time * 0x00010001; 2921238149Sjfv for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2922238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2923185352Sjfv 2924238149Sjfv /* Configure flow control refresh threshold value */ 2925238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2926185352Sjfv 2927190873Sjfvout: 2928190873Sjfv return ret_val; 2929190873Sjfv} 2930190873Sjfv 2931190873Sjfv/** 2932238149Sjfv * ixgbe_negotiate_fc - Negotiate flow control 2933190873Sjfv * @hw: pointer to hardware structure 2934238149Sjfv * @adv_reg: flow control advertised settings 2935238149Sjfv * @lp_reg: link partner's flow control settings 2936238149Sjfv * @adv_sym: symmetric pause bit in advertisement 2937238149Sjfv * @adv_asm: asymmetric pause bit in advertisement 2938238149Sjfv * @lp_sym: symmetric pause bit in link partner advertisement 2939238149Sjfv * @lp_asm: asymmetric pause bit in link partner advertisement 2940190873Sjfv * 2941238149Sjfv * Find the intersection between advertised settings and link partner's 2942238149Sjfv * advertised settings 2943190873Sjfv **/ 2944315333Serjs32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2945315333Serj u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2946190873Sjfv{ 2947251964Sjfv if ((!(adv_reg)) || (!(lp_reg))) { 2948251964Sjfv ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2949251964Sjfv "Local or link partner's advertised flow control " 2950251964Sjfv "settings are NULL. Local: %x, link partner: %x\n", 2951251964Sjfv adv_reg, lp_reg); 2952238149Sjfv return IXGBE_ERR_FC_NOT_NEGOTIATED; 2953251964Sjfv } 2954190873Sjfv 2955238149Sjfv if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2956238149Sjfv /* 2957238149Sjfv * Now we need to check if the user selected Rx ONLY 2958238149Sjfv * of pause frames. In this case, we had to advertise 2959238149Sjfv * FULL flow control because we could not advertise RX 2960238149Sjfv * ONLY. Hence, we must now check to see if we need to 2961238149Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 2962238149Sjfv */ 2963238149Sjfv if (hw->fc.requested_mode == ixgbe_fc_full) { 2964238149Sjfv hw->fc.current_mode = ixgbe_fc_full; 2965238149Sjfv DEBUGOUT("Flow Control = FULL.\n"); 2966238149Sjfv } else { 2967238149Sjfv hw->fc.current_mode = ixgbe_fc_rx_pause; 2968238149Sjfv DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2969238149Sjfv } 2970238149Sjfv } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2971238149Sjfv (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2972238149Sjfv hw->fc.current_mode = ixgbe_fc_tx_pause; 2973238149Sjfv DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2974238149Sjfv } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2975238149Sjfv !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2976238149Sjfv hw->fc.current_mode = ixgbe_fc_rx_pause; 2977238149Sjfv DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2978215911Sjfv } else { 2979238149Sjfv hw->fc.current_mode = ixgbe_fc_none; 2980238149Sjfv DEBUGOUT("Flow Control = NONE.\n"); 2981185352Sjfv } 2982238149Sjfv return IXGBE_SUCCESS; 2983215911Sjfv} 2984185352Sjfv 2985215911Sjfv/** 2986215911Sjfv * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2987215911Sjfv * @hw: pointer to hardware structure 2988215911Sjfv * 2989215911Sjfv * Enable flow control according on 1 gig fiber. 2990215911Sjfv **/ 2991215911Sjfvstatic s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2992215911Sjfv{ 2993215911Sjfv u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2994238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2995200239Sjfv 2996200239Sjfv /* 2997200239Sjfv * On multispeed fiber at 1g, bail out if 2998200239Sjfv * - link is up but AN did not complete, or if 2999200239Sjfv * - link is up and AN completed but timed out 3000200239Sjfv */ 3001215911Sjfv 3002215911Sjfv linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3003230775Sjfv if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3004251964Sjfv (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3005283620Serj DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3006215911Sjfv goto out; 3007251964Sjfv } 3008200239Sjfv 3009215911Sjfv pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3010215911Sjfv pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3011215911Sjfv 3012215911Sjfv ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3013230775Sjfv pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3014230775Sjfv IXGBE_PCS1GANA_ASM_PAUSE, 3015230775Sjfv IXGBE_PCS1GANA_SYM_PAUSE, 3016230775Sjfv IXGBE_PCS1GANA_ASM_PAUSE); 3017215911Sjfv 3018215911Sjfvout: 3019215911Sjfv return ret_val; 3020215911Sjfv} 3021215911Sjfv 3022215911Sjfv/** 3023215911Sjfv * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3024215911Sjfv * @hw: pointer to hardware structure 3025215911Sjfv * 3026215911Sjfv * Enable flow control according to IEEE clause 37. 3027215911Sjfv **/ 3028215911Sjfvstatic s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3029215911Sjfv{ 3030215911Sjfv u32 links2, anlp1_reg, autoc_reg, links; 3031238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3032215911Sjfv 3033200239Sjfv /* 3034215911Sjfv * On backplane, bail out if 3035215911Sjfv * - backplane autoneg was not completed, or if 3036215911Sjfv * - we are 82599 and link partner is not AN enabled 3037200239Sjfv */ 3038215911Sjfv links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3039251964Sjfv if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3040283620Serj DEBUGOUT("Auto-Negotiation did not complete\n"); 3041200239Sjfv goto out; 3042251964Sjfv } 3043200239Sjfv 3044215911Sjfv if (hw->mac.type == ixgbe_mac_82599EB) { 3045215911Sjfv links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3046251964Sjfv if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3047283620Serj DEBUGOUT("Link partner is not AN enabled\n"); 3048215911Sjfv goto out; 3049251964Sjfv } 3050215911Sjfv } 3051200239Sjfv /* 3052215911Sjfv * Read the 10g AN autoc and LP ability registers and resolve 3053185352Sjfv * local flow control settings accordingly 3054185352Sjfv */ 3055215911Sjfv autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3056215911Sjfv anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3057200239Sjfv 3058215911Sjfv ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3059215911Sjfv anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3060215911Sjfv IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3061215911Sjfv 3062215911Sjfvout: 3063215911Sjfv return ret_val; 3064215911Sjfv} 3065215911Sjfv 3066215911Sjfv/** 3067215911Sjfv * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3068215911Sjfv * @hw: pointer to hardware structure 3069215911Sjfv * 3070215911Sjfv * Enable flow control according to IEEE clause 37. 3071215911Sjfv **/ 3072215911Sjfvstatic s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3073215911Sjfv{ 3074215911Sjfv u16 technology_ability_reg = 0; 3075215911Sjfv u16 lp_technology_ability_reg = 0; 3076215911Sjfv 3077215911Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3078215911Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3079215911Sjfv &technology_ability_reg); 3080215911Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3081215911Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3082215911Sjfv &lp_technology_ability_reg); 3083215911Sjfv 3084215911Sjfv return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3085215911Sjfv (u32)lp_technology_ability_reg, 3086215911Sjfv IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3087215911Sjfv IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3088215911Sjfv} 3089215911Sjfv 3090215911Sjfv/** 3091238149Sjfv * ixgbe_fc_autoneg - Configure flow control 3092215911Sjfv * @hw: pointer to hardware structure 3093215911Sjfv * 3094238149Sjfv * Compares our advertised flow control capabilities to those advertised by 3095238149Sjfv * our link partner, and determines the proper flow control mode to use. 3096215911Sjfv **/ 3097238149Sjfvvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3098215911Sjfv{ 3099238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3100238149Sjfv ixgbe_link_speed speed; 3101238149Sjfv bool link_up; 3102215911Sjfv 3103238149Sjfv DEBUGFUNC("ixgbe_fc_autoneg"); 3104185352Sjfv 3105190873Sjfv /* 3106238149Sjfv * AN should have completed when the cable was plugged in. 3107238149Sjfv * Look for reasons to bail out. Bail out if: 3108238149Sjfv * - FC autoneg is disabled, or if 3109238149Sjfv * - link is not up. 3110190873Sjfv */ 3111251964Sjfv if (hw->fc.disable_fc_autoneg) { 3112251964Sjfv ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3113251964Sjfv "Flow control autoneg is disabled"); 3114190873Sjfv goto out; 3115251964Sjfv } 3116190873Sjfv 3117238149Sjfv hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3118251964Sjfv if (!link_up) { 3119251964Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3120190873Sjfv goto out; 3121251964Sjfv } 3122190873Sjfv 3123215911Sjfv switch (hw->phy.media_type) { 3124238149Sjfv /* Autoneg flow control on fiber adapters */ 3125247822Sjfv case ixgbe_media_type_fiber_fixed: 3126283620Serj case ixgbe_media_type_fiber_qsfp: 3127215911Sjfv case ixgbe_media_type_fiber: 3128238149Sjfv if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3129238149Sjfv ret_val = ixgbe_fc_autoneg_fiber(hw); 3130238149Sjfv break; 3131238149Sjfv 3132238149Sjfv /* Autoneg flow control on backplane adapters */ 3133215911Sjfv case ixgbe_media_type_backplane: 3134238149Sjfv ret_val = ixgbe_fc_autoneg_backplane(hw); 3135215911Sjfv break; 3136215911Sjfv 3137238149Sjfv /* Autoneg flow control on copper adapters */ 3138215911Sjfv case ixgbe_media_type_copper: 3139251964Sjfv if (ixgbe_device_supports_autoneg_fc(hw)) 3140238149Sjfv ret_val = ixgbe_fc_autoneg_copper(hw); 3141215911Sjfv break; 3142215911Sjfv 3143215911Sjfv default: 3144190873Sjfv break; 3145190873Sjfv } 3146190873Sjfv 3147238149Sjfvout: 3148238149Sjfv if (ret_val == IXGBE_SUCCESS) { 3149238149Sjfv hw->fc.fc_was_autonegged = TRUE; 3150238149Sjfv } else { 3151238149Sjfv hw->fc.fc_was_autonegged = FALSE; 3152238149Sjfv hw->fc.current_mode = hw->fc.requested_mode; 3153230775Sjfv } 3154190873Sjfv} 3155190873Sjfv 3156251964Sjfv/* 3157251964Sjfv * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3158251964Sjfv * @hw: pointer to hardware structure 3159251964Sjfv * 3160251964Sjfv * System-wide timeout range is encoded in PCIe Device Control2 register. 3161251964Sjfv * 3162251964Sjfv * Add 10% to specified maximum and return the number of times to poll for 3163251964Sjfv * completion timeout, in units of 100 microsec. Never return less than 3164251964Sjfv * 800 = 80 millisec. 3165251964Sjfv */ 3166251964Sjfvstatic u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3167251964Sjfv{ 3168251964Sjfv s16 devctl2; 3169251964Sjfv u32 pollcnt; 3170251964Sjfv 3171251964Sjfv devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3172251964Sjfv devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3173251964Sjfv 3174251964Sjfv switch (devctl2) { 3175251964Sjfv case IXGBE_PCIDEVCTRL2_65_130ms: 3176251964Sjfv pollcnt = 1300; /* 130 millisec */ 3177251964Sjfv break; 3178251964Sjfv case IXGBE_PCIDEVCTRL2_260_520ms: 3179251964Sjfv pollcnt = 5200; /* 520 millisec */ 3180251964Sjfv break; 3181251964Sjfv case IXGBE_PCIDEVCTRL2_1_2s: 3182251964Sjfv pollcnt = 20000; /* 2 sec */ 3183251964Sjfv break; 3184251964Sjfv case IXGBE_PCIDEVCTRL2_4_8s: 3185251964Sjfv pollcnt = 80000; /* 8 sec */ 3186251964Sjfv break; 3187251964Sjfv case IXGBE_PCIDEVCTRL2_17_34s: 3188251964Sjfv pollcnt = 34000; /* 34 sec */ 3189251964Sjfv break; 3190251964Sjfv case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3191251964Sjfv case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3192251964Sjfv case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3193251964Sjfv case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3194251964Sjfv default: 3195251964Sjfv pollcnt = 800; /* 80 millisec minimum */ 3196251964Sjfv break; 3197251964Sjfv } 3198251964Sjfv 3199251964Sjfv /* add 10% to spec maximum */ 3200251964Sjfv return (pollcnt * 11) / 10; 3201251964Sjfv} 3202251964Sjfv 3203185352Sjfv/** 3204171384Sjfv * ixgbe_disable_pcie_master - Disable PCI-express master access 3205171384Sjfv * @hw: pointer to hardware structure 3206171384Sjfv * 3207171384Sjfv * Disables PCI-Express master access and verifies there are no pending 3208171384Sjfv * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3209171384Sjfv * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3210171384Sjfv * is returned signifying master requests disabled. 3211171384Sjfv **/ 3212171384Sjfvs32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3213171384Sjfv{ 3214230775Sjfv s32 status = IXGBE_SUCCESS; 3215251964Sjfv u32 i, poll; 3216283620Serj u16 value; 3217171384Sjfv 3218200239Sjfv DEBUGFUNC("ixgbe_disable_pcie_master"); 3219200239Sjfv 3220230775Sjfv /* Always set this bit to ensure any future transactions are blocked */ 3221230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3222230775Sjfv 3223251964Sjfv /* Exit if master requests are blocked */ 3224283620Serj if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3225283620Serj IXGBE_REMOVED(hw->hw_addr)) 3226205720Sjfv goto out; 3227205720Sjfv 3228230775Sjfv /* Poll for master request bit to clear */ 3229171384Sjfv for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3230230775Sjfv usec_delay(100); 3231205720Sjfv if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3232230775Sjfv goto out; 3233205720Sjfv } 3234205720Sjfv 3235230775Sjfv /* 3236230775Sjfv * Two consecutive resets are required via CTRL.RST per datasheet 3237230775Sjfv * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3238230775Sjfv * of this need. The first reset prevents new master requests from 3239230775Sjfv * being issued by our device. We then must wait 1usec or more for any 3240230775Sjfv * remaining completions from the PCIe bus to trickle in, and then reset 3241230775Sjfv * again to clear out any effects they may have had on our device. 3242230775Sjfv */ 3243205720Sjfv DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3244230775Sjfv hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3245205720Sjfv 3246295524Ssbruno if (hw->mac.type >= ixgbe_mac_X550) 3247295524Ssbruno goto out; 3248295524Ssbruno 3249205720Sjfv /* 3250217593Sjfv * Before proceeding, make sure that the PCIe block does not have 3251217593Sjfv * transactions pending. 3252205720Sjfv */ 3253251964Sjfv poll = ixgbe_pcie_timeout_poll(hw); 3254251964Sjfv for (i = 0; i < poll; i++) { 3255230775Sjfv usec_delay(100); 3256283620Serj value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3257283620Serj if (IXGBE_REMOVED(hw->hw_addr)) 3258230775Sjfv goto out; 3259283620Serj if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3260283620Serj goto out; 3261171384Sjfv } 3262171384Sjfv 3263251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 3264251964Sjfv "PCIe transaction pending bit also did not clear.\n"); 3265230775Sjfv status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3266205720Sjfv 3267205720Sjfvout: 3268171384Sjfv return status; 3269171384Sjfv} 3270171384Sjfv 3271171384Sjfv/** 3272179055Sjfv * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3273171384Sjfv * @hw: pointer to hardware structure 3274179055Sjfv * @mask: Mask to specify which semaphore to acquire 3275171384Sjfv * 3276230775Sjfv * Acquires the SWFW semaphore through the GSSR register for the specified 3277171384Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 3278171384Sjfv **/ 3279283620Serjs32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3280171384Sjfv{ 3281251964Sjfv u32 gssr = 0; 3282171384Sjfv u32 swmask = mask; 3283171384Sjfv u32 fwmask = mask << 5; 3284251964Sjfv u32 timeout = 200; 3285251964Sjfv u32 i; 3286171384Sjfv 3287200239Sjfv DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3288200239Sjfv 3289251964Sjfv for (i = 0; i < timeout; i++) { 3290190873Sjfv /* 3291251964Sjfv * SW NVM semaphore bit is used for access to all 3292251964Sjfv * SW_FW_SYNC bits (not just NVM) 3293190873Sjfv */ 3294171384Sjfv if (ixgbe_get_eeprom_semaphore(hw)) 3295200239Sjfv return IXGBE_ERR_SWFW_SYNC; 3296171384Sjfv 3297171384Sjfv gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3298251964Sjfv if (!(gssr & (fwmask | swmask))) { 3299251964Sjfv gssr |= swmask; 3300251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3301251964Sjfv ixgbe_release_eeprom_semaphore(hw); 3302251964Sjfv return IXGBE_SUCCESS; 3303251964Sjfv } else { 3304251964Sjfv /* Resource is currently in use by FW or SW */ 3305251964Sjfv ixgbe_release_eeprom_semaphore(hw); 3306251964Sjfv msec_delay(5); 3307251964Sjfv } 3308171384Sjfv } 3309171384Sjfv 3310251964Sjfv /* If time expired clear the bits holding the lock and retry */ 3311251964Sjfv if (gssr & (fwmask | swmask)) 3312251964Sjfv ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3313171384Sjfv 3314251964Sjfv msec_delay(5); 3315251964Sjfv return IXGBE_ERR_SWFW_SYNC; 3316171384Sjfv} 3317171384Sjfv 3318171384Sjfv/** 3319171384Sjfv * ixgbe_release_swfw_sync - Release SWFW semaphore 3320171384Sjfv * @hw: pointer to hardware structure 3321179055Sjfv * @mask: Mask to specify which semaphore to release 3322171384Sjfv * 3323230775Sjfv * Releases the SWFW semaphore through the GSSR register for the specified 3324171384Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 3325171384Sjfv **/ 3326283620Serjvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3327171384Sjfv{ 3328171384Sjfv u32 gssr; 3329171384Sjfv u32 swmask = mask; 3330171384Sjfv 3331200239Sjfv DEBUGFUNC("ixgbe_release_swfw_sync"); 3332200239Sjfv 3333171384Sjfv ixgbe_get_eeprom_semaphore(hw); 3334171384Sjfv 3335171384Sjfv gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3336171384Sjfv gssr &= ~swmask; 3337171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3338171384Sjfv 3339171384Sjfv ixgbe_release_eeprom_semaphore(hw); 3340171384Sjfv} 3341171384Sjfv 3342190873Sjfv/** 3343230775Sjfv * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3344230775Sjfv * @hw: pointer to hardware structure 3345230775Sjfv * 3346230775Sjfv * Stops the receive data path and waits for the HW to internally empty 3347230775Sjfv * the Rx security block 3348230775Sjfv **/ 3349230775Sjfvs32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3350230775Sjfv{ 3351230775Sjfv#define IXGBE_MAX_SECRX_POLL 40 3352230775Sjfv 3353230775Sjfv int i; 3354230775Sjfv int secrxreg; 3355230775Sjfv 3356230775Sjfv DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3357230775Sjfv 3358230775Sjfv 3359230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3360230775Sjfv secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3361230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3362230775Sjfv for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3363230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3364230775Sjfv if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3365230775Sjfv break; 3366230775Sjfv else 3367230775Sjfv /* Use interrupt-safe sleep just in case */ 3368230775Sjfv usec_delay(1000); 3369230775Sjfv } 3370230775Sjfv 3371230775Sjfv /* For informational purposes only */ 3372230775Sjfv if (i >= IXGBE_MAX_SECRX_POLL) 3373230775Sjfv DEBUGOUT("Rx unit being enabled before security " 3374230775Sjfv "path fully disabled. Continuing with init.\n"); 3375230775Sjfv 3376230775Sjfv return IXGBE_SUCCESS; 3377230775Sjfv} 3378230775Sjfv 3379230775Sjfv/** 3380283620Serj * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3381283620Serj * @hw: pointer to hardware structure 3382283620Serj * @reg_val: Value we read from AUTOC 3383283620Serj * 3384283620Serj * The default case requires no protection so just to the register read. 3385283620Serj */ 3386283620Serjs32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3387283620Serj{ 3388283620Serj *locked = FALSE; 3389283620Serj *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3390283620Serj return IXGBE_SUCCESS; 3391283620Serj} 3392283620Serj 3393283620Serj/** 3394283620Serj * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3395283620Serj * @hw: pointer to hardware structure 3396283620Serj * @reg_val: value to write to AUTOC 3397283620Serj * @locked: bool to indicate whether the SW/FW lock was already taken by 3398283620Serj * previous read. 3399283620Serj * 3400283620Serj * The default case requires no protection so just to the register write. 3401283620Serj */ 3402283620Serjs32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3403283620Serj{ 3404283620Serj UNREFERENCED_1PARAMETER(locked); 3405283620Serj 3406283620Serj IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3407283620Serj return IXGBE_SUCCESS; 3408283620Serj} 3409283620Serj 3410283620Serj/** 3411230775Sjfv * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3412230775Sjfv * @hw: pointer to hardware structure 3413230775Sjfv * 3414230775Sjfv * Enables the receive data path. 3415230775Sjfv **/ 3416230775Sjfvs32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3417230775Sjfv{ 3418315333Serj u32 secrxreg; 3419230775Sjfv 3420230775Sjfv DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3421230775Sjfv 3422230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3423230775Sjfv secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3424230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3425230775Sjfv IXGBE_WRITE_FLUSH(hw); 3426230775Sjfv 3427230775Sjfv return IXGBE_SUCCESS; 3428230775Sjfv} 3429230775Sjfv 3430230775Sjfv/** 3431190873Sjfv * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3432190873Sjfv * @hw: pointer to hardware structure 3433190873Sjfv * @regval: register value to write to RXCTRL 3434190873Sjfv * 3435190873Sjfv * Enables the Rx DMA unit 3436190873Sjfv **/ 3437190873Sjfvs32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3438190873Sjfv{ 3439200239Sjfv DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3440200239Sjfv 3441283620Serj if (regval & IXGBE_RXCTRL_RXEN) 3442283620Serj ixgbe_enable_rx(hw); 3443283620Serj else 3444283620Serj ixgbe_disable_rx(hw); 3445190873Sjfv 3446190873Sjfv return IXGBE_SUCCESS; 3447190873Sjfv} 3448190873Sjfv 3449190873Sjfv/** 3450190873Sjfv * ixgbe_blink_led_start_generic - Blink LED based on index. 3451190873Sjfv * @hw: pointer to hardware structure 3452190873Sjfv * @index: led number to blink 3453190873Sjfv **/ 3454190873Sjfvs32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3455190873Sjfv{ 3456190873Sjfv ixgbe_link_speed speed = 0; 3457190873Sjfv bool link_up = 0; 3458283620Serj u32 autoc_reg = 0; 3459190873Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3460247822Sjfv s32 ret_val = IXGBE_SUCCESS; 3461283620Serj bool locked = FALSE; 3462190873Sjfv 3463200239Sjfv DEBUGFUNC("ixgbe_blink_led_start_generic"); 3464200239Sjfv 3465315333Serj if (index > 3) 3466315333Serj return IXGBE_ERR_PARAM; 3467315333Serj 3468190873Sjfv /* 3469190873Sjfv * Link must be up to auto-blink the LEDs; 3470190873Sjfv * Force it if link is down. 3471190873Sjfv */ 3472190873Sjfv hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3473190873Sjfv 3474190873Sjfv if (!link_up) { 3475283620Serj ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3476283620Serj if (ret_val != IXGBE_SUCCESS) 3477283620Serj goto out; 3478247822Sjfv 3479194875Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3480190873Sjfv autoc_reg |= IXGBE_AUTOC_FLU; 3481283620Serj 3482283620Serj ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3483283620Serj if (ret_val != IXGBE_SUCCESS) 3484283620Serj goto out; 3485283620Serj 3486230775Sjfv IXGBE_WRITE_FLUSH(hw); 3487190873Sjfv msec_delay(10); 3488190873Sjfv } 3489190873Sjfv 3490190873Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 3491190873Sjfv led_reg |= IXGBE_LED_BLINK(index); 3492190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3493190873Sjfv IXGBE_WRITE_FLUSH(hw); 3494190873Sjfv 3495247822Sjfvout: 3496247822Sjfv return ret_val; 3497190873Sjfv} 3498190873Sjfv 3499190873Sjfv/** 3500190873Sjfv * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3501190873Sjfv * @hw: pointer to hardware structure 3502190873Sjfv * @index: led number to stop blinking 3503190873Sjfv **/ 3504190873Sjfvs32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3505190873Sjfv{ 3506283620Serj u32 autoc_reg = 0; 3507190873Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3508247822Sjfv s32 ret_val = IXGBE_SUCCESS; 3509283620Serj bool locked = FALSE; 3510190873Sjfv 3511200239Sjfv DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3512194875Sjfv 3513315333Serj if (index > 3) 3514315333Serj return IXGBE_ERR_PARAM; 3515315333Serj 3516315333Serj 3517283620Serj ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3518283620Serj if (ret_val != IXGBE_SUCCESS) 3519283620Serj goto out; 3520200239Sjfv 3521190873Sjfv autoc_reg &= ~IXGBE_AUTOC_FLU; 3522190873Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3523190873Sjfv 3524283620Serj ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3525283620Serj if (ret_val != IXGBE_SUCCESS) 3526283620Serj goto out; 3527247822Sjfv 3528190873Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 3529190873Sjfv led_reg &= ~IXGBE_LED_BLINK(index); 3530190873Sjfv led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3531190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3532190873Sjfv IXGBE_WRITE_FLUSH(hw); 3533190873Sjfv 3534247822Sjfvout: 3535247822Sjfv return ret_val; 3536190873Sjfv} 3537190873Sjfv 3538200239Sjfv/** 3539200239Sjfv * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3540200239Sjfv * @hw: pointer to hardware structure 3541200239Sjfv * @san_mac_offset: SAN MAC address offset 3542200239Sjfv * 3543200239Sjfv * This function will read the EEPROM location for the SAN MAC address 3544200239Sjfv * pointer, and returns the value at that location. This is used in both 3545200239Sjfv * get and set mac_addr routines. 3546200239Sjfv **/ 3547200239Sjfvstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3548230775Sjfv u16 *san_mac_offset) 3549200239Sjfv{ 3550251964Sjfv s32 ret_val; 3551251964Sjfv 3552200239Sjfv DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3553200239Sjfv 3554200239Sjfv /* 3555200239Sjfv * First read the EEPROM pointer to see if the MAC addresses are 3556200239Sjfv * available. 3557200239Sjfv */ 3558251964Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3559251964Sjfv san_mac_offset); 3560251964Sjfv if (ret_val) { 3561251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3562251964Sjfv "eeprom at offset %d failed", 3563251964Sjfv IXGBE_SAN_MAC_ADDR_PTR); 3564251964Sjfv } 3565200239Sjfv 3566251964Sjfv return ret_val; 3567200239Sjfv} 3568200239Sjfv 3569200239Sjfv/** 3570200239Sjfv * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3571200239Sjfv * @hw: pointer to hardware structure 3572200239Sjfv * @san_mac_addr: SAN MAC address 3573200239Sjfv * 3574200239Sjfv * Reads the SAN MAC address from the EEPROM, if it's available. This is 3575200239Sjfv * per-port, so set_lan_id() must be called before reading the addresses. 3576200239Sjfv * set_lan_id() is called by identify_sfp(), but this cannot be relied 3577200239Sjfv * upon for non-SFP connections, so we must call it here. 3578200239Sjfv **/ 3579200239Sjfvs32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3580200239Sjfv{ 3581200239Sjfv u16 san_mac_data, san_mac_offset; 3582200239Sjfv u8 i; 3583251964Sjfv s32 ret_val; 3584200239Sjfv 3585200239Sjfv DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3586200239Sjfv 3587200239Sjfv /* 3588200239Sjfv * First read the EEPROM pointer to see if the MAC addresses are 3589200239Sjfv * available. If they're not, no point in calling set_lan_id() here. 3590200239Sjfv */ 3591251964Sjfv ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3592251964Sjfv if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3593200239Sjfv goto san_mac_addr_out; 3594200239Sjfv 3595200239Sjfv /* make sure we know which port we need to program */ 3596200239Sjfv hw->mac.ops.set_lan_id(hw); 3597200239Sjfv /* apply the port offset to the address offset */ 3598200239Sjfv (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3599230775Sjfv (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3600200239Sjfv for (i = 0; i < 3; i++) { 3601251964Sjfv ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3602251964Sjfv &san_mac_data); 3603251964Sjfv if (ret_val) { 3604251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3605251964Sjfv "eeprom read at offset %d failed", 3606251964Sjfv san_mac_offset); 3607251964Sjfv goto san_mac_addr_out; 3608251964Sjfv } 3609200239Sjfv san_mac_addr[i * 2] = (u8)(san_mac_data); 3610200239Sjfv san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3611200239Sjfv san_mac_offset++; 3612200239Sjfv } 3613251964Sjfv return IXGBE_SUCCESS; 3614200239Sjfv 3615200239Sjfvsan_mac_addr_out: 3616251964Sjfv /* 3617251964Sjfv * No addresses available in this EEPROM. It's not an 3618251964Sjfv * error though, so just wipe the local address and return. 3619251964Sjfv */ 3620251964Sjfv for (i = 0; i < 6; i++) 3621251964Sjfv san_mac_addr[i] = 0xFF; 3622200239Sjfv return IXGBE_SUCCESS; 3623200239Sjfv} 3624200239Sjfv 3625200239Sjfv/** 3626200239Sjfv * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3627200239Sjfv * @hw: pointer to hardware structure 3628200239Sjfv * @san_mac_addr: SAN MAC address 3629200239Sjfv * 3630200239Sjfv * Write a SAN MAC address to the EEPROM. 3631200239Sjfv **/ 3632200239Sjfvs32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3633200239Sjfv{ 3634251964Sjfv s32 ret_val; 3635200239Sjfv u16 san_mac_data, san_mac_offset; 3636200239Sjfv u8 i; 3637200239Sjfv 3638200239Sjfv DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3639200239Sjfv 3640200239Sjfv /* Look for SAN mac address pointer. If not defined, return */ 3641251964Sjfv ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3642251964Sjfv if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3643251964Sjfv return IXGBE_ERR_NO_SAN_ADDR_PTR; 3644200239Sjfv 3645200239Sjfv /* Make sure we know which port we need to write */ 3646200239Sjfv hw->mac.ops.set_lan_id(hw); 3647200239Sjfv /* Apply the port offset to the address offset */ 3648200239Sjfv (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3649230775Sjfv (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3650200239Sjfv 3651200239Sjfv for (i = 0; i < 3; i++) { 3652200239Sjfv san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3653200239Sjfv san_mac_data |= (u16)(san_mac_addr[i * 2]); 3654200239Sjfv hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3655200239Sjfv san_mac_offset++; 3656200239Sjfv } 3657200239Sjfv 3658251964Sjfv return IXGBE_SUCCESS; 3659200239Sjfv} 3660200239Sjfv 3661200239Sjfv/** 3662200239Sjfv * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3663200239Sjfv * @hw: pointer to hardware structure 3664200239Sjfv * 3665200239Sjfv * Read PCIe configuration space, and get the MSI-X vector count from 3666200239Sjfv * the capabilities table. 3667200239Sjfv **/ 3668238149Sjfvu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3669200239Sjfv{ 3670238149Sjfv u16 msix_count = 1; 3671238149Sjfv u16 max_msix_count; 3672238149Sjfv u16 pcie_offset; 3673200239Sjfv 3674238149Sjfv switch (hw->mac.type) { 3675238149Sjfv case ixgbe_mac_82598EB: 3676238149Sjfv pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3677238149Sjfv max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3678238149Sjfv break; 3679238149Sjfv case ixgbe_mac_82599EB: 3680238149Sjfv case ixgbe_mac_X540: 3681283620Serj case ixgbe_mac_X550: 3682283620Serj case ixgbe_mac_X550EM_x: 3683315333Serj case ixgbe_mac_X550EM_a: 3684238149Sjfv pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3685238149Sjfv max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3686238149Sjfv break; 3687238149Sjfv default: 3688238149Sjfv return msix_count; 3689238149Sjfv } 3690238149Sjfv 3691200239Sjfv DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3692238149Sjfv msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3693283620Serj if (IXGBE_REMOVED(hw->hw_addr)) 3694283620Serj msix_count = 0; 3695238149Sjfv msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3696200239Sjfv 3697238149Sjfv /* MSI-X count is zero-based in HW */ 3698238149Sjfv msix_count++; 3699200239Sjfv 3700238149Sjfv if (msix_count > max_msix_count) 3701238149Sjfv msix_count = max_msix_count; 3702238149Sjfv 3703200239Sjfv return msix_count; 3704200239Sjfv} 3705200239Sjfv 3706200239Sjfv/** 3707200239Sjfv * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3708200239Sjfv * @hw: pointer to hardware structure 3709200239Sjfv * @addr: Address to put into receive address register 3710200239Sjfv * @vmdq: VMDq pool to assign 3711200239Sjfv * 3712200239Sjfv * Puts an ethernet address into a receive address register, or 3713200239Sjfv * finds the rar that it is aleady in; adds to the pool list 3714200239Sjfv **/ 3715200239Sjfvs32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3716200239Sjfv{ 3717200239Sjfv static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3718200239Sjfv u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3719200239Sjfv u32 rar; 3720200239Sjfv u32 rar_low, rar_high; 3721200239Sjfv u32 addr_low, addr_high; 3722200239Sjfv 3723200239Sjfv DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3724200239Sjfv 3725200239Sjfv /* swap bytes for HW little endian */ 3726200239Sjfv addr_low = addr[0] | (addr[1] << 8) 3727200239Sjfv | (addr[2] << 16) 3728200239Sjfv | (addr[3] << 24); 3729200239Sjfv addr_high = addr[4] | (addr[5] << 8); 3730200239Sjfv 3731200239Sjfv /* 3732200239Sjfv * Either find the mac_id in rar or find the first empty space. 3733200239Sjfv * rar_highwater points to just after the highest currently used 3734200239Sjfv * rar in order to shorten the search. It grows when we add a new 3735200239Sjfv * rar to the top. 3736200239Sjfv */ 3737200239Sjfv for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3738200239Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3739200239Sjfv 3740200239Sjfv if (((IXGBE_RAH_AV & rar_high) == 0) 3741200239Sjfv && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3742200239Sjfv first_empty_rar = rar; 3743200239Sjfv } else if ((rar_high & 0xFFFF) == addr_high) { 3744200239Sjfv rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3745200239Sjfv if (rar_low == addr_low) 3746200239Sjfv break; /* found it already in the rars */ 3747200239Sjfv } 3748200239Sjfv } 3749200239Sjfv 3750200239Sjfv if (rar < hw->mac.rar_highwater) { 3751200239Sjfv /* already there so just add to the pool bits */ 3752200239Sjfv ixgbe_set_vmdq(hw, rar, vmdq); 3753200239Sjfv } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3754200239Sjfv /* stick it into first empty RAR slot we found */ 3755200239Sjfv rar = first_empty_rar; 3756200239Sjfv ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3757200239Sjfv } else if (rar == hw->mac.rar_highwater) { 3758200239Sjfv /* add it to the top of the list and inc the highwater mark */ 3759200239Sjfv ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3760200239Sjfv hw->mac.rar_highwater++; 3761200239Sjfv } else if (rar >= hw->mac.num_rar_entries) { 3762200239Sjfv return IXGBE_ERR_INVALID_MAC_ADDR; 3763200239Sjfv } 3764200239Sjfv 3765200239Sjfv /* 3766200239Sjfv * If we found rar[0], make sure the default pool bit (we use pool 0) 3767200239Sjfv * remains cleared to be sure default pool packets will get delivered 3768200239Sjfv */ 3769200239Sjfv if (rar == 0) 3770200239Sjfv ixgbe_clear_vmdq(hw, rar, 0); 3771200239Sjfv 3772200239Sjfv return rar; 3773200239Sjfv} 3774200239Sjfv 3775200239Sjfv/** 3776200239Sjfv * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3777200239Sjfv * @hw: pointer to hardware struct 3778200239Sjfv * @rar: receive address register index to disassociate 3779200239Sjfv * @vmdq: VMDq pool index to remove from the rar 3780200239Sjfv **/ 3781200239Sjfvs32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3782200239Sjfv{ 3783200239Sjfv u32 mpsar_lo, mpsar_hi; 3784200239Sjfv u32 rar_entries = hw->mac.num_rar_entries; 3785200239Sjfv 3786200239Sjfv DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3787200239Sjfv 3788215911Sjfv /* Make sure we are using a valid rar index range */ 3789215911Sjfv if (rar >= rar_entries) { 3790251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3791251964Sjfv "RAR index %d is out of range.\n", rar); 3792215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 3793215911Sjfv } 3794200239Sjfv 3795215911Sjfv mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3796215911Sjfv mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3797200239Sjfv 3798283620Serj if (IXGBE_REMOVED(hw->hw_addr)) 3799283620Serj goto done; 3800283620Serj 3801215911Sjfv if (!mpsar_lo && !mpsar_hi) 3802215911Sjfv goto done; 3803215911Sjfv 3804215911Sjfv if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3805215911Sjfv if (mpsar_lo) { 3806215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3807215911Sjfv mpsar_lo = 0; 3808200239Sjfv } 3809215911Sjfv if (mpsar_hi) { 3810215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3811215911Sjfv mpsar_hi = 0; 3812215911Sjfv } 3813215911Sjfv } else if (vmdq < 32) { 3814215911Sjfv mpsar_lo &= ~(1 << vmdq); 3815215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3816200239Sjfv } else { 3817215911Sjfv mpsar_hi &= ~(1 << (vmdq - 32)); 3818215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3819200239Sjfv } 3820200239Sjfv 3821215911Sjfv /* was that the last pool using this rar? */ 3822315333Serj if (mpsar_lo == 0 && mpsar_hi == 0 && 3823315333Serj rar != 0 && rar != hw->mac.san_mac_rar_index) 3824215911Sjfv hw->mac.ops.clear_rar(hw, rar); 3825200239Sjfvdone: 3826200239Sjfv return IXGBE_SUCCESS; 3827200239Sjfv} 3828200239Sjfv 3829200239Sjfv/** 3830200239Sjfv * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3831200239Sjfv * @hw: pointer to hardware struct 3832200239Sjfv * @rar: receive address register index to associate with a VMDq index 3833200239Sjfv * @vmdq: VMDq pool index 3834200239Sjfv **/ 3835200239Sjfvs32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3836200239Sjfv{ 3837200239Sjfv u32 mpsar; 3838200239Sjfv u32 rar_entries = hw->mac.num_rar_entries; 3839200239Sjfv 3840200239Sjfv DEBUGFUNC("ixgbe_set_vmdq_generic"); 3841200239Sjfv 3842215911Sjfv /* Make sure we are using a valid rar index range */ 3843215911Sjfv if (rar >= rar_entries) { 3844251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3845251964Sjfv "RAR index %d is out of range.\n", rar); 3846215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 3847200239Sjfv } 3848215911Sjfv 3849215911Sjfv if (vmdq < 32) { 3850215911Sjfv mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3851215911Sjfv mpsar |= 1 << vmdq; 3852215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3853215911Sjfv } else { 3854215911Sjfv mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3855215911Sjfv mpsar |= 1 << (vmdq - 32); 3856215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3857215911Sjfv } 3858200239Sjfv return IXGBE_SUCCESS; 3859200239Sjfv} 3860200239Sjfv 3861200239Sjfv/** 3862238149Sjfv * This function should only be involved in the IOV mode. 3863238149Sjfv * In IOV mode, Default pool is next pool after the number of 3864238149Sjfv * VFs advertized and not 0. 3865238149Sjfv * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3866238149Sjfv * 3867238149Sjfv * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3868238149Sjfv * @hw: pointer to hardware struct 3869238149Sjfv * @vmdq: VMDq pool index 3870238149Sjfv **/ 3871238149Sjfvs32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3872238149Sjfv{ 3873238149Sjfv u32 rar = hw->mac.san_mac_rar_index; 3874238149Sjfv 3875238149Sjfv DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3876238149Sjfv 3877238149Sjfv if (vmdq < 32) { 3878238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3879238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3880238149Sjfv } else { 3881238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3882238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3883238149Sjfv } 3884238149Sjfv 3885238149Sjfv return IXGBE_SUCCESS; 3886238149Sjfv} 3887238149Sjfv 3888238149Sjfv/** 3889200239Sjfv * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3890200239Sjfv * @hw: pointer to hardware structure 3891200239Sjfv **/ 3892200239Sjfvs32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3893200239Sjfv{ 3894200239Sjfv int i; 3895200239Sjfv 3896200239Sjfv DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3897200239Sjfv DEBUGOUT(" Clearing UTA\n"); 3898200239Sjfv 3899200239Sjfv for (i = 0; i < 128; i++) 3900200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3901200239Sjfv 3902200239Sjfv return IXGBE_SUCCESS; 3903200239Sjfv} 3904200239Sjfv 3905200239Sjfv/** 3906200239Sjfv * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3907200239Sjfv * @hw: pointer to hardware structure 3908200239Sjfv * @vlan: VLAN id to write to VLAN filter 3909200239Sjfv * 3910200239Sjfv * return the VLVF index where this VLAN id should be placed 3911200239Sjfv * 3912200239Sjfv **/ 3913315333Serjs32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3914200239Sjfv{ 3915315333Serj s32 regindex, first_empty_slot; 3916315333Serj u32 bits; 3917200239Sjfv 3918205720Sjfv /* short cut the special case */ 3919205720Sjfv if (vlan == 0) 3920205720Sjfv return 0; 3921205720Sjfv 3922315333Serj /* if vlvf_bypass is set we don't want to use an empty slot, we 3923315333Serj * will simply bypass the VLVF if there are no entries present in the 3924315333Serj * VLVF that contain our VLAN 3925315333Serj */ 3926315333Serj first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3927315333Serj 3928315333Serj /* add VLAN enable bit for comparison */ 3929315333Serj vlan |= IXGBE_VLVF_VIEN; 3930315333Serj 3931315333Serj /* Search for the vlan id in the VLVF entries. Save off the first empty 3932315333Serj * slot found along the way. 3933315333Serj * 3934315333Serj * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3935315333Serj */ 3936315333Serj for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3937200239Sjfv bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3938315333Serj if (bits == vlan) 3939315333Serj return regindex; 3940315333Serj if (!first_empty_slot && !bits) 3941200239Sjfv first_empty_slot = regindex; 3942200239Sjfv } 3943200239Sjfv 3944315333Serj /* If we are here then we didn't find the VLAN. Return first empty 3945315333Serj * slot we found during our search, else error. 3946315333Serj */ 3947315333Serj if (!first_empty_slot) 3948315333Serj ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3949200239Sjfv 3950315333Serj return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3951200239Sjfv} 3952200239Sjfv 3953200239Sjfv/** 3954200239Sjfv * ixgbe_set_vfta_generic - Set VLAN filter table 3955200239Sjfv * @hw: pointer to hardware structure 3956200239Sjfv * @vlan: VLAN id to write to VLAN filter 3957315333Serj * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3958315333Serj * @vlan_on: boolean flag to turn on/off VLAN 3959315333Serj * @vlvf_bypass: boolean flag indicating updating default pool is okay 3960200239Sjfv * 3961200239Sjfv * Turn on/off specified VLAN in the VLAN filter table. 3962200239Sjfv **/ 3963200239Sjfvs32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3964315333Serj bool vlan_on, bool vlvf_bypass) 3965200239Sjfv{ 3966315333Serj u32 regidx, vfta_delta, vfta; 3967315333Serj s32 ret_val; 3968200239Sjfv 3969200239Sjfv DEBUGFUNC("ixgbe_set_vfta_generic"); 3970200239Sjfv 3971315333Serj if (vlan > 4095 || vind > 63) 3972200239Sjfv return IXGBE_ERR_PARAM; 3973200239Sjfv 3974200239Sjfv /* 3975200239Sjfv * this is a 2 part operation - first the VFTA, then the 3976200239Sjfv * VLVF and VLVFB if VT Mode is set 3977205720Sjfv * We don't write the VFTA until we know the VLVF part succeeded. 3978200239Sjfv */ 3979200239Sjfv 3980200239Sjfv /* Part 1 3981200239Sjfv * The VFTA is a bitstring made up of 128 32-bit registers 3982200239Sjfv * that enable the particular VLAN id, much like the MTA: 3983200239Sjfv * bits[11-5]: which register 3984200239Sjfv * bits[4-0]: which bit in the register 3985200239Sjfv */ 3986315333Serj regidx = vlan / 32; 3987315333Serj vfta_delta = 1 << (vlan % 32); 3988315333Serj vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3989200239Sjfv 3990315333Serj /* 3991315333Serj * vfta_delta represents the difference between the current value 3992315333Serj * of vfta and the value we want in the register. Since the diff 3993315333Serj * is an XOR mask we can just update the vfta using an XOR 3994315333Serj */ 3995315333Serj vfta_delta &= vlan_on ? ~vfta : vfta; 3996315333Serj vfta ^= vfta_delta; 3997200239Sjfv 3998200239Sjfv /* Part 2 3999230775Sjfv * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4000230775Sjfv */ 4001315333Serj ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4002315333Serj vfta, vlvf_bypass); 4003315333Serj if (ret_val != IXGBE_SUCCESS) { 4004315333Serj if (vlvf_bypass) 4005315333Serj goto vfta_update; 4006230775Sjfv return ret_val; 4007315333Serj } 4008230775Sjfv 4009315333Serjvfta_update: 4010315333Serj /* Update VFTA now that we are ready for traffic */ 4011315333Serj if (vfta_delta) 4012315333Serj IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4013230775Sjfv 4014230775Sjfv return IXGBE_SUCCESS; 4015230775Sjfv} 4016230775Sjfv 4017230775Sjfv/** 4018230775Sjfv * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4019230775Sjfv * @hw: pointer to hardware structure 4020230775Sjfv * @vlan: VLAN id to write to VLAN filter 4021315333Serj * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4022315333Serj * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4023315333Serj * @vfta_delta: pointer to the difference between the current value of VFTA 4024315333Serj * and the desired value 4025315333Serj * @vfta: the desired value of the VFTA 4026315333Serj * @vlvf_bypass: boolean flag indicating updating default pool is okay 4027230775Sjfv * 4028230775Sjfv * Turn on/off specified bit in VLVF table. 4029230775Sjfv **/ 4030230775Sjfvs32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4031315333Serj bool vlan_on, u32 *vfta_delta, u32 vfta, 4032315333Serj bool vlvf_bypass) 4033230775Sjfv{ 4034315333Serj u32 bits; 4035315333Serj s32 vlvf_index; 4036230775Sjfv 4037230775Sjfv DEBUGFUNC("ixgbe_set_vlvf_generic"); 4038230775Sjfv 4039315333Serj if (vlan > 4095 || vind > 63) 4040230775Sjfv return IXGBE_ERR_PARAM; 4041230775Sjfv 4042230775Sjfv /* If VT Mode is set 4043200239Sjfv * Either vlan_on 4044200239Sjfv * make sure the vlan is in VLVF 4045200239Sjfv * set the vind bit in the matching VLVFB 4046200239Sjfv * Or !vlan_on 4047200239Sjfv * clear the pool bit and possibly the vind 4048200239Sjfv */ 4049315333Serj if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4050315333Serj return IXGBE_SUCCESS; 4051200239Sjfv 4052315333Serj vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4053315333Serj if (vlvf_index < 0) 4054315333Serj return vlvf_index; 4055205720Sjfv 4056315333Serj bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4057200239Sjfv 4058315333Serj /* set the pool bit */ 4059315333Serj bits |= 1 << (vind % 32); 4060315333Serj if (vlan_on) 4061315333Serj goto vlvf_update; 4062315333Serj 4063315333Serj /* clear the pool bit */ 4064315333Serj bits ^= 1 << (vind % 32); 4065315333Serj 4066315333Serj if (!bits && 4067315333Serj !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4068315333Serj /* Clear VFTA first, then disable VLVF. Otherwise 4069315333Serj * we run the risk of stray packets leaking into 4070315333Serj * the PF via the default pool 4071205720Sjfv */ 4072315333Serj if (*vfta_delta) 4073315333Serj IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4074315333Serj 4075315333Serj /* disable VLVF and clear remaining bit from pool */ 4076315333Serj IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4077315333Serj IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4078315333Serj 4079315333Serj return IXGBE_SUCCESS; 4080200239Sjfv } 4081205720Sjfv 4082315333Serj /* If there are still bits set in the VLVFB registers 4083315333Serj * for the VLAN ID indicated we need to see if the 4084315333Serj * caller is requesting that we clear the VFTA entry bit. 4085315333Serj * If the caller has requested that we clear the VFTA 4086315333Serj * entry bit but there are still pools/VFs using this VLAN 4087315333Serj * ID entry then ignore the request. We're not worried 4088315333Serj * about the case where we're turning the VFTA VLAN ID 4089315333Serj * entry bit on, only when requested to turn it off as 4090315333Serj * there may be multiple pools and/or VFs using the 4091315333Serj * VLAN ID entry. In that case we cannot clear the 4092315333Serj * VFTA bit until all pools/VFs using that VLAN ID have also 4093315333Serj * been cleared. This will be indicated by "bits" being 4094315333Serj * zero. 4095315333Serj */ 4096315333Serj *vfta_delta = 0; 4097315333Serj 4098315333Serjvlvf_update: 4099315333Serj /* record pool change and enable VLAN ID if not already enabled */ 4100315333Serj IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4101315333Serj IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4102315333Serj 4103200239Sjfv return IXGBE_SUCCESS; 4104200239Sjfv} 4105200239Sjfv 4106200239Sjfv/** 4107200239Sjfv * ixgbe_clear_vfta_generic - Clear VLAN filter table 4108200239Sjfv * @hw: pointer to hardware structure 4109200239Sjfv * 4110200239Sjfv * Clears the VLAN filer table, and the VMDq index associated with the filter 4111200239Sjfv **/ 4112200239Sjfvs32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4113200239Sjfv{ 4114200239Sjfv u32 offset; 4115200239Sjfv 4116200239Sjfv DEBUGFUNC("ixgbe_clear_vfta_generic"); 4117200239Sjfv 4118200239Sjfv for (offset = 0; offset < hw->mac.vft_size; offset++) 4119200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4120200239Sjfv 4121200239Sjfv for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4122200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4123230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4124315333Serj IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4125200239Sjfv } 4126200239Sjfv 4127200239Sjfv return IXGBE_SUCCESS; 4128200239Sjfv} 4129200239Sjfv 4130200239Sjfv/** 4131315333Serj * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4132315333Serj * @hw: pointer to hardware structure 4133315333Serj * 4134315333Serj * Contains the logic to identify if we need to verify link for the 4135315333Serj * crosstalk fix 4136315333Serj **/ 4137315333Serjstatic bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4138315333Serj{ 4139315333Serj 4140315333Serj /* Does FW say we need the fix */ 4141315333Serj if (!hw->need_crosstalk_fix) 4142315333Serj return FALSE; 4143315333Serj 4144315333Serj /* Only consider SFP+ PHYs i.e. media type fiber */ 4145315333Serj switch (hw->mac.ops.get_media_type(hw)) { 4146315333Serj case ixgbe_media_type_fiber: 4147315333Serj case ixgbe_media_type_fiber_qsfp: 4148315333Serj break; 4149315333Serj default: 4150315333Serj return FALSE; 4151315333Serj } 4152315333Serj 4153315333Serj return TRUE; 4154315333Serj} 4155315333Serj 4156315333Serj/** 4157200239Sjfv * ixgbe_check_mac_link_generic - Determine link and speed status 4158200239Sjfv * @hw: pointer to hardware structure 4159200239Sjfv * @speed: pointer to link speed 4160200239Sjfv * @link_up: TRUE when link is up 4161200239Sjfv * @link_up_wait_to_complete: bool used to wait for link up or not 4162200239Sjfv * 4163200239Sjfv * Reads the links register to determine if link is up and the current speed 4164200239Sjfv **/ 4165200239Sjfvs32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4166230775Sjfv bool *link_up, bool link_up_wait_to_complete) 4167200239Sjfv{ 4168205720Sjfv u32 links_reg, links_orig; 4169200239Sjfv u32 i; 4170200239Sjfv 4171200239Sjfv DEBUGFUNC("ixgbe_check_mac_link_generic"); 4172200239Sjfv 4173315333Serj /* If Crosstalk fix enabled do the sanity check of making sure 4174315333Serj * the SFP+ cage is full. 4175315333Serj */ 4176315333Serj if (ixgbe_need_crosstalk_fix(hw)) { 4177315333Serj u32 sfp_cage_full; 4178315333Serj 4179315333Serj switch (hw->mac.type) { 4180315333Serj case ixgbe_mac_82599EB: 4181315333Serj sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4182315333Serj IXGBE_ESDP_SDP2; 4183315333Serj break; 4184315333Serj case ixgbe_mac_X550EM_x: 4185315333Serj case ixgbe_mac_X550EM_a: 4186315333Serj sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4187315333Serj IXGBE_ESDP_SDP0; 4188315333Serj break; 4189315333Serj default: 4190315333Serj /* sanity check - No SFP+ devices here */ 4191315333Serj sfp_cage_full = FALSE; 4192315333Serj break; 4193315333Serj } 4194315333Serj 4195315333Serj if (!sfp_cage_full) { 4196315333Serj *link_up = FALSE; 4197315333Serj *speed = IXGBE_LINK_SPEED_UNKNOWN; 4198315333Serj return IXGBE_SUCCESS; 4199315333Serj } 4200315333Serj } 4201315333Serj 4202205720Sjfv /* clear the old state */ 4203205720Sjfv links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4204205720Sjfv 4205200239Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4206205720Sjfv 4207205720Sjfv if (links_orig != links_reg) { 4208205720Sjfv DEBUGOUT2("LINKS changed from %08X to %08X\n", 4209230775Sjfv links_orig, links_reg); 4210205720Sjfv } 4211205720Sjfv 4212200239Sjfv if (link_up_wait_to_complete) { 4213295524Ssbruno for (i = 0; i < hw->mac.max_link_up_time; i++) { 4214200239Sjfv if (links_reg & IXGBE_LINKS_UP) { 4215200239Sjfv *link_up = TRUE; 4216200239Sjfv break; 4217200239Sjfv } else { 4218200239Sjfv *link_up = FALSE; 4219200239Sjfv } 4220200239Sjfv msec_delay(100); 4221200239Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4222200239Sjfv } 4223200239Sjfv } else { 4224200239Sjfv if (links_reg & IXGBE_LINKS_UP) 4225200239Sjfv *link_up = TRUE; 4226200239Sjfv else 4227200239Sjfv *link_up = FALSE; 4228200239Sjfv } 4229200239Sjfv 4230283620Serj switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4231283620Serj case IXGBE_LINKS_SPEED_10G_82599: 4232200239Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 4233283620Serj if (hw->mac.type >= ixgbe_mac_X550) { 4234283620Serj if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4235283620Serj *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4236283620Serj } 4237283620Serj break; 4238283620Serj case IXGBE_LINKS_SPEED_1G_82599: 4239200239Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 4240283620Serj break; 4241283620Serj case IXGBE_LINKS_SPEED_100_82599: 4242215911Sjfv *speed = IXGBE_LINK_SPEED_100_FULL; 4243315333Serj if (hw->mac.type == ixgbe_mac_X550) { 4244283620Serj if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4245283620Serj *speed = IXGBE_LINK_SPEED_5GB_FULL; 4246283620Serj } 4247283620Serj break; 4248315333Serj case IXGBE_LINKS_SPEED_10_X550EM_A: 4249315333Serj *speed = IXGBE_LINK_SPEED_UNKNOWN; 4250315333Serj if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4251315333Serj hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 4252315333Serj *speed = IXGBE_LINK_SPEED_10_FULL; 4253315333Serj } 4254315333Serj break; 4255283620Serj default: 4256215911Sjfv *speed = IXGBE_LINK_SPEED_UNKNOWN; 4257283620Serj } 4258200239Sjfv 4259200239Sjfv return IXGBE_SUCCESS; 4260200239Sjfv} 4261200239Sjfv 4262200239Sjfv/** 4263200239Sjfv * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4264200239Sjfv * the EEPROM 4265200239Sjfv * @hw: pointer to hardware structure 4266200239Sjfv * @wwnn_prefix: the alternative WWNN prefix 4267200239Sjfv * @wwpn_prefix: the alternative WWPN prefix 4268200239Sjfv * 4269200239Sjfv * This function will read the EEPROM from the alternative SAN MAC address 4270200239Sjfv * block to check the support for the alternative WWNN/WWPN prefix support. 4271200239Sjfv **/ 4272200239Sjfvs32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4273230775Sjfv u16 *wwpn_prefix) 4274200239Sjfv{ 4275200239Sjfv u16 offset, caps; 4276200239Sjfv u16 alt_san_mac_blk_offset; 4277200239Sjfv 4278200239Sjfv DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4279200239Sjfv 4280200239Sjfv /* clear output first */ 4281200239Sjfv *wwnn_prefix = 0xFFFF; 4282200239Sjfv *wwpn_prefix = 0xFFFF; 4283200239Sjfv 4284200239Sjfv /* check if alternative SAN MAC is supported */ 4285251964Sjfv offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4286251964Sjfv if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4287251964Sjfv goto wwn_prefix_err; 4288200239Sjfv 4289200239Sjfv if ((alt_san_mac_blk_offset == 0) || 4290200239Sjfv (alt_san_mac_blk_offset == 0xFFFF)) 4291200239Sjfv goto wwn_prefix_out; 4292200239Sjfv 4293200239Sjfv /* check capability in alternative san mac address block */ 4294200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4295251964Sjfv if (hw->eeprom.ops.read(hw, offset, &caps)) 4296251964Sjfv goto wwn_prefix_err; 4297200239Sjfv if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4298200239Sjfv goto wwn_prefix_out; 4299200239Sjfv 4300200239Sjfv /* get the corresponding prefix for WWNN/WWPN */ 4301200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4302251964Sjfv if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4303251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4304251964Sjfv "eeprom read at offset %d failed", offset); 4305251964Sjfv } 4306200239Sjfv 4307200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4308251964Sjfv if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4309251964Sjfv goto wwn_prefix_err; 4310200239Sjfv 4311200239Sjfvwwn_prefix_out: 4312200239Sjfv return IXGBE_SUCCESS; 4313251964Sjfv 4314251964Sjfvwwn_prefix_err: 4315251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4316251964Sjfv "eeprom read at offset %d failed", offset); 4317251964Sjfv return IXGBE_SUCCESS; 4318200239Sjfv} 4319215911Sjfv 4320215911Sjfv/** 4321215911Sjfv * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4322215911Sjfv * @hw: pointer to hardware structure 4323215911Sjfv * @bs: the fcoe boot status 4324215911Sjfv * 4325215911Sjfv * This function will read the FCOE boot status from the iSCSI FCOE block 4326215911Sjfv **/ 4327215911Sjfvs32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4328215911Sjfv{ 4329215911Sjfv u16 offset, caps, flags; 4330215911Sjfv s32 status; 4331215911Sjfv 4332215911Sjfv DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4333215911Sjfv 4334215911Sjfv /* clear output first */ 4335215911Sjfv *bs = ixgbe_fcoe_bootstatus_unavailable; 4336215911Sjfv 4337215911Sjfv /* check if FCOE IBA block is present */ 4338215911Sjfv offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4339215911Sjfv status = hw->eeprom.ops.read(hw, offset, &caps); 4340215911Sjfv if (status != IXGBE_SUCCESS) 4341215911Sjfv goto out; 4342215911Sjfv 4343215911Sjfv if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4344215911Sjfv goto out; 4345215911Sjfv 4346215911Sjfv /* check if iSCSI FCOE block is populated */ 4347215911Sjfv status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4348215911Sjfv if (status != IXGBE_SUCCESS) 4349215911Sjfv goto out; 4350215911Sjfv 4351215911Sjfv if ((offset == 0) || (offset == 0xFFFF)) 4352215911Sjfv goto out; 4353215911Sjfv 4354215911Sjfv /* read fcoe flags in iSCSI FCOE block */ 4355215911Sjfv offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4356215911Sjfv status = hw->eeprom.ops.read(hw, offset, &flags); 4357215911Sjfv if (status != IXGBE_SUCCESS) 4358215911Sjfv goto out; 4359215911Sjfv 4360215911Sjfv if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4361215911Sjfv *bs = ixgbe_fcoe_bootstatus_enabled; 4362215911Sjfv else 4363215911Sjfv *bs = ixgbe_fcoe_bootstatus_disabled; 4364215911Sjfv 4365215911Sjfvout: 4366215911Sjfv return status; 4367215911Sjfv} 4368215911Sjfv 4369215911Sjfv/** 4370215911Sjfv * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4371215911Sjfv * @hw: pointer to hardware structure 4372315333Serj * @enable: enable or disable switch for MAC anti-spoofing 4373315333Serj * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4374215911Sjfv * 4375215911Sjfv **/ 4376315333Serjvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4377215911Sjfv{ 4378315333Serj int vf_target_reg = vf >> 3; 4379315333Serj int vf_target_shift = vf % 8; 4380315333Serj u32 pfvfspoof; 4381215911Sjfv 4382215911Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 4383215911Sjfv return; 4384215911Sjfv 4385315333Serj pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4386215911Sjfv if (enable) 4387315333Serj pfvfspoof |= (1 << vf_target_shift); 4388315333Serj else 4389315333Serj pfvfspoof &= ~(1 << vf_target_shift); 4390315333Serj IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4391215911Sjfv} 4392215911Sjfv 4393215911Sjfv/** 4394215911Sjfv * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4395215911Sjfv * @hw: pointer to hardware structure 4396215911Sjfv * @enable: enable or disable switch for VLAN anti-spoofing 4397283620Serj * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4398215911Sjfv * 4399215911Sjfv **/ 4400215911Sjfvvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4401215911Sjfv{ 4402215911Sjfv int vf_target_reg = vf >> 3; 4403215911Sjfv int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4404215911Sjfv u32 pfvfspoof; 4405215911Sjfv 4406215911Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 4407215911Sjfv return; 4408215911Sjfv 4409215911Sjfv pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4410215911Sjfv if (enable) 4411215911Sjfv pfvfspoof |= (1 << vf_target_shift); 4412215911Sjfv else 4413215911Sjfv pfvfspoof &= ~(1 << vf_target_shift); 4414215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4415215911Sjfv} 4416217593Sjfv 4417217593Sjfv/** 4418217593Sjfv * ixgbe_get_device_caps_generic - Get additional device capabilities 4419217593Sjfv * @hw: pointer to hardware structure 4420217593Sjfv * @device_caps: the EEPROM word with the extra device capabilities 4421217593Sjfv * 4422217593Sjfv * This function will read the EEPROM location for the device capabilities, 4423217593Sjfv * and return the word through device_caps. 4424217593Sjfv **/ 4425217593Sjfvs32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4426217593Sjfv{ 4427217593Sjfv DEBUGFUNC("ixgbe_get_device_caps_generic"); 4428217593Sjfv 4429217593Sjfv hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4430217593Sjfv 4431217593Sjfv return IXGBE_SUCCESS; 4432217593Sjfv} 4433217593Sjfv 4434217593Sjfv/** 4435217593Sjfv * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4436217593Sjfv * @hw: pointer to hardware structure 4437217593Sjfv * 4438217593Sjfv **/ 4439217593Sjfvvoid ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4440217593Sjfv{ 4441217593Sjfv u32 regval; 4442217593Sjfv u32 i; 4443217593Sjfv 4444217593Sjfv DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4445217593Sjfv 4446217593Sjfv /* Enable relaxed ordering */ 4447217593Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 4448217593Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4449238149Sjfv regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4450217593Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4451217593Sjfv } 4452217593Sjfv 4453217593Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 4454217593Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4455238149Sjfv regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4456238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4457217593Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4458217593Sjfv } 4459217593Sjfv 4460217593Sjfv} 4461230775Sjfv 4462230775Sjfv/** 4463230775Sjfv * ixgbe_calculate_checksum - Calculate checksum for buffer 4464230775Sjfv * @buffer: pointer to EEPROM 4465230775Sjfv * @length: size of EEPROM to calculate a checksum for 4466230775Sjfv * Calculates the checksum for some buffer on a specified length. The 4467230775Sjfv * checksum calculated is returned. 4468230775Sjfv **/ 4469247822Sjfvu8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4470230775Sjfv{ 4471230775Sjfv u32 i; 4472230775Sjfv u8 sum = 0; 4473230775Sjfv 4474230775Sjfv DEBUGFUNC("ixgbe_calculate_checksum"); 4475230775Sjfv 4476230775Sjfv if (!buffer) 4477230775Sjfv return 0; 4478230775Sjfv 4479230775Sjfv for (i = 0; i < length; i++) 4480230775Sjfv sum += buffer[i]; 4481230775Sjfv 4482230775Sjfv return (u8) (0 - sum); 4483230775Sjfv} 4484230775Sjfv 4485230775Sjfv/** 4486315333Serj * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4487230775Sjfv * @hw: pointer to the HW structure 4488315333Serj * @buffer: command to write and where the return status will be placed 4489238149Sjfv * @length: length of buffer, must be multiple of 4 bytes 4490283620Serj * @timeout: time in ms to wait for command completion 4491230775Sjfv * 4492315333Serj * Communicates with the manageability block. On success return IXGBE_SUCCESS 4493315333Serj * else returns semaphore error when encountering an error acquiring 4494315333Serj * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4495315333Serj * 4496315333Serj * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4497315333Serj * by the caller. 4498230775Sjfv **/ 4499315333Serjs32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4500315333Serj u32 timeout) 4501230775Sjfv{ 4502315333Serj u32 hicr, i, fwsts; 4503283620Serj u16 dword_len; 4504230775Sjfv 4505315333Serj DEBUGFUNC("ixgbe_hic_unlocked"); 4506230775Sjfv 4507315333Serj if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4508283620Serj DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4509283620Serj return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4510230775Sjfv } 4511315333Serj 4512283620Serj /* Set bit 9 of FWSTS clearing FW reset indication */ 4513283620Serj fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4514283620Serj IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4515230775Sjfv 4516230775Sjfv /* Check that the host interface is enabled. */ 4517230775Sjfv hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4518315333Serj if (!(hicr & IXGBE_HICR_EN)) { 4519230775Sjfv DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4520283620Serj return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4521230775Sjfv } 4522230775Sjfv 4523283620Serj /* Calculate length in DWORDs. We must be DWORD aligned */ 4524315333Serj if (length % sizeof(u32)) { 4525283620Serj DEBUGOUT("Buffer length failure, not aligned to dword"); 4526283620Serj return IXGBE_ERR_INVALID_ARGUMENT; 4527283620Serj } 4528283620Serj 4529230775Sjfv dword_len = length >> 2; 4530230775Sjfv 4531283620Serj /* The device driver writes the relevant command block 4532230775Sjfv * into the ram area. 4533230775Sjfv */ 4534230775Sjfv for (i = 0; i < dword_len; i++) 4535230775Sjfv IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4536230775Sjfv i, IXGBE_CPU_TO_LE32(buffer[i])); 4537230775Sjfv 4538230775Sjfv /* Setting this bit tells the ARC that a new command is pending. */ 4539230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4540230775Sjfv 4541283620Serj for (i = 0; i < timeout; i++) { 4542230775Sjfv hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4543230775Sjfv if (!(hicr & IXGBE_HICR_C)) 4544230775Sjfv break; 4545230775Sjfv msec_delay(1); 4546230775Sjfv } 4547230775Sjfv 4548283620Serj /* Check command completion */ 4549315333Serj if ((timeout && i == timeout) || 4550283620Serj !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4551283620Serj ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4552283620Serj "Command has failed with no status valid.\n"); 4553283620Serj return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4554230775Sjfv } 4555230775Sjfv 4556315333Serj return IXGBE_SUCCESS; 4557315333Serj} 4558315333Serj 4559315333Serj/** 4560315333Serj * ixgbe_host_interface_command - Issue command to manageability block 4561315333Serj * @hw: pointer to the HW structure 4562315333Serj * @buffer: contains the command to write and where the return status will 4563315333Serj * be placed 4564315333Serj * @length: length of buffer, must be multiple of 4 bytes 4565315333Serj * @timeout: time in ms to wait for command completion 4566315333Serj * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4567315333Serj * Needed because FW structures are big endian and decoding of 4568315333Serj * these fields can be 8 bit or 16 bit based on command. Decoding 4569315333Serj * is not easily understood without making a table of commands. 4570315333Serj * So we will leave this up to the caller to read back the data 4571315333Serj * in these cases. 4572315333Serj * 4573315333Serj * Communicates with the manageability block. On success return IXGBE_SUCCESS 4574315333Serj * else returns semaphore error when encountering an error acquiring 4575315333Serj * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4576315333Serj **/ 4577315333Serjs32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4578315333Serj u32 length, u32 timeout, bool return_data) 4579315333Serj{ 4580315333Serj u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4581315333Serj u16 dword_len; 4582315333Serj u16 buf_len; 4583315333Serj s32 status; 4584315333Serj u32 bi; 4585315333Serj 4586315333Serj DEBUGFUNC("ixgbe_host_interface_command"); 4587315333Serj 4588315333Serj if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4589315333Serj DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4590315333Serj return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4591315333Serj } 4592315333Serj 4593315333Serj /* Take management host interface semaphore */ 4594315333Serj status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4595315333Serj if (status) 4596315333Serj return status; 4597315333Serj 4598315333Serj status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4599315333Serj if (status) 4600315333Serj goto rel_out; 4601315333Serj 4602283620Serj if (!return_data) 4603315333Serj goto rel_out; 4604283620Serj 4605230775Sjfv /* Calculate length in DWORDs */ 4606230775Sjfv dword_len = hdr_size >> 2; 4607230775Sjfv 4608230775Sjfv /* first pull in the header so we know the buffer length */ 4609230775Sjfv for (bi = 0; bi < dword_len; bi++) { 4610230775Sjfv buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4611230775Sjfv IXGBE_LE32_TO_CPUS(&buffer[bi]); 4612230775Sjfv } 4613230775Sjfv 4614230775Sjfv /* If there is any thing in data position pull it in */ 4615230775Sjfv buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 4616315333Serj if (!buf_len) 4617315333Serj goto rel_out; 4618230775Sjfv 4619283620Serj if (length < buf_len + hdr_size) { 4620230775Sjfv DEBUGOUT("Buffer not large enough for reply message.\n"); 4621315333Serj status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4622315333Serj goto rel_out; 4623230775Sjfv } 4624230775Sjfv 4625230775Sjfv /* Calculate length in DWORDs, add 3 for odd lengths */ 4626230775Sjfv dword_len = (buf_len + 3) >> 2; 4627230775Sjfv 4628283620Serj /* Pull in the rest of the buffer (bi is where we left off) */ 4629230775Sjfv for (; bi <= dword_len; bi++) { 4630230775Sjfv buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4631230775Sjfv IXGBE_LE32_TO_CPUS(&buffer[bi]); 4632230775Sjfv } 4633230775Sjfv 4634315333Serjrel_out: 4635315333Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4636315333Serj 4637315333Serj return status; 4638230775Sjfv} 4639230775Sjfv 4640230775Sjfv/** 4641230775Sjfv * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4642230775Sjfv * @hw: pointer to the HW structure 4643230775Sjfv * @maj: driver version major number 4644230775Sjfv * @min: driver version minor number 4645230775Sjfv * @build: driver version build number 4646230775Sjfv * @sub: driver version sub build number 4647230775Sjfv * 4648230775Sjfv * Sends driver version number to firmware through the manageability 4649230775Sjfv * block. On success return IXGBE_SUCCESS 4650230775Sjfv * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4651230775Sjfv * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4652230775Sjfv **/ 4653230775Sjfvs32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4654315333Serj u8 build, u8 sub, u16 len, 4655315333Serj const char *driver_ver) 4656230775Sjfv{ 4657230775Sjfv struct ixgbe_hic_drv_info fw_cmd; 4658230775Sjfv int i; 4659230775Sjfv s32 ret_val = IXGBE_SUCCESS; 4660230775Sjfv 4661230775Sjfv DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4662315333Serj UNREFERENCED_2PARAMETER(len, driver_ver); 4663230775Sjfv 4664230775Sjfv fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4665230775Sjfv fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4666230775Sjfv fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4667230775Sjfv fw_cmd.port_num = (u8)hw->bus.func; 4668230775Sjfv fw_cmd.ver_maj = maj; 4669230775Sjfv fw_cmd.ver_min = min; 4670230775Sjfv fw_cmd.ver_build = build; 4671230775Sjfv fw_cmd.ver_sub = sub; 4672230775Sjfv fw_cmd.hdr.checksum = 0; 4673230775Sjfv fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4674230775Sjfv (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4675230775Sjfv fw_cmd.pad = 0; 4676230775Sjfv fw_cmd.pad2 = 0; 4677230775Sjfv 4678230775Sjfv for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4679230775Sjfv ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4680283620Serj sizeof(fw_cmd), 4681283620Serj IXGBE_HI_COMMAND_TIMEOUT, 4682283620Serj TRUE); 4683230775Sjfv if (ret_val != IXGBE_SUCCESS) 4684230775Sjfv continue; 4685230775Sjfv 4686230775Sjfv if (fw_cmd.hdr.cmd_or_resp.ret_status == 4687230775Sjfv FW_CEM_RESP_STATUS_SUCCESS) 4688230775Sjfv ret_val = IXGBE_SUCCESS; 4689230775Sjfv else 4690230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4691230775Sjfv 4692230775Sjfv break; 4693230775Sjfv } 4694230775Sjfv 4695230775Sjfv return ret_val; 4696230775Sjfv} 4697230775Sjfv 4698230775Sjfv/** 4699230775Sjfv * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4700230775Sjfv * @hw: pointer to hardware structure 4701230775Sjfv * @num_pb: number of packet buffers to allocate 4702230775Sjfv * @headroom: reserve n KB of headroom 4703230775Sjfv * @strategy: packet buffer allocation strategy 4704230775Sjfv **/ 4705230775Sjfvvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4706230775Sjfv int strategy) 4707230775Sjfv{ 4708230775Sjfv u32 pbsize = hw->mac.rx_pb_size; 4709230775Sjfv int i = 0; 4710230775Sjfv u32 rxpktsize, txpktsize, txpbthresh; 4711230775Sjfv 4712230775Sjfv /* Reserve headroom */ 4713230775Sjfv pbsize -= headroom; 4714230775Sjfv 4715230775Sjfv if (!num_pb) 4716230775Sjfv num_pb = 1; 4717230775Sjfv 4718230775Sjfv /* Divide remaining packet buffer space amongst the number of packet 4719230775Sjfv * buffers requested using supplied strategy. 4720230775Sjfv */ 4721230775Sjfv switch (strategy) { 4722238149Sjfv case PBA_STRATEGY_WEIGHTED: 4723230775Sjfv /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4724230775Sjfv * buffer with 5/8 of the packet buffer space. 4725230775Sjfv */ 4726238149Sjfv rxpktsize = (pbsize * 5) / (num_pb * 4); 4727230775Sjfv pbsize -= rxpktsize * (num_pb / 2); 4728230775Sjfv rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4729230775Sjfv for (; i < (num_pb / 2); i++) 4730230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4731230775Sjfv /* Fall through to configure remaining packet buffers */ 4732238149Sjfv case PBA_STRATEGY_EQUAL: 4733230775Sjfv rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4734230775Sjfv for (; i < num_pb; i++) 4735230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4736230775Sjfv break; 4737230775Sjfv default: 4738230775Sjfv break; 4739230775Sjfv } 4740230775Sjfv 4741230775Sjfv /* Only support an equally distributed Tx packet buffer strategy. */ 4742230775Sjfv txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4743230775Sjfv txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4744230775Sjfv for (i = 0; i < num_pb; i++) { 4745230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4746230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4747230775Sjfv } 4748230775Sjfv 4749230775Sjfv /* Clear unused TCs, if any, to zero buffer size*/ 4750230775Sjfv for (; i < IXGBE_MAX_PB; i++) { 4751230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4752230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4753230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4754230775Sjfv } 4755230775Sjfv} 4756230775Sjfv 4757230775Sjfv/** 4758230775Sjfv * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4759230775Sjfv * @hw: pointer to the hardware structure 4760230775Sjfv * 4761230775Sjfv * The 82599 and x540 MACs can experience issues if TX work is still pending 4762230775Sjfv * when a reset occurs. This function prevents this by flushing the PCIe 4763230775Sjfv * buffers on the system. 4764230775Sjfv **/ 4765230775Sjfvvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4766230775Sjfv{ 4767283620Serj u32 gcr_ext, hlreg0, i, poll; 4768283620Serj u16 value; 4769230775Sjfv 4770230775Sjfv /* 4771230775Sjfv * If double reset is not requested then all transactions should 4772230775Sjfv * already be clear and as such there is no work to do 4773230775Sjfv */ 4774230775Sjfv if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4775230775Sjfv return; 4776230775Sjfv 4777230775Sjfv /* 4778230775Sjfv * Set loopback enable to prevent any transmits from being sent 4779230775Sjfv * should the link come up. This assumes that the RXCTRL.RXEN bit 4780230775Sjfv * has already been cleared. 4781230775Sjfv */ 4782230775Sjfv hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4783230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4784230775Sjfv 4785283620Serj /* Wait for a last completion before clearing buffers */ 4786283620Serj IXGBE_WRITE_FLUSH(hw); 4787283620Serj msec_delay(3); 4788283620Serj 4789283620Serj /* 4790283620Serj * Before proceeding, make sure that the PCIe block does not have 4791283620Serj * transactions pending. 4792283620Serj */ 4793283620Serj poll = ixgbe_pcie_timeout_poll(hw); 4794283620Serj for (i = 0; i < poll; i++) { 4795283620Serj usec_delay(100); 4796283620Serj value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4797283620Serj if (IXGBE_REMOVED(hw->hw_addr)) 4798283620Serj goto out; 4799283620Serj if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4800283620Serj goto out; 4801283620Serj } 4802283620Serj 4803283620Serjout: 4804230775Sjfv /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4805230775Sjfv gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4806230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4807230775Sjfv gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4808230775Sjfv 4809230775Sjfv /* Flush all writes and allow 20usec for all transactions to clear */ 4810230775Sjfv IXGBE_WRITE_FLUSH(hw); 4811230775Sjfv usec_delay(20); 4812230775Sjfv 4813230775Sjfv /* restore previous register values */ 4814230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4815230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4816230775Sjfv} 4817230775Sjfv 4818315333Serj/** 4819315333Serj * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4820315333Serj * 4821315333Serj * @hw: pointer to hardware structure 4822315333Serj * @cmd: Command we send to the FW 4823315333Serj * @status: The reply from the FW 4824315333Serj * 4825315333Serj * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4826315333Serj **/ 4827315333Serj#define IXGBE_BYPASS_BB_WAIT 1 4828315333Serjs32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4829315333Serj{ 4830315333Serj int i; 4831315333Serj u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4832315333Serj u32 esdp; 4833251964Sjfv 4834315333Serj if (!status) 4835315333Serj return IXGBE_ERR_PARAM; 4836315333Serj 4837315333Serj *status = 0; 4838315333Serj 4839315333Serj /* SDP vary by MAC type */ 4840315333Serj switch (hw->mac.type) { 4841315333Serj case ixgbe_mac_82599EB: 4842315333Serj sck = IXGBE_ESDP_SDP7; 4843315333Serj sdi = IXGBE_ESDP_SDP0; 4844315333Serj sdo = IXGBE_ESDP_SDP6; 4845315333Serj dir_sck = IXGBE_ESDP_SDP7_DIR; 4846315333Serj dir_sdi = IXGBE_ESDP_SDP0_DIR; 4847315333Serj dir_sdo = IXGBE_ESDP_SDP6_DIR; 4848315333Serj break; 4849315333Serj case ixgbe_mac_X540: 4850315333Serj sck = IXGBE_ESDP_SDP2; 4851315333Serj sdi = IXGBE_ESDP_SDP0; 4852315333Serj sdo = IXGBE_ESDP_SDP1; 4853315333Serj dir_sck = IXGBE_ESDP_SDP2_DIR; 4854315333Serj dir_sdi = IXGBE_ESDP_SDP0_DIR; 4855315333Serj dir_sdo = IXGBE_ESDP_SDP1_DIR; 4856315333Serj break; 4857315333Serj default: 4858315333Serj return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4859315333Serj } 4860315333Serj 4861315333Serj /* Set SDP pins direction */ 4862315333Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4863315333Serj esdp |= dir_sck; /* SCK as output */ 4864315333Serj esdp |= dir_sdi; /* SDI as output */ 4865315333Serj esdp &= ~dir_sdo; /* SDO as input */ 4866315333Serj esdp |= sck; 4867315333Serj esdp |= sdi; 4868315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4869315333Serj IXGBE_WRITE_FLUSH(hw); 4870315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4871315333Serj 4872315333Serj /* Generate start condition */ 4873315333Serj esdp &= ~sdi; 4874315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4875315333Serj IXGBE_WRITE_FLUSH(hw); 4876315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4877315333Serj 4878315333Serj esdp &= ~sck; 4879315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4880315333Serj IXGBE_WRITE_FLUSH(hw); 4881315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4882315333Serj 4883315333Serj /* Clock out the new control word and clock in the status */ 4884315333Serj for (i = 0; i < 32; i++) { 4885315333Serj if ((cmd >> (31 - i)) & 0x01) { 4886315333Serj esdp |= sdi; 4887315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4888315333Serj } else { 4889315333Serj esdp &= ~sdi; 4890315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4891315333Serj } 4892315333Serj IXGBE_WRITE_FLUSH(hw); 4893315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4894315333Serj 4895315333Serj esdp |= sck; 4896315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4897315333Serj IXGBE_WRITE_FLUSH(hw); 4898315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4899315333Serj 4900315333Serj esdp &= ~sck; 4901315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4902315333Serj IXGBE_WRITE_FLUSH(hw); 4903315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4904315333Serj 4905315333Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4906315333Serj if (esdp & sdo) 4907315333Serj *status = (*status << 1) | 0x01; 4908315333Serj else 4909315333Serj *status = (*status << 1) | 0x00; 4910315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4911315333Serj } 4912315333Serj 4913315333Serj /* stop condition */ 4914315333Serj esdp |= sck; 4915315333Serj esdp &= ~sdi; 4916315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4917315333Serj IXGBE_WRITE_FLUSH(hw); 4918315333Serj msec_delay(IXGBE_BYPASS_BB_WAIT); 4919315333Serj 4920315333Serj esdp |= sdi; 4921315333Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4922315333Serj IXGBE_WRITE_FLUSH(hw); 4923315333Serj 4924315333Serj /* set the page bits to match the cmd that the status it belongs to */ 4925315333Serj *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 4926315333Serj 4927315333Serj return IXGBE_SUCCESS; 4928315333Serj} 4929315333Serj 4930251964Sjfv/** 4931315333Serj * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 4932315333Serj * 4933315333Serj * If we send a write we can't be sure it took until we can read back 4934315333Serj * that same register. It can be a problem as some of the feilds may 4935315333Serj * for valid reasons change inbetween the time wrote the register and 4936315333Serj * we read it again to verify. So this function check everything we 4937315333Serj * can check and then assumes it worked. 4938315333Serj * 4939315333Serj * @u32 in_reg - The register cmd for the bit-bang read. 4940315333Serj * @u32 out_reg - The register returned from a bit-bang read. 4941315333Serj **/ 4942315333Serjbool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 4943315333Serj{ 4944315333Serj u32 mask; 4945315333Serj 4946315333Serj /* Page must match for all control pages */ 4947315333Serj if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 4948315333Serj return FALSE; 4949315333Serj 4950315333Serj switch (in_reg & BYPASS_PAGE_M) { 4951315333Serj case BYPASS_PAGE_CTL0: 4952315333Serj /* All the following can't change since the last write 4953315333Serj * - All the event actions 4954315333Serj * - The timeout value 4955315333Serj */ 4956315333Serj mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 4957315333Serj BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 4958315333Serj BYPASS_WDTIMEOUT_M | 4959315333Serj BYPASS_WDT_VALUE_M; 4960315333Serj if ((out_reg & mask) != (in_reg & mask)) 4961315333Serj return FALSE; 4962315333Serj 4963315333Serj /* 0x0 is never a valid value for bypass status */ 4964315333Serj if (!(out_reg & BYPASS_STATUS_OFF_M)) 4965315333Serj return FALSE; 4966315333Serj break; 4967315333Serj case BYPASS_PAGE_CTL1: 4968315333Serj /* All the following can't change since the last write 4969315333Serj * - time valid bit 4970315333Serj * - time we last sent 4971315333Serj */ 4972315333Serj mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 4973315333Serj if ((out_reg & mask) != (in_reg & mask)) 4974315333Serj return FALSE; 4975315333Serj break; 4976315333Serj case BYPASS_PAGE_CTL2: 4977315333Serj /* All we can check in this page is control number 4978315333Serj * which is already done above. 4979315333Serj */ 4980315333Serj break; 4981315333Serj } 4982315333Serj 4983315333Serj /* We are as sure as we can be return TRUE */ 4984315333Serj return TRUE; 4985315333Serj} 4986315333Serj 4987315333Serj/** 4988315333Serj * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 4989315333Serj * 4990315333Serj * @hw: pointer to hardware structure 4991315333Serj * @cmd: The control word we are setting. 4992315333Serj * @event: The event we are setting in the FW. This also happens to 4993315333Serj * be the mask for the event we are setting (handy) 4994315333Serj * @action: The action we set the event to in the FW. This is in a 4995315333Serj * bit field that happens to be what we want to put in 4996315333Serj * the event spot (also handy) 4997315333Serj **/ 4998315333Serjs32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 4999315333Serj u32 action) 5000315333Serj{ 5001315333Serj u32 by_ctl = 0; 5002315333Serj u32 cmd, verify; 5003315333Serj u32 count = 0; 5004315333Serj 5005315333Serj /* Get current values */ 5006315333Serj cmd = ctrl; /* just reading only need control number */ 5007315333Serj if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5008315333Serj return IXGBE_ERR_INVALID_ARGUMENT; 5009315333Serj 5010315333Serj /* Set to new action */ 5011315333Serj cmd = (by_ctl & ~event) | BYPASS_WE | action; 5012315333Serj if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5013315333Serj return IXGBE_ERR_INVALID_ARGUMENT; 5014315333Serj 5015315333Serj /* Page 0 force a FW eeprom write which is slow so verify */ 5016315333Serj if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5017315333Serj verify = BYPASS_PAGE_CTL0; 5018315333Serj do { 5019315333Serj if (count++ > 5) 5020315333Serj return IXGBE_BYPASS_FW_WRITE_FAILURE; 5021315333Serj 5022315333Serj if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5023315333Serj return IXGBE_ERR_INVALID_ARGUMENT; 5024315333Serj } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5025315333Serj } else { 5026315333Serj /* We have give the FW time for the write to stick */ 5027315333Serj msec_delay(100); 5028315333Serj } 5029315333Serj 5030315333Serj return IXGBE_SUCCESS; 5031315333Serj} 5032315333Serj 5033315333Serj/** 5034315333Serj * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5035315333Serj * 5036315333Serj * @hw: pointer to hardware structure 5037315333Serj * @addr: The bypass eeprom address to read. 5038315333Serj * @value: The 8b of data at the address above. 5039315333Serj **/ 5040315333Serjs32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5041315333Serj{ 5042315333Serj u32 cmd; 5043315333Serj u32 status; 5044315333Serj 5045315333Serj 5046315333Serj /* send the request */ 5047315333Serj cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5048315333Serj cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5049315333Serj if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5050315333Serj return IXGBE_ERR_INVALID_ARGUMENT; 5051315333Serj 5052315333Serj /* We have give the FW time for the write to stick */ 5053315333Serj msec_delay(100); 5054315333Serj 5055315333Serj /* now read the results */ 5056315333Serj cmd &= ~BYPASS_WE; 5057315333Serj if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5058315333Serj return IXGBE_ERR_INVALID_ARGUMENT; 5059315333Serj 5060315333Serj *value = status & BYPASS_CTL2_DATA_M; 5061315333Serj 5062315333Serj return IXGBE_SUCCESS; 5063315333Serj} 5064315333Serj 5065315333Serj 5066315333Serj/** 5067251964Sjfv * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5068251964Sjfv * @hw: pointer to hardware structure 5069251964Sjfv * @map: pointer to u8 arr for returning map 5070251964Sjfv * 5071251964Sjfv * Read the rtrup2tc HW register and resolve its content into map 5072251964Sjfv **/ 5073251964Sjfvvoid ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5074251964Sjfv{ 5075251964Sjfv u32 reg, i; 5076251964Sjfv 5077251964Sjfv reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5078251964Sjfv for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5079251964Sjfv map[i] = IXGBE_RTRUP2TC_UP_MASK & 5080251964Sjfv (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5081251964Sjfv return; 5082251964Sjfv} 5083283620Serj 5084283620Serjvoid ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5085283620Serj{ 5086283620Serj u32 pfdtxgswc; 5087283620Serj u32 rxctrl; 5088283620Serj 5089283620Serj rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5090283620Serj if (rxctrl & IXGBE_RXCTRL_RXEN) { 5091283620Serj if (hw->mac.type != ixgbe_mac_82598EB) { 5092283620Serj pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5093283620Serj if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5094283620Serj pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5095283620Serj IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5096283620Serj hw->mac.set_lben = TRUE; 5097283620Serj } else { 5098283620Serj hw->mac.set_lben = FALSE; 5099283620Serj } 5100283620Serj } 5101283620Serj rxctrl &= ~IXGBE_RXCTRL_RXEN; 5102283620Serj IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5103283620Serj } 5104283620Serj} 5105283620Serj 5106283620Serjvoid ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5107283620Serj{ 5108283620Serj u32 pfdtxgswc; 5109283620Serj u32 rxctrl; 5110283620Serj 5111283620Serj rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5112283620Serj IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5113283620Serj 5114283620Serj if (hw->mac.type != ixgbe_mac_82598EB) { 5115283620Serj if (hw->mac.set_lben) { 5116283620Serj pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5117283620Serj pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5118283620Serj IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5119283620Serj hw->mac.set_lben = FALSE; 5120283620Serj } 5121283620Serj } 5122283620Serj} 5123283620Serj 5124283620Serj/** 5125283620Serj * ixgbe_mng_present - returns TRUE when management capability is present 5126283620Serj * @hw: pointer to hardware structure 5127283620Serj */ 5128283620Serjbool ixgbe_mng_present(struct ixgbe_hw *hw) 5129283620Serj{ 5130283620Serj u32 fwsm; 5131283620Serj 5132283620Serj if (hw->mac.type < ixgbe_mac_82599EB) 5133283620Serj return FALSE; 5134283620Serj 5135295524Ssbruno fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5136283620Serj fwsm &= IXGBE_FWSM_MODE_MASK; 5137283620Serj return fwsm == IXGBE_FWSM_FW_MODE_PT; 5138283620Serj} 5139283620Serj 5140283620Serj/** 5141283620Serj * ixgbe_mng_enabled - Is the manageability engine enabled? 5142283620Serj * @hw: pointer to hardware structure 5143283620Serj * 5144283620Serj * Returns TRUE if the manageability engine is enabled. 5145283620Serj **/ 5146283620Serjbool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5147283620Serj{ 5148283620Serj u32 fwsm, manc, factps; 5149283620Serj 5150295524Ssbruno fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5151283620Serj if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5152283620Serj return FALSE; 5153283620Serj 5154283620Serj manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5155283620Serj if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5156283620Serj return FALSE; 5157283620Serj 5158283620Serj if (hw->mac.type <= ixgbe_mac_X540) { 5159295524Ssbruno factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5160283620Serj if (factps & IXGBE_FACTPS_MNGCG) 5161283620Serj return FALSE; 5162283620Serj } 5163283620Serj 5164283620Serj return TRUE; 5165283620Serj} 5166283620Serj 5167283620Serj/** 5168283620Serj * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5169283620Serj * @hw: pointer to hardware structure 5170283620Serj * @speed: new link speed 5171283620Serj * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5172283620Serj * 5173283620Serj * Set the link speed in the MAC and/or PHY register and restarts link. 5174283620Serj **/ 5175283620Serjs32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5176283620Serj ixgbe_link_speed speed, 5177283620Serj bool autoneg_wait_to_complete) 5178283620Serj{ 5179283620Serj ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5180283620Serj ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5181283620Serj s32 status = IXGBE_SUCCESS; 5182283620Serj u32 speedcnt = 0; 5183283620Serj u32 i = 0; 5184283620Serj bool autoneg, link_up = FALSE; 5185283620Serj 5186283620Serj DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5187283620Serj 5188283620Serj /* Mask off requested but non-supported speeds */ 5189283620Serj status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5190283620Serj if (status != IXGBE_SUCCESS) 5191283620Serj return status; 5192283620Serj 5193283620Serj speed &= link_speed; 5194283620Serj 5195283620Serj /* Try each speed one by one, highest priority first. We do this in 5196283620Serj * software because 10Gb fiber doesn't support speed autonegotiation. 5197283620Serj */ 5198283620Serj if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5199283620Serj speedcnt++; 5200283620Serj highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5201283620Serj 5202283620Serj /* Set the module link speed */ 5203283620Serj switch (hw->phy.media_type) { 5204283620Serj case ixgbe_media_type_fiber_fixed: 5205283620Serj case ixgbe_media_type_fiber: 5206283620Serj ixgbe_set_rate_select_speed(hw, 5207283620Serj IXGBE_LINK_SPEED_10GB_FULL); 5208283620Serj break; 5209283620Serj case ixgbe_media_type_fiber_qsfp: 5210283620Serj /* QSFP module automatically detects MAC link speed */ 5211283620Serj break; 5212283620Serj default: 5213283620Serj DEBUGOUT("Unexpected media type.\n"); 5214283620Serj break; 5215283620Serj } 5216283620Serj 5217283620Serj /* Allow module to change analog characteristics (1G->10G) */ 5218283620Serj msec_delay(40); 5219283620Serj 5220283620Serj status = ixgbe_setup_mac_link(hw, 5221283620Serj IXGBE_LINK_SPEED_10GB_FULL, 5222283620Serj autoneg_wait_to_complete); 5223283620Serj if (status != IXGBE_SUCCESS) 5224283620Serj return status; 5225283620Serj 5226283620Serj /* Flap the Tx laser if it has not already been done */ 5227283620Serj ixgbe_flap_tx_laser(hw); 5228283620Serj 5229283620Serj /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5230283620Serj * Section 73.10.2, we may have to wait up to 500ms if KR is 5231283620Serj * attempted. 82599 uses the same timing for 10g SFI. 5232283620Serj */ 5233283620Serj for (i = 0; i < 5; i++) { 5234283620Serj /* Wait for the link partner to also set speed */ 5235283620Serj msec_delay(100); 5236283620Serj 5237283620Serj /* If we have link, just jump out */ 5238283620Serj status = ixgbe_check_link(hw, &link_speed, 5239283620Serj &link_up, FALSE); 5240283620Serj if (status != IXGBE_SUCCESS) 5241283620Serj return status; 5242283620Serj 5243283620Serj if (link_up) 5244283620Serj goto out; 5245283620Serj } 5246283620Serj } 5247283620Serj 5248283620Serj if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5249283620Serj speedcnt++; 5250283620Serj if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5251283620Serj highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5252283620Serj 5253283620Serj /* Set the module link speed */ 5254283620Serj switch (hw->phy.media_type) { 5255283620Serj case ixgbe_media_type_fiber_fixed: 5256283620Serj case ixgbe_media_type_fiber: 5257283620Serj ixgbe_set_rate_select_speed(hw, 5258283620Serj IXGBE_LINK_SPEED_1GB_FULL); 5259283620Serj break; 5260283620Serj case ixgbe_media_type_fiber_qsfp: 5261283620Serj /* QSFP module automatically detects link speed */ 5262283620Serj break; 5263283620Serj default: 5264283620Serj DEBUGOUT("Unexpected media type.\n"); 5265283620Serj break; 5266283620Serj } 5267283620Serj 5268283620Serj /* Allow module to change analog characteristics (10G->1G) */ 5269283620Serj msec_delay(40); 5270283620Serj 5271283620Serj status = ixgbe_setup_mac_link(hw, 5272283620Serj IXGBE_LINK_SPEED_1GB_FULL, 5273283620Serj autoneg_wait_to_complete); 5274283620Serj if (status != IXGBE_SUCCESS) 5275283620Serj return status; 5276283620Serj 5277283620Serj /* Flap the Tx laser if it has not already been done */ 5278283620Serj ixgbe_flap_tx_laser(hw); 5279283620Serj 5280283620Serj /* Wait for the link partner to also set speed */ 5281283620Serj msec_delay(100); 5282283620Serj 5283283620Serj /* If we have link, just jump out */ 5284283620Serj status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5285283620Serj if (status != IXGBE_SUCCESS) 5286283620Serj return status; 5287283620Serj 5288283620Serj if (link_up) 5289283620Serj goto out; 5290283620Serj } 5291283620Serj 5292283620Serj /* We didn't get link. Configure back to the highest speed we tried, 5293283620Serj * (if there was more than one). We call ourselves back with just the 5294283620Serj * single highest speed that the user requested. 5295283620Serj */ 5296283620Serj if (speedcnt > 1) 5297283620Serj status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5298283620Serj highest_link_speed, 5299283620Serj autoneg_wait_to_complete); 5300283620Serj 5301283620Serjout: 5302283620Serj /* Set autoneg_advertised value based on input link speed */ 5303283620Serj hw->phy.autoneg_advertised = 0; 5304283620Serj 5305283620Serj if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5306283620Serj hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5307283620Serj 5308283620Serj if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5309283620Serj hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5310283620Serj 5311283620Serj return status; 5312283620Serj} 5313283620Serj 5314283620Serj/** 5315283620Serj * ixgbe_set_soft_rate_select_speed - Set module link speed 5316283620Serj * @hw: pointer to hardware structure 5317283620Serj * @speed: link speed to set 5318283620Serj * 5319283620Serj * Set module link speed via the soft rate select. 5320283620Serj */ 5321283620Serjvoid ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5322283620Serj ixgbe_link_speed speed) 5323283620Serj{ 5324283620Serj s32 status; 5325283620Serj u8 rs, eeprom_data; 5326283620Serj 5327283620Serj switch (speed) { 5328283620Serj case IXGBE_LINK_SPEED_10GB_FULL: 5329283620Serj /* one bit mask same as setting on */ 5330283620Serj rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5331283620Serj break; 5332283620Serj case IXGBE_LINK_SPEED_1GB_FULL: 5333283620Serj rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5334283620Serj break; 5335283620Serj default: 5336283620Serj DEBUGOUT("Invalid fixed module speed\n"); 5337283620Serj return; 5338283620Serj } 5339283620Serj 5340283620Serj /* Set RS0 */ 5341283620Serj status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5342283620Serj IXGBE_I2C_EEPROM_DEV_ADDR2, 5343283620Serj &eeprom_data); 5344283620Serj if (status) { 5345283620Serj DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5346283620Serj goto out; 5347283620Serj } 5348283620Serj 5349283620Serj eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5350283620Serj 5351283620Serj status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5352283620Serj IXGBE_I2C_EEPROM_DEV_ADDR2, 5353283620Serj eeprom_data); 5354283620Serj if (status) { 5355283620Serj DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5356283620Serj goto out; 5357283620Serj } 5358283620Serj 5359283620Serj /* Set RS1 */ 5360283620Serj status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5361283620Serj IXGBE_I2C_EEPROM_DEV_ADDR2, 5362283620Serj &eeprom_data); 5363283620Serj if (status) { 5364283620Serj DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5365283620Serj goto out; 5366283620Serj } 5367283620Serj 5368283620Serj eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5369283620Serj 5370283620Serj status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5371283620Serj IXGBE_I2C_EEPROM_DEV_ADDR2, 5372283620Serj eeprom_data); 5373283620Serj if (status) { 5374283620Serj DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5375283620Serj goto out; 5376283620Serj } 5377283620Serjout: 5378283620Serj return; 5379283620Serj} 5380