ixgbe.h revision 286810
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe.h 286810 2015-08-15 17:52:55Z melifaro $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#ifndef IXGBE_LEGACY_TX 43#include <sys/buf_ring.h> 44#endif 45#include <sys/mbuf.h> 46#include <sys/protosw.h> 47#include <sys/socket.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/sockio.h> 52 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59 60#include <net/bpf.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in_systm.h> 65#include <netinet/in.h> 66#include <netinet/if_ether.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/tcp_lro.h> 71#include <netinet/udp.h> 72 73#include <machine/in_cksum.h> 74 75#include <sys/bus.h> 76#include <machine/bus.h> 77#include <sys/rman.h> 78#include <machine/resource.h> 79#include <vm/vm.h> 80#include <vm/pmap.h> 81#include <machine/clock.h> 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <sys/proc.h> 85#include <sys/sysctl.h> 86#include <sys/endian.h> 87#include <sys/taskqueue.h> 88#include <sys/pcpu.h> 89#include <sys/smp.h> 90#include <machine/smp.h> 91#include <sys/sbuf.h> 92 93#include "ixgbe_api.h" 94#include "ixgbe_common.h" 95#include "ixgbe_phy.h" 96#include "ixgbe_vf.h" 97 98/* Tunables */ 99 100/* 101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102 * number of transmit descriptors allocated by the driver. Increasing this 103 * value allows the driver to queue more transmits. Each descriptor is 16 104 * bytes. Performance tests have show the 2K value to be optimal for top 105 * performance. 106 */ 107#define DEFAULT_TXD 1024 108#define PERFORM_TXD 2048 109#define MAX_TXD 4096 110#define MIN_TXD 64 111 112/* 113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114 * number of receive descriptors allocated for each RX queue. Increasing this 115 * value allows the driver to buffer more incoming packets. Each descriptor 116 * is 16 bytes. A receive buffer is also allocated for each descriptor. 117 * 118 * Note: with 8 rings and a dual port card, it is possible to bump up 119 * against the system mbuf pool limit, you can tune nmbclusters 120 * to adjust for this. 121 */ 122#define DEFAULT_RXD 1024 123#define PERFORM_RXD 2048 124#define MAX_RXD 4096 125#define MIN_RXD 64 126 127/* Alignment for rings */ 128#define DBA_ALIGN 128 129 130/* 131 * This parameter controls the maximum no of times the driver will loop in 132 * the isr. Minimum Value = 1 133 */ 134#define MAX_LOOP 10 135 136/* 137 * This is the max watchdog interval, ie. the time that can 138 * pass between any two TX clean operations, such only happening 139 * when the TX hardware is functioning. 140 */ 141#define IXGBE_WATCHDOG (10 * hz) 142 143/* 144 * This parameters control when the driver calls the routine to reclaim 145 * transmit descriptors. 146 */ 147#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 148#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 149 150/* These defines are used in MTU calculations */ 151#define IXGBE_MAX_FRAME_SIZE 9728 152#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 153 ETHER_VLAN_ENCAP_LEN) 154#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 155 156/* Flow control constants */ 157#define IXGBE_FC_PAUSE 0xFFFF 158#define IXGBE_FC_HI 0x20000 159#define IXGBE_FC_LO 0x10000 160 161/* 162 * Used for optimizing small rx mbufs. Effort is made to keep the copy 163 * small and aligned for the CPU L1 cache. 164 * 165 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 166 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 167 * wasted. Getting 64 byte alignment, which _should_ be ideal for 168 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 169 * in observed efficiency of the optimization, 97.9% -> 81.8%. 170 */ 171#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 172#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 173#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 174 175/* Keep older OS drivers building... */ 176#if !defined(SYSCTL_ADD_UQUAD) 177#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 178#endif 179 180/* Defines for printing debug information */ 181#define DEBUG_INIT 0 182#define DEBUG_IOCTL 0 183#define DEBUG_HW 0 184 185#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 186#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 187#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 188#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 189#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 190#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 191#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 192#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 193#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 194 195#define MAX_NUM_MULTICAST_ADDRESSES 128 196#define IXGBE_82598_SCATTER 100 197#define IXGBE_82599_SCATTER 32 198#define MSIX_82598_BAR 3 199#define MSIX_82599_BAR 4 200#define IXGBE_TSO_SIZE 262140 201#define IXGBE_TX_BUFFER_SIZE ((u32) 1514) 202#define IXGBE_RX_HDR 128 203#define IXGBE_VFTA_SIZE 128 204#define IXGBE_BR_SIZE 4096 205#define IXGBE_QUEUE_MIN_FREE 32 206#define IXGBE_MAX_TX_BUSY 10 207#define IXGBE_QUEUE_HUNG 0x80000000 208 209#define IXV_EITR_DEFAULT 128 210 211/* Offload bits in mbuf flag */ 212#if __FreeBSD_version >= 800000 213#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 214#else 215#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 216#endif 217 218/* Backward compatibility items for very old versions */ 219#ifndef pci_find_cap 220#define pci_find_cap pci_find_extcap 221#endif 222 223#ifndef DEVMETHOD_END 224#define DEVMETHOD_END { NULL, NULL } 225#endif 226 227/* 228 * Interrupt Moderation parameters 229 */ 230#define IXGBE_LOW_LATENCY 128 231#define IXGBE_AVE_LATENCY 400 232#define IXGBE_BULK_LATENCY 1200 233#define IXGBE_LINK_ITR 2000 234 235/* MAC type macros */ 236#define IXGBE_IS_X550VF(_adapter) \ 237 ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ 238 (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf)) 239 240#define IXGBE_IS_VF(_adapter) \ 241 (IXGBE_IS_X550VF(_adapter) || \ 242 (_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \ 243 (_adapter->hw.mac.type == ixgbe_mac_82599_vf)) 244 245 246/* 247 ***************************************************************************** 248 * vendor_info_array 249 * 250 * This array contains the list of Subvendor/Subdevice IDs on which the driver 251 * should load. 252 * 253 ***************************************************************************** 254 */ 255typedef struct _ixgbe_vendor_info_t { 256 unsigned int vendor_id; 257 unsigned int device_id; 258 unsigned int subvendor_id; 259 unsigned int subdevice_id; 260 unsigned int index; 261} ixgbe_vendor_info_t; 262 263struct ixgbe_tx_buf { 264 union ixgbe_adv_tx_desc *eop; 265 struct mbuf *m_head; 266 bus_dmamap_t map; 267}; 268 269struct ixgbe_rx_buf { 270 struct mbuf *buf; 271 struct mbuf *fmp; 272 bus_dmamap_t pmap; 273 u_int flags; 274#define IXGBE_RX_COPY 0x01 275 uint64_t addr; 276}; 277 278/* 279 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 280 */ 281struct ixgbe_dma_alloc { 282 bus_addr_t dma_paddr; 283 caddr_t dma_vaddr; 284 bus_dma_tag_t dma_tag; 285 bus_dmamap_t dma_map; 286 bus_dma_segment_t dma_seg; 287 bus_size_t dma_size; 288 int dma_nseg; 289}; 290 291/* 292** Driver queue struct: this is the interrupt container 293** for the associated tx and rx ring. 294*/ 295struct ix_queue { 296 struct adapter *adapter; 297 u32 msix; /* This queue's MSIX vector */ 298 u32 eims; /* This queue's EIMS bit */ 299 u32 eitr_setting; 300 u32 me; 301 struct resource *res; 302 void *tag; 303 int busy; 304 struct tx_ring *txr; 305 struct rx_ring *rxr; 306 struct task que_task; 307 struct taskqueue *tq; 308 u64 irqs; 309}; 310 311/* 312 * The transmit ring, one per queue 313 */ 314struct tx_ring { 315 struct adapter *adapter; 316 struct mtx tx_mtx; 317 u32 me; 318 u32 tail; 319 int busy; 320 union ixgbe_adv_tx_desc *tx_base; 321 struct ixgbe_tx_buf *tx_buffers; 322 struct ixgbe_dma_alloc txdma; 323 volatile u16 tx_avail; 324 u16 next_avail_desc; 325 u16 next_to_clean; 326 u16 process_limit; 327 u16 num_desc; 328 u32 txd_cmd; 329 bus_dma_tag_t txtag; 330 char mtx_name[16]; 331#ifndef IXGBE_LEGACY_TX 332 struct buf_ring *br; 333 struct task txq_task; 334#endif 335#ifdef IXGBE_FDIR 336 u16 atr_sample; 337 u16 atr_count; 338#endif 339 u32 bytes; /* used for AIM */ 340 u32 packets; 341 /* Soft Stats */ 342 unsigned long tso_tx; 343 unsigned long no_tx_map_avail; 344 unsigned long no_tx_dma_setup; 345 u64 no_desc_avail; 346 u64 total_packets; 347}; 348 349 350/* 351 * The Receive ring, one per rx queue 352 */ 353struct rx_ring { 354 struct adapter *adapter; 355 struct mtx rx_mtx; 356 u32 me; 357 u32 tail; 358 union ixgbe_adv_rx_desc *rx_base; 359 struct ixgbe_dma_alloc rxdma; 360 struct lro_ctrl lro; 361 bool lro_enabled; 362 bool hw_rsc; 363 bool vtag_strip; 364 u16 next_to_refresh; 365 u16 next_to_check; 366 u16 num_desc; 367 u16 mbuf_sz; 368 u16 process_limit; 369 char mtx_name[16]; 370 struct ixgbe_rx_buf *rx_buffers; 371 bus_dma_tag_t ptag; 372 373 u32 bytes; /* Used for AIM calc */ 374 u32 packets; 375 376 /* Soft stats */ 377 u64 rx_irq; 378 u64 rx_copies; 379 u64 rx_packets; 380 u64 rx_bytes; 381 u64 rx_discarded; 382 u64 rsc_num; 383#ifdef IXGBE_FDIR 384 u64 flm; 385#endif 386}; 387 388/* Our adapter structure */ 389struct adapter { 390 struct ifnet *ifp; 391 struct ixgbe_hw hw; 392 393 struct ixgbe_osdep osdep; 394 struct device *dev; 395 396 struct resource *pci_mem; 397 struct resource *msix_mem; 398 399 /* 400 * Interrupt resources: this set is 401 * either used for legacy, or for Link 402 * when doing MSIX 403 */ 404 void *tag; 405 struct resource *res; 406 407 struct ifmedia media; 408 struct callout timer; 409 int msix; 410 int if_flags; 411 412 struct mtx core_mtx; 413 414 eventhandler_tag vlan_attach; 415 eventhandler_tag vlan_detach; 416 417 u16 num_vlans; 418 u16 num_queues; 419 420 /* 421 ** Shadow VFTA table, this is needed because 422 ** the real vlan filter table gets cleared during 423 ** a soft reset and the driver needs to be able 424 ** to repopulate it. 425 */ 426 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 427 428 /* Info about the interface */ 429 u32 optics; 430 u32 fc; /* local flow ctrl setting */ 431 int advertise; /* link speeds */ 432 bool link_active; 433 u16 max_frame_size; 434 u16 num_segs; 435 u32 link_speed; 436 bool link_up; 437 u32 vector; 438 u16 dmac; 439 bool eee_support; 440 bool eee_enabled; 441 442 /* Power management-related */ 443 bool wol_support; 444 u32 wufc; 445 446 /* Mbuf cluster size */ 447 u32 rx_mbuf_sz; 448 449 /* Support for pluggable optics */ 450 bool sfp_probe; 451 struct task link_task; /* Link tasklet */ 452 struct task mod_task; /* SFP tasklet */ 453 struct task msf_task; /* Multispeed Fiber */ 454#ifdef IXGBE_FDIR 455 int fdir_reinit; 456 struct task fdir_task; 457#endif 458 struct task phy_task; /* PHY intr tasklet */ 459 struct taskqueue *tq; 460 461 /* 462 ** Queues: 463 ** This is the irq holder, it has 464 ** and RX/TX pair or rings associated 465 ** with it. 466 */ 467 struct ix_queue *queues; 468 469 /* 470 * Transmit rings: 471 * Allocated at run time, an array of rings. 472 */ 473 struct tx_ring *tx_rings; 474 u32 num_tx_desc; 475 476 /* 477 * Receive rings: 478 * Allocated at run time, an array of rings. 479 */ 480 struct rx_ring *rx_rings; 481 u64 active_queues; 482 u32 num_rx_desc; 483 484 /* Multicast array memory */ 485 u8 *mta; 486 487 488 /* Misc stats maintained by the driver */ 489 unsigned long dropped_pkts; 490 unsigned long mbuf_defrag_failed; 491 unsigned long mbuf_header_failed; 492 unsigned long mbuf_packet_failed; 493 unsigned long watchdog_events; 494 unsigned long link_irq; 495 union { 496 struct ixgbe_hw_stats pf; 497 struct ixgbevf_hw_stats vf; 498 } stats; 499#if __FreeBSD_version >= 1100036 500 /* counter(9) stats */ 501 u64 ipackets; 502 u64 ierrors; 503 u64 opackets; 504 u64 oerrors; 505 u64 ibytes; 506 u64 obytes; 507 u64 imcasts; 508 u64 omcasts; 509 u64 iqdrops; 510 u64 noproto; 511#endif 512}; 513 514 515/* Precision Time Sync (IEEE 1588) defines */ 516#define ETHERTYPE_IEEE1588 0x88F7 517#define PICOSECS_PER_TICK 20833 518#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 519#define IXGBE_ADVTXD_TSTAMP 0x00080000 520 521 522#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 523 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 524#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 525#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 526#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 527#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 528#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 529#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 530#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 531#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 532#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 533#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 534#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 535#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 536 537/* For backward compatibility */ 538#if !defined(PCIER_LINK_STA) 539#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 540#endif 541 542/* Stats macros */ 543#if __FreeBSD_version >= 1100036 544#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 545#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 546#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 547#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 548#define IXGBE_SET_COLLISIONS(sc, count) 549#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 550#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 551#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 552#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 553#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 554#else 555#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 556#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 557#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 558#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 559#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 560#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 561#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 562#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 563#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 564#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 565#endif 566 567/* External PHY register addresses */ 568#define IXGBE_PHY_CURRENT_TEMP 0xC820 569#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 570 571/* Sysctl help messages; displayed with sysctl -d */ 572#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 573 "\nControl advertised link speed using these flags:\n" \ 574 "\t0x1 - advertise 100M\n" \ 575 "\t0x2 - advertise 1G\n" \ 576 "\t0x4 - advertise 10G\n\n" \ 577 "\t100M is only supported on certain 10GBaseT adapters.\n" 578 579#define IXGBE_SYSCTL_DESC_SET_FC \ 580 "\nSet flow control mode using these values:\n" \ 581 "\t0 - off\n" \ 582 "\t1 - rx pause\n" \ 583 "\t2 - tx pause\n" \ 584 "\t3 - tx and rx pause" 585 586static inline bool 587ixgbe_is_sfp(struct ixgbe_hw *hw) 588{ 589 switch (hw->phy.type) { 590 case ixgbe_phy_sfp_avago: 591 case ixgbe_phy_sfp_ftl: 592 case ixgbe_phy_sfp_intel: 593 case ixgbe_phy_sfp_unknown: 594 case ixgbe_phy_sfp_passive_tyco: 595 case ixgbe_phy_sfp_passive_unknown: 596 case ixgbe_phy_qsfp_passive_unknown: 597 case ixgbe_phy_qsfp_active_unknown: 598 case ixgbe_phy_qsfp_intel: 599 case ixgbe_phy_qsfp_unknown: 600 return TRUE; 601 default: 602 return FALSE; 603 } 604} 605 606/* Workaround to make 8.0 buildable */ 607#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 608static __inline int 609drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 610{ 611#ifdef ALTQ 612 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 613 return (1); 614#endif 615 return (!buf_ring_empty(br)); 616} 617#endif 618 619/* 620** Find the number of unrefreshed RX descriptors 621*/ 622static inline u16 623ixgbe_rx_unrefreshed(struct rx_ring *rxr) 624{ 625 if (rxr->next_to_check > rxr->next_to_refresh) 626 return (rxr->next_to_check - rxr->next_to_refresh - 1); 627 else 628 return ((rxr->num_desc + rxr->next_to_check) - 629 rxr->next_to_refresh - 1); 630} 631 632/* 633** This checks for a zero mac addr, something that will be likely 634** unless the Admin on the Host has created one. 635*/ 636static inline bool 637ixv_check_ether_addr(u8 *addr) 638{ 639 bool status = TRUE; 640 641 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 642 addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 643 status = FALSE; 644 return (status); 645} 646 647/* Shared Prototypes */ 648 649#ifdef IXGBE_LEGACY_TX 650void ixgbe_start(struct ifnet *); 651void ixgbe_start_locked(struct tx_ring *, struct ifnet *); 652#else /* ! IXGBE_LEGACY_TX */ 653int ixgbe_mq_start(struct ifnet *, struct mbuf *); 654int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 655void ixgbe_qflush(struct ifnet *); 656void ixgbe_deferred_mq_start(void *, int); 657#endif /* IXGBE_LEGACY_TX */ 658 659int ixgbe_allocate_queues(struct adapter *); 660int ixgbe_allocate_transmit_buffers(struct tx_ring *); 661int ixgbe_setup_transmit_structures(struct adapter *); 662void ixgbe_free_transmit_structures(struct adapter *); 663int ixgbe_allocate_receive_buffers(struct rx_ring *); 664int ixgbe_setup_receive_structures(struct adapter *); 665void ixgbe_free_receive_structures(struct adapter *); 666void ixgbe_txeof(struct tx_ring *); 667bool ixgbe_rxeof(struct ix_queue *); 668 669int ixgbe_dma_malloc(struct adapter *, 670 bus_size_t, struct ixgbe_dma_alloc *, int); 671void ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *); 672#endif /* _IXGBE_H_ */ 673