isp_pci.c revision 290782
1/*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26/* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/dev/isp/isp_pci.c 290782 2015-11-13 19:36:43Z mav $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/linker.h> 38#include <sys/firmware.h> 39#include <sys/bus.h> 40#include <sys/stdint.h> 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46#include <sys/malloc.h> 47#include <sys/uio.h> 48 49#ifdef __sparc64__ 50#include <dev/ofw/openfirm.h> 51#include <machine/ofw_machdep.h> 52#endif 53 54#include <dev/isp/isp_freebsd.h> 55 56static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65static int isp_pci_mbxdma(ispsoftc_t *); 66static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69static void isp_pci_reset0(ispsoftc_t *); 70static void isp_pci_reset1(ispsoftc_t *); 71static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85}; 86 87static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99}; 100 101static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113}; 114 115static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125}; 126 127static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137}; 138 139static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149}; 150 151static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161}; 162 163static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173}; 174 175#ifndef PCIM_CMD_INVEN 176#define PCIM_CMD_INVEN 0x10 177#endif 178#ifndef PCIM_CMD_BUSMASTEREN 179#define PCIM_CMD_BUSMASTEREN 0x0004 180#endif 181#ifndef PCIM_CMD_PERRESPEN 182#define PCIM_CMD_PERRESPEN 0x0040 183#endif 184#ifndef PCIM_CMD_SEREN 185#define PCIM_CMD_SEREN 0x0100 186#endif 187#ifndef PCIM_CMD_INTX_DISABLE 188#define PCIM_CMD_INTX_DISABLE 0x0400 189#endif 190 191#ifndef PCIR_COMMAND 192#define PCIR_COMMAND 0x04 193#endif 194 195#ifndef PCIR_CACHELNSZ 196#define PCIR_CACHELNSZ 0x0c 197#endif 198 199#ifndef PCIR_LATTIMER 200#define PCIR_LATTIMER 0x0d 201#endif 202 203#ifndef PCIR_ROMADDR 204#define PCIR_ROMADDR 0x30 205#endif 206 207#ifndef PCI_VENDOR_QLOGIC 208#define PCI_VENDOR_QLOGIC 0x1077 209#endif 210 211#ifndef PCI_PRODUCT_QLOGIC_ISP1020 212#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213#endif 214 215#ifndef PCI_PRODUCT_QLOGIC_ISP1080 216#define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217#endif 218 219#ifndef PCI_PRODUCT_QLOGIC_ISP10160 220#define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221#endif 222 223#ifndef PCI_PRODUCT_QLOGIC_ISP12160 224#define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225#endif 226 227#ifndef PCI_PRODUCT_QLOGIC_ISP1240 228#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229#endif 230 231#ifndef PCI_PRODUCT_QLOGIC_ISP1280 232#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233#endif 234 235#ifndef PCI_PRODUCT_QLOGIC_ISP2100 236#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237#endif 238 239#ifndef PCI_PRODUCT_QLOGIC_ISP2200 240#define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241#endif 242 243#ifndef PCI_PRODUCT_QLOGIC_ISP2300 244#define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245#endif 246 247#ifndef PCI_PRODUCT_QLOGIC_ISP2312 248#define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249#endif 250 251#ifndef PCI_PRODUCT_QLOGIC_ISP2322 252#define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253#endif 254 255#ifndef PCI_PRODUCT_QLOGIC_ISP2422 256#define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257#endif 258 259#ifndef PCI_PRODUCT_QLOGIC_ISP2432 260#define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261#endif 262 263#ifndef PCI_PRODUCT_QLOGIC_ISP2532 264#define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265#endif 266 267#ifndef PCI_PRODUCT_QLOGIC_ISP6312 268#define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269#endif 270 271#ifndef PCI_PRODUCT_QLOGIC_ISP6322 272#define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273#endif 274 275#ifndef PCI_PRODUCT_QLOGIC_ISP5432 276#define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277#endif 278 279#define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282#define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285#define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288#define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291#define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294#define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297#define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300#define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303#define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306#define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309#define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312#define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315#define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318#define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321#define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324#define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327#define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330/* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333#define AMI_RAID_SUBVENDOR_ID 0x101e 334 335#define IO_MAP_REG 0x10 336#define MEM_MAP_REG 0x14 337 338#define PCI_DFLT_LTNCY 0x40 339#define PCI_DFLT_LNSZ 0x10 340 341static int isp_pci_probe (device_t); 342static int isp_pci_attach (device_t); 343static int isp_pci_detach (device_t); 344 345 346#define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359}; 360 361 362static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368}; 369 370static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372}; 373static devclass_t isp_devclass; 374DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375MODULE_DEPEND(isp, cam, 1, 1, 1); 376MODULE_DEPEND(isp, firmware, 1, 1, 1); 377static int isp_nvports = 0; 378 379static int 380isp_pci_probe(device_t dev) 381{ 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452} 453 454static void 455isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456{ 457 int tval; 458 459 /* 460 * Figure out if we're supposed to skip this one. 461 */ 462 tval = 0; 463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 464 device_printf(dev, "disabled at user request\n"); 465 isp->isp_osinfo.disabled = 1; 466 return; 467 } 468 469 tval = 0; 470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 471 isp->isp_confopts |= ISP_CFG_NORELOAD; 472 } 473 tval = 0; 474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 475 isp->isp_confopts |= ISP_CFG_NONVRAM; 476 } 477 tval = 0; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 479 if (tval) { 480 isp->isp_dblev = tval; 481 } else { 482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 483 } 484 if (bootverbose) { 485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 486 } 487 tval = -1; 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 489 if (tval > 0 && tval < 127) { 490 isp_nvports = tval; 491 } 492 tval = 1; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 494 isp_autoconfig = tval; 495 tval = 7; 496 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 497 isp_quickboot_time = tval; 498} 499 500static void 501isp_get_pci_options(device_t dev, int *m1, int *m2) 502{ 503 int tval; 504 /* 505 * Which we should try first - memory mapping or i/o mapping? 506 * 507 * We used to try memory first followed by i/o on alpha, otherwise 508 * the reverse, but we should just try memory first all the time now. 509 */ 510 *m1 = PCIM_CMD_MEMEN; 511 *m2 = PCIM_CMD_PORTEN; 512 513 tval = 0; 514 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 515 *m1 = PCIM_CMD_PORTEN; 516 *m2 = PCIM_CMD_MEMEN; 517 } 518 tval = 0; 519 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 520 *m1 = PCIM_CMD_MEMEN; 521 *m2 = PCIM_CMD_PORTEN; 522 } 523} 524 525static void 526isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 527{ 528 const char *sptr; 529 int tval = 0; 530 char prefix[12], name[16]; 531 532 if (chan == 0) 533 prefix[0] = 0; 534 else 535 snprintf(prefix, sizeof(prefix), "chan%d.", chan); 536 snprintf(name, sizeof(name), "%siid", prefix); 537 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 538 name, &tval)) { 539 if (IS_FC(isp)) { 540 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 541 } else { 542#ifdef __sparc64__ 543 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 544#else 545 ISP_SPI_PC(isp, chan)->iid = 7; 546#endif 547 } 548 } else { 549 if (IS_FC(isp)) { 550 ISP_FC_PC(isp, chan)->default_id = tval - chan; 551 } else { 552 ISP_SPI_PC(isp, chan)->iid = tval; 553 } 554 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 555 } 556 557 tval = -1; 558 snprintf(name, sizeof(name), "%srole", prefix); 559 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 560 name, &tval) == 0) { 561 switch (tval) { 562 case ISP_ROLE_NONE: 563 case ISP_ROLE_INITIATOR: 564 case ISP_ROLE_TARGET: 565 case ISP_ROLE_BOTH: 566 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval); 567 break; 568 default: 569 tval = -1; 570 break; 571 } 572 } 573 if (tval == -1) { 574 tval = ISP_DEFAULT_ROLES; 575 } 576 577 if (IS_SCSI(isp)) { 578 ISP_SPI_PC(isp, chan)->def_role = tval; 579 return; 580 } 581 ISP_FC_PC(isp, chan)->def_role = tval; 582 583 tval = 0; 584 snprintf(name, sizeof(name), "%sfullduplex", prefix); 585 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 586 name, &tval) == 0 && tval != 0) { 587 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 588 } 589 sptr = 0; 590 snprintf(name, sizeof(name), "%stopology", prefix); 591 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 592 name, (const char **) &sptr) == 0 && sptr != 0) { 593 if (strcmp(sptr, "lport") == 0) { 594 isp->isp_confopts |= ISP_CFG_LPORT; 595 } else if (strcmp(sptr, "nport") == 0) { 596 isp->isp_confopts |= ISP_CFG_NPORT; 597 } else if (strcmp(sptr, "lport-only") == 0) { 598 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 599 } else if (strcmp(sptr, "nport-only") == 0) { 600 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 601 } 602 } 603 604 tval = 0; 605 snprintf(name, sizeof(name), "%snofctape", prefix); 606 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 607 name, &tval); 608 if (tval) { 609 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 610 } 611 612 tval = 0; 613 snprintf(name, sizeof(name), "%sfctape", prefix); 614 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 615 name, &tval); 616 if (tval) { 617 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 618 isp->isp_confopts |= ISP_CFG_FCTAPE; 619 } 620 621 622 /* 623 * Because the resource_*_value functions can neither return 624 * 64 bit integer values, nor can they be directly coerced 625 * to interpret the right hand side of the assignment as 626 * you want them to interpret it, we have to force WWN 627 * hint replacement to specify WWN strings with a leading 628 * 'w' (e..g w50000000aaaa0001). Sigh. 629 */ 630 sptr = 0; 631 snprintf(name, sizeof(name), "%sportwwn", prefix); 632 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 633 name, (const char **) &sptr); 634 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 635 char *eptr = 0; 636 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 637 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 638 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 639 ISP_FC_PC(isp, chan)->def_wwpn = 0; 640 } 641 } 642 643 sptr = 0; 644 snprintf(name, sizeof(name), "%snodewwn", prefix); 645 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 646 name, (const char **) &sptr); 647 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 648 char *eptr = 0; 649 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 650 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 651 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 652 ISP_FC_PC(isp, chan)->def_wwnn = 0; 653 } 654 } 655 656 tval = 0; 657 snprintf(name, sizeof(name), "%shysteresis", prefix); 658 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 659 "name", &tval); 660 if (tval >= 0 && tval < 256) { 661 ISP_FC_PC(isp, chan)->hysteresis = tval; 662 } else { 663 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 664 } 665 666 tval = -1; 667 snprintf(name, sizeof(name), "%sloop_down_limit", prefix); 668 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 669 name, &tval); 670 if (tval >= 0 && tval < 0xffff) { 671 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 672 } else { 673 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 674 } 675 676 tval = -1; 677 snprintf(name, sizeof(name), "%sgone_device_time", prefix); 678 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 679 name, &tval); 680 if (tval >= 0 && tval < 0xffff) { 681 ISP_FC_PC(isp, chan)->gone_device_time = tval; 682 } else { 683 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 684 } 685} 686 687static int 688isp_pci_attach(device_t dev) 689{ 690 int i, m1, m2, locksetup = 0; 691 uint32_t data, cmd, linesz, did; 692 struct isp_pcisoftc *pcs; 693 ispsoftc_t *isp; 694 size_t psize, xsize; 695 char fwname[32]; 696 697 pcs = device_get_softc(dev); 698 if (pcs == NULL) { 699 device_printf(dev, "cannot get softc\n"); 700 return (ENOMEM); 701 } 702 memset(pcs, 0, sizeof (*pcs)); 703 704 pcs->pci_dev = dev; 705 isp = &pcs->pci_isp; 706 isp->isp_dev = dev; 707 isp->isp_nchan = 1; 708 if (sizeof (bus_addr_t) > 4) 709 isp->isp_osinfo.sixtyfourbit = 1; 710 711 /* 712 * Get Generic Options 713 */ 714 isp_nvports = 0; 715 isp_get_generic_options(dev, isp); 716 717 /* 718 * Check to see if options have us disabled 719 */ 720 if (isp->isp_osinfo.disabled) { 721 /* 722 * But return zero to preserve unit numbering 723 */ 724 return (0); 725 } 726 727 /* 728 * Get PCI options- which in this case are just mapping preferences. 729 */ 730 isp_get_pci_options(dev, &m1, &m2); 731 732 linesz = PCI_DFLT_LNSZ; 733 pcs->irq = pcs->regs = NULL; 734 pcs->rgd = pcs->rtp = pcs->iqd = 0; 735 736 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 737 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 738 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 739 if (pcs->regs == NULL) { 740 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 741 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 742 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 743 } 744 if (pcs->regs == NULL) { 745 device_printf(dev, "unable to map any ports\n"); 746 goto bad; 747 } 748 if (bootverbose) { 749 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 750 } 751 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 752 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 753 754 pcs->pci_dev = dev; 755 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 756 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 757 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 758 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 759 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 760 761 switch (pci_get_devid(dev)) { 762 case PCI_QLOGIC_ISP1020: 763 did = 0x1040; 764 isp->isp_mdvec = &mdvec; 765 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 766 break; 767 case PCI_QLOGIC_ISP1080: 768 did = 0x1080; 769 isp->isp_mdvec = &mdvec_1080; 770 isp->isp_type = ISP_HA_SCSI_1080; 771 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 772 break; 773 case PCI_QLOGIC_ISP1240: 774 did = 0x1080; 775 isp->isp_mdvec = &mdvec_1080; 776 isp->isp_type = ISP_HA_SCSI_1240; 777 isp->isp_nchan = 2; 778 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 779 break; 780 case PCI_QLOGIC_ISP1280: 781 did = 0x1080; 782 isp->isp_mdvec = &mdvec_1080; 783 isp->isp_type = ISP_HA_SCSI_1280; 784 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 785 break; 786 case PCI_QLOGIC_ISP10160: 787 did = 0x12160; 788 isp->isp_mdvec = &mdvec_12160; 789 isp->isp_type = ISP_HA_SCSI_10160; 790 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 791 break; 792 case PCI_QLOGIC_ISP12160: 793 did = 0x12160; 794 isp->isp_nchan = 2; 795 isp->isp_mdvec = &mdvec_12160; 796 isp->isp_type = ISP_HA_SCSI_12160; 797 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 798 break; 799 case PCI_QLOGIC_ISP2100: 800 did = 0x2100; 801 isp->isp_mdvec = &mdvec_2100; 802 isp->isp_type = ISP_HA_FC_2100; 803 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 804 if (pci_get_revid(dev) < 3) { 805 /* 806 * XXX: Need to get the actual revision 807 * XXX: number of the 2100 FB. At any rate, 808 * XXX: lower cache line size for early revision 809 * XXX; boards. 810 */ 811 linesz = 1; 812 } 813 break; 814 case PCI_QLOGIC_ISP2200: 815 did = 0x2200; 816 isp->isp_mdvec = &mdvec_2200; 817 isp->isp_type = ISP_HA_FC_2200; 818 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 819 break; 820 case PCI_QLOGIC_ISP2300: 821 did = 0x2300; 822 isp->isp_mdvec = &mdvec_2300; 823 isp->isp_type = ISP_HA_FC_2300; 824 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 825 break; 826 case PCI_QLOGIC_ISP2312: 827 case PCI_QLOGIC_ISP6312: 828 did = 0x2300; 829 isp->isp_mdvec = &mdvec_2300; 830 isp->isp_type = ISP_HA_FC_2312; 831 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 832 break; 833 case PCI_QLOGIC_ISP2322: 834 case PCI_QLOGIC_ISP6322: 835 did = 0x2322; 836 isp->isp_mdvec = &mdvec_2300; 837 isp->isp_type = ISP_HA_FC_2322; 838 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 839 break; 840 case PCI_QLOGIC_ISP2422: 841 case PCI_QLOGIC_ISP2432: 842 did = 0x2400; 843 isp->isp_nchan += isp_nvports; 844 isp->isp_mdvec = &mdvec_2400; 845 isp->isp_type = ISP_HA_FC_2400; 846 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 847 break; 848 case PCI_QLOGIC_ISP2532: 849 did = 0x2500; 850 isp->isp_nchan += isp_nvports; 851 isp->isp_mdvec = &mdvec_2500; 852 isp->isp_type = ISP_HA_FC_2500; 853 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 854 break; 855 case PCI_QLOGIC_ISP5432: 856 did = 0x2500; 857 isp->isp_mdvec = &mdvec_2500; 858 isp->isp_type = ISP_HA_FC_2500; 859 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 860 break; 861 default: 862 device_printf(dev, "unknown device type\n"); 863 goto bad; 864 break; 865 } 866 isp->isp_revision = pci_get_revid(dev); 867 868 if (IS_FC(isp)) { 869 psize = sizeof (fcparam); 870 xsize = sizeof (struct isp_fc); 871 } else { 872 psize = sizeof (sdparam); 873 xsize = sizeof (struct isp_spi); 874 } 875 psize *= isp->isp_nchan; 876 xsize *= isp->isp_nchan; 877 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 878 if (isp->isp_param == NULL) { 879 device_printf(dev, "cannot allocate parameter data\n"); 880 goto bad; 881 } 882 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 883 if (isp->isp_osinfo.pc.ptr == NULL) { 884 device_printf(dev, "cannot allocate parameter data\n"); 885 goto bad; 886 } 887 888 /* 889 * Now that we know who we are (roughly) get/set specific options 890 */ 891 for (i = 0; i < isp->isp_nchan; i++) { 892 isp_get_specific_options(dev, i, isp); 893 } 894 895 /* 896 * The 'it' suffix really only matters for SCSI cards in target mode. 897 */ 898 isp->isp_osinfo.fw = NULL; 899 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 900 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 901 isp->isp_osinfo.fw = firmware_get(fwname); 902 } 903 if (isp->isp_osinfo.fw == NULL) { 904 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 905 isp->isp_osinfo.fw = firmware_get(fwname); 906 } 907 if (isp->isp_osinfo.fw != NULL) { 908 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 909 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 910 } 911 912 /* 913 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 914 */ 915 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 916 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 917 if (IS_2300(isp)) { /* per QLogic errata */ 918 cmd &= ~PCIM_CMD_INVEN; 919 } 920 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 921 cmd &= ~PCIM_CMD_INTX_DISABLE; 922 } 923 if (IS_24XX(isp)) { 924 cmd &= ~PCIM_CMD_INTX_DISABLE; 925 } 926 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 927 928 /* 929 * Make sure the Cache Line Size register is set sensibly. 930 */ 931 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 932 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 933 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 934 data = linesz; 935 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 936 } 937 938 /* 939 * Make sure the Latency Timer is sane. 940 */ 941 data = pci_read_config(dev, PCIR_LATTIMER, 1); 942 if (data < PCI_DFLT_LTNCY) { 943 data = PCI_DFLT_LTNCY; 944 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 945 pci_write_config(dev, PCIR_LATTIMER, data, 1); 946 } 947 948 /* 949 * Make sure we've disabled the ROM. 950 */ 951 data = pci_read_config(dev, PCIR_ROMADDR, 4); 952 data &= ~1; 953 pci_write_config(dev, PCIR_ROMADDR, data, 4); 954 955 /* 956 * Do MSI 957 * 958 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 959 */ 960 if (IS_24XX(isp) || IS_2322(isp)) { 961 pcs->msicount = pci_msi_count(dev); 962 if (pcs->msicount > 1) { 963 pcs->msicount = 1; 964 } 965 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 966 pcs->iqd = 1; 967 } else { 968 pcs->iqd = 0; 969 } 970 } 971 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 972 if (pcs->irq == NULL) { 973 device_printf(dev, "could not allocate interrupt\n"); 974 goto bad; 975 } 976 977 /* Make sure the lock is set up. */ 978 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 979 locksetup++; 980 981 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 982 device_printf(dev, "could not setup interrupt\n"); 983 goto bad; 984 } 985 986 /* 987 * Last minute checks... 988 */ 989 if (IS_23XX(isp) || IS_24XX(isp)) { 990 isp->isp_port = pci_get_function(dev); 991 } 992 993 /* 994 * Make sure we're in reset state. 995 */ 996 ISP_LOCK(isp); 997 isp_reset(isp, 1); 998 if (isp->isp_state != ISP_RESETSTATE) { 999 ISP_UNLOCK(isp); 1000 goto bad; 1001 } 1002 isp_init(isp); 1003 if (isp->isp_state == ISP_INITSTATE) { 1004 isp->isp_state = ISP_RUNSTATE; 1005 } 1006 ISP_UNLOCK(isp); 1007 if (isp_attach(isp)) { 1008 ISP_LOCK(isp); 1009 isp_uninit(isp); 1010 ISP_UNLOCK(isp); 1011 goto bad; 1012 } 1013 return (0); 1014 1015bad: 1016 if (pcs->ih) { 1017 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1018 } 1019 if (locksetup) { 1020 mtx_destroy(&isp->isp_osinfo.lock); 1021 } 1022 if (pcs->irq) { 1023 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1024 } 1025 if (pcs->msicount) { 1026 pci_release_msi(dev); 1027 } 1028 if (pcs->regs) { 1029 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1030 } 1031 if (pcs->pci_isp.isp_param) { 1032 free(pcs->pci_isp.isp_param, M_DEVBUF); 1033 pcs->pci_isp.isp_param = NULL; 1034 } 1035 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1036 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1037 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1038 } 1039 return (ENXIO); 1040} 1041 1042static int 1043isp_pci_detach(device_t dev) 1044{ 1045 struct isp_pcisoftc *pcs; 1046 ispsoftc_t *isp; 1047 int status; 1048 1049 pcs = device_get_softc(dev); 1050 if (pcs == NULL) { 1051 return (ENXIO); 1052 } 1053 isp = (ispsoftc_t *) pcs; 1054 status = isp_detach(isp); 1055 if (status) 1056 return (status); 1057 ISP_LOCK(isp); 1058 isp_uninit(isp); 1059 if (pcs->ih) { 1060 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1061 } 1062 ISP_UNLOCK(isp); 1063 mtx_destroy(&isp->isp_osinfo.lock); 1064 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1065 if (pcs->msicount) { 1066 pci_release_msi(dev); 1067 } 1068 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1069 /* 1070 * XXX: THERE IS A LOT OF LEAKAGE HERE 1071 */ 1072 if (pcs->pci_isp.isp_param) { 1073 free(pcs->pci_isp.isp_param, M_DEVBUF); 1074 pcs->pci_isp.isp_param = NULL; 1075 } 1076 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1077 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1078 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1079 } 1080 return (0); 1081} 1082 1083#define IspVirt2Off(a, x) \ 1084 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1085 _BLK_REG_SHFT] + ((x) & 0xfff)) 1086 1087#define BXR2(isp, off) \ 1088 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1089#define BXW2(isp, off, v) \ 1090 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1091#define BXR4(isp, off) \ 1092 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1093#define BXW4(isp, off, v) \ 1094 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1095 1096 1097static ISP_INLINE int 1098isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1099{ 1100 uint32_t val0, val1; 1101 int i = 0; 1102 1103 do { 1104 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1105 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1106 } while (val0 != val1 && ++i < 1000); 1107 if (val0 != val1) { 1108 return (1); 1109 } 1110 *rp = val0; 1111 return (0); 1112} 1113 1114static int 1115isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1116{ 1117 uint16_t isr, sema; 1118 1119 if (IS_2100(isp)) { 1120 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1121 return (0); 1122 } 1123 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1124 return (0); 1125 } 1126 } else { 1127 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1128 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1129 } 1130 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1131 isr &= INT_PENDING_MASK(isp); 1132 sema &= BIU_SEMA_LOCK; 1133 if (isr == 0 && sema == 0) { 1134 return (0); 1135 } 1136 *isrp = isr; 1137 if ((*semap = sema) != 0) { 1138 if (IS_2100(isp)) { 1139 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1140 return (0); 1141 } 1142 } else { 1143 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1144 } 1145 } 1146 return (1); 1147} 1148 1149static int 1150isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1151{ 1152 uint32_t hccr; 1153 uint32_t r2hisr; 1154 1155 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1156 *isrp = 0; 1157 return (0); 1158 } 1159 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1160 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1161 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1162 *isrp = 0; 1163 return (0); 1164 } 1165 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1166 case ISPR2HST_ROM_MBX_OK: 1167 case ISPR2HST_ROM_MBX_FAIL: 1168 case ISPR2HST_MBX_OK: 1169 case ISPR2HST_MBX_FAIL: 1170 case ISPR2HST_ASYNC_EVENT: 1171 *isrp = r2hisr & 0xffff; 1172 *mbox0p = (r2hisr >> 16); 1173 *semap = 1; 1174 return (1); 1175 case ISPR2HST_RIO_16: 1176 *isrp = r2hisr & 0xffff; 1177 *mbox0p = ASYNC_RIO16_1; 1178 *semap = 1; 1179 return (1); 1180 case ISPR2HST_FPOST: 1181 *isrp = r2hisr & 0xffff; 1182 *mbox0p = ASYNC_CMD_CMPLT; 1183 *semap = 1; 1184 return (1); 1185 case ISPR2HST_FPOST_CTIO: 1186 *isrp = r2hisr & 0xffff; 1187 *mbox0p = ASYNC_CTIO_DONE; 1188 *semap = 1; 1189 return (1); 1190 case ISPR2HST_RSPQ_UPDATE: 1191 *isrp = r2hisr & 0xffff; 1192 *mbox0p = 0; 1193 *semap = 0; 1194 return (1); 1195 default: 1196 hccr = ISP_READ(isp, HCCR); 1197 if (hccr & HCCR_PAUSE) { 1198 ISP_WRITE(isp, HCCR, HCCR_RESET); 1199 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1200 ISP_WRITE(isp, BIU_ICR, 0); 1201 } else { 1202 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1203 } 1204 return (0); 1205 } 1206} 1207 1208static int 1209isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1210{ 1211 uint32_t r2hisr; 1212 1213 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1214 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1215 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1216 *isrp = 0; 1217 return (0); 1218 } 1219 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1220 case ISP2400R2HST_ROM_MBX_OK: 1221 case ISP2400R2HST_ROM_MBX_FAIL: 1222 case ISP2400R2HST_MBX_OK: 1223 case ISP2400R2HST_MBX_FAIL: 1224 case ISP2400R2HST_ASYNC_EVENT: 1225 *isrp = r2hisr & 0xffff; 1226 *mbox0p = (r2hisr >> 16); 1227 *semap = 1; 1228 return (1); 1229 case ISP2400R2HST_RSPQ_UPDATE: 1230 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1231 case ISP2400R2HST_ATIO_RQST_UPDATE: 1232 *isrp = r2hisr & 0xffff; 1233 *mbox0p = 0; 1234 *semap = 0; 1235 return (1); 1236 default: 1237 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1238 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1239 return (0); 1240 } 1241} 1242 1243static uint32_t 1244isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1245{ 1246 uint16_t rv; 1247 int oldconf = 0; 1248 1249 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1250 /* 1251 * We will assume that someone has paused the RISC processor. 1252 */ 1253 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1254 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1255 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1256 } 1257 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1258 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1259 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1260 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1261 } 1262 return (rv); 1263} 1264 1265static void 1266isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1267{ 1268 int oldconf = 0; 1269 1270 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1271 /* 1272 * We will assume that someone has paused the RISC processor. 1273 */ 1274 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1275 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1276 oldconf | BIU_PCI_CONF1_SXP); 1277 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1278 } 1279 BXW2(isp, IspVirt2Off(isp, regoff), val); 1280 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1281 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1282 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1283 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1284 } 1285 1286} 1287 1288static uint32_t 1289isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1290{ 1291 uint32_t rv, oc = 0; 1292 1293 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1294 uint32_t tc; 1295 /* 1296 * We will assume that someone has paused the RISC processor. 1297 */ 1298 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1299 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1300 if (regoff & SXP_BANK1_SELECT) 1301 tc |= BIU_PCI1080_CONF1_SXP1; 1302 else 1303 tc |= BIU_PCI1080_CONF1_SXP0; 1304 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1305 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1306 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1307 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1308 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1309 oc | BIU_PCI1080_CONF1_DMA); 1310 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1311 } 1312 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1313 if (oc) { 1314 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1315 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1316 } 1317 return (rv); 1318} 1319 1320static void 1321isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1322{ 1323 int oc = 0; 1324 1325 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1326 uint32_t tc; 1327 /* 1328 * We will assume that someone has paused the RISC processor. 1329 */ 1330 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1331 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1332 if (regoff & SXP_BANK1_SELECT) 1333 tc |= BIU_PCI1080_CONF1_SXP1; 1334 else 1335 tc |= BIU_PCI1080_CONF1_SXP0; 1336 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1337 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1338 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1339 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1340 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1341 oc | BIU_PCI1080_CONF1_DMA); 1342 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1343 } 1344 BXW2(isp, IspVirt2Off(isp, regoff), val); 1345 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1346 if (oc) { 1347 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1348 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1349 } 1350} 1351 1352static uint32_t 1353isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1354{ 1355 uint32_t rv; 1356 int block = regoff & _BLK_REG_MASK; 1357 1358 switch (block) { 1359 case BIU_BLOCK: 1360 break; 1361 case MBOX_BLOCK: 1362 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1363 case SXP_BLOCK: 1364 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1365 return (0xffffffff); 1366 case RISC_BLOCK: 1367 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1368 return (0xffffffff); 1369 case DMA_BLOCK: 1370 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1371 return (0xffffffff); 1372 default: 1373 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1374 return (0xffffffff); 1375 } 1376 1377 1378 switch (regoff) { 1379 case BIU2400_FLASH_ADDR: 1380 case BIU2400_FLASH_DATA: 1381 case BIU2400_ICR: 1382 case BIU2400_ISR: 1383 case BIU2400_CSR: 1384 case BIU2400_REQINP: 1385 case BIU2400_REQOUTP: 1386 case BIU2400_RSPINP: 1387 case BIU2400_RSPOUTP: 1388 case BIU2400_PRI_REQINP: 1389 case BIU2400_PRI_REQOUTP: 1390 case BIU2400_ATIO_RSPINP: 1391 case BIU2400_ATIO_RSPOUTP: 1392 case BIU2400_HCCR: 1393 case BIU2400_GPIOD: 1394 case BIU2400_GPIOE: 1395 case BIU2400_HSEMA: 1396 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1397 break; 1398 case BIU2400_R2HSTSLO: 1399 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1400 break; 1401 case BIU2400_R2HSTSHI: 1402 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1403 break; 1404 default: 1405 isp_prt(isp, ISP_LOGERR, 1406 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1407 rv = 0xffffffff; 1408 break; 1409 } 1410 return (rv); 1411} 1412 1413static void 1414isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1415{ 1416 int block = regoff & _BLK_REG_MASK; 1417 1418 switch (block) { 1419 case BIU_BLOCK: 1420 break; 1421 case MBOX_BLOCK: 1422 BXW2(isp, IspVirt2Off(isp, regoff), val); 1423 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1424 return; 1425 case SXP_BLOCK: 1426 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1427 return; 1428 case RISC_BLOCK: 1429 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1430 return; 1431 case DMA_BLOCK: 1432 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1433 return; 1434 default: 1435 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1436 regoff); 1437 break; 1438 } 1439 1440 switch (regoff) { 1441 case BIU2400_FLASH_ADDR: 1442 case BIU2400_FLASH_DATA: 1443 case BIU2400_ICR: 1444 case BIU2400_ISR: 1445 case BIU2400_CSR: 1446 case BIU2400_REQINP: 1447 case BIU2400_REQOUTP: 1448 case BIU2400_RSPINP: 1449 case BIU2400_RSPOUTP: 1450 case BIU2400_PRI_REQINP: 1451 case BIU2400_PRI_REQOUTP: 1452 case BIU2400_ATIO_RSPINP: 1453 case BIU2400_ATIO_RSPOUTP: 1454 case BIU2400_HCCR: 1455 case BIU2400_GPIOD: 1456 case BIU2400_GPIOE: 1457 case BIU2400_HSEMA: 1458 BXW4(isp, IspVirt2Off(isp, regoff), val); 1459#ifdef MEMORYBARRIERW 1460 if (regoff == BIU2400_REQINP || 1461 regoff == BIU2400_RSPOUTP || 1462 regoff == BIU2400_PRI_REQINP || 1463 regoff == BIU2400_ATIO_RSPOUTP) 1464 MEMORYBARRIERW(isp, SYNC_REG, 1465 IspVirt2Off(isp, regoff), 4, -1) 1466 else 1467#endif 1468 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1469 break; 1470 default: 1471 isp_prt(isp, ISP_LOGERR, 1472 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1473 break; 1474 } 1475} 1476 1477 1478struct imush { 1479 ispsoftc_t *isp; 1480 caddr_t vbase; 1481 int chan; 1482 int error; 1483}; 1484 1485static void imc(void *, bus_dma_segment_t *, int, int); 1486static void imc1(void *, bus_dma_segment_t *, int, int); 1487 1488static void 1489imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1490{ 1491 struct imush *imushp = (struct imush *) arg; 1492 isp_ecmd_t *ecmd; 1493 1494 if (error) { 1495 imushp->error = error; 1496 return; 1497 } 1498 if (nseg != 1) { 1499 imushp->error = EINVAL; 1500 return; 1501 } 1502 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1503 1504 imushp->isp->isp_rquest = imushp->vbase; 1505 imushp->isp->isp_rquest_dma = segs->ds_addr; 1506 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1507 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1508 1509 imushp->isp->isp_result_dma = segs->ds_addr; 1510 imushp->isp->isp_result = imushp->vbase; 1511 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1512 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1513 1514 if (imushp->isp->isp_type >= ISP_HA_FC_2300) { 1515 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr; 1516 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase; 1517 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free; 1518 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1519 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) { 1520 ecmd->next = NULL; 1521 } else { 1522 ecmd->next = ecmd + 1; 1523 } 1524 } 1525 } 1526#ifdef ISP_TARGET_MODE 1527 segs->ds_addr += (N_XCMDS * XCMD_SIZE); 1528 imushp->vbase += (N_XCMDS * XCMD_SIZE); 1529 if (IS_24XX(imushp->isp)) { 1530 imushp->isp->isp_atioq_dma = segs->ds_addr; 1531 imushp->isp->isp_atioq = imushp->vbase; 1532 } 1533#endif 1534} 1535 1536static void 1537imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1538{ 1539 struct imush *imushp = (struct imush *) arg; 1540 if (error) { 1541 imushp->error = error; 1542 return; 1543 } 1544 if (nseg != 1) { 1545 imushp->error = EINVAL; 1546 return; 1547 } 1548 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1549 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1550 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1551} 1552 1553static int 1554isp_pci_mbxdma(ispsoftc_t *isp) 1555{ 1556 caddr_t base; 1557 uint32_t len, nsegs; 1558 int i, error, cmap = 0; 1559 bus_size_t slim; /* segment size */ 1560 bus_addr_t llim; /* low limit of unavailable dma */ 1561 bus_addr_t hlim; /* high limit of unavailable dma */ 1562 struct imush im; 1563 1564 /* 1565 * Already been here? If so, leave... 1566 */ 1567 if (isp->isp_rquest) { 1568 return (0); 1569 } 1570 ISP_UNLOCK(isp); 1571 1572 if (isp->isp_maxcmds == 0) { 1573 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1574 ISP_LOCK(isp); 1575 return (1); 1576 } 1577 1578 hlim = BUS_SPACE_MAXADDR; 1579 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1580 if (sizeof (bus_size_t) > 4) { 1581 slim = (bus_size_t) (1ULL << 32); 1582 } else { 1583 slim = (bus_size_t) (1UL << 31); 1584 } 1585 llim = BUS_SPACE_MAXADDR; 1586 } else { 1587 llim = BUS_SPACE_MAXADDR_32BIT; 1588 slim = (1UL << 24); 1589 } 1590 1591 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1592 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1593 if (isp->isp_osinfo.pcmd_pool == NULL) { 1594 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1595 ISP_LOCK(isp); 1596 return (1); 1597 } 1598 1599 if (isp->isp_osinfo.sixtyfourbit) { 1600 nsegs = ISP_NSEG64_MAX; 1601 } else { 1602 nsegs = ISP_NSEG_MAX; 1603 } 1604#ifdef ISP_TARGET_MODE 1605 /* 1606 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1607 */ 1608 if (IS_SCSI(isp) && isp->isp_osinfo.sixtyfourbit) { 1609 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1610 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1611 ISP_LOCK(isp); 1612 return (1); 1613 } 1614#endif 1615 1616 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) { 1617 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1618 ISP_LOCK(isp); 1619 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1620 return (1); 1621 } 1622 1623 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1624 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1625 if (isp->isp_xflist == NULL) { 1626 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1627 ISP_LOCK(isp); 1628 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1629 return (1); 1630 } 1631 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1632 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1633 } 1634 isp->isp_xffree = isp->isp_xflist; 1635#ifdef ISP_TARGET_MODE 1636 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1637 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1638 if (isp->isp_tgtlist == NULL) { 1639 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1640 free(isp->isp_xflist, M_DEVBUF); 1641 ISP_LOCK(isp); 1642 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1643 return (1); 1644 } 1645 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1646 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1647 } 1648 isp->isp_tgtfree = isp->isp_tgtlist; 1649#endif 1650 1651 /* 1652 * Allocate and map the request and result queues (and ATIO queue 1653 * if we're a 2400 supporting target mode), and a region for 1654 * external dma addressable command/status structures (23XX and 1655 * later). 1656 */ 1657 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1658 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1659#ifdef ISP_TARGET_MODE 1660 if (IS_24XX(isp)) { 1661 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1662 } 1663#endif 1664 if (isp->isp_type >= ISP_HA_FC_2300) { 1665 len += (N_XCMDS * XCMD_SIZE); 1666 } 1667 1668 /* 1669 * Create a tag for the control spaces. We don't always need this 1670 * to be 32 bits, but we do this for simplicity and speed's sake. 1671 */ 1672 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) { 1673 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1674 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1675 free(isp->isp_xflist, M_DEVBUF); 1676#ifdef ISP_TARGET_MODE 1677 free(isp->isp_tgtlist, M_DEVBUF); 1678#endif 1679 ISP_LOCK(isp); 1680 return (1); 1681 } 1682 1683 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1684 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1685 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1686 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1687 free(isp->isp_xflist, M_DEVBUF); 1688#ifdef ISP_TARGET_MODE 1689 free(isp->isp_tgtlist, M_DEVBUF); 1690#endif 1691 ISP_LOCK(isp); 1692 return (1); 1693 } 1694 1695 im.isp = isp; 1696 im.chan = 0; 1697 im.vbase = base; 1698 im.error = 0; 1699 1700 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1701 if (im.error) { 1702 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1703 goto bad; 1704 } 1705 1706 if (IS_FC(isp)) { 1707 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1708 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1709 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1710 goto bad; 1711 } 1712 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1713 bus_dma_tag_destroy(fc->tdmat); 1714 goto bad; 1715 } 1716 im.isp = isp; 1717 im.chan = cmap; 1718 im.vbase = base; 1719 im.error = 0; 1720 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1721 if (im.error) { 1722 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1723 bus_dma_tag_destroy(fc->tdmat); 1724 goto bad; 1725 } 1726 if (isp->isp_type >= ISP_HA_FC_2300) { 1727 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1728 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1729 if (n == NULL) { 1730 while (fc->nexus_free_list) { 1731 n = fc->nexus_free_list; 1732 fc->nexus_free_list = n->next; 1733 free(n, M_DEVBUF); 1734 } 1735 goto bad; 1736 } 1737 n->next = fc->nexus_free_list; 1738 fc->nexus_free_list = n; 1739 } 1740 } 1741 } 1742 } 1743 1744 for (i = 0; i < isp->isp_maxcmds; i++) { 1745 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1746 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1747 if (error) { 1748 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1749 while (--i >= 0) { 1750 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1751 } 1752 goto bad; 1753 } 1754 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1755 if (i == isp->isp_maxcmds-1) { 1756 pcmd->next = NULL; 1757 } else { 1758 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1759 } 1760 } 1761 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1762 ISP_LOCK(isp); 1763 return (0); 1764 1765bad: 1766 while (--cmap >= 0) { 1767 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1768 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1769 bus_dma_tag_destroy(fc->tdmat); 1770 while (fc->nexus_free_list) { 1771 struct isp_nexus *n = fc->nexus_free_list; 1772 fc->nexus_free_list = n->next; 1773 free(n, M_DEVBUF); 1774 } 1775 } 1776 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1777 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1778 free(isp->isp_xflist, M_DEVBUF); 1779#ifdef ISP_TARGET_MODE 1780 free(isp->isp_tgtlist, M_DEVBUF); 1781#endif 1782 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1783 isp->isp_rquest = NULL; 1784 ISP_LOCK(isp); 1785 return (1); 1786} 1787 1788typedef struct { 1789 ispsoftc_t *isp; 1790 void *cmd_token; 1791 void *rq; /* original request */ 1792 int error; 1793 bus_size_t mapsize; 1794} mush_t; 1795 1796#define MUSHERR_NOQENTRIES -2 1797 1798#ifdef ISP_TARGET_MODE 1799static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1800static void tdma2(void *, bus_dma_segment_t *, int, int); 1801 1802static void 1803tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1804{ 1805 mush_t *mp; 1806 mp = (mush_t *)arg; 1807 mp->mapsize = mapsize; 1808 tdma2(arg, dm_segs, nseg, error); 1809} 1810 1811static void 1812tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1813{ 1814 mush_t *mp; 1815 ispsoftc_t *isp; 1816 struct ccb_scsiio *csio; 1817 isp_ddir_t ddir; 1818 ispreq_t *rq; 1819 1820 mp = (mush_t *) arg; 1821 if (error) { 1822 mp->error = error; 1823 return; 1824 } 1825 csio = mp->cmd_token; 1826 isp = mp->isp; 1827 rq = mp->rq; 1828 if (nseg) { 1829 if (isp->isp_osinfo.sixtyfourbit) { 1830 if (nseg >= ISP_NSEG64_MAX) { 1831 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1832 mp->error = EFAULT; 1833 return; 1834 } 1835 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1836 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1837 } 1838 } else { 1839 if (nseg >= ISP_NSEG_MAX) { 1840 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1841 mp->error = EFAULT; 1842 return; 1843 } 1844 } 1845 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1846 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1847 ddir = ISP_TO_DEVICE; 1848 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1849 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1850 ddir = ISP_FROM_DEVICE; 1851 } else { 1852 dm_segs = NULL; 1853 nseg = 0; 1854 ddir = ISP_NOXFR; 1855 } 1856 } else { 1857 dm_segs = NULL; 1858 nseg = 0; 1859 ddir = ISP_NOXFR; 1860 } 1861 1862 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len); 1863 switch (error) { 1864 case CMD_EAGAIN: 1865 mp->error = MUSHERR_NOQENTRIES; 1866 case CMD_QUEUED: 1867 break; 1868 default: 1869 mp->error = EIO; 1870 } 1871} 1872#endif 1873 1874static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1875static void dma2(void *, bus_dma_segment_t *, int, int); 1876 1877static void 1878dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1879{ 1880 mush_t *mp; 1881 mp = (mush_t *)arg; 1882 mp->mapsize = mapsize; 1883 dma2(arg, dm_segs, nseg, error); 1884} 1885 1886static void 1887dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1888{ 1889 mush_t *mp; 1890 ispsoftc_t *isp; 1891 struct ccb_scsiio *csio; 1892 isp_ddir_t ddir; 1893 ispreq_t *rq; 1894 1895 mp = (mush_t *) arg; 1896 if (error) { 1897 mp->error = error; 1898 return; 1899 } 1900 csio = mp->cmd_token; 1901 isp = mp->isp; 1902 rq = mp->rq; 1903 if (nseg) { 1904 if (isp->isp_osinfo.sixtyfourbit) { 1905 if (nseg >= ISP_NSEG64_MAX) { 1906 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1907 mp->error = EFAULT; 1908 return; 1909 } 1910 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1911 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1912 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1913 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1914 } 1915 } else { 1916 if (nseg >= ISP_NSEG_MAX) { 1917 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1918 mp->error = EFAULT; 1919 return; 1920 } 1921 } 1922 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1923 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1924 ddir = ISP_FROM_DEVICE; 1925 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1926 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1927 ddir = ISP_TO_DEVICE; 1928 } else { 1929 ddir = ISP_NOXFR; 1930 } 1931 } else { 1932 dm_segs = NULL; 1933 nseg = 0; 1934 ddir = ISP_NOXFR; 1935 } 1936 1937 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map); 1938 switch (error) { 1939 case CMD_EAGAIN: 1940 mp->error = MUSHERR_NOQENTRIES; 1941 break; 1942 case CMD_QUEUED: 1943 break; 1944 default: 1945 mp->error = EIO; 1946 break; 1947 } 1948} 1949 1950static int 1951isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1952{ 1953 mush_t mush, *mp; 1954 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1955 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1956 int error; 1957 1958 mp = &mush; 1959 mp->isp = isp; 1960 mp->cmd_token = csio; 1961 mp->rq = ff; 1962 mp->error = 0; 1963 mp->mapsize = 0; 1964 1965#ifdef ISP_TARGET_MODE 1966 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1967 eptr = tdma2; 1968 eptr2 = tdma2_2; 1969 } else 1970#endif 1971 { 1972 eptr = dma2; 1973 eptr2 = dma2_2; 1974 } 1975 1976 1977 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1978 (union ccb *)csio, eptr, mp, 0); 1979 if (error == EINPROGRESS) { 1980 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1981 mp->error = EINVAL; 1982 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1983 } else if (error && mp->error == 0) { 1984#ifdef DIAGNOSTIC 1985 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1986#endif 1987 mp->error = error; 1988 } 1989 if (mp->error) { 1990 int retval = CMD_COMPLETE; 1991 if (mp->error == MUSHERR_NOQENTRIES) { 1992 retval = CMD_EAGAIN; 1993 } else if (mp->error == EFBIG) { 1994 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1995 } else if (mp->error == EINVAL) { 1996 csio->ccb_h.status = CAM_REQ_INVALID; 1997 } else { 1998 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1999 } 2000 return (retval); 2001 } 2002 return (CMD_QUEUED); 2003} 2004 2005static void 2006isp_pci_reset0(ispsoftc_t *isp) 2007{ 2008 ISP_DISABLE_INTS(isp); 2009} 2010 2011static void 2012isp_pci_reset1(ispsoftc_t *isp) 2013{ 2014 if (!IS_24XX(isp)) { 2015 /* Make sure the BIOS is disabled */ 2016 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 2017 } 2018 /* and enable interrupts */ 2019 ISP_ENABLE_INTS(isp); 2020} 2021 2022static void 2023isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2024{ 2025 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2026 if (msg) 2027 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2028 else 2029 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2030 if (IS_SCSI(isp)) 2031 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2032 else 2033 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2034 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2035 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2036 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2037 2038 2039 if (IS_SCSI(isp)) { 2040 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2041 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2042 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2043 ISP_READ(isp, CDMA_FIFO_STS)); 2044 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2045 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2046 ISP_READ(isp, DDMA_FIFO_STS)); 2047 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2048 ISP_READ(isp, SXP_INTERRUPT), 2049 ISP_READ(isp, SXP_GROSS_ERR), 2050 ISP_READ(isp, SXP_PINS_CTRL)); 2051 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2052 } 2053 printf(" mbox regs: %x %x %x %x %x\n", 2054 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2055 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2056 ISP_READ(isp, OUTMAILBOX4)); 2057 printf(" PCI Status Command/Status=%x\n", 2058 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2059} 2060