ioat_hw.h revision 300661 
1/*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27__FBSDID("$FreeBSD: stable/10/sys/dev/ioat/ioat_hw.h 300661 2016-05-25 07:09:54Z mav $");
28
29#ifndef __IOAT_HW_H__
30#define __IOAT_HW_H__
31
32#define	IOAT_MAX_CHANNELS		32
33
34#define	IOAT_CHANCNT_OFFSET		0x00
35
36#define	IOAT_XFERCAP_OFFSET		0x01
37/* Only bits [4:0] are valid. */
38#define	IOAT_XFERCAP_VALID_MASK		0x1f
39
40#define	IOAT_GENCTRL_OFFSET		0x02
41
42#define	IOAT_INTRCTRL_OFFSET		0x03
43#define	IOAT_INTRCTRL_MASTER_INT_EN	0x01
44
45#define	IOAT_ATTNSTATUS_OFFSET		0x04
46
47#define	IOAT_CBVER_OFFSET		0x08
48
49#define	IOAT_INTRDELAY_OFFSET		0x0C
50#define	IOAT_INTRDELAY_SUPPORTED	(1 << 15)
51/* Reserved.				(1 << 14) */
52/* [13:0] is the coalesce period, in microseconds. */
53#define	IOAT_INTRDELAY_US_MASK		((1 << 14) - 1)
54
55#define	IOAT_CS_STATUS_OFFSET		0x0E
56
57#define	IOAT_DMACAPABILITY_OFFSET	0x10
58#define	IOAT_DMACAP_PB			(1 << 0)
59#define	IOAT_DMACAP_CRC			(1 << 1)
60#define	IOAT_DMACAP_MARKER_SKIP		(1 << 2)
61#define	IOAT_DMACAP_OLD_XOR		(1 << 3)
62#define	IOAT_DMACAP_DCA			(1 << 4)
63#define	IOAT_DMACAP_MOVECRC		(1 << 5)
64#define	IOAT_DMACAP_BFILL		(1 << 6)
65#define	IOAT_DMACAP_EXT_APIC		(1 << 7)
66#define	IOAT_DMACAP_XOR			(1 << 8)
67#define	IOAT_DMACAP_PQ			(1 << 9)
68#define	IOAT_DMACAP_DMA_DIF		(1 << 10)
69#define	IOAT_DMACAP_DWBES		(1 << 13)
70#define	IOAT_DMACAP_RAID16SS		(1 << 17)
71#define	IOAT_DMACAP_DMAMC		(1 << 18)
72#define	IOAT_DMACAP_CTOS		(1 << 19)
73
74#define	IOAT_DMACAP_STR \
75    "\20\24Completion_Timeout_Support\23DMA_with_Multicasting_Support" \
76    "\22RAID_Super_descriptors\16Descriptor_Write_Back_Error_Support" \
77    "\13DMA_with_DIF\12PQ\11XOR\10Extended_APIC_ID\07Block_Fill\06Move_CRC" \
78    "\05DCA\04Old_XOR\03Marker_Skipping\02CRC\01Page_Break"
79
80/* DMA Channel Registers */
81#define	IOAT_CHANCTRL_OFFSET			0x80
82#define	IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK	0xF000
83#define	IOAT_CHANCTRL_COMPL_DCA_EN		0x0200
84#define	IOAT_CHANCTRL_CHANNEL_IN_USE		0x0100
85#define	IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL	0x0020
86#define	IOAT_CHANCTRL_ERR_INT_EN		0x0010
87#define	IOAT_CHANCTRL_ANY_ERR_ABORT_EN		0x0008
88#define	IOAT_CHANCTRL_ERR_COMPLETION_EN		0x0004
89#define	IOAT_CHANCTRL_INT_REARM			0x0001
90#define	IOAT_CHANCTRL_RUN			(IOAT_CHANCTRL_INT_REARM |\
91						 IOAT_CHANCTRL_ERR_COMPLETION_EN |\
92						 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\
93						 IOAT_CHANCTRL_ERR_INT_EN)
94
95#define	IOAT_CHANCMD_OFFSET		0x84
96#define	IOAT_CHANCMD_RESET		0x20
97#define	IOAT_CHANCMD_SUSPEND		0x04
98
99#define	IOAT_DMACOUNT_OFFSET		0x86
100
101#define	IOAT_CHANSTS_OFFSET_LOW		0x88
102#define	IOAT_CHANSTS_OFFSET_HIGH	0x8C
103#define	IOAT_CHANSTS_OFFSET		0x88
104
105#define	IOAT_CHANSTS_STATUS		0x7ULL
106#define	IOAT_CHANSTS_ACTIVE		0x0
107#define	IOAT_CHANSTS_IDLE		0x1
108#define	IOAT_CHANSTS_SUSPENDED		0x2
109#define	IOAT_CHANSTS_HALTED		0x3
110#define	IOAT_CHANSTS_ARMED		0x4
111
112#define	IOAT_CHANSTS_UNAFFILIATED_ERROR	0x8ULL
113#define	IOAT_CHANSTS_SOFT_ERROR		0x10ULL
114
115#define	IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK	(~0x3FULL)
116
117#define	IOAT_CHAINADDR_OFFSET_LOW	0x90
118#define	IOAT_CHAINADDR_OFFSET_HIGH	0x94
119
120#define	IOAT_CHANCMP_OFFSET_LOW		0x98
121#define	IOAT_CHANCMP_OFFSET_HIGH	0x9C
122
123#define	IOAT_CHANERR_OFFSET		0xA8
124
125#define	IOAT_CHANERR_XSADDERR		(1 << 0)
126#define	IOAT_CHANERR_XDADDERR		(1 << 1)
127#define	IOAT_CHANERR_NDADDERR		(1 << 2)
128#define	IOAT_CHANERR_DERR		(1 << 3)
129#define	IOAT_CHANERR_CHADDERR		(1 << 4)
130#define	IOAT_CHANERR_CCMDERR		(1 << 5)
131#define	IOAT_CHANERR_CUNCORERR		(1 << 6)
132#define	IOAT_CHANERR_DUNCORERR		(1 << 7)
133#define	IOAT_CHANERR_RDERR		(1 << 8)
134#define	IOAT_CHANERR_WDERR		(1 << 9)
135#define	IOAT_CHANERR_DCERR		(1 << 10)
136#define	IOAT_CHANERR_DXSERR		(1 << 11)
137#define	IOAT_CHANERR_CMPADDERR		(1 << 12)
138#define	IOAT_CHANERR_INTCFGERR		(1 << 13)
139#define	IOAT_CHANERR_SEDERR		(1 << 14)
140#define	IOAT_CHANERR_UNAFFERR		(1 << 15)
141#define	IOAT_CHANERR_CXPERR		(1 << 16)
142/* Reserved.				(1 << 17) */
143#define	IOAT_CHANERR_DCNTERR		(1 << 18)
144#define	IOAT_CHANERR_DIFFERR		(1 << 19)
145#define	IOAT_CHANERR_GTVERR		(1 << 20)
146#define	IOAT_CHANERR_ATVERR		(1 << 21)
147#define	IOAT_CHANERR_RTVERR		(1 << 22)
148#define	IOAT_CHANERR_BBERR		(1 << 23)
149#define	IOAT_CHANERR_RDIFFERR		(1 << 24)
150#define	IOAT_CHANERR_RGTVERR		(1 << 25)
151#define	IOAT_CHANERR_RATVERR		(1 << 26)
152#define	IOAT_CHANERR_RRTVERR		(1 << 27)
153
154#define	IOAT_CHANERR_STR \
155    "\20\34RRTVERR\33RATVERR\32RGTVERR\31RDIFFERR\30BBERR\27RTVERR\26ATVERR" \
156    "\25GTVERR\24DIFFERR\23DCNTERR\21CXPERR\20UNAFFERR\17SEDERR\16INTCFGERR" \
157    "\15CMPADDERR\14DXSERR\13DCERR\12WDERR\11RDERR\10DUNCORERR\07CUNCORERR" \
158    "\06CCMDERR\05CHADDERR\04DERR\03NDADDERR\02XDADDERR\01XSADDERR"
159
160
161#define	IOAT_CFG_CHANERR_INT_OFFSET		0x180
162#define	IOAT_CFG_CHANERRMASK_INT_OFFSET		0x184
163
164#define	IOAT_MIN_ORDER			4
165#define	IOAT_MAX_ORDER			16
166
167#endif /* __IOAT_HW_H__ */
168