hwpmc_core.c revision 280455
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/10/sys/dev/hwpmc/hwpmc_core.c 280455 2015-03-24 20:00:11Z rrs $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#if (__FreeBSD_version >= 1100000) 42#include <x86/apicvar.h> 43#else 44#include <machine/apicvar.h> 45#endif 46#include <machine/cpu.h> 47#include <machine/cpufunc.h> 48#include <machine/md_var.h> 49#include <machine/specialreg.h> 50 51#define CORE_CPUID_REQUEST 0xA 52#define CORE_CPUID_REQUEST_SIZE 0x4 53#define CORE_CPUID_EAX 0x0 54#define CORE_CPUID_EBX 0x1 55#define CORE_CPUID_ECX 0x2 56#define CORE_CPUID_EDX 0x3 57 58#define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67#define EV_IS_NOTARCH 0 68#define EV_IS_ARCH_SUPP 1 69#define EV_IS_ARCH_NOTSUPP -1 70 71/* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84}; 85 86static enum pmc_cputype core_cputype; 87 88struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93}; 94 95static struct core_cpu **core_pcpu; 96 97static uint32_t core_architectural_events; 98static uint64_t core_pmcmask; 99 100static int core_iaf_ri; /* relative index of fixed counters */ 101static int core_iaf_width; 102static int core_iaf_npmc; 103 104static int core_iap_width; 105static int core_iap_npmc; 106 107static int 108core_pcpu_noop(struct pmc_mdep *md, int cpu) 109{ 110 (void) md; 111 (void) cpu; 112 return (0); 113} 114 115static int 116core_pcpu_init(struct pmc_mdep *md, int cpu) 117{ 118 struct pmc_cpu *pc; 119 struct core_cpu *cc; 120 struct pmc_hw *phw; 121 int core_ri, n, npmc; 122 123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 125 126 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 127 128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 130 131 if (core_cputype != PMC_CPU_INTEL_CORE) 132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 133 134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 135 M_PMC, M_WAITOK | M_ZERO); 136 137 core_pcpu[cpu] = cc; 138 pc = pmc_pcpu[cpu]; 139 140 KASSERT(pc != NULL && cc != NULL, 141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 142 143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 145 PMC_PHW_CPU_TO_STATE(cpu) | 146 PMC_PHW_INDEX_TO_STATE(n + core_ri); 147 phw->phw_pmc = NULL; 148 pc->pc_hwpmcs[n + core_ri] = phw; 149 } 150 151 return (0); 152} 153 154static int 155core_pcpu_fini(struct pmc_mdep *md, int cpu) 156{ 157 int core_ri, n, npmc; 158 struct pmc_cpu *pc; 159 struct core_cpu *cc; 160 uint64_t msr = 0; 161 162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 164 165 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 166 167 if ((cc = core_pcpu[cpu]) == NULL) 168 return (0); 169 170 core_pcpu[cpu] = NULL; 171 172 pc = pmc_pcpu[cpu]; 173 174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 175 cpu)); 176 177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 179 180 for (n = 0; n < npmc; n++) { 181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 182 wrmsr(IAP_EVSEL0 + n, msr); 183 } 184 185 if (core_cputype != PMC_CPU_INTEL_CORE) { 186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 187 wrmsr(IAF_CTRL, msr); 188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 189 } 190 191 for (n = 0; n < npmc; n++) 192 pc->pc_hwpmcs[n + core_ri] = NULL; 193 194 free(cc, M_PMC); 195 196 return (0); 197} 198 199/* 200 * Fixed function counters. 201 */ 202 203static pmc_value_t 204iaf_perfctr_value_to_reload_count(pmc_value_t v) 205{ 206 v &= (1ULL << core_iaf_width) - 1; 207 return (1ULL << core_iaf_width) - v; 208} 209 210static pmc_value_t 211iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 212{ 213 return (1ULL << core_iaf_width) - rlc; 214} 215 216static int 217iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 218 const struct pmc_op_pmcallocate *a) 219{ 220 enum pmc_event ev; 221 uint32_t caps, flags, validflags; 222 223 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 224 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 225 226 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 227 228 if (ri < 0 || ri > core_iaf_npmc) 229 return (EINVAL); 230 231 caps = a->pm_caps; 232 233 if (a->pm_class != PMC_CLASS_IAF || 234 (caps & IAF_PMC_CAPS) != caps) 235 return (EINVAL); 236 237 ev = pm->pm_event; 238 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 239 return (EINVAL); 240 241 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 242 return (EINVAL); 243 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 244 return (EINVAL); 245 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 246 return (EINVAL); 247 248 flags = a->pm_md.pm_iaf.pm_iaf_flags; 249 250 validflags = IAF_MASK; 251 252 if (core_cputype != PMC_CPU_INTEL_ATOM && 253 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 254 validflags &= ~IAF_ANY; 255 256 if ((flags & ~validflags) != 0) 257 return (EINVAL); 258 259 if (caps & PMC_CAP_INTERRUPT) 260 flags |= IAF_PMI; 261 if (caps & PMC_CAP_SYSTEM) 262 flags |= IAF_OS; 263 if (caps & PMC_CAP_USER) 264 flags |= IAF_USR; 265 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 266 flags |= (IAF_OS | IAF_USR); 267 268 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 269 270 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 271 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 272 273 return (0); 274} 275 276static int 277iaf_config_pmc(int cpu, int ri, struct pmc *pm) 278{ 279 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 280 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 281 282 KASSERT(ri >= 0 && ri < core_iaf_npmc, 283 ("[core,%d] illegal row-index %d", __LINE__, ri)); 284 285 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 286 287 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 288 cpu)); 289 290 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 291 292 return (0); 293} 294 295static int 296iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 297{ 298 int error; 299 struct pmc_hw *phw; 300 char iaf_name[PMC_NAME_MAX]; 301 302 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 303 304 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 305 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 306 NULL)) != 0) 307 return (error); 308 309 pi->pm_class = PMC_CLASS_IAF; 310 311 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 312 pi->pm_enabled = TRUE; 313 *ppmc = phw->phw_pmc; 314 } else { 315 pi->pm_enabled = FALSE; 316 *ppmc = NULL; 317 } 318 319 return (0); 320} 321 322static int 323iaf_get_config(int cpu, int ri, struct pmc **ppm) 324{ 325 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 326 327 return (0); 328} 329 330static int 331iaf_get_msr(int ri, uint32_t *msr) 332{ 333 KASSERT(ri >= 0 && ri < core_iaf_npmc, 334 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 335 336 *msr = IAF_RI_TO_MSR(ri); 337 338 return (0); 339} 340 341static int 342iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 343{ 344 struct pmc *pm; 345 pmc_value_t tmp; 346 347 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 348 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 349 KASSERT(ri >= 0 && ri < core_iaf_npmc, 350 ("[core,%d] illegal row-index %d", __LINE__, ri)); 351 352 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 353 354 KASSERT(pm, 355 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 356 ri, ri + core_iaf_ri)); 357 358 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 359 360 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 361 *v = iaf_perfctr_value_to_reload_count(tmp); 362 else 363 *v = tmp; 364 365 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 366 IAF_RI_TO_MSR(ri), *v); 367 368 return (0); 369} 370 371static int 372iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 373{ 374 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 375 376 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 377 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 378 KASSERT(ri >= 0 && ri < core_iaf_npmc, 379 ("[core,%d] illegal row-index %d", __LINE__, ri)); 380 381 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 382 ("[core,%d] PHW pmc non-NULL", __LINE__)); 383 384 return (0); 385} 386 387static int 388iaf_start_pmc(int cpu, int ri) 389{ 390 struct pmc *pm; 391 struct core_cpu *iafc; 392 uint64_t msr = 0; 393 394 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 395 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 396 KASSERT(ri >= 0 && ri < core_iaf_npmc, 397 ("[core,%d] illegal row-index %d", __LINE__, ri)); 398 399 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 400 401 iafc = core_pcpu[cpu]; 402 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 403 404 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 405 406 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 407 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 408 409 do { 410 iafc->pc_resync = 0; 411 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 412 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 413 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 414 IAF_GLOBAL_CTRL_MASK)); 415 } while (iafc->pc_resync != 0); 416 417 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 418 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 419 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 420 421 return (0); 422} 423 424static int 425iaf_stop_pmc(int cpu, int ri) 426{ 427 uint32_t fc; 428 struct core_cpu *iafc; 429 uint64_t msr = 0; 430 431 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 432 433 iafc = core_pcpu[cpu]; 434 435 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 436 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 437 KASSERT(ri >= 0 && ri < core_iaf_npmc, 438 ("[core,%d] illegal row-index %d", __LINE__, ri)); 439 440 fc = (IAF_MASK << (ri * 4)); 441 442 if (core_cputype != PMC_CPU_INTEL_ATOM && 443 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 444 fc &= ~IAF_ANY; 445 446 iafc->pc_iafctrl &= ~fc; 447 448 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 449 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 450 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 451 452 do { 453 iafc->pc_resync = 0; 454 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 455 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 456 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 457 IAF_GLOBAL_CTRL_MASK)); 458 } while (iafc->pc_resync != 0); 459 460 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 461 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 462 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 463 464 return (0); 465} 466 467static int 468iaf_write_pmc(int cpu, int ri, pmc_value_t v) 469{ 470 struct core_cpu *cc; 471 struct pmc *pm; 472 uint64_t msr; 473 474 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 475 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 476 KASSERT(ri >= 0 && ri < core_iaf_npmc, 477 ("[core,%d] illegal row-index %d", __LINE__, ri)); 478 479 cc = core_pcpu[cpu]; 480 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 481 482 KASSERT(pm, 483 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 484 485 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 486 v = iaf_reload_count_to_perfctr_value(v); 487 488 /* Turn off fixed counters */ 489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 490 wrmsr(IAF_CTRL, msr); 491 492 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 493 494 /* Turn on fixed counters */ 495 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 496 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 497 498 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 499 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 500 (uintmax_t) rdmsr(IAF_CTRL), 501 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 502 503 return (0); 504} 505 506 507static void 508iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 509{ 510 struct pmc_classdep *pcd; 511 512 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 513 514 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 515 516 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 517 518 pcd->pcd_caps = IAF_PMC_CAPS; 519 pcd->pcd_class = PMC_CLASS_IAF; 520 pcd->pcd_num = npmc; 521 pcd->pcd_ri = md->pmd_npmc; 522 pcd->pcd_width = pmcwidth; 523 524 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 525 pcd->pcd_config_pmc = iaf_config_pmc; 526 pcd->pcd_describe = iaf_describe; 527 pcd->pcd_get_config = iaf_get_config; 528 pcd->pcd_get_msr = iaf_get_msr; 529 pcd->pcd_pcpu_fini = core_pcpu_noop; 530 pcd->pcd_pcpu_init = core_pcpu_noop; 531 pcd->pcd_read_pmc = iaf_read_pmc; 532 pcd->pcd_release_pmc = iaf_release_pmc; 533 pcd->pcd_start_pmc = iaf_start_pmc; 534 pcd->pcd_stop_pmc = iaf_stop_pmc; 535 pcd->pcd_write_pmc = iaf_write_pmc; 536 537 md->pmd_npmc += npmc; 538} 539 540/* 541 * Intel programmable PMCs. 542 */ 543 544/* 545 * Event descriptor tables. 546 * 547 * For each event id, we track: 548 * 549 * 1. The CPUs that the event is valid for. 550 * 551 * 2. If the event uses a fixed UMASK, the value of the umask field. 552 * If the event doesn't use a fixed UMASK, a mask of legal bits 553 * to check against. 554 */ 555 556struct iap_event_descr { 557 enum pmc_event iap_ev; 558 unsigned char iap_evcode; 559 unsigned char iap_umask; 560 unsigned int iap_flags; 561}; 562 563#define IAP_F_CC (1 << 0) /* CPU: Core */ 564#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 565#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 566#define IAP_F_CA (1 << 3) /* CPU: Atom */ 567#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 568#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 569#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 570#define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 571#define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 572#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 573#define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 574#define IAP_F_HW (1 << 10) /* CPU: Haswell */ 575#define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 576#define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 577#define IAP_F_FM (1 << 13) /* Fixed mask */ 578 579#define IAP_F_ALLCPUSCORE2 \ 580 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 581 582/* Sub fields of UMASK that this event supports. */ 583#define IAP_M_CORE (1 << 0) /* Core specificity */ 584#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 585#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 586#define IAP_M_MESI (1 << 3) /* MESI */ 587#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 588#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 589#define IAP_M_TRANSITION (1 << 6) /* Transition */ 590 591#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 592#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 593#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 594#define IAP_F_MESI (0xF << 8) /* MESI */ 595#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 596#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 597#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 598 599#define IAP_PREFETCH_RESERVED (0x2 << 12) 600#define IAP_CORE_THIS (0x1 << 14) 601#define IAP_CORE_ALL (0x3 << 14) 602#define IAP_F_CMASK 0xFF000000 603 604static struct iap_event_descr iap_events[] = { 605#undef IAPDESCR 606#define IAPDESCR(N,EV,UM,FLAGS) { \ 607 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 608 .iap_evcode = (EV), \ 609 .iap_umask = (UM), \ 610 .iap_flags = (FLAGS) \ 611 } 612 613 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 614 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 615 616 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 617 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 618 IAP_F_SBX | IAP_F_CAS), 619 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 620 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 621 IAP_F_CAS | IAP_F_HWX), 622 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 623 IAP_F_CAS), 624 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 625 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 626 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 627 IAP_F_SBX | IAP_F_CAS), 628 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 629 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), 630 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), 631 632 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 633 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 634 IAP_F_CAS), 635 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 636 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), 637 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 638 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 639 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), 640 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), 641 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), 642 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), 643 644 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 645 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 646 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 647 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 648 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 649 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 650 651 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 652 IAP_F_CC2E | IAP_F_CA), 653 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 654 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 655 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 656 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 657 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 658 659 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 660 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 661 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 662 IAP_F_HW | IAP_F_HWX), 663 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 664 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 665 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 666 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 667 IAP_F_SBX), 668 669 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 670 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 671 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 672 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 673 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 674 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 675 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 676 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 677 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 678 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 679 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 680 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 681 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 682 IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 683 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX), 684 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 685 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 686 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 687 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 688 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 689 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 690 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX), 691 692 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 693 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 694 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 695 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 696 697 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 698 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 699 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 701 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 702 IAP_F_WM), 703 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 704 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 705 706 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 707 IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 708 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 709 710 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 711 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 712 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 713 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 714 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 715 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 716 717 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 718 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 719 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 720 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 721 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 724 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 725 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 726 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 727 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 728 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 731 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 732 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 733 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 734 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 735 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 736 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 737 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 738 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 739 740 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 741 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 742 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 743 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 744 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 745 746 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 747 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 750 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 751 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 755 756 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 757 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 762 763 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 764 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 765 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 766 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 768 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 769 IAP_F_SBX), 770 771 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 772 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 774 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 775 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 776 IAP_F_I7 | IAP_F_WM), 777 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 778 779 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 780 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 781 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 782 783 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 784 785 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 787 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 788 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 789 790 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 791 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 792 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 793 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 794 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 795 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 796 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 797 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 798 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 800 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 802 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 803 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 804 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 805 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 806 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 807 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 808 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 809 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 810 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 811 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 812 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 813 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 814 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 815 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 816 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 817 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 818 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 819 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 820 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 821 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 822 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 823 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 824 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 825 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 826 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 827 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 828 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 829 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX), 830 831 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 832 833 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 834 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 835 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 836 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 837 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 838 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 839 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 840 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 841 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 842 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 843 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 844 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 845 846 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 847 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 848 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 849 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 850 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 851 IAP_F_SBX), 852 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 853 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 854 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 855 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 856 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 857 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 858 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 859 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 860 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 861 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 862 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 863 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 864 865 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 866 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 867 IAP_F_SBX | IAP_F_IBX), 868 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 869 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 870 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 871 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 872 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 873 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 874 IAP_F_SBX | IAP_F_IBX), 875 876 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 877 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 878 IAP_F_CA | IAP_F_CC2), 879 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 880 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 881 882 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 883 IAP_F_ALLCPUSCORE2), 884 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 885 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 886 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 887 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 888 IAP_F_CAS | IAP_F_HWX), 889 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 890 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 891 IAP_F_CAS | IAP_F_HWX), 892 893 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 894 IAP_F_ALLCPUSCORE2), 895 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), 896 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), 897 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 898 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 899 900 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 901 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 902 903 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 904 905 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 906 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 907 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 908 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 909 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 910 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 911 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 912 913 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 914 915 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 916 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 917 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 918 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 919 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 920 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 921 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 922 923 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 924 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 925 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 926 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 927 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 928 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 929 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 930 931 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 932 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 933 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 934 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 935 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 936 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 937 938 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 939 IAP_F_I7), 940 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 941 IAP_F_CC2 | IAP_F_I7), 942 943 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 944 945 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 946 947 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 948 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 949 950 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 951 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 952 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 953 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 954 955 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 956 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 957 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 958 IAP_F_HW | IAP_F_HWX), 959 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 960 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 961 IAP_F_HW | IAP_F_HWX), 962 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 963 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 964 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 965 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 966 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 967 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 968 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 969 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 970 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 971 972 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 973 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 974 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 975 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 976 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 977 978 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 979 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 980 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 981 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 982 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 983 984 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 985 986 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 987 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 988 IAP_F_SB | IAP_F_SBX), 989 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 990 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 991 992 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 993 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 994 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 995 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 996 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 997 998 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 999 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1000 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1001 IAP_F_SB | IAP_F_SBX), 1002 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1003 IAP_F_SB | IAP_F_SBX), 1004 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1005 IAP_F_SB | IAP_F_SBX), 1006 1007 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1008 1009 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1010 1011 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1012 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1013 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1014 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1015 1016 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1017 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1018 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1019 1020 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1021 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1022 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1023 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1024 1025 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1026 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1027 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1028 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1029 1030 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1031 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1032 1033 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1034 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB), 1035 1036 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1037 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1038 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1039 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1040 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1041 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1042 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1043 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1044 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1045 1046 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1047 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1048 1049 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1050 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1051 1052 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1053 IAP_F_CA | IAP_F_CC2), 1054 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1055 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1056 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1057 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1058 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1059 1060 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1061 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1062 1063 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1064 IAP_F_CA | IAP_F_CC2), 1065 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1066 1067 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1068 1069 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1070 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1071 1072 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1073 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1074 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1075 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1076 1077 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1078 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1079 1080 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1081 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1082 1083 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1084 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1085 1086 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1087 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1088 1089 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1090 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1091 1092 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1093 IAP_F_CA | IAP_F_CC2), 1094 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1095 1096 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1097 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1098 1099 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1100 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1101 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1102 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1103 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1104 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1105 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1106 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1107 1108 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1109 1110 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1111 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1112 1113 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1114 1115 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1116 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1117 1118 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1119 1120 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1121 1122 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1123 1124 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1125 1126 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1127 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1128 1129 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1130 1131 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1132 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1133 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1134 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1135 IAP_F_CAS | IAP_F_HWX), 1136 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1137 IAP_F_WM | IAP_F_CAS), 1138 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX), 1139 1140 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1141 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1142 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1143 1144 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1145 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1146 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1147 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1148 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1149 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1150 1151 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1152 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1153 1154 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1155 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1156 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1157 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1158 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1159 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1160 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1161 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1162 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1163 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1164 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1165 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1166 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1167 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1168 1169 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1170 1171 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1172 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1173 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1174 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1175 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1176 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1177 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1178 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1179 1180 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1181 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1182 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1183 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1184 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1185 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1186 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1187 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1188 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1189 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1190 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1191 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1192 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1193 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1194 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1195 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1196 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1197 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1198 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1199 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1200 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1201 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1202 1203 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1204 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1205 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1206 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1207 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1208 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1209 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1210 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1211 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1212 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1213 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1214 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1215 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1216 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1217 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1219 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1220 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1221 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1222 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1223 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1224 1225 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1226 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1227 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1228 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1229 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1230 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1231 1232 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1233 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1234 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1235 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1236 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1237 1238 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1239 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1240 1241 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1242 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1243 1244 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1245 1246 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1247 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1248 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1249 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1250 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1251 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1252 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1253 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1254 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_IB | IAP_F_IBX), 1255 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1256 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1257 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1258 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1259 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1260 IAP_F_SBX | IAP_F_IBX), 1261 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1262 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1263 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1264 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1265 1266 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1267 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1268 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1269 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1270 IAP_F_SB | IAP_F_SBX), 1271 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1272 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1273 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1274 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1275 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1276 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1277 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1278 IAP_F_SB | IAP_F_SBX), 1279 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1280 IAP_F_SB | IAP_F_SBX), 1281 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1282 IAP_F_SB | IAP_F_SBX), 1283 1284 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1285 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1286 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB), 1287 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1288 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX), 1289 IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1290 1291 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1292 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1293 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1294 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 1295 1296 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1297 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1298 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1299 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1300 1301 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1302 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1303 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1304 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1305 1306 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1307 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1308 IAP_F_SBX | IAP_F_IBX), 1309 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1310 1311 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1312 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1313 1314 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1315 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1316 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1317 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1318 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1319 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1320 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1321 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1322 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1323 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1324 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1325 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1326 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1327 1328 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1329 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1330 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1331 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1332 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1333 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1334 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1335 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1336 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1337 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1338 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1339 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1340 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1341 IAP_F_WM), 1342 1343 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1344 IAP_F_SB | IAP_F_SBX), 1345 1346 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1347 IAP_F_WM | IAP_F_I7O), 1348 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1349 IAP_F_WM | IAP_F_I7O), 1350 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1351 IAP_F_WM | IAP_F_I7O), 1352 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1353 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1354 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1355 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1356 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1357 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1358 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1359 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1360 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1361 1362 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1363 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1364 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1365 1366 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1367 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), 1368 1369 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1370 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_CAS), 1371 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1372 1373 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1374 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1375 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1376 1377 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1378 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1379 1380 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1381 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1382 1383 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1384 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1385 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1386 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1387 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1388 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1389 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1390 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1391 1392 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1393 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1394 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1395 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1396 1397 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1398 1399 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1400 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1401 IAP_F_CAS | IAP_F_HWX), 1402 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1403 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1404 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1405 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1406 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1407 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1408 IAP_F_I7 | IAP_F_WM), 1409 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1410 1411 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1412 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1413 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1414 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1415 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1416 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1417 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1418 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1419 IAP_F_SBX | IAP_F_IBX), 1420 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1421 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX), 1422 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1423 1424 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1425 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1426 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1427 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1428 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1429 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1430 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1431 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1432 IAP_F_I7 | IAP_F_WM), 1433 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1434 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1435 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1436 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1437 1438 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1439 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1440 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1441 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1442 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1443 IAP_F_CAS | IAP_F_HWX), 1444 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1445 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1446 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1447 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), 1448 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1449 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1450 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1451 1452 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1453 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1454 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1455 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1456 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1457 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1458 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1459 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1460 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1461 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1462 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1463 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1464 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1465 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1466 IAP_F_HWX), 1467 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1468 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1469 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1470 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1471 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1472 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1473 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1474 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1475 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), 1476 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), 1477 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), 1478 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), 1479 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), 1480 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), 1481 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), 1482 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), 1483 1484 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1485 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1486 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1487 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1488 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1489 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1490 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1491 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1492 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1493 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1494 IAP_F_SBX | IAP_F_IBX), 1495 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1496 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1497 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), 1498 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), 1499 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), 1500 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), 1501 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), 1502 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), 1503 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), 1504 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), 1505 1506 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1507 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1508 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1509 1510 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1511 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1512 IAP_F_I7 | IAP_F_WM), 1513 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1514 IAP_F_I7 | IAP_F_WM), 1515 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1516 IAP_F_I7 | IAP_F_WM), 1517 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1518 IAP_F_I7 | IAP_F_WM), 1519 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1520 IAP_F_I7 | IAP_F_WM), 1521 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1522 1523 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1524 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1525 1526 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1527 1528 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1529 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1530 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1531 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1532 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1533 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1534 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1535 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1536 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1537 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1538 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1539 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1540 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), 1541 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), 1542 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), 1543 1544 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1545 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1546 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1547 IAP_F_I7 | IAP_F_WM), 1548 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1549 IAP_F_I7 | IAP_F_WM), 1550 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1551 IAP_F_I7 | IAP_F_WM), 1552 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1553 IAP_F_WM), 1554 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), 1555 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1556 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1557 1558 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1559 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1560 IAP_F_I7 | IAP_F_WM), 1561 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1562 IAP_F_I7 | IAP_F_WM), 1563 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1564 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1565 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1566 1567 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1568 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1569 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1570 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1571 IAP_F_SBX | IAP_F_IBX), 1572 1573 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1574 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1575 1576 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1577 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1578 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1579 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1580 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1581 IAP_F_HWX), 1582 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1583 IAP_F_HWX), 1584 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1585 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1586 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1587 IAP_F_HWX), 1588 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1589 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1590 IAP_F_HWX), 1591 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1592 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ 1593 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1594 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ 1595 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1596 IAP_F_HWX), 1597 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1598 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ 1599 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1600 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ 1601 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1602 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1603 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1604 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1605 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1606 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1607 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1608 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1609 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 1610 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1611 IAP_F_HW | IAP_F_HWX), 1612 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1613 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1614 1615 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1616 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1617 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1618 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1619 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1620 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1621 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1622 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1623 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1624 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1625 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1626 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1627 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1628 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1629 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1630 1631 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1632 1633 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1634 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1635 IAPDESCR(D3H_03H, 0xD0, 0x3, IAP_F_IBX ), 1636 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1637 IAPDESCR(D3H_0CH, 0xD0, 0x0, IAP_F_IBX ), 1638 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ), 1639 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ), 1640 1641 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1642 IAP_F_I7 | IAP_F_WM), 1643 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1644 IAP_F_SB | IAP_F_SBX), 1645 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1646 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1647 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1648 1649 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1650 IAP_F_I7 | IAP_F_WM), 1651 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1652 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1653 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1654 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1655 1656 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1657 1658 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1659 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1660 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1661 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1662 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1663 1664 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1665 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1666 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1667 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1668 1669 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1670 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1671 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1672 1673 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1674 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1675 1676 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1677 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1678 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1679 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1680 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1681 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1682 1683 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1684 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1685 IAP_F_WM), 1686 1687 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1688 1689 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1690 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1691 1692 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1693 1694 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1695 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1696 IAP_F_WM | IAP_F_SBX | IAP_F_CAS), 1697 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1698 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), 1699 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), 1700 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1701 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1702 1703 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), 1704 1705 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1706 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1707 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1708 1709 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1710 1711 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1712 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1713 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1714 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1715 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1716 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1717 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1718 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1719 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1720 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1721 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1722 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1723 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1724 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1725 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1726 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1727 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1728 1729 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1730 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1731 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1732 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1733 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1734 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1735 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1736 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1737 1738 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1739 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1740 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1741 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1742 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1743 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1744 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1745 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1746 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1747 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1748 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1749 IAP_F_IBX), 1750 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1751 1752 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1753 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1754 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1755 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1756 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1757 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1758 1759 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1760 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1761 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1762 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1763 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1764 IAP_F_SB | IAP_F_SBX), 1765 1766 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1767 1768 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1769 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1770 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1771 1772 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1773 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1774 1775 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1776 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1777 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1778 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1779 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1780 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1781 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1782}; 1783 1784static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1785 1786static pmc_value_t 1787iap_perfctr_value_to_reload_count(pmc_value_t v) 1788{ 1789 v &= (1ULL << core_iap_width) - 1; 1790 return (1ULL << core_iap_width) - v; 1791} 1792 1793static pmc_value_t 1794iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1795{ 1796 return (1ULL << core_iap_width) - rlc; 1797} 1798 1799static int 1800iap_pmc_has_overflowed(int ri) 1801{ 1802 uint64_t v; 1803 1804 /* 1805 * We treat a Core (i.e., Intel architecture v1) PMC as has 1806 * having overflowed if its MSB is zero. 1807 */ 1808 v = rdpmc(ri); 1809 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1810} 1811 1812/* 1813 * Check an event against the set of supported architectural events. 1814 * 1815 * If the event is not architectural EV_IS_NOTARCH is returned. 1816 * If the event is architectural and supported on this CPU, the correct 1817 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1818 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1819 */ 1820 1821static int 1822iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1823{ 1824 enum core_arch_events ae; 1825 1826 switch (pe) { 1827 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1828 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1829 *map = PMC_EV_IAP_EVENT_3CH_00H; 1830 break; 1831 case PMC_EV_IAP_ARCH_INS_RET: 1832 ae = CORE_AE_INSTRUCTION_RETIRED; 1833 *map = PMC_EV_IAP_EVENT_C0H_00H; 1834 break; 1835 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1836 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1837 *map = PMC_EV_IAP_EVENT_3CH_01H; 1838 break; 1839 case PMC_EV_IAP_ARCH_LLC_REF: 1840 ae = CORE_AE_LLC_REFERENCE; 1841 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1842 break; 1843 case PMC_EV_IAP_ARCH_LLC_MIS: 1844 ae = CORE_AE_LLC_MISSES; 1845 *map = PMC_EV_IAP_EVENT_2EH_41H; 1846 break; 1847 case PMC_EV_IAP_ARCH_BR_INS_RET: 1848 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1849 *map = PMC_EV_IAP_EVENT_C4H_00H; 1850 break; 1851 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1852 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1853 *map = PMC_EV_IAP_EVENT_C5H_00H; 1854 break; 1855 1856 default: /* Non architectural event. */ 1857 return (EV_IS_NOTARCH); 1858 } 1859 1860 return (((core_architectural_events & (1 << ae)) == 0) ? 1861 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1862} 1863 1864static int 1865iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1866{ 1867 uint32_t mask; 1868 1869 switch (pe) { 1870 /* 1871 * Events valid only on counter 0, 1. 1872 */ 1873 case PMC_EV_IAP_EVENT_40H_01H: 1874 case PMC_EV_IAP_EVENT_40H_02H: 1875 case PMC_EV_IAP_EVENT_40H_04H: 1876 case PMC_EV_IAP_EVENT_40H_08H: 1877 case PMC_EV_IAP_EVENT_40H_0FH: 1878 case PMC_EV_IAP_EVENT_41H_02H: 1879 case PMC_EV_IAP_EVENT_41H_04H: 1880 case PMC_EV_IAP_EVENT_41H_08H: 1881 case PMC_EV_IAP_EVENT_42H_01H: 1882 case PMC_EV_IAP_EVENT_42H_02H: 1883 case PMC_EV_IAP_EVENT_42H_04H: 1884 case PMC_EV_IAP_EVENT_42H_08H: 1885 case PMC_EV_IAP_EVENT_43H_01H: 1886 case PMC_EV_IAP_EVENT_43H_02H: 1887 case PMC_EV_IAP_EVENT_51H_01H: 1888 case PMC_EV_IAP_EVENT_51H_02H: 1889 case PMC_EV_IAP_EVENT_51H_04H: 1890 case PMC_EV_IAP_EVENT_51H_08H: 1891 case PMC_EV_IAP_EVENT_63H_01H: 1892 case PMC_EV_IAP_EVENT_63H_02H: 1893 mask = 0x3; 1894 break; 1895 1896 default: 1897 mask = ~0; /* Any row index is ok. */ 1898 } 1899 1900 return (mask & (1 << ri)); 1901} 1902 1903static int 1904iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1905{ 1906 uint32_t mask; 1907 1908 switch (pe) { 1909 /* 1910 * Events valid only on counter 0. 1911 */ 1912 case PMC_EV_IAP_EVENT_60H_01H: 1913 case PMC_EV_IAP_EVENT_60H_02H: 1914 case PMC_EV_IAP_EVENT_60H_04H: 1915 case PMC_EV_IAP_EVENT_60H_08H: 1916 case PMC_EV_IAP_EVENT_B3H_01H: 1917 case PMC_EV_IAP_EVENT_B3H_02H: 1918 case PMC_EV_IAP_EVENT_B3H_04H: 1919 mask = 0x1; 1920 break; 1921 1922 /* 1923 * Events valid only on counter 0, 1. 1924 */ 1925 case PMC_EV_IAP_EVENT_4CH_01H: 1926 case PMC_EV_IAP_EVENT_4EH_01H: 1927 case PMC_EV_IAP_EVENT_4EH_02H: 1928 case PMC_EV_IAP_EVENT_4EH_04H: 1929 case PMC_EV_IAP_EVENT_51H_01H: 1930 case PMC_EV_IAP_EVENT_51H_02H: 1931 case PMC_EV_IAP_EVENT_51H_04H: 1932 case PMC_EV_IAP_EVENT_51H_08H: 1933 case PMC_EV_IAP_EVENT_63H_01H: 1934 case PMC_EV_IAP_EVENT_63H_02H: 1935 mask = 0x3; 1936 break; 1937 1938 default: 1939 mask = ~0; /* Any row index is ok. */ 1940 } 1941 1942 return (mask & (1 << ri)); 1943} 1944 1945static int 1946iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1947{ 1948 uint32_t mask; 1949 1950 switch (pe) { 1951 /* Events valid only on counter 0. */ 1952 case PMC_EV_IAP_EVENT_B7H_01H: 1953 mask = 0x1; 1954 break; 1955 /* Events valid only on counter 1. */ 1956 case PMC_EV_IAP_EVENT_C0H_01H: 1957 mask = 0x1; 1958 break; 1959 /* Events valid only on counter 2. */ 1960 case PMC_EV_IAP_EVENT_48H_01H: 1961 case PMC_EV_IAP_EVENT_A2H_02H: 1962 mask = 0x4; 1963 break; 1964 /* Events valid only on counter 3. */ 1965 case PMC_EV_IAP_EVENT_A3H_08H: 1966 case PMC_EV_IAP_EVENT_BBH_01H: 1967 case PMC_EV_IAP_EVENT_CDH_01H: 1968 case PMC_EV_IAP_EVENT_CDH_02H: 1969 mask = 0x8; 1970 break; 1971 default: 1972 mask = ~0; /* Any row index is ok. */ 1973 } 1974 1975 return (mask & (1 << ri)); 1976} 1977 1978static int 1979iap_event_ok_on_counter(enum pmc_event pe, int ri) 1980{ 1981 uint32_t mask; 1982 1983 switch (pe) { 1984 /* 1985 * Events valid only on counter 0. 1986 */ 1987 case PMC_EV_IAP_EVENT_10H_00H: 1988 case PMC_EV_IAP_EVENT_14H_00H: 1989 case PMC_EV_IAP_EVENT_18H_00H: 1990 case PMC_EV_IAP_EVENT_B3H_01H: 1991 case PMC_EV_IAP_EVENT_B3H_02H: 1992 case PMC_EV_IAP_EVENT_B3H_04H: 1993 case PMC_EV_IAP_EVENT_C1H_00H: 1994 case PMC_EV_IAP_EVENT_CBH_01H: 1995 case PMC_EV_IAP_EVENT_CBH_02H: 1996 mask = (1 << 0); 1997 break; 1998 1999 /* 2000 * Events valid only on counter 1. 2001 */ 2002 case PMC_EV_IAP_EVENT_11H_00H: 2003 case PMC_EV_IAP_EVENT_12H_00H: 2004 case PMC_EV_IAP_EVENT_13H_00H: 2005 mask = (1 << 1); 2006 break; 2007 2008 default: 2009 mask = ~0; /* Any row index is ok. */ 2010 } 2011 2012 return (mask & (1 << ri)); 2013} 2014 2015static int 2016iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2017 const struct pmc_op_pmcallocate *a) 2018{ 2019 int arch, n, model; 2020 enum pmc_event ev, map; 2021 struct iap_event_descr *ie; 2022 uint32_t c, caps, config, cpuflag, evsel, mask; 2023 2024 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2025 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2026 KASSERT(ri >= 0 && ri < core_iap_npmc, 2027 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2028 2029 /* check requested capabilities */ 2030 caps = a->pm_caps; 2031 if ((IAP_PMC_CAPS & caps) != caps) 2032 return (EPERM); 2033 map = 0; /* XXX: silent GCC warning */ 2034 arch = iap_is_event_architectural(pm->pm_event, &map); 2035 if (arch == EV_IS_ARCH_NOTSUPP) 2036 return (EOPNOTSUPP); 2037 else if (arch == EV_IS_ARCH_SUPP) 2038 ev = map; 2039 else 2040 ev = pm->pm_event; 2041 2042 /* 2043 * A small number of events are not supported in all the 2044 * processors based on a given microarchitecture. 2045 */ 2046 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2047 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2048 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2049 return (EINVAL); 2050 } 2051 2052 switch (core_cputype) { 2053 case PMC_CPU_INTEL_COREI7: 2054 case PMC_CPU_INTEL_NEHALEM_EX: 2055 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2056 return (EINVAL); 2057 break; 2058 case PMC_CPU_INTEL_SANDYBRIDGE: 2059 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2060 case PMC_CPU_INTEL_IVYBRIDGE: 2061 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2062 case PMC_CPU_INTEL_HASWELL: 2063 case PMC_CPU_INTEL_HASWELL_XEON: 2064 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2065 return (EINVAL); 2066 break; 2067 case PMC_CPU_INTEL_WESTMERE: 2068 case PMC_CPU_INTEL_WESTMERE_EX: 2069 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2070 return (EINVAL); 2071 break; 2072 default: 2073 if (iap_event_ok_on_counter(ev, ri) == 0) 2074 return (EINVAL); 2075 } 2076 2077 /* 2078 * Look for an event descriptor with matching CPU and event id 2079 * fields. 2080 */ 2081 2082 switch (core_cputype) { 2083 default: 2084 case PMC_CPU_INTEL_ATOM: 2085 cpuflag = IAP_F_CA; 2086 break; 2087 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2088 cpuflag = IAP_F_CAS; 2089 break; 2090 case PMC_CPU_INTEL_CORE: 2091 cpuflag = IAP_F_CC; 2092 break; 2093 case PMC_CPU_INTEL_CORE2: 2094 cpuflag = IAP_F_CC2; 2095 break; 2096 case PMC_CPU_INTEL_CORE2EXTREME: 2097 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2098 break; 2099 case PMC_CPU_INTEL_COREI7: 2100 cpuflag = IAP_F_I7; 2101 break; 2102 case PMC_CPU_INTEL_HASWELL: 2103 cpuflag = IAP_F_HW; 2104 break; 2105 case PMC_CPU_INTEL_HASWELL_XEON: 2106 cpuflag = IAP_F_HWX; 2107 break; 2108 case PMC_CPU_INTEL_IVYBRIDGE: 2109 cpuflag = IAP_F_IB; 2110 break; 2111 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2112 cpuflag = IAP_F_IBX; 2113 break; 2114 case PMC_CPU_INTEL_SANDYBRIDGE: 2115 cpuflag = IAP_F_SB; 2116 break; 2117 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2118 cpuflag = IAP_F_SBX; 2119 break; 2120 case PMC_CPU_INTEL_WESTMERE: 2121 cpuflag = IAP_F_WM; 2122 break; 2123 } 2124 2125 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2126 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2127 break; 2128 2129 if (n == niap_events) 2130 return (EINVAL); 2131 2132 /* 2133 * A matching event descriptor has been found, so start 2134 * assembling the contents of the event select register. 2135 */ 2136 evsel = ie->iap_evcode; 2137 2138 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2139 2140 /* 2141 * If the event uses a fixed umask value, reject any umask 2142 * bits set by the user. 2143 */ 2144 if (ie->iap_flags & IAP_F_FM) { 2145 2146 if (IAP_UMASK(config) != 0) 2147 return (EINVAL); 2148 2149 evsel |= (ie->iap_umask << 8); 2150 2151 } else { 2152 2153 /* 2154 * Otherwise, the UMASK value needs to be taken from 2155 * the MD fields of the allocation request. Reject 2156 * requests that specify reserved bits. 2157 */ 2158 2159 mask = 0; 2160 2161 if (ie->iap_umask & IAP_M_CORE) { 2162 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2163 c != IAP_CORE_THIS) 2164 return (EINVAL); 2165 mask |= IAP_F_CORE; 2166 } 2167 2168 if (ie->iap_umask & IAP_M_AGENT) 2169 mask |= IAP_F_AGENT; 2170 2171 if (ie->iap_umask & IAP_M_PREFETCH) { 2172 2173 if ((c = (config & IAP_F_PREFETCH)) == 2174 IAP_PREFETCH_RESERVED) 2175 return (EINVAL); 2176 2177 mask |= IAP_F_PREFETCH; 2178 } 2179 2180 if (ie->iap_umask & IAP_M_MESI) 2181 mask |= IAP_F_MESI; 2182 2183 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2184 mask |= IAP_F_SNOOPRESPONSE; 2185 2186 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2187 mask |= IAP_F_SNOOPTYPE; 2188 2189 if (ie->iap_umask & IAP_M_TRANSITION) 2190 mask |= IAP_F_TRANSITION; 2191 2192 /* 2193 * If bits outside of the allowed set of umask bits 2194 * are set, reject the request. 2195 */ 2196 if (config & ~mask) 2197 return (EINVAL); 2198 2199 evsel |= (config & mask); 2200 2201 } 2202 2203 /* 2204 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2205 */ 2206 if (core_cputype == PMC_CPU_INTEL_ATOM || 2207 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2208 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2209 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2210 evsel |= (config & IAP_ANY); 2211 else if (config & IAP_ANY) 2212 return (EINVAL); 2213 2214 /* 2215 * Check offcore response configuration. 2216 */ 2217 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2218 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2219 ev != PMC_EV_IAP_EVENT_BBH_01H) 2220 return (EINVAL); 2221 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2222 ev == PMC_EV_IAP_EVENT_BBH_01H) 2223 return (EINVAL); 2224 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2225 core_cputype == PMC_CPU_INTEL_WESTMERE || 2226 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2227 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2228 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2229 return (EINVAL); 2230 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2231 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2232 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2233 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2234 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2235 return (EINVAL); 2236 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2237 } 2238 2239 if (caps & PMC_CAP_THRESHOLD) 2240 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2241 if (caps & PMC_CAP_USER) 2242 evsel |= IAP_USR; 2243 if (caps & PMC_CAP_SYSTEM) 2244 evsel |= IAP_OS; 2245 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2246 evsel |= (IAP_OS | IAP_USR); 2247 if (caps & PMC_CAP_EDGE) 2248 evsel |= IAP_EDGE; 2249 if (caps & PMC_CAP_INVERT) 2250 evsel |= IAP_INV; 2251 if (caps & PMC_CAP_INTERRUPT) 2252 evsel |= IAP_INT; 2253 2254 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2255 2256 return (0); 2257} 2258 2259static int 2260iap_config_pmc(int cpu, int ri, struct pmc *pm) 2261{ 2262 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2263 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2264 2265 KASSERT(ri >= 0 && ri < core_iap_npmc, 2266 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2267 2268 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2269 2270 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2271 cpu)); 2272 2273 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2274 2275 return (0); 2276} 2277 2278static int 2279iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2280{ 2281 int error; 2282 struct pmc_hw *phw; 2283 char iap_name[PMC_NAME_MAX]; 2284 2285 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2286 2287 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2288 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2289 NULL)) != 0) 2290 return (error); 2291 2292 pi->pm_class = PMC_CLASS_IAP; 2293 2294 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2295 pi->pm_enabled = TRUE; 2296 *ppmc = phw->phw_pmc; 2297 } else { 2298 pi->pm_enabled = FALSE; 2299 *ppmc = NULL; 2300 } 2301 2302 return (0); 2303} 2304 2305static int 2306iap_get_config(int cpu, int ri, struct pmc **ppm) 2307{ 2308 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2309 2310 return (0); 2311} 2312 2313static int 2314iap_get_msr(int ri, uint32_t *msr) 2315{ 2316 KASSERT(ri >= 0 && ri < core_iap_npmc, 2317 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2318 2319 *msr = ri; 2320 2321 return (0); 2322} 2323 2324static int 2325iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2326{ 2327 struct pmc *pm; 2328 pmc_value_t tmp; 2329 2330 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2331 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2332 KASSERT(ri >= 0 && ri < core_iap_npmc, 2333 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2334 2335 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2336 2337 KASSERT(pm, 2338 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2339 ri)); 2340 2341 tmp = rdpmc(ri); 2342 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2343 *v = iap_perfctr_value_to_reload_count(tmp); 2344 else 2345 *v = tmp & ((1ULL << core_iap_width) - 1); 2346 2347 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2348 ri, *v); 2349 2350 return (0); 2351} 2352 2353static int 2354iap_release_pmc(int cpu, int ri, struct pmc *pm) 2355{ 2356 (void) pm; 2357 2358 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2359 pm); 2360 2361 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2362 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2363 KASSERT(ri >= 0 && ri < core_iap_npmc, 2364 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2365 2366 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2367 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2368 2369 return (0); 2370} 2371 2372static int 2373iap_start_pmc(int cpu, int ri) 2374{ 2375 struct pmc *pm; 2376 uint32_t evsel; 2377 struct core_cpu *cc; 2378 2379 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2380 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2381 KASSERT(ri >= 0 && ri < core_iap_npmc, 2382 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2383 2384 cc = core_pcpu[cpu]; 2385 pm = cc->pc_corepmcs[ri].phw_pmc; 2386 2387 KASSERT(pm, 2388 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2389 __LINE__, cpu, ri)); 2390 2391 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2392 2393 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2394 2395 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2396 cpu, ri, IAP_EVSEL0 + ri, evsel); 2397 2398 /* Event specific configuration. */ 2399 switch (pm->pm_event) { 2400 case PMC_EV_IAP_EVENT_B7H_01H: 2401 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2402 break; 2403 case PMC_EV_IAP_EVENT_BBH_01H: 2404 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2405 break; 2406 default: 2407 break; 2408 } 2409 2410 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2411 2412 if (core_cputype == PMC_CPU_INTEL_CORE) 2413 return (0); 2414 2415 do { 2416 cc->pc_resync = 0; 2417 cc->pc_globalctrl |= (1ULL << ri); 2418 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2419 } while (cc->pc_resync != 0); 2420 2421 return (0); 2422} 2423 2424static int 2425iap_stop_pmc(int cpu, int ri) 2426{ 2427 struct pmc *pm; 2428 struct core_cpu *cc; 2429 uint64_t msr; 2430 2431 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2432 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2433 KASSERT(ri >= 0 && ri < core_iap_npmc, 2434 ("[core,%d] illegal row index %d", __LINE__, ri)); 2435 2436 cc = core_pcpu[cpu]; 2437 pm = cc->pc_corepmcs[ri].phw_pmc; 2438 2439 KASSERT(pm, 2440 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2441 cpu, ri)); 2442 2443 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2444 2445 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2446 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2447 2448 if (core_cputype == PMC_CPU_INTEL_CORE) 2449 return (0); 2450 2451 msr = 0; 2452 do { 2453 cc->pc_resync = 0; 2454 cc->pc_globalctrl &= ~(1ULL << ri); 2455 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2456 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2457 } while (cc->pc_resync != 0); 2458 2459 return (0); 2460} 2461 2462static int 2463iap_write_pmc(int cpu, int ri, pmc_value_t v) 2464{ 2465 struct pmc *pm; 2466 struct core_cpu *cc; 2467 2468 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2469 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2470 KASSERT(ri >= 0 && ri < core_iap_npmc, 2471 ("[core,%d] illegal row index %d", __LINE__, ri)); 2472 2473 cc = core_pcpu[cpu]; 2474 pm = cc->pc_corepmcs[ri].phw_pmc; 2475 2476 KASSERT(pm, 2477 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2478 cpu, ri)); 2479 2480 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2481 IAP_PMC0 + ri, v); 2482 2483 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2484 v = iap_reload_count_to_perfctr_value(v); 2485 2486 /* 2487 * Write the new value to the counter. The counter will be in 2488 * a stopped state when the pcd_write() entry point is called. 2489 */ 2490 2491 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2492 2493 return (0); 2494} 2495 2496 2497static void 2498iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2499 int flags) 2500{ 2501 struct pmc_classdep *pcd; 2502 2503 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2504 2505 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2506 2507 /* Remember the set of architectural events supported. */ 2508 core_architectural_events = ~flags; 2509 2510 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2511 2512 pcd->pcd_caps = IAP_PMC_CAPS; 2513 pcd->pcd_class = PMC_CLASS_IAP; 2514 pcd->pcd_num = npmc; 2515 pcd->pcd_ri = md->pmd_npmc; 2516 pcd->pcd_width = pmcwidth; 2517 2518 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2519 pcd->pcd_config_pmc = iap_config_pmc; 2520 pcd->pcd_describe = iap_describe; 2521 pcd->pcd_get_config = iap_get_config; 2522 pcd->pcd_get_msr = iap_get_msr; 2523 pcd->pcd_pcpu_fini = core_pcpu_fini; 2524 pcd->pcd_pcpu_init = core_pcpu_init; 2525 pcd->pcd_read_pmc = iap_read_pmc; 2526 pcd->pcd_release_pmc = iap_release_pmc; 2527 pcd->pcd_start_pmc = iap_start_pmc; 2528 pcd->pcd_stop_pmc = iap_stop_pmc; 2529 pcd->pcd_write_pmc = iap_write_pmc; 2530 2531 md->pmd_npmc += npmc; 2532} 2533 2534static int 2535core_intr(int cpu, struct trapframe *tf) 2536{ 2537 pmc_value_t v; 2538 struct pmc *pm; 2539 struct core_cpu *cc; 2540 int error, found_interrupt, ri; 2541 uint64_t msr; 2542 2543 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2544 TRAPF_USERMODE(tf)); 2545 2546 found_interrupt = 0; 2547 cc = core_pcpu[cpu]; 2548 2549 for (ri = 0; ri < core_iap_npmc; ri++) { 2550 2551 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2552 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2553 continue; 2554 2555 if (!iap_pmc_has_overflowed(ri)) 2556 continue; 2557 2558 found_interrupt = 1; 2559 2560 if (pm->pm_state != PMC_STATE_RUNNING) 2561 continue; 2562 2563 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2564 TRAPF_USERMODE(tf)); 2565 2566 v = pm->pm_sc.pm_reloadcount; 2567 v = iaf_reload_count_to_perfctr_value(v); 2568 2569 /* 2570 * Stop the counter, reload it but only restart it if 2571 * the PMC is not stalled. 2572 */ 2573 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2574 wrmsr(IAP_EVSEL0 + ri, msr); 2575 wrmsr(IAP_PMC0 + ri, v); 2576 2577 if (error) 2578 continue; 2579 2580 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2581 IAP_EN)); 2582 } 2583 2584 if (found_interrupt) 2585 lapic_reenable_pmc(); 2586 2587 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2588 &pmc_stats.pm_intr_ignored, 1); 2589 2590 return (found_interrupt); 2591} 2592 2593static int 2594core2_intr(int cpu, struct trapframe *tf) 2595{ 2596 int error, found_interrupt, n; 2597 uint64_t flag, intrstatus, intrenable, msr; 2598 struct pmc *pm; 2599 struct core_cpu *cc; 2600 pmc_value_t v; 2601 2602 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2603 TRAPF_USERMODE(tf)); 2604 2605 /* 2606 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2607 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2608 * the current set of interrupting PMCs and process these 2609 * after stopping them. 2610 */ 2611 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2612 intrenable = intrstatus & core_pmcmask; 2613 2614 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2615 (uintmax_t) intrstatus); 2616 2617 found_interrupt = 0; 2618 cc = core_pcpu[cpu]; 2619 2620 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2621 2622 cc->pc_globalctrl &= ~intrenable; 2623 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2624 2625 /* 2626 * Stop PMCs and clear overflow status bits. 2627 */ 2628 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2629 wrmsr(IA_GLOBAL_CTRL, msr); 2630 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2631 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2632 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2633 2634 /* 2635 * Look for interrupts from fixed function PMCs. 2636 */ 2637 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2638 n++, flag <<= 1) { 2639 2640 if ((intrstatus & flag) == 0) 2641 continue; 2642 2643 found_interrupt = 1; 2644 2645 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2646 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2647 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2648 continue; 2649 2650 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2651 TRAPF_USERMODE(tf)); 2652 if (error) 2653 intrenable &= ~flag; 2654 2655 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2656 2657 /* Reload sampling count. */ 2658 wrmsr(IAF_CTR0 + n, v); 2659 2660 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2661 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2662 } 2663 2664 /* 2665 * Process interrupts from the programmable counters. 2666 */ 2667 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2668 if ((intrstatus & flag) == 0) 2669 continue; 2670 2671 found_interrupt = 1; 2672 2673 pm = cc->pc_corepmcs[n].phw_pmc; 2674 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2675 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2676 continue; 2677 2678 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2679 TRAPF_USERMODE(tf)); 2680 if (error) 2681 intrenable &= ~flag; 2682 2683 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2684 2685 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2686 (uintmax_t) v); 2687 2688 /* Reload sampling count. */ 2689 wrmsr(IAP_PMC0 + n, v); 2690 } 2691 2692 /* 2693 * Reenable all non-stalled PMCs. 2694 */ 2695 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2696 (uintmax_t) intrenable); 2697 2698 cc->pc_globalctrl |= intrenable; 2699 2700 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2701 2702 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2703 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2704 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2705 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2706 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2707 2708 if (found_interrupt) 2709 lapic_reenable_pmc(); 2710 2711 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2712 &pmc_stats.pm_intr_ignored, 1); 2713 2714 return (found_interrupt); 2715} 2716 2717int 2718pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2719{ 2720 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2721 int ipa_version, flags, nflags; 2722 2723 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2724 2725 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2726 2727 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2728 md->pmd_cputype, maxcpu, ipa_version); 2729 2730 if (ipa_version < 1 || ipa_version > 3) { 2731 /* Unknown PMC architecture. */ 2732 printf("hwpc_core: unknown PMC architecture: %d\n", 2733 ipa_version); 2734 return (EPROGMISMATCH); 2735 } 2736 2737 core_cputype = md->pmd_cputype; 2738 2739 core_pmcmask = 0; 2740 2741 /* 2742 * Initialize programmable counters. 2743 */ 2744 KASSERT(ipa_version >= 1, 2745 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2746 2747 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2748 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2749 2750 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2751 2752 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2753 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2754 2755 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2756 2757 /* 2758 * Initialize fixed function counters, if present. 2759 */ 2760 if (core_cputype != PMC_CPU_INTEL_CORE) { 2761 KASSERT(ipa_version >= 2, 2762 ("[core,%d] ipa_version %d too small", __LINE__, 2763 ipa_version)); 2764 2765 core_iaf_ri = core_iap_npmc; 2766 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2767 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2768 2769 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2770 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2771 } 2772 2773 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2774 core_iaf_ri); 2775 2776 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2777 M_ZERO | M_WAITOK); 2778 2779 /* 2780 * Choose the appropriate interrupt handler. 2781 */ 2782 if (ipa_version == 1) 2783 md->pmd_intr = core_intr; 2784 else 2785 md->pmd_intr = core2_intr; 2786 2787 md->pmd_pcpu_fini = NULL; 2788 md->pmd_pcpu_init = NULL; 2789 2790 return (0); 2791} 2792 2793void 2794pmc_core_finalize(struct pmc_mdep *md) 2795{ 2796 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2797 2798 free(core_pcpu, M_PMC); 2799 core_pcpu = NULL; 2800} 2801