si_blit_shaders.c revision 282199 
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *     Alex Deucher <alexander.deucher@amd.com>
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/si_blit_shaders.c 282199 2015-04-28 19:35:05Z dumbbell $");
29
30#include <dev/drm2/drmP.h>
31
32const u32 si_default_state[] =
33{
34	0xc0066900,
35	0x00000000,
36	0x00000060, /* DB_RENDER_CONTROL */
37	0x00000000, /* DB_COUNT_CONTROL */
38	0x00000000, /* DB_DEPTH_VIEW */
39	0x0000002a, /* DB_RENDER_OVERRIDE */
40	0x00000000, /* DB_RENDER_OVERRIDE2 */
41	0x00000000, /* DB_HTILE_DATA_BASE */
42
43	0xc0046900,
44	0x00000008,
45	0x00000000, /* DB_DEPTH_BOUNDS_MIN */
46	0x00000000, /* DB_DEPTH_BOUNDS_MAX */
47	0x00000000, /* DB_STENCIL_CLEAR */
48	0x00000000, /* DB_DEPTH_CLEAR */
49
50	0xc0036900,
51	0x0000000f,
52	0x00000000, /* DB_DEPTH_INFO */
53	0x00000000, /* DB_Z_INFO */
54	0x00000000, /* DB_STENCIL_INFO */
55
56	0xc0016900,
57	0x00000080,
58	0x00000000, /* PA_SC_WINDOW_OFFSET */
59
60	0xc00d6900,
61	0x00000083,
62	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
63	0x00000000, /* PA_SC_CLIPRECT_0_TL */
64	0x20002000, /* PA_SC_CLIPRECT_0_BR */
65	0x00000000,
66	0x20002000,
67	0x00000000,
68	0x20002000,
69	0x00000000,
70	0x20002000,
71	0xaaaaaaaa, /* PA_SC_EDGERULE */
72	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
73	0x0000000f, /* CB_TARGET_MASK */
74	0x0000000f, /* CB_SHADER_MASK */
75
76	0xc0226900,
77	0x00000094,
78	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
79	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
80	0x80000000,
81	0x20002000,
82	0x80000000,
83	0x20002000,
84	0x80000000,
85	0x20002000,
86	0x80000000,
87	0x20002000,
88	0x80000000,
89	0x20002000,
90	0x80000000,
91	0x20002000,
92	0x80000000,
93	0x20002000,
94	0x80000000,
95	0x20002000,
96	0x80000000,
97	0x20002000,
98	0x80000000,
99	0x20002000,
100	0x80000000,
101	0x20002000,
102	0x80000000,
103	0x20002000,
104	0x80000000,
105	0x20002000,
106	0x80000000,
107	0x20002000,
108	0x80000000,
109	0x20002000,
110	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
111	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
112
113	0xc0026900,
114	0x000000d9,
115	0x00000000, /* CP_RINGID */
116	0x00000000, /* CP_VMID */
117
118	0xc0046900,
119	0x00000100,
120	0xffffffff, /* VGT_MAX_VTX_INDX */
121	0x00000000, /* VGT_MIN_VTX_INDX */
122	0x00000000, /* VGT_INDX_OFFSET */
123	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
124
125	0xc0046900,
126	0x00000105,
127	0x00000000, /* CB_BLEND_RED */
128	0x00000000, /* CB_BLEND_GREEN */
129	0x00000000, /* CB_BLEND_BLUE */
130	0x00000000, /* CB_BLEND_ALPHA */
131
132	0xc0016900,
133	0x000001e0,
134	0x00000000, /* CB_BLEND0_CONTROL */
135
136	0xc00e6900,
137	0x00000200,
138	0x00000000, /* DB_DEPTH_CONTROL */
139	0x00000000, /* DB_EQAA */
140	0x00cc0010, /* CB_COLOR_CONTROL */
141	0x00000210, /* DB_SHADER_CONTROL */
142	0x00010000, /* PA_CL_CLIP_CNTL */
143	0x00000004, /* PA_SU_SC_MODE_CNTL */
144	0x00000100, /* PA_CL_VTE_CNTL */
145	0x00000000, /* PA_CL_VS_OUT_CNTL */
146	0x00000000, /* PA_CL_NANINF_CNTL */
147	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
148	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
149	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
150	0x00000000, /*  */
151	0x00000000, /*  */
152
153	0xc0116900,
154	0x00000280,
155	0x00000000, /* PA_SU_POINT_SIZE */
156	0x00000000, /* PA_SU_POINT_MINMAX */
157	0x00000008, /* PA_SU_LINE_CNTL */
158	0x00000000, /* PA_SC_LINE_STIPPLE */
159	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
160	0x00000000, /* VGT_HOS_CNTL */
161	0x00000000,
162	0x00000000,
163	0x00000000,
164	0x00000000,
165	0x00000000,
166	0x00000000,
167	0x00000000,
168	0x00000000,
169	0x00000000,
170	0x00000000,
171	0x00000000, /* VGT_GS_MODE */
172
173	0xc0026900,
174	0x00000292,
175	0x00000000, /* PA_SC_MODE_CNTL_0 */
176	0x00000000, /* PA_SC_MODE_CNTL_1 */
177
178	0xc0016900,
179	0x000002a1,
180	0x00000000, /* VGT_PRIMITIVEID_EN */
181
182	0xc0016900,
183	0x000002a5,
184	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
185
186	0xc0026900,
187	0x000002a8,
188	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
189	0x00000000,
190
191	0xc0026900,
192	0x000002ad,
193	0x00000000, /* VGT_REUSE_OFF */
194	0x00000000,
195
196	0xc0016900,
197	0x000002d5,
198	0x00000000, /* VGT_SHADER_STAGES_EN */
199
200	0xc0016900,
201	0x000002dc,
202	0x0000aa00, /* DB_ALPHA_TO_MASK */
203
204	0xc0066900,
205	0x000002de,
206	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
207	0x00000000,
208	0x00000000,
209	0x00000000,
210	0x00000000,
211	0x00000000,
212
213	0xc0026900,
214	0x000002e5,
215	0x00000000, /* VGT_STRMOUT_CONFIG */
216	0x00000000,
217
218	0xc01b6900,
219	0x000002f5,
220	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
221	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
222	0x00000000, /* PA_SC_LINE_CNTL */
223	0x00000000, /* PA_SC_AA_CONFIG */
224	0x00000005, /* PA_SU_VTX_CNTL */
225	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
226	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
227	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
228	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
229	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
230	0x00000000,
231	0x00000000,
232	0x00000000,
233	0x00000000,
234	0x00000000,
235	0x00000000,
236	0x00000000,
237	0x00000000,
238	0x00000000,
239	0x00000000,
240	0x00000000,
241	0x00000000,
242	0x00000000,
243	0x00000000,
244	0x00000000,
245	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
246	0xffffffff,
247
248	0xc0026900,
249	0x00000316,
250	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
251	0x00000010, /*  */
252};
253
254const u32 si_default_size = ARRAY_SIZE(si_default_state);
255