rs600.c revision 282199
1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28/* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/rs600.c 282199 2015-04-28 19:35:05Z dumbbell $"); 41 42#include <dev/drm2/drmP.h> 43#include "radeon.h" 44#include "radeon_asic.h" 45#include "atom.h" 46#include "rs600d.h" 47 48#include "rs600_reg_safe.h" 49 50static void rs600_gpu_init(struct radeon_device *rdev); 51#ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */ 52int rs600_mc_wait_for_idle(struct radeon_device *rdev); 53#endif 54 55static const u32 crtc_offsets[2] = 56{ 57 0, 58 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 59}; 60 61static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 62{ 63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 64 return true; 65 else 66 return false; 67} 68 69static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 70{ 71 u32 pos1, pos2; 72 73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 75 76 if (pos1 != pos2) 77 return true; 78 else 79 return false; 80} 81 82/** 83 * avivo_wait_for_vblank - vblank wait asic callback. 84 * 85 * @rdev: radeon_device pointer 86 * @crtc: crtc to wait for vblank on 87 * 88 * Wait for vblank on the requested crtc (r5xx-r7xx). 89 */ 90void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 91{ 92 unsigned i = 0; 93 94 if (crtc >= rdev->num_crtc) 95 return; 96 97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 98 return; 99 100 /* depending on when we hit vblank, we may be close to active; if so, 101 * wait for another frame. 102 */ 103 while (avivo_is_in_vblank(rdev, crtc)) { 104 if (i++ % 100 == 0) { 105 if (!avivo_is_counter_moving(rdev, crtc)) 106 break; 107 } 108 } 109 110 while (!avivo_is_in_vblank(rdev, crtc)) { 111 if (i++ % 100 == 0) { 112 if (!avivo_is_counter_moving(rdev, crtc)) 113 break; 114 } 115 } 116} 117 118void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 119{ 120 /* enable the pflip int */ 121 radeon_irq_kms_pflip_irq_get(rdev, crtc); 122} 123 124void rs600_post_page_flip(struct radeon_device *rdev, int crtc) 125{ 126 /* disable the pflip int */ 127 radeon_irq_kms_pflip_irq_put(rdev, crtc); 128} 129 130u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 131{ 132 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 133 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 134 int i; 135 136 /* Lock the graphics update lock */ 137 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 138 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 139 140 /* update the scanout addresses */ 141 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 142 (u32)crtc_base); 143 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 144 (u32)crtc_base); 145 146 /* Wait for update_pending to go high. */ 147 for (i = 0; i < rdev->usec_timeout; i++) { 148 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 149 break; 150 udelay(1); 151 } 152 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 153 154 /* Unlock the lock, so double-buffering can take place inside vblank */ 155 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 156 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 157 158 /* Return current update_pending status: */ 159 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 160} 161 162void rs600_pm_misc(struct radeon_device *rdev) 163{ 164 int requested_index = rdev->pm.requested_power_state_index; 165 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 166 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 167 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 168 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 169 170 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 171 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 172 tmp = RREG32(voltage->gpio.reg); 173 if (voltage->active_high) 174 tmp |= voltage->gpio.mask; 175 else 176 tmp &= ~(voltage->gpio.mask); 177 WREG32(voltage->gpio.reg, tmp); 178 if (voltage->delay) 179 udelay(voltage->delay); 180 } else { 181 tmp = RREG32(voltage->gpio.reg); 182 if (voltage->active_high) 183 tmp &= ~voltage->gpio.mask; 184 else 185 tmp |= voltage->gpio.mask; 186 WREG32(voltage->gpio.reg, tmp); 187 if (voltage->delay) 188 udelay(voltage->delay); 189 } 190 } else if (voltage->type == VOLTAGE_VDDC) 191 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 192 193 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 194 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 195 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 196 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 197 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 198 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 199 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 200 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 201 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 202 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 203 } 204 } else { 205 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 206 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 207 } 208 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 209 210 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 211 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 212 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 213 if (voltage->delay) { 214 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 215 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 216 } else 217 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 218 } else 219 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 220 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 221 222 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 223 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 224 hdp_dyn_cntl &= ~HDP_FORCEON; 225 else 226 hdp_dyn_cntl |= HDP_FORCEON; 227 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 228#if 0 229 /* mc_host_dyn seems to cause hangs from time to time */ 230 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 231 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 232 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 233 else 234 mc_host_dyn_cntl |= MC_HOST_FORCEON; 235 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 236#endif 237 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 238 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 239 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 240 else 241 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 242 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 243 244 /* set pcie lanes */ 245 if ((rdev->flags & RADEON_IS_PCIE) && 246 !(rdev->flags & RADEON_IS_IGP) && 247 rdev->asic->pm.set_pcie_lanes && 248 (ps->pcie_lanes != 249 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 250 radeon_set_pcie_lanes(rdev, 251 ps->pcie_lanes); 252 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 253 } 254} 255 256void rs600_pm_prepare(struct radeon_device *rdev) 257{ 258 struct drm_device *ddev = rdev->ddev; 259 struct drm_crtc *crtc; 260 struct radeon_crtc *radeon_crtc; 261 u32 tmp; 262 263 /* disable any active CRTCs */ 264 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 265 radeon_crtc = to_radeon_crtc(crtc); 266 if (radeon_crtc->enabled) { 267 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 268 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 269 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 270 } 271 } 272} 273 274void rs600_pm_finish(struct radeon_device *rdev) 275{ 276 struct drm_device *ddev = rdev->ddev; 277 struct drm_crtc *crtc; 278 struct radeon_crtc *radeon_crtc; 279 u32 tmp; 280 281 /* enable any active CRTCs */ 282 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 283 radeon_crtc = to_radeon_crtc(crtc); 284 if (radeon_crtc->enabled) { 285 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 286 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 287 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 288 } 289 } 290} 291 292/* hpd for digital panel detect/disconnect */ 293bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 294{ 295 u32 tmp; 296 bool connected = false; 297 298 switch (hpd) { 299 case RADEON_HPD_1: 300 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 301 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 302 connected = true; 303 break; 304 case RADEON_HPD_2: 305 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 306 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 307 connected = true; 308 break; 309 default: 310 break; 311 } 312 return connected; 313} 314 315void rs600_hpd_set_polarity(struct radeon_device *rdev, 316 enum radeon_hpd_id hpd) 317{ 318 u32 tmp; 319 bool connected = rs600_hpd_sense(rdev, hpd); 320 321 switch (hpd) { 322 case RADEON_HPD_1: 323 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 324 if (connected) 325 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 326 else 327 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 328 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 329 break; 330 case RADEON_HPD_2: 331 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 332 if (connected) 333 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 334 else 335 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 336 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 337 break; 338 default: 339 break; 340 } 341} 342 343void rs600_hpd_init(struct radeon_device *rdev) 344{ 345 struct drm_device *dev = rdev->ddev; 346 struct drm_connector *connector; 347 unsigned enable = 0; 348 349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 350 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 351 switch (radeon_connector->hpd.hpd) { 352 case RADEON_HPD_1: 353 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 354 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 355 break; 356 case RADEON_HPD_2: 357 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 358 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 359 break; 360 default: 361 break; 362 } 363 enable |= 1 << radeon_connector->hpd.hpd; 364 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 365 } 366 radeon_irq_kms_enable_hpd(rdev, enable); 367} 368 369void rs600_hpd_fini(struct radeon_device *rdev) 370{ 371 struct drm_device *dev = rdev->ddev; 372 struct drm_connector *connector; 373 unsigned disable = 0; 374 375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 376 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 377 switch (radeon_connector->hpd.hpd) { 378 case RADEON_HPD_1: 379 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 380 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 381 break; 382 case RADEON_HPD_2: 383 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 384 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 385 break; 386 default: 387 break; 388 } 389 disable |= 1 << radeon_connector->hpd.hpd; 390 } 391 radeon_irq_kms_disable_hpd(rdev, disable); 392} 393 394int rs600_asic_reset(struct radeon_device *rdev) 395{ 396 struct rv515_mc_save save; 397 u32 status, tmp; 398 int ret = 0; 399 400 status = RREG32(R_000E40_RBBM_STATUS); 401 if (!G_000E40_GUI_ACTIVE(status)) { 402 return 0; 403 } 404 /* Stops all mc clients */ 405 rv515_mc_stop(rdev, &save); 406 status = RREG32(R_000E40_RBBM_STATUS); 407 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 408 /* stop CP */ 409 WREG32(RADEON_CP_CSQ_CNTL, 0); 410 tmp = RREG32(RADEON_CP_RB_CNTL); 411 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 412 WREG32(RADEON_CP_RB_RPTR_WR, 0); 413 WREG32(RADEON_CP_RB_WPTR, 0); 414 WREG32(RADEON_CP_RB_CNTL, tmp); 415 pci_save_state(device_get_parent(rdev->dev)); 416 /* disable bus mastering */ 417 pci_disable_busmaster(rdev->dev); 418 mdelay(1); 419 /* reset GA+VAP */ 420 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 421 S_0000F0_SOFT_RESET_GA(1)); 422 RREG32(R_0000F0_RBBM_SOFT_RESET); 423 mdelay(500); 424 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 425 mdelay(1); 426 status = RREG32(R_000E40_RBBM_STATUS); 427 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 428 /* reset CP */ 429 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 430 RREG32(R_0000F0_RBBM_SOFT_RESET); 431 mdelay(500); 432 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 433 mdelay(1); 434 status = RREG32(R_000E40_RBBM_STATUS); 435 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 436 /* reset MC */ 437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 438 RREG32(R_0000F0_RBBM_SOFT_RESET); 439 mdelay(500); 440 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 441 mdelay(1); 442 status = RREG32(R_000E40_RBBM_STATUS); 443 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 444 /* restore PCI & busmastering */ 445 pci_restore_state(device_get_parent(rdev->dev)); 446 /* Check if GPU is idle */ 447 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 448 dev_err(rdev->dev, "failed to reset GPU\n"); 449 ret = -1; 450 } else 451 dev_info(rdev->dev, "GPU reset succeed\n"); 452 rv515_mc_resume(rdev, &save); 453 return ret; 454} 455 456/* 457 * GART. 458 */ 459void rs600_gart_tlb_flush(struct radeon_device *rdev) 460{ 461 uint32_t tmp; 462 463 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 464 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 465 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 466 467 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 468 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 469 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 470 471 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 472 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 473 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 474 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 475} 476 477static int rs600_gart_init(struct radeon_device *rdev) 478{ 479 int r; 480 481 if (rdev->gart.robj) { 482 DRM_ERROR("RS600 GART already initialized\n"); 483 return 0; 484 } 485 /* Initialize common gart structure */ 486 r = radeon_gart_init(rdev); 487 if (r) { 488 return r; 489 } 490 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 491 return radeon_gart_table_vram_alloc(rdev); 492} 493 494static int rs600_gart_enable(struct radeon_device *rdev) 495{ 496 u32 tmp; 497 int r, i; 498 499 if (rdev->gart.robj == NULL) { 500 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 501 return -EINVAL; 502 } 503 r = radeon_gart_table_vram_pin(rdev); 504 if (r) 505 return r; 506 radeon_gart_restore(rdev); 507 /* Enable bus master */ 508 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 509 WREG32(RADEON_BUS_CNTL, tmp); 510 /* FIXME: setup default page */ 511 WREG32_MC(R_000100_MC_PT0_CNTL, 512 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 513 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 514 515 for (i = 0; i < 19; i++) { 516 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 517 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 518 S_00016C_SYSTEM_ACCESS_MODE_MASK( 519 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 520 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 521 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 522 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 523 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 524 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 525 } 526 /* enable first context */ 527 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 528 S_000102_ENABLE_PAGE_TABLE(1) | 529 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 530 531 /* disable all other contexts */ 532 for (i = 1; i < 8; i++) 533 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 534 535 /* setup the page table */ 536 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 537 rdev->gart.table_addr); 538 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 539 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 540 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 541 542 /* System context maps to VRAM space */ 543 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 544 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 545 546 /* enable page tables */ 547 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 548 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 549 tmp = RREG32_MC(R_000009_MC_CNTL1); 550 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 551 rs600_gart_tlb_flush(rdev); 552 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 553 (unsigned)(rdev->mc.gtt_size >> 20), 554 (unsigned long long)rdev->gart.table_addr); 555 rdev->gart.ready = true; 556 return 0; 557} 558 559static void rs600_gart_disable(struct radeon_device *rdev) 560{ 561 u32 tmp; 562 563 /* FIXME: disable out of gart access */ 564 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 565 tmp = RREG32_MC(R_000009_MC_CNTL1); 566 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 567 radeon_gart_table_vram_unpin(rdev); 568} 569 570static void rs600_gart_fini(struct radeon_device *rdev) 571{ 572 radeon_gart_fini(rdev); 573 rs600_gart_disable(rdev); 574 radeon_gart_table_vram_free(rdev); 575} 576 577#define R600_PTE_VALID (1 << 0) 578#define R600_PTE_SYSTEM (1 << 1) 579#define R600_PTE_SNOOPED (1 << 2) 580#define R600_PTE_READABLE (1 << 5) 581#define R600_PTE_WRITEABLE (1 << 6) 582 583int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 584{ 585 uint64_t *ptr = rdev->gart.ptr; 586 587 if (i < 0 || i > rdev->gart.num_gpu_pages) { 588 return -EINVAL; 589 } 590 addr = addr & 0xFFFFFFFFFFFFF000ULL; 591 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 592 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 593 ptr[i] = addr; 594 return 0; 595} 596 597int rs600_irq_set(struct radeon_device *rdev) 598{ 599 uint32_t tmp = 0; 600 uint32_t mode_int = 0; 601 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 602 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 603 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 604 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 605 u32 hdmi0; 606 if (ASIC_IS_DCE2(rdev)) 607 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 608 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 609 else 610 hdmi0 = 0; 611 612 if (!rdev->irq.installed) { 613 DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 614 WREG32(R_000040_GEN_INT_CNTL, 0); 615 return -EINVAL; 616 } 617 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 618 tmp |= S_000040_SW_INT_EN(1); 619 } 620 if (rdev->irq.crtc_vblank_int[0] || 621 atomic_read(&rdev->irq.pflip[0])) { 622 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 623 } 624 if (rdev->irq.crtc_vblank_int[1] || 625 atomic_read(&rdev->irq.pflip[1])) { 626 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 627 } 628 if (rdev->irq.hpd[0]) { 629 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 630 } 631 if (rdev->irq.hpd[1]) { 632 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 633 } 634 if (rdev->irq.afmt[0]) { 635 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 636 } 637 WREG32(R_000040_GEN_INT_CNTL, tmp); 638 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 639 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 640 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 641 if (ASIC_IS_DCE2(rdev)) 642 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 643 return 0; 644} 645 646static inline u32 rs600_irq_ack(struct radeon_device *rdev) 647{ 648 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 649 uint32_t irq_mask = S_000044_SW_INT(1); 650 u32 tmp; 651 652 if (G_000044_DISPLAY_INT_STAT(irqs)) { 653 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 654 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 655 WREG32(R_006534_D1MODE_VBLANK_STATUS, 656 S_006534_D1MODE_VBLANK_ACK(1)); 657 } 658 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 659 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 660 S_006D34_D2MODE_VBLANK_ACK(1)); 661 } 662 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 663 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 664 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 665 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 666 } 667 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 668 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 669 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 670 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 671 } 672 } else { 673 rdev->irq.stat_regs.r500.disp_int = 0; 674 } 675 676 if (ASIC_IS_DCE2(rdev)) { 677 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 678 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 679 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 680 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 681 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 682 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 683 } 684 } else 685 rdev->irq.stat_regs.r500.hdmi0_status = 0; 686 687 if (irqs) { 688 WREG32(R_000044_GEN_INT_STATUS, irqs); 689 } 690 return irqs & irq_mask; 691} 692 693void rs600_irq_disable(struct radeon_device *rdev) 694{ 695 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 696 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 697 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 698 WREG32(R_000040_GEN_INT_CNTL, 0); 699 WREG32(R_006540_DxMODE_INT_MASK, 0); 700 /* Wait and acknowledge irq */ 701 mdelay(1); 702 rs600_irq_ack(rdev); 703} 704 705irqreturn_t rs600_irq_process(struct radeon_device *rdev) 706{ 707 u32 status, msi_rearm; 708 bool queue_hotplug = false; 709 bool queue_hdmi = false; 710 711 status = rs600_irq_ack(rdev); 712 if (!status && 713 !rdev->irq.stat_regs.r500.disp_int && 714 !rdev->irq.stat_regs.r500.hdmi0_status) { 715 return IRQ_NONE; 716 } 717 while (status || 718 rdev->irq.stat_regs.r500.disp_int || 719 rdev->irq.stat_regs.r500.hdmi0_status) { 720 /* SW interrupt */ 721 if (G_000044_SW_INT(status)) { 722 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 723 } 724 /* Vertical blank interrupts */ 725 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 726 if (rdev->irq.crtc_vblank_int[0]) { 727 drm_handle_vblank(rdev->ddev, 0); 728 rdev->pm.vblank_sync = true; 729 DRM_WAKEUP(&rdev->irq.vblank_queue); 730 } 731 if (atomic_read(&rdev->irq.pflip[0])) 732 radeon_crtc_handle_flip(rdev, 0); 733 } 734 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 735 if (rdev->irq.crtc_vblank_int[1]) { 736 drm_handle_vblank(rdev->ddev, 1); 737 rdev->pm.vblank_sync = true; 738 DRM_WAKEUP(&rdev->irq.vblank_queue); 739 } 740 if (atomic_read(&rdev->irq.pflip[1])) 741 radeon_crtc_handle_flip(rdev, 1); 742 } 743 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 744 queue_hotplug = true; 745 DRM_DEBUG("HPD1\n"); 746 } 747 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 748 queue_hotplug = true; 749 DRM_DEBUG("HPD2\n"); 750 } 751 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 752 queue_hdmi = true; 753 DRM_DEBUG("HDMI0\n"); 754 } 755 status = rs600_irq_ack(rdev); 756 } 757 if (queue_hotplug) 758 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 759 if (queue_hdmi) 760 taskqueue_enqueue(rdev->tq, &rdev->audio_work); 761 if (rdev->msi_enabled) { 762 switch (rdev->family) { 763 case CHIP_RS600: 764 case CHIP_RS690: 765 case CHIP_RS740: 766 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 767 WREG32(RADEON_BUS_CNTL, msi_rearm); 768 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 769 break; 770 default: 771 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 772 break; 773 } 774 } 775 return IRQ_HANDLED; 776} 777 778u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 779{ 780 if (crtc == 0) 781 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 782 else 783 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 784} 785 786int rs600_mc_wait_for_idle(struct radeon_device *rdev) 787{ 788 unsigned i; 789 790 for (i = 0; i < rdev->usec_timeout; i++) { 791 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 792 return 0; 793 udelay(1); 794 } 795 return -1; 796} 797 798static void rs600_gpu_init(struct radeon_device *rdev) 799{ 800 r420_pipes_init(rdev); 801 /* Wait for mc idle */ 802 if (rs600_mc_wait_for_idle(rdev)) 803 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 804} 805 806static void rs600_mc_init(struct radeon_device *rdev) 807{ 808 u64 base; 809 810 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 811 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 812 rdev->mc.vram_is_ddr = true; 813 rdev->mc.vram_width = 128; 814 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 815 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 816 rdev->mc.visible_vram_size = rdev->mc.aper_size; 817 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 818 base = RREG32_MC(R_000004_MC_FB_LOCATION); 819 base = G_000004_MC_FB_START(base) << 16; 820 radeon_vram_location(rdev, &rdev->mc, base); 821 rdev->mc.gtt_base_align = 0; 822 radeon_gtt_location(rdev, &rdev->mc); 823 radeon_update_bandwidth_info(rdev); 824} 825 826void rs600_bandwidth_update(struct radeon_device *rdev) 827{ 828 struct drm_display_mode *mode0 = NULL; 829 struct drm_display_mode *mode1 = NULL; 830 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 831 /* FIXME: implement full support */ 832 833 radeon_update_display_priority(rdev); 834 835 if (rdev->mode_info.crtcs[0]->base.enabled) 836 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 837 if (rdev->mode_info.crtcs[1]->base.enabled) 838 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 839 840 rs690_line_buffer_adjust(rdev, mode0, mode1); 841 842 if (rdev->disp_priority == 2) { 843 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 844 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 845 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 846 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 847 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 848 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 849 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 850 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 851 } 852} 853 854uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 855{ 856 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 857 S_000070_MC_IND_CITF_ARB0(1)); 858 return RREG32(R_000074_MC_IND_DATA); 859} 860 861void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 862{ 863 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 864 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 865 WREG32(R_000074_MC_IND_DATA, v); 866} 867 868static void rs600_debugfs(struct radeon_device *rdev) 869{ 870 if (r100_debugfs_rbbm_init(rdev)) 871 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 872} 873 874void rs600_set_safe_registers(struct radeon_device *rdev) 875{ 876 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 877 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 878} 879 880static void rs600_mc_program(struct radeon_device *rdev) 881{ 882 struct rv515_mc_save save; 883 884 /* Stops all mc clients */ 885 rv515_mc_stop(rdev, &save); 886 887 /* Wait for mc idle */ 888 if (rs600_mc_wait_for_idle(rdev)) 889 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 890 891 /* FIXME: What does AGP means for such chipset ? */ 892 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 893 WREG32_MC(R_000006_AGP_BASE, 0); 894 WREG32_MC(R_000007_AGP_BASE_2, 0); 895 /* Program MC */ 896 WREG32_MC(R_000004_MC_FB_LOCATION, 897 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 898 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 899 WREG32(R_000134_HDP_FB_LOCATION, 900 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 901 902 rv515_mc_resume(rdev, &save); 903} 904 905static int rs600_startup(struct radeon_device *rdev) 906{ 907 int r; 908 909 rs600_mc_program(rdev); 910 /* Resume clock */ 911 rv515_clock_startup(rdev); 912 /* Initialize GPU configuration (# pipes, ...) */ 913 rs600_gpu_init(rdev); 914 /* Initialize GART (initialize after TTM so we can allocate 915 * memory through TTM but finalize after TTM) */ 916 r = rs600_gart_enable(rdev); 917 if (r) 918 return r; 919 920 /* allocate wb buffer */ 921 r = radeon_wb_init(rdev); 922 if (r) 923 return r; 924 925 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 926 if (r) { 927 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 928 return r; 929 } 930 931 /* Enable IRQ */ 932 rs600_irq_set(rdev); 933 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 934 /* 1M ring buffer */ 935 r = r100_cp_init(rdev, 1024 * 1024); 936 if (r) { 937 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 938 return r; 939 } 940 941 r = radeon_ib_pool_init(rdev); 942 if (r) { 943 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 944 return r; 945 } 946 947 r = r600_audio_init(rdev); 948 if (r) { 949 dev_err(rdev->dev, "failed initializing audio\n"); 950 return r; 951 } 952 953 return 0; 954} 955 956int rs600_resume(struct radeon_device *rdev) 957{ 958 int r; 959 960 /* Make sur GART are not working */ 961 rs600_gart_disable(rdev); 962 /* Resume clock before doing reset */ 963 rv515_clock_startup(rdev); 964 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 965 if (radeon_asic_reset(rdev)) { 966 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 967 RREG32(R_000E40_RBBM_STATUS), 968 RREG32(R_0007C0_CP_STAT)); 969 } 970 /* post */ 971 atom_asic_init(rdev->mode_info.atom_context); 972 /* Resume clock after posting */ 973 rv515_clock_startup(rdev); 974 /* Initialize surface registers */ 975 radeon_surface_init(rdev); 976 977 rdev->accel_working = true; 978 r = rs600_startup(rdev); 979 if (r) { 980 rdev->accel_working = false; 981 } 982 return r; 983} 984 985int rs600_suspend(struct radeon_device *rdev) 986{ 987 r600_audio_fini(rdev); 988 r100_cp_disable(rdev); 989 radeon_wb_disable(rdev); 990 rs600_irq_disable(rdev); 991 rs600_gart_disable(rdev); 992 return 0; 993} 994 995void rs600_fini(struct radeon_device *rdev) 996{ 997 r600_audio_fini(rdev); 998 r100_cp_fini(rdev); 999 radeon_wb_fini(rdev); 1000 radeon_ib_pool_fini(rdev); 1001 radeon_gem_fini(rdev); 1002 rs600_gart_fini(rdev); 1003 radeon_irq_kms_fini(rdev); 1004 radeon_fence_driver_fini(rdev); 1005 radeon_bo_fini(rdev); 1006 radeon_atombios_fini(rdev); 1007 free(rdev->bios, DRM_MEM_DRIVER); 1008 rdev->bios = NULL; 1009} 1010 1011int rs600_init(struct radeon_device *rdev) 1012{ 1013 int r; 1014 1015 /* Disable VGA */ 1016 rv515_vga_render_disable(rdev); 1017 /* Initialize scratch registers */ 1018 radeon_scratch_init(rdev); 1019 /* Initialize surface registers */ 1020 radeon_surface_init(rdev); 1021 /* restore some register to sane defaults */ 1022 r100_restore_sanity(rdev); 1023 /* BIOS */ 1024 if (!radeon_get_bios(rdev)) { 1025 if (ASIC_IS_AVIVO(rdev)) 1026 return -EINVAL; 1027 } 1028 if (rdev->is_atom_bios) { 1029 r = radeon_atombios_init(rdev); 1030 if (r) 1031 return r; 1032 } else { 1033 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1034 return -EINVAL; 1035 } 1036 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1037 if (radeon_asic_reset(rdev)) { 1038 dev_warn(rdev->dev, 1039 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1040 RREG32(R_000E40_RBBM_STATUS), 1041 RREG32(R_0007C0_CP_STAT)); 1042 } 1043 /* check if cards are posted or not */ 1044 if (radeon_boot_test_post_card(rdev) == false) 1045 return -EINVAL; 1046 1047 /* Initialize clocks */ 1048 radeon_get_clock_info(rdev->ddev); 1049 /* initialize memory controller */ 1050 rs600_mc_init(rdev); 1051 rs600_debugfs(rdev); 1052 /* Fence driver */ 1053 r = radeon_fence_driver_init(rdev); 1054 if (r) 1055 return r; 1056 r = radeon_irq_kms_init(rdev); 1057 if (r) 1058 return r; 1059 /* Memory manager */ 1060 r = radeon_bo_init(rdev); 1061 if (r) 1062 return r; 1063 r = rs600_gart_init(rdev); 1064 if (r) 1065 return r; 1066 rs600_set_safe_registers(rdev); 1067 1068 rdev->accel_working = true; 1069 r = rs600_startup(rdev); 1070 if (r) { 1071 /* Somethings want wront with the accel init stop accel */ 1072 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1073 r100_cp_fini(rdev); 1074 radeon_wb_fini(rdev); 1075 radeon_ib_pool_fini(rdev); 1076 rs600_gart_fini(rdev); 1077 radeon_irq_kms_fini(rdev); 1078 rdev->accel_working = false; 1079 } 1080 return 0; 1081} 1082