r420.c revision 282199
11553Srgrimes/* 21553Srgrimes * Copyright 2008 Advanced Micro Devices, Inc. 31553Srgrimes * Copyright 2008 Red Hat Inc. 41553Srgrimes * Copyright 2009 Jerome Glisse. 51553Srgrimes * 61553Srgrimes * Permission is hereby granted, free of charge, to any person obtaining a 71553Srgrimes * copy of this software and associated documentation files (the "Software"), 81553Srgrimes * to deal in the Software without restriction, including without limitation 91553Srgrimes * the rights to use, copy, modify, merge, publish, distribute, sublicense, 101553Srgrimes * and/or sell copies of the Software, and to permit persons to whom the 111553Srgrimes * Software is furnished to do so, subject to the following conditions: 121553Srgrimes * 13121300Sphk * The above copyright notice and this permission notice shall be included in 141553Srgrimes * all copies or substantial portions of the Software. 151553Srgrimes * 161553Srgrimes * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 171553Srgrimes * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 181553Srgrimes * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 191553Srgrimes * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 201553Srgrimes * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 211553Srgrimes * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 221553Srgrimes * OTHER DEALINGS IN THE SOFTWARE. 231553Srgrimes * 241553Srgrimes * Authors: Dave Airlie 251553Srgrimes * Alex Deucher 261553Srgrimes * Jerome Glisse 271553Srgrimes */ 281553Srgrimes 291553Srgrimes#include <sys/cdefs.h> 30114601Sobrien__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/r420.c 282199 2015-04-28 19:35:05Z dumbbell $"); 311553Srgrimes 321553Srgrimes#include <dev/drm2/drmP.h> 33114601Sobrien#include "radeon_reg.h" 3430027Scharnier#include "radeon.h" 35114601Sobrien#include "radeon_asic.h" 36114601Sobrien#include "atom.h" 371553Srgrimes#include "r100d.h" 381553Srgrimes#include "r420d.h" 391553Srgrimes#include "r420_reg_safe.h" 4030027Scharnier 4130027Scharniervoid r420_pm_init_profile(struct radeon_device *rdev) 4230027Scharnier{ 431553Srgrimes /* default */ 441553Srgrimes rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 451553Srgrimes rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 4644303Swollman rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 4730027Scharnier rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 4844303Swollman /* low sh */ 4944303Swollman rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 5044303Swollman rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 5144303Swollman rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 5244303Swollman rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 5344303Swollman /* mid sh */ 5444303Swollman rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 55144295Stobez rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 56144295Stobez rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 57144295Stobez rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 581553Srgrimes /* high sh */ 59100070Sdes rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 6030027Scharnier rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 6130027Scharnier rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 621553Srgrimes rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 6342561Sjkoshy /* low mh */ 641553Srgrimes rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 651553Srgrimes rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 661553Srgrimes rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 671553Srgrimes rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 681553Srgrimes /* mid mh */ 691553Srgrimes rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 701553Srgrimes rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 711553Srgrimes rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 721553Srgrimes rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 7366584Sphk /* high mh */ 741553Srgrimes rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 75103726Swollman rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 7699800Salfred rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 7799800Salfred rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 7899800Salfred} 791553Srgrimes 801553Srgrimesstatic void r420_set_reg_safe(struct radeon_device *rdev) 81121299Sphk{ 821553Srgrimes rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 83121299Sphk rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 84121299Sphk} 8599802Salfred 861553Srgrimesvoid r420_pipes_init(struct radeon_device *rdev) 8799802Salfred{ 882860Srgrimes unsigned tmp; 891553Srgrimes unsigned gb_pipe_select; 90124265Sphk unsigned num_pipes; 91124265Sphk 92124265Sphk /* GA_ENHANCE workaround TCL deadlock issue */ 93124265Sphk WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 94124265Sphk (1 << 2) | (1 << 3)); 95124265Sphk /* add idle wait as per freedesktop.org bug 24041 */ 96124265Sphk if (r100_gui_wait_for_idle(rdev)) { 97124265Sphk DRM_ERROR("Failed to wait GUI idle while " 98124265Sphk "programming pipes. Bad things might happen.\n"); 99124265Sphk } 1001553Srgrimes /* get max number of pipes */ 10199802Salfred gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 1021553Srgrimes num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 1031553Srgrimes 104124389Sphk /* SE chips have 1 pipe */ 1052860Srgrimes if ((rdev->ddev->pci_device == 0x5e4c) || 1062860Srgrimes (rdev->ddev->pci_device == 0x5e4f)) 1072860Srgrimes num_pipes = 1; 10860418Swollman 10960418Swollman rdev->num_gb_pipes = num_pipes; 11060418Swollman tmp = 0; 11160418Swollman switch (num_pipes) { 1121553Srgrimes default: 1131553Srgrimes /* force to 1 pipe */ 1142860Srgrimes num_pipes = 1; 1152860Srgrimes case 1: 1162860Srgrimes tmp = (0 << 1); 1172860Srgrimes break; 11854375Sjoe case 2: 1192860Srgrimes tmp = (3 << 1); 1201553Srgrimes break; 1211553Srgrimes case 3: 1222860Srgrimes tmp = (6 << 1); 1232860Srgrimes break; 1242860Srgrimes case 4: 1252860Srgrimes tmp = (7 << 1); 1262860Srgrimes break; 1271553Srgrimes } 1281553Srgrimes WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 1291553Srgrimes /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 1301553Srgrimes tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 13130027Scharnier WREG32(R300_GB_TILE_CONFIG, tmp); 1321553Srgrimes if (r100_gui_wait_for_idle(rdev)) { 1331553Srgrimes DRM_ERROR("Failed to wait GUI idle while " 1341553Srgrimes "programming pipes. Bad things might happen.\n"); 1352860Srgrimes } 1361553Srgrimes 1378857Srgrimes tmp = RREG32(R300_DST_PIPE_CONFIG); 1381553Srgrimes WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 1392860Srgrimes 1401553Srgrimes WREG32(R300_RB2D_DSTCACHE_MODE, 1411553Srgrimes RREG32(R300_RB2D_DSTCACHE_MODE) | 142112214Srobert R300_DC_AUTOFLUSH_ENABLE | 1431553Srgrimes R300_DC_DC_DISABLE_IGNORE_PE); 1441553Srgrimes 1451553Srgrimes if (r100_gui_wait_for_idle(rdev)) { 146121299Sphk DRM_ERROR("Failed to wait GUI idle while " 1471553Srgrimes "programming pipes. Bad things might happen.\n"); 1481553Srgrimes } 1491553Srgrimes 150112214Srobert if (rdev->family == CHIP_RV530) { 151112214Srobert tmp = RREG32(RV530_GB_PIPE_SELECT2); 1522860Srgrimes if ((tmp & 3) == 3) 15361749Sjoe rdev->num_z_pipes = 2; 15442561Sjkoshy else 1551553Srgrimes rdev->num_z_pipes = 1; 15642561Sjkoshy } else 15742561Sjkoshy rdev->num_z_pipes = 1; 15842561Sjkoshy 159121731Sphk DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 16042561Sjkoshy rdev->num_gb_pipes, rdev->num_z_pipes); 1612860Srgrimes} 16242561Sjkoshy 1631553Srgrimesu32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 16442561Sjkoshy{ 165121300Sphk u32 r; 16642561Sjkoshy 1671553Srgrimes WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 1682860Srgrimes r = RREG32(R_0001FC_MC_IND_DATA); 1692860Srgrimes return r; 1701553Srgrimes} 1712860Srgrimes 1721553Srgrimesvoid r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1732860Srgrimes{ 1742860Srgrimes WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 1752860Srgrimes S_0001F8_MC_IND_WR_EN(1)); 1762860Srgrimes WREG32(R_0001FC_MC_IND_DATA, v); 177124389Sphk} 178124389Sphk 179124389Sphkstatic void r420_debugfs(struct radeon_device *rdev) 180124389Sphk{ 181124389Sphk if (r100_debugfs_rbbm_init(rdev)) { 182124389Sphk DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 183124389Sphk } 18430027Scharnier if (r420_debugfs_pipes_info_init(rdev)) { 185124389Sphk DRM_ERROR("Failed to register debugfs file for pipes !\n"); 186124389Sphk } 1872860Srgrimes} 1882860Srgrimes 1892860Srgrimesstatic void r420_clock_resume(struct radeon_device *rdev) 1902860Srgrimes{ 1912860Srgrimes u32 sclk_cntl; 1922860Srgrimes 193124389Sphk if (radeon_dynclks != -1 && radeon_dynclks) 194124389Sphk radeon_atom_set_clock_gating(rdev, 1); 195124389Sphk sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 196124389Sphk sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 197124389Sphk if (rdev->family == CHIP_R420) 198124389Sphk sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 199124389Sphk WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 20030027Scharnier} 201124389Sphk 202124389Sphkstatic void r420_cp_errata_init(struct radeon_device *rdev) 2032860Srgrimes{ 2042860Srgrimes struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2052860Srgrimes 2062860Srgrimes /* RV410 and R420 can lock up if CP DMA to host memory happens 2071553Srgrimes * while the 2D engine is busy. 2082860Srgrimes * 2091553Srgrimes * The proper workaround is to queue a RESYNC at the beginning 2102860Srgrimes * of the CP init, apparently. 211255483Sdelphij */ 212100070Sdes radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 213100070Sdes radeon_ring_lock(rdev, ring, 8); 2141553Srgrimes radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 215187940Skientzle radeon_ring_write(ring, rdev->config.r300.resync_scratch); 216205793Sed radeon_ring_write(ring, 0xDEADBEEF); 217205793Sed radeon_ring_unlock_commit(rdev, ring); 2181553Srgrimes} 2191553Srgrimes 2201553Srgrimesstatic void r420_cp_errata_fini(struct radeon_device *rdev) 221124389Sphk{ 2221553Srgrimes struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 223112214Srobert 2241553Srgrimes /* Catch the RESYNC we dispatched all the way back, 22544303Swollman * at the very beginning of the CP init. 2266286Swollman */ 22744303Swollman radeon_ring_lock(rdev, ring, 8); 2286286Swollman radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 22944303Swollman radeon_ring_write(ring, R300_RB3D_DC_FINISH); 230122134Sphk radeon_ring_unlock_commit(rdev, ring); 231124389Sphk radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 232122134Sphk} 2336286Swollman 23444303Swollmanstatic int r420_startup(struct radeon_device *rdev) 23544303Swollman{ 23644303Swollman int r; 23744303Swollman 23844303Swollman /* set common regs */ 23944303Swollman r100_set_common_regs(rdev); 240122134Sphk /* program mc */ 241124389Sphk r300_mc_program(rdev); 242122134Sphk /* Resume clock */ 24344303Swollman r420_clock_resume(rdev); 24444303Swollman /* Initialize GART (initialize after TTM so we can allocate 24544303Swollman * memory through TTM but finalize after TTM) */ 24644303Swollman if (rdev->flags & RADEON_IS_PCIE) { 24744303Swollman r = rv370_pcie_gart_enable(rdev); 24844303Swollman if (r) 24944303Swollman return r; 250122134Sphk } 251124389Sphk if (rdev->flags & RADEON_IS_PCI) { 252122134Sphk r = r100_pci_gart_enable(rdev); 25344303Swollman if (r) 25444303Swollman return r; 255144295Stobez } 256144295Stobez r420_pipes_init(rdev); 257144295Stobez 258144295Stobez /* allocate wb buffer */ 259144295Stobez r = radeon_wb_init(rdev); 260144295Stobez if (r) 261144295Stobez return r; 262144295Stobez 263144295Stobez r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 264144295Stobez if (r) { 2651553Srgrimes dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2661553Srgrimes return r; 2672860Srgrimes } 26861749Sjoe 26961749Sjoe /* Enable IRQ */ 27061749Sjoe r100_irq_set(rdev); 27161749Sjoe rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 27261749Sjoe /* 1M ring buffer */ 2731553Srgrimes r = r100_cp_init(rdev, 1024 * 1024); 2741553Srgrimes if (r) { 2751553Srgrimes dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 2761553Srgrimes return r; 2771553Srgrimes } 2781553Srgrimes r420_cp_errata_init(rdev); 27954375Sjoe 28054375Sjoe r = radeon_ib_pool_init(rdev); 2811553Srgrimes if (r) { 2821553Srgrimes dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 283121299Sphk return r; 2841553Srgrimes } 285121299Sphk 286121299Sphk return 0; 287121299Sphk} 288121299Sphk 289121299Sphkint r420_resume(struct radeon_device *rdev) 2901553Srgrimes{ 2911553Srgrimes int r; 2922860Srgrimes 2932860Srgrimes /* Make sur GART are not working */ 2942860Srgrimes if (rdev->flags & RADEON_IS_PCIE) 29566584Sphk rv370_pcie_gart_disable(rdev); 29654375Sjoe if (rdev->flags & RADEON_IS_PCI) 29754375Sjoe r100_pci_gart_disable(rdev); 29861749Sjoe /* Resume clock before doing reset */ 2992877Srgrimes r420_clock_resume(rdev); 3001553Srgrimes /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3011553Srgrimes if (radeon_asic_reset(rdev)) { 3021553Srgrimes dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 303124389Sphk RREG32(R_000E40_RBBM_STATUS), 3041553Srgrimes RREG32(R_0007C0_CP_STAT)); 3051553Srgrimes } 3061553Srgrimes /* check if cards are posted or not */ 3071553Srgrimes if (rdev->is_atom_bios) { 3081553Srgrimes atom_asic_init(rdev->mode_info.atom_context); 3091553Srgrimes } else { 31054375Sjoe radeon_combios_asic_init(rdev->ddev); 3111553Srgrimes } 31254375Sjoe /* Resume clock after posting */ 3131553Srgrimes r420_clock_resume(rdev); 3142860Srgrimes /* Initialize surface registers */ 3152860Srgrimes radeon_surface_init(rdev); 3162860Srgrimes 3172860Srgrimes rdev->accel_working = true; 3182860Srgrimes r = r420_startup(rdev); 3192860Srgrimes if (r) { 3202860Srgrimes rdev->accel_working = false; 3212860Srgrimes } 3222860Srgrimes return r; 3232860Srgrimes} 3242860Srgrimes 3252860Srgrimesint r420_suspend(struct radeon_device *rdev) 3262860Srgrimes{ 3272860Srgrimes r420_cp_errata_fini(rdev); 3282860Srgrimes r100_cp_disable(rdev); 3292860Srgrimes radeon_wb_disable(rdev); 33054375Sjoe r100_irq_disable(rdev); 33154375Sjoe if (rdev->flags & RADEON_IS_PCIE) 33254375Sjoe rv370_pcie_gart_disable(rdev); 33354375Sjoe if (rdev->flags & RADEON_IS_PCI) 33454375Sjoe r100_pci_gart_disable(rdev); 33554375Sjoe return 0; 33654375Sjoe} 33754375Sjoe 33854375Sjoevoid r420_fini(struct radeon_device *rdev) 33954375Sjoe{ 34054375Sjoe r100_cp_fini(rdev); 34154375Sjoe radeon_wb_fini(rdev); 34266584Sphk radeon_ib_pool_fini(rdev); 34354375Sjoe radeon_gem_fini(rdev); 3441553Srgrimes if (rdev->flags & RADEON_IS_PCIE) 3451553Srgrimes rv370_pcie_gart_fini(rdev); 3462860Srgrimes if (rdev->flags & RADEON_IS_PCI) 3472860Srgrimes r100_pci_gart_fini(rdev); 3482877Srgrimes radeon_agp_fini(rdev); 3492877Srgrimes radeon_irq_kms_fini(rdev); 3502860Srgrimes radeon_fence_driver_fini(rdev); 3512860Srgrimes radeon_bo_fini(rdev); 3522860Srgrimes if (rdev->is_atom_bios) { 353121300Sphk radeon_atombios_fini(rdev); 35466584Sphk } else { 35566584Sphk radeon_combios_fini(rdev); 3562877Srgrimes } 3572860Srgrimes free(rdev->bios, DRM_MEM_DRIVER); 3582860Srgrimes rdev->bios = NULL; 3591553Srgrimes} 3602860Srgrimes 36151705Sbillfint r420_init(struct radeon_device *rdev) 362124389Sphk{ 363124389Sphk int r; 3642860Srgrimes 365124389Sphk /* Initialize scratch registers */ 366124389Sphk radeon_scratch_init(rdev); 3672860Srgrimes /* Initialize surface registers */ 368124389Sphk radeon_surface_init(rdev); 36951705Sbillf /* TODO: disable VGA need to use VGA request */ 3702860Srgrimes /* restore some register to sane defaults */ 37138020Sbde r100_restore_sanity(rdev); 37251705Sbillf /* BIOS*/ 373124389Sphk if (!radeon_get_bios(rdev)) { 374124389Sphk if (ASIC_IS_AVIVO(rdev)) 3752860Srgrimes return -EINVAL; 376124389Sphk } 377124389Sphk if (rdev->is_atom_bios) { 3782860Srgrimes r = radeon_atombios_init(rdev); 379124389Sphk if (r) { 38051705Sbillf return r; 3812860Srgrimes } 38238020Sbde } else { 3832860Srgrimes r = radeon_combios_init(rdev); 3842860Srgrimes if (r) { 3852860Srgrimes return r; 3862860Srgrimes } 38766584Sphk } 38861749Sjoe /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 38961749Sjoe if (radeon_asic_reset(rdev)) { 39061749Sjoe dev_warn(rdev->dev, 39161749Sjoe "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3922860Srgrimes RREG32(R_000E40_RBBM_STATUS), 3932860Srgrimes RREG32(R_0007C0_CP_STAT)); 3942860Srgrimes } 3952860Srgrimes /* check if cards are posted or not */ 39654375Sjoe if (radeon_boot_test_post_card(rdev) == false) 3972860Srgrimes return -EINVAL; 3981553Srgrimes 3991553Srgrimes /* Initialize clocks */ 4001553Srgrimes radeon_get_clock_info(rdev->ddev); 4011553Srgrimes /* initialize AGP */ 402121299Sphk if (rdev->flags & RADEON_IS_AGP) { 4031553Srgrimes r = radeon_agp_init(rdev); 4041553Srgrimes if (r) { 4051553Srgrimes radeon_agp_disable(rdev); 4061553Srgrimes } 4071553Srgrimes } 4081553Srgrimes /* initialize memory controller */ 4091553Srgrimes r300_mc_init(rdev); 4101553Srgrimes r420_debugfs(rdev); 4111553Srgrimes /* Fence driver */ 4121553Srgrimes r = radeon_fence_driver_init(rdev); 4131553Srgrimes if (r) { 4141553Srgrimes return r; 4152860Srgrimes } 4161553Srgrimes r = radeon_irq_kms_init(rdev); 4171553Srgrimes if (r) { 4181553Srgrimes return r; 4191553Srgrimes } 4201553Srgrimes /* Memory manager */ 4211553Srgrimes r = radeon_bo_init(rdev); 4221553Srgrimes if (r) { 4231553Srgrimes return r; 4242860Srgrimes } 4252860Srgrimes if (rdev->family == CHIP_R420) 4261553Srgrimes r100_enable_bm(rdev); 4271553Srgrimes 4281553Srgrimes if (rdev->flags & RADEON_IS_PCIE) { 429 r = rv370_pcie_gart_init(rdev); 430 if (r) 431 return r; 432 } 433 if (rdev->flags & RADEON_IS_PCI) { 434 r = r100_pci_gart_init(rdev); 435 if (r) 436 return r; 437 } 438 r420_set_reg_safe(rdev); 439 440 rdev->accel_working = true; 441 r = r420_startup(rdev); 442 if (r) { 443 /* Somethings want wront with the accel init stop accel */ 444 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 445 r100_cp_fini(rdev); 446 radeon_wb_fini(rdev); 447 radeon_ib_pool_fini(rdev); 448 radeon_irq_kms_fini(rdev); 449 if (rdev->flags & RADEON_IS_PCIE) 450 rv370_pcie_gart_fini(rdev); 451 if (rdev->flags & RADEON_IS_PCI) 452 r100_pci_gart_fini(rdev); 453 radeon_agp_fini(rdev); 454 rdev->accel_working = false; 455 } 456 return 0; 457} 458 459/* 460 * Debugfs info 461 */ 462#if defined(CONFIG_DEBUG_FS) 463static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 464{ 465 struct drm_info_node *node = (struct drm_info_node *) m->private; 466 struct drm_device *dev = node->minor->dev; 467 struct radeon_device *rdev = dev->dev_private; 468 uint32_t tmp; 469 470 tmp = RREG32(R400_GB_PIPE_SELECT); 471 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 472 tmp = RREG32(R300_GB_TILE_CONFIG); 473 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 474 tmp = RREG32(R300_DST_PIPE_CONFIG); 475 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 476 return 0; 477} 478 479static struct drm_info_list r420_pipes_info_list[] = { 480 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 481}; 482#endif 483 484int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 485{ 486#if defined(CONFIG_DEBUG_FS) 487 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 488#else 489 return 0; 490#endif 491} 492