atombios_encoders.c revision 280369
1/* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/atombios_encoders.c 280369 2015-03-23 13:38:33Z kib $"); 29 30#include <dev/drm2/drmP.h> 31#include <dev/drm2/drm_crtc_helper.h> 32#include <dev/drm2/radeon/radeon_drm.h> 33#include "radeon.h" 34#include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */ 35#include "atom.h" 36 37static u8 38radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 39{ 40 u8 backlight_level; 41 u32 bios_2_scratch; 42 43 if (rdev->family >= CHIP_R600) 44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 45 else 46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 47 48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 50 51 return backlight_level; 52} 53 54static void 55radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 56 u8 backlight_level) 57{ 58 u32 bios_2_scratch; 59 60 if (rdev->family >= CHIP_R600) 61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 62 else 63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 64 65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 67 ATOM_S2_CURRENT_BL_LEVEL_MASK); 68 69 if (rdev->family >= CHIP_R600) 70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 71 else 72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 73} 74 75u8 76atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 77{ 78 struct drm_device *dev = radeon_encoder->base.dev; 79 struct radeon_device *rdev = dev->dev_private; 80 81 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 82 return 0; 83 84 return radeon_atom_get_backlight_level_from_reg(rdev); 85} 86 87void 88atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 89{ 90 struct drm_encoder *encoder = &radeon_encoder->base; 91 struct drm_device *dev = radeon_encoder->base.dev; 92 struct radeon_device *rdev = dev->dev_private; 93 struct radeon_encoder_atom_dig *dig; 94 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 95 int index; 96 97 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 98 return; 99 100 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 101 radeon_encoder->enc_priv) { 102 dig = radeon_encoder->enc_priv; 103 dig->backlight_level = level; 104 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 105 106 switch (radeon_encoder->encoder_id) { 107 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 108 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 109 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 110 if (dig->backlight_level == 0) { 111 args.ucAction = ATOM_LCD_BLOFF; 112 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 113 } else { 114 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 args.ucAction = ATOM_LCD_BLON; 117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 } 119 break; 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 124 if (dig->backlight_level == 0) 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 126 else { 127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 128 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 129 } 130 break; 131 default: 132 break; 133 } 134 } 135} 136 137#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 138 139static u8 radeon_atom_bl_level(struct backlight_device *bd) 140{ 141 u8 level; 142 143 /* Convert brightness to hardware level */ 144 if (bd->props.brightness < 0) 145 level = 0; 146 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 147 level = RADEON_MAX_BL_LEVEL; 148 else 149 level = bd->props.brightness; 150 151 return level; 152} 153 154static int radeon_atom_backlight_update_status(struct backlight_device *bd) 155{ 156 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 157 struct radeon_encoder *radeon_encoder = pdata->encoder; 158 159 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 160 161 return 0; 162} 163 164static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 165{ 166 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 167 struct radeon_encoder *radeon_encoder = pdata->encoder; 168 struct drm_device *dev = radeon_encoder->base.dev; 169 struct radeon_device *rdev = dev->dev_private; 170 171 return radeon_atom_get_backlight_level_from_reg(rdev); 172} 173 174static const struct backlight_ops radeon_atom_backlight_ops = { 175 .get_brightness = radeon_atom_backlight_get_brightness, 176 .update_status = radeon_atom_backlight_update_status, 177}; 178 179void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 180 struct drm_connector *drm_connector) 181{ 182 struct drm_device *dev = radeon_encoder->base.dev; 183 struct radeon_device *rdev = dev->dev_private; 184 struct backlight_device *bd; 185 struct backlight_properties props; 186 struct radeon_backlight_privdata *pdata; 187 struct radeon_encoder_atom_dig *dig; 188 u8 backlight_level; 189 char bl_name[16]; 190 191 if (!radeon_encoder->enc_priv) 192 return; 193 194 if (!rdev->is_atom_bios) 195 return; 196 197 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 198 return; 199 200 pdata = malloc(sizeof(struct radeon_backlight_privdata), DRM_MEM_DRIVER, M_WAITOK); 201 if (!pdata) { 202 DRM_ERROR("Memory allocation failed\n"); 203 goto error; 204 } 205 206 memset(&props, 0, sizeof(props)); 207 props.max_brightness = RADEON_MAX_BL_LEVEL; 208 props.type = BACKLIGHT_RAW; 209 snprintf(bl_name, sizeof(bl_name), 210 "radeon_bl%d", dev->primary->index); 211 bd = backlight_device_register(bl_name, &drm_connector->kdev, 212 pdata, &radeon_atom_backlight_ops, &props); 213 if (IS_ERR(bd)) { 214 DRM_ERROR("Backlight registration failed\n"); 215 goto error; 216 } 217 218 pdata->encoder = radeon_encoder; 219 220 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 221 222 dig = radeon_encoder->enc_priv; 223 dig->bl_dev = bd; 224 225 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 226 bd->props.power = FB_BLANK_UNBLANK; 227 backlight_update_status(bd); 228 229 DRM_INFO("radeon atom DIG backlight initialized\n"); 230 231 return; 232 233error: 234 free(pdata, DRM_MEM_DRIVER); 235 return; 236} 237 238static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 239{ 240 struct drm_device *dev = radeon_encoder->base.dev; 241 struct radeon_device *rdev = dev->dev_private; 242 struct backlight_device *bd = NULL; 243 struct radeon_encoder_atom_dig *dig; 244 245 if (!radeon_encoder->enc_priv) 246 return; 247 248 if (!rdev->is_atom_bios) 249 return; 250 251 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 252 return; 253 254 dig = radeon_encoder->enc_priv; 255 bd = dig->bl_dev; 256 dig->bl_dev = NULL; 257 258 if (bd) { 259 struct radeon_legacy_backlight_privdata *pdata; 260 261 pdata = bl_get_data(bd); 262 backlight_device_unregister(bd); 263 free(pdata, DRM_MEM_DRIVER); 264 265 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 266 } 267} 268 269#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 270 271void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 272 struct drm_connector *drm_connector) 273{ 274} 275 276static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 277{ 278} 279 280#endif 281 282 283static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 284{ 285 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 286 switch (radeon_encoder->encoder_id) { 287 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 288 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 289 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 290 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 291 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 293 case ENCODER_OBJECT_ID_INTERNAL_DDI: 294 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 298 return true; 299 default: 300 return false; 301 } 302} 303 304static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 305 struct drm_display_mode *mode, 306 struct drm_display_mode *adjusted_mode) 307{ 308 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 309 struct drm_device *dev = encoder->dev; 310 struct radeon_device *rdev = dev->dev_private; 311 312 /* set the active encoder to connector routing */ 313 radeon_encoder_set_active_device(encoder); 314 drm_mode_set_crtcinfo(adjusted_mode, 0); 315 316 /* hw bug */ 317 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 318 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 319 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 320 321 /* get the native mode for LVDS */ 322 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 323 radeon_panel_mode_fixup(encoder, adjusted_mode); 324 325 /* get the native mode for TV */ 326 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 327 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 328 if (tv_dac) { 329 if (tv_dac->tv_std == TV_STD_NTSC || 330 tv_dac->tv_std == TV_STD_NTSC_J || 331 tv_dac->tv_std == TV_STD_PAL_M) 332 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 333 else 334 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 335 } 336 } 337 338 if (ASIC_IS_DCE3(rdev) && 339 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 340 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 341 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 342 radeon_dp_set_link_config(connector, adjusted_mode); 343 } 344 345 return true; 346} 347 348static void 349atombios_dac_setup(struct drm_encoder *encoder, int action) 350{ 351 struct drm_device *dev = encoder->dev; 352 struct radeon_device *rdev = dev->dev_private; 353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 354 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 355 int index = 0; 356 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 357 358 memset(&args, 0, sizeof(args)); 359 360 switch (radeon_encoder->encoder_id) { 361 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 362 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 363 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 364 break; 365 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 366 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 367 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 368 break; 369 } 370 371 args.ucAction = action; 372 373 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 374 args.ucDacStandard = ATOM_DAC1_PS2; 375 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 376 args.ucDacStandard = ATOM_DAC1_CV; 377 else { 378 switch (dac_info->tv_std) { 379 case TV_STD_PAL: 380 case TV_STD_PAL_M: 381 case TV_STD_SCART_PAL: 382 case TV_STD_SECAM: 383 case TV_STD_PAL_CN: 384 args.ucDacStandard = ATOM_DAC1_PAL; 385 break; 386 case TV_STD_NTSC: 387 case TV_STD_NTSC_J: 388 case TV_STD_PAL_60: 389 default: 390 args.ucDacStandard = ATOM_DAC1_NTSC; 391 break; 392 } 393 } 394 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 395 396 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 397 398} 399 400static void 401atombios_tv_setup(struct drm_encoder *encoder, int action) 402{ 403 struct drm_device *dev = encoder->dev; 404 struct radeon_device *rdev = dev->dev_private; 405 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 406 TV_ENCODER_CONTROL_PS_ALLOCATION args; 407 int index = 0; 408 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 409 410 memset(&args, 0, sizeof(args)); 411 412 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 413 414 args.sTVEncoder.ucAction = action; 415 416 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 417 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 418 else { 419 switch (dac_info->tv_std) { 420 case TV_STD_NTSC: 421 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 422 break; 423 case TV_STD_PAL: 424 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 425 break; 426 case TV_STD_PAL_M: 427 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 428 break; 429 case TV_STD_PAL_60: 430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 431 break; 432 case TV_STD_NTSC_J: 433 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 434 break; 435 case TV_STD_SCART_PAL: 436 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 437 break; 438 case TV_STD_SECAM: 439 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 440 break; 441 case TV_STD_PAL_CN: 442 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 443 break; 444 default: 445 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 446 break; 447 } 448 } 449 450 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 451 452 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 453 454} 455 456static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 457{ 458 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 459 int bpc = 8; 460 461 if (connector) 462 bpc = radeon_get_monitor_bpc(connector); 463 464 switch (bpc) { 465 case 0: 466 return PANEL_BPC_UNDEFINE; 467 case 6: 468 return PANEL_6BIT_PER_COLOR; 469 case 8: 470 default: 471 return PANEL_8BIT_PER_COLOR; 472 case 10: 473 return PANEL_10BIT_PER_COLOR; 474 case 12: 475 return PANEL_12BIT_PER_COLOR; 476 case 16: 477 return PANEL_16BIT_PER_COLOR; 478 } 479} 480 481 482union dvo_encoder_control { 483 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 484 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 485 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 486}; 487 488void 489atombios_dvo_setup(struct drm_encoder *encoder, int action) 490{ 491 struct drm_device *dev = encoder->dev; 492 struct radeon_device *rdev = dev->dev_private; 493 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 494 union dvo_encoder_control args; 495 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 496 uint8_t frev, crev; 497 498 memset(&args, 0, sizeof(args)); 499 500 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 501 return; 502 503 /* some R4xx chips have the wrong frev */ 504 if (rdev->family <= CHIP_RV410) 505 frev = 1; 506 507 switch (frev) { 508 case 1: 509 switch (crev) { 510 case 1: 511 /* R4xx, R5xx */ 512 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 513 514 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 515 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 516 517 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 518 break; 519 case 2: 520 /* RS600/690/740 */ 521 args.dvo.sDVOEncoder.ucAction = action; 522 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 523 /* DFP1, CRT1, TV1 depending on the type of port */ 524 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 525 526 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 527 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 528 break; 529 case 3: 530 /* R6xx */ 531 args.dvo_v3.ucAction = action; 532 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 533 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 534 break; 535 default: 536 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 537 break; 538 } 539 break; 540 default: 541 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 542 break; 543 } 544 545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 546} 547 548union lvds_encoder_control { 549 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 550 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 551}; 552 553void 554atombios_digital_setup(struct drm_encoder *encoder, int action) 555{ 556 struct drm_device *dev = encoder->dev; 557 struct radeon_device *rdev = dev->dev_private; 558 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 559 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 560 union lvds_encoder_control args; 561 int index = 0; 562 int hdmi_detected = 0; 563 uint8_t frev, crev; 564 565 if (!dig) 566 return; 567 568 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 569 hdmi_detected = 1; 570 571 memset(&args, 0, sizeof(args)); 572 573 switch (radeon_encoder->encoder_id) { 574 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 575 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 576 break; 577 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 579 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 580 break; 581 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 582 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 584 else 585 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 586 break; 587 } 588 589 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 590 return; 591 592 switch (frev) { 593 case 1: 594 case 2: 595 switch (crev) { 596 case 1: 597 args.v1.ucMisc = 0; 598 args.v1.ucAction = action; 599 if (hdmi_detected) 600 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 601 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 602 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 603 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 604 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 605 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 606 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 607 } else { 608 if (dig->linkb) 609 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 610 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 611 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 612 /*if (pScrn->rgbBits == 8) */ 613 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 614 } 615 break; 616 case 2: 617 case 3: 618 args.v2.ucMisc = 0; 619 args.v2.ucAction = action; 620 if (crev == 3) { 621 if (dig->coherent_mode) 622 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 623 } 624 if (hdmi_detected) 625 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 626 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 627 args.v2.ucTruncate = 0; 628 args.v2.ucSpatial = 0; 629 args.v2.ucTemporal = 0; 630 args.v2.ucFRC = 0; 631 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 632 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 633 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 634 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 635 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 636 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 637 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 638 } 639 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 640 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 641 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 642 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 643 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 644 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 645 } 646 } else { 647 if (dig->linkb) 648 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 649 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 650 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 651 } 652 break; 653 default: 654 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 655 break; 656 } 657 break; 658 default: 659 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 660 break; 661 } 662 663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 664} 665 666int 667atombios_get_encoder_mode(struct drm_encoder *encoder) 668{ 669 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 670 struct drm_connector *connector; 671 struct radeon_connector *radeon_connector; 672 struct radeon_connector_atom_dig *dig_connector; 673 674 /* dp bridges are always DP */ 675 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 676 return ATOM_ENCODER_MODE_DP; 677 678 /* DVO is always DVO */ 679 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 680 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 681 return ATOM_ENCODER_MODE_DVO; 682 683 connector = radeon_get_connector_for_encoder(encoder); 684 /* if we don't have an active device yet, just use one of 685 * the connectors tied to the encoder. 686 */ 687 if (!connector) 688 connector = radeon_get_connector_for_encoder_init(encoder); 689 radeon_connector = to_radeon_connector(connector); 690 691 switch (connector->connector_type) { 692 case DRM_MODE_CONNECTOR_DVII: 693 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 694 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 695 radeon_audio) 696 return ATOM_ENCODER_MODE_HDMI; 697 else if (radeon_connector->use_digital) 698 return ATOM_ENCODER_MODE_DVI; 699 else 700 return ATOM_ENCODER_MODE_CRT; 701 break; 702 case DRM_MODE_CONNECTOR_DVID: 703 case DRM_MODE_CONNECTOR_HDMIA: 704 default: 705 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 706 radeon_audio) 707 return ATOM_ENCODER_MODE_HDMI; 708 else 709 return ATOM_ENCODER_MODE_DVI; 710 break; 711 case DRM_MODE_CONNECTOR_LVDS: 712 return ATOM_ENCODER_MODE_LVDS; 713 break; 714 case DRM_MODE_CONNECTOR_DisplayPort: 715 dig_connector = radeon_connector->con_priv; 716 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 717 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 718 return ATOM_ENCODER_MODE_DP; 719 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 720 radeon_audio) 721 return ATOM_ENCODER_MODE_HDMI; 722 else 723 return ATOM_ENCODER_MODE_DVI; 724 break; 725 case DRM_MODE_CONNECTOR_eDP: 726 return ATOM_ENCODER_MODE_DP; 727 case DRM_MODE_CONNECTOR_DVIA: 728 case DRM_MODE_CONNECTOR_VGA: 729 return ATOM_ENCODER_MODE_CRT; 730 break; 731 case DRM_MODE_CONNECTOR_Composite: 732 case DRM_MODE_CONNECTOR_SVIDEO: 733 case DRM_MODE_CONNECTOR_9PinDIN: 734 /* fix me */ 735 return ATOM_ENCODER_MODE_TV; 736 /*return ATOM_ENCODER_MODE_CV;*/ 737 break; 738 } 739} 740 741/* 742 * DIG Encoder/Transmitter Setup 743 * 744 * DCE 3.0/3.1 745 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 746 * Supports up to 3 digital outputs 747 * - 2 DIG encoder blocks. 748 * DIG1 can drive UNIPHY link A or link B 749 * DIG2 can drive UNIPHY link B or LVTMA 750 * 751 * DCE 3.2 752 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 753 * Supports up to 5 digital outputs 754 * - 2 DIG encoder blocks. 755 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 756 * 757 * DCE 4.0/5.0/6.0 758 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 759 * Supports up to 6 digital outputs 760 * - 6 DIG encoder blocks. 761 * - DIG to PHY mapping is hardcoded 762 * DIG1 drives UNIPHY0 link A, A+B 763 * DIG2 drives UNIPHY0 link B 764 * DIG3 drives UNIPHY1 link A, A+B 765 * DIG4 drives UNIPHY1 link B 766 * DIG5 drives UNIPHY2 link A, A+B 767 * DIG6 drives UNIPHY2 link B 768 * 769 * DCE 4.1 770 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 771 * Supports up to 6 digital outputs 772 * - 2 DIG encoder blocks. 773 * llano 774 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 775 * ontario 776 * DIG1 drives UNIPHY0/1/2 link A 777 * DIG2 drives UNIPHY0/1/2 link B 778 * 779 * Routing 780 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 781 * Examples: 782 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 783 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 784 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 785 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 786 */ 787 788union dig_encoder_control { 789 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 790 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 791 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 792 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 793}; 794 795void 796atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 797{ 798 struct drm_device *dev = encoder->dev; 799 struct radeon_device *rdev = dev->dev_private; 800 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 801 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 802 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 803 union dig_encoder_control args; 804 int index = 0; 805 uint8_t frev, crev; 806 int dp_clock = 0; 807 int dp_lane_count = 0; 808 int hpd_id = RADEON_HPD_NONE; 809 810 if (connector) { 811 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 812 struct radeon_connector_atom_dig *dig_connector = 813 radeon_connector->con_priv; 814 815 dp_clock = dig_connector->dp_clock; 816 dp_lane_count = dig_connector->dp_lane_count; 817 hpd_id = radeon_connector->hpd.hpd; 818 } 819 820 /* no dig encoder assigned */ 821 if (dig->dig_encoder == -1) 822 return; 823 824 memset(&args, 0, sizeof(args)); 825 826 if (ASIC_IS_DCE4(rdev)) 827 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 828 else { 829 if (dig->dig_encoder) 830 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 831 else 832 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 833 } 834 835 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 836 return; 837 838 switch (frev) { 839 case 1: 840 switch (crev) { 841 case 1: 842 args.v1.ucAction = action; 843 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 844 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 845 args.v3.ucPanelMode = panel_mode; 846 else 847 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 848 849 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 850 args.v1.ucLaneNum = dp_lane_count; 851 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 852 args.v1.ucLaneNum = 8; 853 else 854 args.v1.ucLaneNum = 4; 855 856 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 857 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 858 switch (radeon_encoder->encoder_id) { 859 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 860 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 861 break; 862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 863 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 864 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 865 break; 866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 867 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 868 break; 869 } 870 if (dig->linkb) 871 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 872 else 873 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 874 break; 875 case 2: 876 case 3: 877 args.v3.ucAction = action; 878 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 879 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 880 args.v3.ucPanelMode = panel_mode; 881 else 882 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 883 884 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 885 args.v3.ucLaneNum = dp_lane_count; 886 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 887 args.v3.ucLaneNum = 8; 888 else 889 args.v3.ucLaneNum = 4; 890 891 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 892 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 893 args.v3.acConfig.ucDigSel = dig->dig_encoder; 894 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 895 break; 896 case 4: 897 args.v4.ucAction = action; 898 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 899 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 900 args.v4.ucPanelMode = panel_mode; 901 else 902 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 903 904 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 905 args.v4.ucLaneNum = dp_lane_count; 906 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 907 args.v4.ucLaneNum = 8; 908 else 909 args.v4.ucLaneNum = 4; 910 911 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 912 if (dp_clock == 270000) 913 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 914 else if (dp_clock == 540000) 915 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 916 } 917 args.v4.acConfig.ucDigSel = dig->dig_encoder; 918 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 919 if (hpd_id == RADEON_HPD_NONE) 920 args.v4.ucHPD_ID = 0; 921 else 922 args.v4.ucHPD_ID = hpd_id + 1; 923 break; 924 default: 925 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 926 break; 927 } 928 break; 929 default: 930 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 931 break; 932 } 933 934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 935 936} 937 938union dig_transmitter_control { 939 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 940 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 941 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 942 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 943 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 944}; 945 946void 947atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 948{ 949 struct drm_device *dev = encoder->dev; 950 struct radeon_device *rdev = dev->dev_private; 951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 952 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 953 struct drm_connector *connector; 954 union dig_transmitter_control args; 955 int index = 0; 956 uint8_t frev, crev; 957 bool is_dp = false; 958 int pll_id = 0; 959 int dp_clock = 0; 960 int dp_lane_count = 0; 961 int connector_object_id = 0; 962 int igp_lane_info = 0; 963 int dig_encoder = dig->dig_encoder; 964 int hpd_id = RADEON_HPD_NONE; 965 966 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 967 connector = radeon_get_connector_for_encoder_init(encoder); 968 /* just needed to avoid bailing in the encoder check. the encoder 969 * isn't used for init 970 */ 971 dig_encoder = 0; 972 } else 973 connector = radeon_get_connector_for_encoder(encoder); 974 975 if (connector) { 976 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 977 struct radeon_connector_atom_dig *dig_connector = 978 radeon_connector->con_priv; 979 980 hpd_id = radeon_connector->hpd.hpd; 981 dp_clock = dig_connector->dp_clock; 982 dp_lane_count = dig_connector->dp_lane_count; 983 connector_object_id = 984 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 985 igp_lane_info = dig_connector->igp_lane_info; 986 } 987 988 if (encoder->crtc) { 989 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 990 pll_id = radeon_crtc->pll_id; 991 } 992 993 /* no dig encoder assigned */ 994 if (dig_encoder == -1) 995 return; 996 997 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 998 is_dp = true; 999 1000 memset(&args, 0, sizeof(args)); 1001 1002 switch (radeon_encoder->encoder_id) { 1003 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1004 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1005 break; 1006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1008 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1009 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1010 break; 1011 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1012 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1013 break; 1014 } 1015 1016 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1017 return; 1018 1019 switch (frev) { 1020 case 1: 1021 switch (crev) { 1022 case 1: 1023 args.v1.ucAction = action; 1024 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1025 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1026 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1027 args.v1.asMode.ucLaneSel = lane_num; 1028 args.v1.asMode.ucLaneSet = lane_set; 1029 } else { 1030 if (is_dp) 1031 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1032 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1033 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1034 else 1035 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1036 } 1037 1038 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1039 1040 if (dig_encoder) 1041 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1042 else 1043 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1044 1045 if ((rdev->flags & RADEON_IS_IGP) && 1046 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1047 if (is_dp || 1048 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1049 if (igp_lane_info & 0x1) 1050 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1051 else if (igp_lane_info & 0x2) 1052 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1053 else if (igp_lane_info & 0x4) 1054 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1055 else if (igp_lane_info & 0x8) 1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1057 } else { 1058 if (igp_lane_info & 0x3) 1059 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1060 else if (igp_lane_info & 0xc) 1061 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1062 } 1063 } 1064 1065 if (dig->linkb) 1066 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1067 else 1068 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1069 1070 if (is_dp) 1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1072 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1073 if (dig->coherent_mode) 1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1075 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1076 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1077 } 1078 break; 1079 case 2: 1080 args.v2.ucAction = action; 1081 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1082 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1083 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1084 args.v2.asMode.ucLaneSel = lane_num; 1085 args.v2.asMode.ucLaneSet = lane_set; 1086 } else { 1087 if (is_dp) 1088 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1089 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1090 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1091 else 1092 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1093 } 1094 1095 args.v2.acConfig.ucEncoderSel = dig_encoder; 1096 if (dig->linkb) 1097 args.v2.acConfig.ucLinkSel = 1; 1098 1099 switch (radeon_encoder->encoder_id) { 1100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1101 args.v2.acConfig.ucTransmitterSel = 0; 1102 break; 1103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1104 args.v2.acConfig.ucTransmitterSel = 1; 1105 break; 1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1107 args.v2.acConfig.ucTransmitterSel = 2; 1108 break; 1109 } 1110 1111 if (is_dp) { 1112 args.v2.acConfig.fCoherentMode = 1; 1113 args.v2.acConfig.fDPConnector = 1; 1114 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1115 if (dig->coherent_mode) 1116 args.v2.acConfig.fCoherentMode = 1; 1117 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1118 args.v2.acConfig.fDualLinkConnector = 1; 1119 } 1120 break; 1121 case 3: 1122 args.v3.ucAction = action; 1123 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1124 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1125 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1126 args.v3.asMode.ucLaneSel = lane_num; 1127 args.v3.asMode.ucLaneSet = lane_set; 1128 } else { 1129 if (is_dp) 1130 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1131 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1132 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1133 else 1134 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1135 } 1136 1137 if (is_dp) 1138 args.v3.ucLaneNum = dp_lane_count; 1139 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1140 args.v3.ucLaneNum = 8; 1141 else 1142 args.v3.ucLaneNum = 4; 1143 1144 if (dig->linkb) 1145 args.v3.acConfig.ucLinkSel = 1; 1146 if (dig_encoder & 1) 1147 args.v3.acConfig.ucEncoderSel = 1; 1148 1149 /* Select the PLL for the PHY 1150 * DP PHY should be clocked from external src if there is 1151 * one. 1152 */ 1153 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1154 if (is_dp && rdev->clock.dp_extclk) 1155 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1156 else 1157 args.v3.acConfig.ucRefClkSource = pll_id; 1158 1159 switch (radeon_encoder->encoder_id) { 1160 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1161 args.v3.acConfig.ucTransmitterSel = 0; 1162 break; 1163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1164 args.v3.acConfig.ucTransmitterSel = 1; 1165 break; 1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1167 args.v3.acConfig.ucTransmitterSel = 2; 1168 break; 1169 } 1170 1171 if (is_dp) 1172 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1173 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1174 if (dig->coherent_mode) 1175 args.v3.acConfig.fCoherentMode = 1; 1176 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1177 args.v3.acConfig.fDualLinkConnector = 1; 1178 } 1179 break; 1180 case 4: 1181 args.v4.ucAction = action; 1182 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1183 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1184 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1185 args.v4.asMode.ucLaneSel = lane_num; 1186 args.v4.asMode.ucLaneSet = lane_set; 1187 } else { 1188 if (is_dp) 1189 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1190 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1191 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1192 else 1193 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1194 } 1195 1196 if (is_dp) 1197 args.v4.ucLaneNum = dp_lane_count; 1198 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1199 args.v4.ucLaneNum = 8; 1200 else 1201 args.v4.ucLaneNum = 4; 1202 1203 if (dig->linkb) 1204 args.v4.acConfig.ucLinkSel = 1; 1205 if (dig_encoder & 1) 1206 args.v4.acConfig.ucEncoderSel = 1; 1207 1208 /* Select the PLL for the PHY 1209 * DP PHY should be clocked from external src if there is 1210 * one. 1211 */ 1212 /* On DCE5 DCPLL usually generates the DP ref clock */ 1213 if (is_dp) { 1214 if (rdev->clock.dp_extclk) 1215 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1216 else 1217 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1218 } else 1219 args.v4.acConfig.ucRefClkSource = pll_id; 1220 1221 switch (radeon_encoder->encoder_id) { 1222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1223 args.v4.acConfig.ucTransmitterSel = 0; 1224 break; 1225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1226 args.v4.acConfig.ucTransmitterSel = 1; 1227 break; 1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1229 args.v4.acConfig.ucTransmitterSel = 2; 1230 break; 1231 } 1232 1233 if (is_dp) 1234 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1235 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1236 if (dig->coherent_mode) 1237 args.v4.acConfig.fCoherentMode = 1; 1238 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1239 args.v4.acConfig.fDualLinkConnector = 1; 1240 } 1241 break; 1242 case 5: 1243 args.v5.ucAction = action; 1244 if (is_dp) 1245 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1246 else 1247 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1248 1249 switch (radeon_encoder->encoder_id) { 1250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1251 if (dig->linkb) 1252 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1253 else 1254 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1255 break; 1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1257 if (dig->linkb) 1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1259 else 1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1261 break; 1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1263 if (dig->linkb) 1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1265 else 1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1267 break; 1268 } 1269 if (is_dp) 1270 args.v5.ucLaneNum = dp_lane_count; 1271 else if (radeon_encoder->pixel_clock > 165000) 1272 args.v5.ucLaneNum = 8; 1273 else 1274 args.v5.ucLaneNum = 4; 1275 args.v5.ucConnObjId = connector_object_id; 1276 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1277 1278 if (is_dp && rdev->clock.dp_extclk) 1279 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1280 else 1281 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1282 1283 if (is_dp) 1284 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1285 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1286 if (dig->coherent_mode) 1287 args.v5.asConfig.ucCoherentMode = 1; 1288 } 1289 if (hpd_id == RADEON_HPD_NONE) 1290 args.v5.asConfig.ucHPDSel = 0; 1291 else 1292 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1293 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1294 args.v5.ucDPLaneSet = lane_set; 1295 break; 1296 default: 1297 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1298 break; 1299 } 1300 break; 1301 default: 1302 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1303 break; 1304 } 1305 1306 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1307} 1308 1309bool 1310atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1311{ 1312 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1313 struct drm_device *dev = radeon_connector->base.dev; 1314 struct radeon_device *rdev = dev->dev_private; 1315 union dig_transmitter_control args; 1316 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1317 uint8_t frev, crev; 1318 1319 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1320 goto done; 1321 1322 if (!ASIC_IS_DCE4(rdev)) 1323 goto done; 1324 1325 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1326 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1327 goto done; 1328 1329 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1330 goto done; 1331 1332 memset(&args, 0, sizeof(args)); 1333 1334 args.v1.ucAction = action; 1335 1336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1337 1338 /* wait for the panel to power up */ 1339 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1340 int i; 1341 1342 for (i = 0; i < 300; i++) { 1343 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1344 return true; 1345 DRM_MDELAY(1); 1346 } 1347 return false; 1348 } 1349done: 1350 return true; 1351} 1352 1353union external_encoder_control { 1354 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1355 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1356}; 1357 1358static void 1359atombios_external_encoder_setup(struct drm_encoder *encoder, 1360 struct drm_encoder *ext_encoder, 1361 int action) 1362{ 1363 struct drm_device *dev = encoder->dev; 1364 struct radeon_device *rdev = dev->dev_private; 1365 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1366 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1367 union external_encoder_control args; 1368 struct drm_connector *connector; 1369 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1370 u8 frev, crev; 1371 int dp_clock = 0; 1372 int dp_lane_count = 0; 1373 int connector_object_id = 0; 1374 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1375 1376 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1377 connector = radeon_get_connector_for_encoder_init(encoder); 1378 else 1379 connector = radeon_get_connector_for_encoder(encoder); 1380 1381 if (connector) { 1382 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1383 struct radeon_connector_atom_dig *dig_connector = 1384 radeon_connector->con_priv; 1385 1386 dp_clock = dig_connector->dp_clock; 1387 dp_lane_count = dig_connector->dp_lane_count; 1388 connector_object_id = 1389 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1390 } 1391 1392 memset(&args, 0, sizeof(args)); 1393 1394 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1395 return; 1396 1397 switch (frev) { 1398 case 1: 1399 /* no params on frev 1 */ 1400 break; 1401 case 2: 1402 switch (crev) { 1403 case 1: 1404 case 2: 1405 args.v1.sDigEncoder.ucAction = action; 1406 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1407 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1408 1409 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1410 if (dp_clock == 270000) 1411 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1412 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1413 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1414 args.v1.sDigEncoder.ucLaneNum = 8; 1415 else 1416 args.v1.sDigEncoder.ucLaneNum = 4; 1417 break; 1418 case 3: 1419 args.v3.sExtEncoder.ucAction = action; 1420 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1421 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1422 else 1423 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1424 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1425 1426 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1427 if (dp_clock == 270000) 1428 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1429 else if (dp_clock == 540000) 1430 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1431 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1432 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1433 args.v3.sExtEncoder.ucLaneNum = 8; 1434 else 1435 args.v3.sExtEncoder.ucLaneNum = 4; 1436 switch (ext_enum) { 1437 case GRAPH_OBJECT_ENUM_ID1: 1438 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1439 break; 1440 case GRAPH_OBJECT_ENUM_ID2: 1441 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1442 break; 1443 case GRAPH_OBJECT_ENUM_ID3: 1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1445 break; 1446 } 1447 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1448 break; 1449 default: 1450 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1451 return; 1452 } 1453 break; 1454 default: 1455 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1456 return; 1457 } 1458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1459} 1460 1461static void 1462atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1463{ 1464 struct drm_device *dev = encoder->dev; 1465 struct radeon_device *rdev = dev->dev_private; 1466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1467 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1468 ENABLE_YUV_PS_ALLOCATION args; 1469 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1470 uint32_t temp, reg; 1471 1472 memset(&args, 0, sizeof(args)); 1473 1474 if (rdev->family >= CHIP_R600) 1475 reg = R600_BIOS_3_SCRATCH; 1476 else 1477 reg = RADEON_BIOS_3_SCRATCH; 1478 1479 /* XXX: fix up scratch reg handling */ 1480 temp = RREG32(reg); 1481 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1482 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1483 (radeon_crtc->crtc_id << 18))); 1484 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1485 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1486 else 1487 WREG32(reg, 0); 1488 1489 if (enable) 1490 args.ucEnable = ATOM_ENABLE; 1491 args.ucCRTC = radeon_crtc->crtc_id; 1492 1493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1494 1495 WREG32(reg, temp); 1496} 1497 1498static void 1499radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1500{ 1501 struct drm_device *dev = encoder->dev; 1502 struct radeon_device *rdev = dev->dev_private; 1503 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1504 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1505 int index = 0; 1506 1507 memset(&args, 0, sizeof(args)); 1508 1509 switch (radeon_encoder->encoder_id) { 1510 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1512 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1513 break; 1514 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1515 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1516 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1517 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1518 break; 1519 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1520 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1521 break; 1522 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1524 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1525 else 1526 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1527 break; 1528 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1529 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1530 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1531 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1532 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1533 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1534 else 1535 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1536 break; 1537 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1539 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1540 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1541 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1542 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1543 else 1544 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1545 break; 1546 default: 1547 return; 1548 } 1549 1550 switch (mode) { 1551 case DRM_MODE_DPMS_ON: 1552 args.ucAction = ATOM_ENABLE; 1553 /* workaround for DVOOutputControl on some RS690 systems */ 1554 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1555 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1556 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1558 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1559 } else 1560 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1561 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1562 args.ucAction = ATOM_LCD_BLON; 1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1564 } 1565 break; 1566 case DRM_MODE_DPMS_STANDBY: 1567 case DRM_MODE_DPMS_SUSPEND: 1568 case DRM_MODE_DPMS_OFF: 1569 args.ucAction = ATOM_DISABLE; 1570 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1571 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1572 args.ucAction = ATOM_LCD_BLOFF; 1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1574 } 1575 break; 1576 } 1577} 1578 1579static void 1580radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1581{ 1582 struct drm_device *dev = encoder->dev; 1583 struct radeon_device *rdev = dev->dev_private; 1584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1585 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1586 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1587 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1588 struct radeon_connector *radeon_connector = NULL; 1589 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1590 1591 if (connector) { 1592 radeon_connector = to_radeon_connector(connector); 1593 radeon_dig_connector = radeon_connector->con_priv; 1594 } 1595 1596 switch (mode) { 1597 case DRM_MODE_DPMS_ON: 1598 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1599 if (!connector) 1600 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1601 else 1602 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1603 1604 /* setup and enable the encoder */ 1605 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1606 atombios_dig_encoder_setup(encoder, 1607 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1608 dig->panel_mode); 1609 if (ext_encoder) { 1610 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1611 atombios_external_encoder_setup(encoder, ext_encoder, 1612 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1613 } 1614 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1615 } else if (ASIC_IS_DCE4(rdev)) { 1616 /* setup and enable the encoder */ 1617 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1618 /* enable the transmitter */ 1619 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1621 } else { 1622 /* setup and enable the encoder and transmitter */ 1623 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1624 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1626 /* some early dce3.2 boards have a bug in their transmitter control table */ 1627 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730)) 1628 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1629 } 1630 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1631 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1632 atombios_set_edp_panel_power(connector, 1633 ATOM_TRANSMITTER_ACTION_POWER_ON); 1634 radeon_dig_connector->edp_on = true; 1635 } 1636 radeon_dp_link_train(encoder, connector); 1637 if (ASIC_IS_DCE4(rdev)) 1638 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1639 } 1640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1642 break; 1643 case DRM_MODE_DPMS_STANDBY: 1644 case DRM_MODE_DPMS_SUSPEND: 1645 case DRM_MODE_DPMS_OFF: 1646 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1647 /* disable the transmitter */ 1648 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1649 } else if (ASIC_IS_DCE4(rdev)) { 1650 /* disable the transmitter */ 1651 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1652 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1653 } else { 1654 /* disable the encoder and transmitter */ 1655 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1656 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1657 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1658 } 1659 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1660 if (ASIC_IS_DCE4(rdev)) 1661 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1662 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1663 atombios_set_edp_panel_power(connector, 1664 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1665 radeon_dig_connector->edp_on = false; 1666 } 1667 } 1668 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1670 break; 1671 } 1672} 1673 1674static void 1675radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1676 struct drm_encoder *ext_encoder, 1677 int mode) 1678{ 1679 struct drm_device *dev = encoder->dev; 1680 struct radeon_device *rdev = dev->dev_private; 1681 1682 switch (mode) { 1683 case DRM_MODE_DPMS_ON: 1684 default: 1685 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1686 atombios_external_encoder_setup(encoder, ext_encoder, 1687 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1688 atombios_external_encoder_setup(encoder, ext_encoder, 1689 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1690 } else 1691 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1692 break; 1693 case DRM_MODE_DPMS_STANDBY: 1694 case DRM_MODE_DPMS_SUSPEND: 1695 case DRM_MODE_DPMS_OFF: 1696 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1697 atombios_external_encoder_setup(encoder, ext_encoder, 1698 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1699 atombios_external_encoder_setup(encoder, ext_encoder, 1700 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1701 } else 1702 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1703 break; 1704 } 1705} 1706 1707static void 1708radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1709{ 1710 struct drm_device *dev = encoder->dev; 1711 struct radeon_device *rdev = dev->dev_private; 1712 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1713 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1714 1715 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1716 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1717 radeon_encoder->active_device); 1718 switch (radeon_encoder->encoder_id) { 1719 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1720 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1721 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1722 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1723 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1724 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1725 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1727 radeon_atom_encoder_dpms_avivo(encoder, mode); 1728 break; 1729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1731 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1733 radeon_atom_encoder_dpms_dig(encoder, mode); 1734 break; 1735 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1736 if (ASIC_IS_DCE5(rdev)) { 1737 switch (mode) { 1738 case DRM_MODE_DPMS_ON: 1739 atombios_dvo_setup(encoder, ATOM_ENABLE); 1740 break; 1741 case DRM_MODE_DPMS_STANDBY: 1742 case DRM_MODE_DPMS_SUSPEND: 1743 case DRM_MODE_DPMS_OFF: 1744 atombios_dvo_setup(encoder, ATOM_DISABLE); 1745 break; 1746 } 1747 } else if (ASIC_IS_DCE3(rdev)) 1748 radeon_atom_encoder_dpms_dig(encoder, mode); 1749 else 1750 radeon_atom_encoder_dpms_avivo(encoder, mode); 1751 break; 1752 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1753 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1754 if (ASIC_IS_DCE5(rdev)) { 1755 switch (mode) { 1756 case DRM_MODE_DPMS_ON: 1757 atombios_dac_setup(encoder, ATOM_ENABLE); 1758 break; 1759 case DRM_MODE_DPMS_STANDBY: 1760 case DRM_MODE_DPMS_SUSPEND: 1761 case DRM_MODE_DPMS_OFF: 1762 atombios_dac_setup(encoder, ATOM_DISABLE); 1763 break; 1764 } 1765 } else 1766 radeon_atom_encoder_dpms_avivo(encoder, mode); 1767 break; 1768 default: 1769 return; 1770 } 1771 1772 if (ext_encoder) 1773 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1774 1775 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1776 1777} 1778 1779union crtc_source_param { 1780 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1781 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1782}; 1783 1784static void 1785atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1786{ 1787 struct drm_device *dev = encoder->dev; 1788 struct radeon_device *rdev = dev->dev_private; 1789 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1790 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1791 union crtc_source_param args; 1792 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1793 uint8_t frev, crev; 1794 struct radeon_encoder_atom_dig *dig; 1795 1796 memset(&args, 0, sizeof(args)); 1797 1798 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1799 return; 1800 1801 switch (frev) { 1802 case 1: 1803 switch (crev) { 1804 case 1: 1805 default: 1806 if (ASIC_IS_AVIVO(rdev)) 1807 args.v1.ucCRTC = radeon_crtc->crtc_id; 1808 else { 1809 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1810 args.v1.ucCRTC = radeon_crtc->crtc_id; 1811 } else { 1812 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1813 } 1814 } 1815 switch (radeon_encoder->encoder_id) { 1816 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1817 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1818 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1819 break; 1820 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1821 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1822 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1823 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1824 else 1825 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1826 break; 1827 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1828 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1829 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1830 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1831 break; 1832 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1834 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1835 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1836 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1837 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1838 else 1839 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1840 break; 1841 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1843 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1844 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1845 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1846 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1847 else 1848 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1849 break; 1850 } 1851 break; 1852 case 2: 1853 args.v2.ucCRTC = radeon_crtc->crtc_id; 1854 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1855 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1856 1857 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1858 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1859 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1860 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1861 else 1862 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1863 } else 1864 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1865 switch (radeon_encoder->encoder_id) { 1866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1867 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1870 dig = radeon_encoder->enc_priv; 1871 switch (dig->dig_encoder) { 1872 case 0: 1873 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1874 break; 1875 case 1: 1876 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1877 break; 1878 case 2: 1879 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1880 break; 1881 case 3: 1882 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1883 break; 1884 case 4: 1885 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1886 break; 1887 case 5: 1888 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1889 break; 1890 } 1891 break; 1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1893 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1894 break; 1895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1896 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1897 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1898 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1899 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1900 else 1901 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1902 break; 1903 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1904 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1905 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1906 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1907 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1908 else 1909 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1910 break; 1911 } 1912 break; 1913 } 1914 break; 1915 default: 1916 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1917 return; 1918 } 1919 1920 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1921 1922 /* update scratch regs with new routing */ 1923 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1924} 1925 1926static void 1927atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1928 struct drm_display_mode *mode) 1929{ 1930 struct drm_device *dev = encoder->dev; 1931 struct radeon_device *rdev = dev->dev_private; 1932 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1933 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1934 1935 /* Funky macbooks */ 1936 if ((dev->pci_device == 0x71C5) && 1937 (dev->pci_subvendor == 0x106b) && 1938 (dev->pci_subdevice == 0x0080)) { 1939 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1940 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1941 1942 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1943 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1944 1945 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1946 } 1947 } 1948 1949 /* set scaler clears this on some chips */ 1950 if (ASIC_IS_AVIVO(rdev) && 1951 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1952 if (ASIC_IS_DCE4(rdev)) { 1953 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1954 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1955 EVERGREEN_INTERLEAVE_EN); 1956 else 1957 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1958 } else { 1959 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1960 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1961 AVIVO_D1MODE_INTERLEAVE_EN); 1962 else 1963 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1964 } 1965 } 1966} 1967 1968static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1969{ 1970 struct drm_device *dev = encoder->dev; 1971 struct radeon_device *rdev = dev->dev_private; 1972 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1973 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1974 struct drm_encoder *test_encoder; 1975 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1976 uint32_t dig_enc_in_use = 0; 1977 1978 if (ASIC_IS_DCE6(rdev)) { 1979 /* DCE6 */ 1980 switch (radeon_encoder->encoder_id) { 1981 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1982 if (dig->linkb) 1983 return 1; 1984 else 1985 return 0; 1986 break; 1987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1988 if (dig->linkb) 1989 return 3; 1990 else 1991 return 2; 1992 break; 1993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1994 if (dig->linkb) 1995 return 5; 1996 else 1997 return 4; 1998 break; 1999 } 2000 } else if (ASIC_IS_DCE4(rdev)) { 2001 /* DCE4/5 */ 2002 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2003 /* ontario follows DCE4 */ 2004 if (rdev->family == CHIP_PALM) { 2005 if (dig->linkb) 2006 return 1; 2007 else 2008 return 0; 2009 } else 2010 /* llano follows DCE3.2 */ 2011 return radeon_crtc->crtc_id; 2012 } else { 2013 switch (radeon_encoder->encoder_id) { 2014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2015 if (dig->linkb) 2016 return 1; 2017 else 2018 return 0; 2019 break; 2020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2021 if (dig->linkb) 2022 return 3; 2023 else 2024 return 2; 2025 break; 2026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2027 if (dig->linkb) 2028 return 5; 2029 else 2030 return 4; 2031 break; 2032 } 2033 } 2034 } 2035 2036 /* on DCE32 and encoder can driver any block so just crtc id */ 2037 if (ASIC_IS_DCE32(rdev)) { 2038 return radeon_crtc->crtc_id; 2039 } 2040 2041 /* on DCE3 - LVTMA can only be driven by DIGB */ 2042 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2043 struct radeon_encoder *radeon_test_encoder; 2044 2045 if (encoder == test_encoder) 2046 continue; 2047 2048 if (!radeon_encoder_is_digital(test_encoder)) 2049 continue; 2050 2051 radeon_test_encoder = to_radeon_encoder(test_encoder); 2052 dig = radeon_test_encoder->enc_priv; 2053 2054 if (dig->dig_encoder >= 0) 2055 dig_enc_in_use |= (1 << dig->dig_encoder); 2056 } 2057 2058 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2059 if (dig_enc_in_use & 0x2) 2060 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2061 return 1; 2062 } 2063 if (!(dig_enc_in_use & 1)) 2064 return 0; 2065 return 1; 2066} 2067 2068/* This only needs to be called once at startup */ 2069void 2070radeon_atom_encoder_init(struct radeon_device *rdev) 2071{ 2072 struct drm_device *dev = rdev->ddev; 2073 struct drm_encoder *encoder; 2074 2075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2076 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2077 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2078 2079 switch (radeon_encoder->encoder_id) { 2080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2081 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2082 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2083 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2084 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2085 break; 2086 default: 2087 break; 2088 } 2089 2090 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2091 atombios_external_encoder_setup(encoder, ext_encoder, 2092 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2093 } 2094} 2095 2096static void 2097radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2098 struct drm_display_mode *mode, 2099 struct drm_display_mode *adjusted_mode) 2100{ 2101 struct drm_device *dev = encoder->dev; 2102 struct radeon_device *rdev = dev->dev_private; 2103 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2104 2105 radeon_encoder->pixel_clock = adjusted_mode->clock; 2106 2107 /* need to call this here rather than in prepare() since we need some crtc info */ 2108 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2109 2110 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2111 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2112 atombios_yuv_setup(encoder, true); 2113 else 2114 atombios_yuv_setup(encoder, false); 2115 } 2116 2117 switch (radeon_encoder->encoder_id) { 2118 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2120 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2121 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2122 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2123 break; 2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2128 /* handled in dpms */ 2129 break; 2130 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2131 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2132 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2133 atombios_dvo_setup(encoder, ATOM_ENABLE); 2134 break; 2135 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2137 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2139 atombios_dac_setup(encoder, ATOM_ENABLE); 2140 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2141 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2142 atombios_tv_setup(encoder, ATOM_ENABLE); 2143 else 2144 atombios_tv_setup(encoder, ATOM_DISABLE); 2145 } 2146 break; 2147 } 2148 2149 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2150 2151 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2152 r600_hdmi_enable(encoder); 2153 if (ASIC_IS_DCE6(rdev)) 2154 ; /* TODO (use pointers instead of if-s?) */ 2155 else if (ASIC_IS_DCE4(rdev)) 2156 evergreen_hdmi_setmode(encoder, adjusted_mode); 2157 else 2158 r600_hdmi_setmode(encoder, adjusted_mode); 2159 } 2160} 2161 2162static bool 2163atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2164{ 2165 struct drm_device *dev = encoder->dev; 2166 struct radeon_device *rdev = dev->dev_private; 2167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2168 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2169 2170 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2171 ATOM_DEVICE_CV_SUPPORT | 2172 ATOM_DEVICE_CRT_SUPPORT)) { 2173 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2174 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2175 uint8_t frev, crev; 2176 2177 memset(&args, 0, sizeof(args)); 2178 2179 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2180 return false; 2181 2182 args.sDacload.ucMisc = 0; 2183 2184 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2185 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2186 args.sDacload.ucDacType = ATOM_DAC_A; 2187 else 2188 args.sDacload.ucDacType = ATOM_DAC_B; 2189 2190 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2191 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2192 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2193 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2194 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2195 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2196 if (crev >= 3) 2197 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2198 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2199 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2200 if (crev >= 3) 2201 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2202 } 2203 2204 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2205 2206 return true; 2207 } else 2208 return false; 2209} 2210 2211static enum drm_connector_status 2212radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2213{ 2214 struct drm_device *dev = encoder->dev; 2215 struct radeon_device *rdev = dev->dev_private; 2216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2217 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2218 uint32_t bios_0_scratch; 2219 2220 if (!atombios_dac_load_detect(encoder, connector)) { 2221 DRM_DEBUG_KMS("detect returned false \n"); 2222 return connector_status_unknown; 2223 } 2224 2225 if (rdev->family >= CHIP_R600) 2226 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2227 else 2228 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2229 2230 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2231 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2232 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2233 return connector_status_connected; 2234 } 2235 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2236 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2237 return connector_status_connected; 2238 } 2239 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2240 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2241 return connector_status_connected; 2242 } 2243 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2244 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2245 return connector_status_connected; /* CTV */ 2246 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2247 return connector_status_connected; /* STV */ 2248 } 2249 return connector_status_disconnected; 2250} 2251 2252static enum drm_connector_status 2253radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2254{ 2255 struct drm_device *dev = encoder->dev; 2256 struct radeon_device *rdev = dev->dev_private; 2257 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2258 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2259 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2260 u32 bios_0_scratch; 2261 2262 if (!ASIC_IS_DCE4(rdev)) 2263 return connector_status_unknown; 2264 2265 if (!ext_encoder) 2266 return connector_status_unknown; 2267 2268 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2269 return connector_status_unknown; 2270 2271 /* load detect on the dp bridge */ 2272 atombios_external_encoder_setup(encoder, ext_encoder, 2273 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2274 2275 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2276 2277 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2278 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2279 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2280 return connector_status_connected; 2281 } 2282 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2283 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2284 return connector_status_connected; 2285 } 2286 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2287 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2288 return connector_status_connected; 2289 } 2290 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2291 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2292 return connector_status_connected; /* CTV */ 2293 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2294 return connector_status_connected; /* STV */ 2295 } 2296 return connector_status_disconnected; 2297} 2298 2299void 2300radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2301{ 2302 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2303 2304 if (ext_encoder) 2305 /* ddc_setup on the dp bridge */ 2306 atombios_external_encoder_setup(encoder, ext_encoder, 2307 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2308 2309} 2310 2311static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2312{ 2313 struct radeon_device *rdev = encoder->dev->dev_private; 2314 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2315 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2316 2317 if ((radeon_encoder->active_device & 2318 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2319 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2320 ENCODER_OBJECT_ID_NONE)) { 2321 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2322 if (dig) { 2323 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2324 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2325 if (rdev->family >= CHIP_R600) 2326 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2327 else 2328 /* RS600/690/740 have only 1 afmt block */ 2329 dig->afmt = rdev->mode_info.afmt[0]; 2330 } 2331 } 2332 } 2333 2334 radeon_atom_output_lock(encoder, true); 2335 2336 if (connector) { 2337 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2338 2339 /* select the clock/data port if it uses a router */ 2340 if (radeon_connector->router.cd_valid) 2341 radeon_router_select_cd_port(radeon_connector); 2342 2343 /* turn eDP panel on for mode set */ 2344 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2345 atombios_set_edp_panel_power(connector, 2346 ATOM_TRANSMITTER_ACTION_POWER_ON); 2347 } 2348 2349 /* this is needed for the pll/ss setup to work correctly in some cases */ 2350 atombios_set_encoder_crtc_source(encoder); 2351} 2352 2353static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2354{ 2355 /* need to call this here as we need the crtc set up */ 2356 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2357 radeon_atom_output_lock(encoder, false); 2358} 2359 2360static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2361{ 2362 struct drm_device *dev = encoder->dev; 2363 struct radeon_device *rdev = dev->dev_private; 2364 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2365 struct radeon_encoder_atom_dig *dig; 2366 2367 /* check for pre-DCE3 cards with shared encoders; 2368 * can't really use the links individually, so don't disable 2369 * the encoder if it's in use by another connector 2370 */ 2371 if (!ASIC_IS_DCE3(rdev)) { 2372 struct drm_encoder *other_encoder; 2373 struct radeon_encoder *other_radeon_encoder; 2374 2375 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2376 other_radeon_encoder = to_radeon_encoder(other_encoder); 2377 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2378 drm_helper_encoder_in_use(other_encoder)) 2379 goto disable_done; 2380 } 2381 } 2382 2383 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2384 2385 switch (radeon_encoder->encoder_id) { 2386 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2388 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2389 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2390 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2391 break; 2392 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2393 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2395 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2396 /* handled in dpms */ 2397 break; 2398 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2399 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2401 atombios_dvo_setup(encoder, ATOM_DISABLE); 2402 break; 2403 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2404 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2405 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2407 atombios_dac_setup(encoder, ATOM_DISABLE); 2408 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2409 atombios_tv_setup(encoder, ATOM_DISABLE); 2410 break; 2411 } 2412 2413disable_done: 2414 if (radeon_encoder_is_digital(encoder)) { 2415 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2416 r600_hdmi_disable(encoder); 2417 dig = radeon_encoder->enc_priv; 2418 dig->dig_encoder = -1; 2419 } 2420 radeon_encoder->active_device = 0; 2421} 2422 2423/* these are handled by the primary encoders */ 2424static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2425{ 2426 2427} 2428 2429static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2430{ 2431 2432} 2433 2434static void 2435radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2436 struct drm_display_mode *mode, 2437 struct drm_display_mode *adjusted_mode) 2438{ 2439 2440} 2441 2442static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2443{ 2444 2445} 2446 2447static void 2448radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2449{ 2450 2451} 2452 2453static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2454 struct drm_display_mode *mode, 2455 struct drm_display_mode *adjusted_mode) 2456{ 2457 return true; 2458} 2459 2460static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2461 .dpms = radeon_atom_ext_dpms, 2462 .mode_fixup = radeon_atom_ext_mode_fixup, 2463 .prepare = radeon_atom_ext_prepare, 2464 .mode_set = radeon_atom_ext_mode_set, 2465 .commit = radeon_atom_ext_commit, 2466 .disable = radeon_atom_ext_disable, 2467 /* no detect for TMDS/LVDS yet */ 2468}; 2469 2470static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2471 .dpms = radeon_atom_encoder_dpms, 2472 .mode_fixup = radeon_atom_mode_fixup, 2473 .prepare = radeon_atom_encoder_prepare, 2474 .mode_set = radeon_atom_encoder_mode_set, 2475 .commit = radeon_atom_encoder_commit, 2476 .disable = radeon_atom_encoder_disable, 2477 .detect = radeon_atom_dig_detect, 2478}; 2479 2480static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2481 .dpms = radeon_atom_encoder_dpms, 2482 .mode_fixup = radeon_atom_mode_fixup, 2483 .prepare = radeon_atom_encoder_prepare, 2484 .mode_set = radeon_atom_encoder_mode_set, 2485 .commit = radeon_atom_encoder_commit, 2486 .detect = radeon_atom_dac_detect, 2487}; 2488 2489void radeon_enc_destroy(struct drm_encoder *encoder) 2490{ 2491 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2492 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2493 radeon_atom_backlight_exit(radeon_encoder); 2494 free(radeon_encoder->enc_priv, DRM_MEM_DRIVER); 2495 drm_encoder_cleanup(encoder); 2496 free(radeon_encoder, DRM_MEM_DRIVER); 2497} 2498 2499static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2500 .destroy = radeon_enc_destroy, 2501}; 2502 2503static struct radeon_encoder_atom_dac * 2504radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2505{ 2506 struct drm_device *dev = radeon_encoder->base.dev; 2507 struct radeon_device *rdev = dev->dev_private; 2508 struct radeon_encoder_atom_dac *dac = malloc(sizeof(struct radeon_encoder_atom_dac), 2509 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2510 2511 if (!dac) 2512 return NULL; 2513 2514 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2515 return dac; 2516} 2517 2518static struct radeon_encoder_atom_dig * 2519radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2520{ 2521 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2522 struct radeon_encoder_atom_dig *dig = malloc(sizeof(struct radeon_encoder_atom_dig), 2523 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2524 2525 if (!dig) 2526 return NULL; 2527 2528 /* coherent mode by default */ 2529 dig->coherent_mode = true; 2530 dig->dig_encoder = -1; 2531 2532 if (encoder_enum == 2) 2533 dig->linkb = true; 2534 else 2535 dig->linkb = false; 2536 2537 return dig; 2538} 2539 2540void 2541radeon_add_atom_encoder(struct drm_device *dev, 2542 uint32_t encoder_enum, 2543 uint32_t supported_device, 2544 u16 caps) 2545{ 2546 struct radeon_device *rdev = dev->dev_private; 2547 struct drm_encoder *encoder; 2548 struct radeon_encoder *radeon_encoder; 2549 2550 /* see if we already added it */ 2551 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2552 radeon_encoder = to_radeon_encoder(encoder); 2553 if (radeon_encoder->encoder_enum == encoder_enum) { 2554 radeon_encoder->devices |= supported_device; 2555 return; 2556 } 2557 2558 } 2559 2560 /* add a new one */ 2561 radeon_encoder = malloc(sizeof(struct radeon_encoder), 2562 DRM_MEM_DRIVER, M_ZERO | M_WAITOK); 2563 if (!radeon_encoder) 2564 return; 2565 2566 encoder = &radeon_encoder->base; 2567 switch (rdev->num_crtc) { 2568 case 1: 2569 encoder->possible_crtcs = 0x1; 2570 break; 2571 case 2: 2572 default: 2573 encoder->possible_crtcs = 0x3; 2574 break; 2575 case 4: 2576 encoder->possible_crtcs = 0xf; 2577 break; 2578 case 6: 2579 encoder->possible_crtcs = 0x3f; 2580 break; 2581 } 2582 2583 radeon_encoder->enc_priv = NULL; 2584 2585 radeon_encoder->encoder_enum = encoder_enum; 2586 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2587 radeon_encoder->devices = supported_device; 2588 radeon_encoder->rmx_type = RMX_OFF; 2589 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2590 radeon_encoder->is_ext_encoder = false; 2591 radeon_encoder->caps = caps; 2592 2593 switch (radeon_encoder->encoder_id) { 2594 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2595 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2596 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2599 radeon_encoder->rmx_type = RMX_FULL; 2600 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2601 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2602 } else { 2603 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2604 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2605 } 2606 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2607 break; 2608 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2609 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2610 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2611 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2612 break; 2613 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2615 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2616 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2617 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2618 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2619 break; 2620 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2621 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2622 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2623 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2624 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2625 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2626 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2628 radeon_encoder->rmx_type = RMX_FULL; 2629 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2630 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2631 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2632 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2633 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2634 } else { 2635 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2636 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2637 } 2638 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2639 break; 2640 case ENCODER_OBJECT_ID_SI170B: 2641 case ENCODER_OBJECT_ID_CH7303: 2642 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2643 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2644 case ENCODER_OBJECT_ID_TITFP513: 2645 case ENCODER_OBJECT_ID_VT1623: 2646 case ENCODER_OBJECT_ID_HDMI_SI1930: 2647 case ENCODER_OBJECT_ID_TRAVIS: 2648 case ENCODER_OBJECT_ID_NUTMEG: 2649 /* these are handled by the primary encoders */ 2650 radeon_encoder->is_ext_encoder = true; 2651 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2653 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2654 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2655 else 2656 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2657 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2658 break; 2659 } 2660} 2661