i915_drv.h revision 271816
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/i915/i915_drv.h 271816 2014-09-18 20:32:40Z dumbbell $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36#include <dev/agp/agp_i810.h> 37#include <dev/drm2/drm_mm.h> 38#include <dev/drm2/i915/i915_reg.h> 39#include <dev/drm2/i915/intel_ringbuffer.h> 40#include <dev/drm2/i915/intel_bios.h> 41 42/* General customization: 43 */ 44 45#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47#define DRIVER_NAME "i915" 48#define DRIVER_DESC "Intel Graphics" 49#define DRIVER_DATE "20080730" 50 51MALLOC_DECLARE(DRM_I915_GEM); 52 53enum pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58}; 59#define pipe_name(p) ((p) + 'A') 60#define I915_NUM_PIPE 2 61 62enum plane { 63 PLANE_A = 0, 64 PLANE_B, 65 PLANE_C, 66}; 67#define plane_name(p) ((p) + 'A') 68 69#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 70 71#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 72 73/* Interface history: 74 * 75 * 1.1: Original. 76 * 1.2: Add Power Management 77 * 1.3: Add vblank support 78 * 1.4: Fix cmdbuffer path, add heap destroy 79 * 1.5: Add vblank pipe configuration 80 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 81 * - Support vertical blank on secondary display pipe 82 */ 83#define DRIVER_MAJOR 1 84#define DRIVER_MINOR 6 85#define DRIVER_PATCHLEVEL 0 86 87#define WATCH_COHERENCY 0 88#define WATCH_BUF 0 89#define WATCH_EXEC 0 90#define WATCH_LRU 0 91#define WATCH_RELOC 0 92#define WATCH_INACTIVE 0 93#define WATCH_PWRITE 0 94 95#define I915_GEM_PHYS_CURSOR_0 1 96#define I915_GEM_PHYS_CURSOR_1 2 97#define I915_GEM_PHYS_OVERLAY_REGS 3 98#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 99 100struct drm_i915_gem_phys_object { 101 int id; 102 drm_dma_handle_t *handle; 103 struct drm_i915_gem_object *cur_obj; 104}; 105 106struct drm_i915_private; 107 108struct drm_i915_display_funcs { 109 void (*dpms)(struct drm_crtc *crtc, int mode); 110 bool (*fbc_enabled)(struct drm_device *dev); 111 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 112 void (*disable_fbc)(struct drm_device *dev); 113 int (*get_display_clock_speed)(struct drm_device *dev); 114 int (*get_fifo_size)(struct drm_device *dev, int plane); 115 void (*update_wm)(struct drm_device *dev); 116 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 117 uint32_t sprite_width, int pixel_size); 118 int (*crtc_mode_set)(struct drm_crtc *crtc, 119 struct drm_display_mode *mode, 120 struct drm_display_mode *adjusted_mode, 121 int x, int y, 122 struct drm_framebuffer *old_fb); 123 void (*write_eld)(struct drm_connector *connector, 124 struct drm_crtc *crtc); 125 void (*fdi_link_train)(struct drm_crtc *crtc); 126 void (*init_clock_gating)(struct drm_device *dev); 127 void (*init_pch_clock_gating)(struct drm_device *dev); 128 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 129 struct drm_framebuffer *fb, 130 struct drm_i915_gem_object *obj); 131 void (*force_wake_get)(struct drm_i915_private *dev_priv); 132 void (*force_wake_put)(struct drm_i915_private *dev_priv); 133 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 134 int x, int y); 135 /* clock updates for mode set */ 136 /* cursor updates */ 137 /* render clock increase/decrease */ 138 /* display clock increase/decrease */ 139 /* pll clock increase/decrease */ 140}; 141 142struct intel_device_info { 143 u8 gen; 144 u8 is_mobile:1; 145 u8 is_i85x:1; 146 u8 is_i915g:1; 147 u8 is_i945gm:1; 148 u8 is_g33:1; 149 u8 need_gfx_hws:1; 150 u8 is_g4x:1; 151 u8 is_pineview:1; 152 u8 is_broadwater:1; 153 u8 is_crestline:1; 154 u8 is_ivybridge:1; 155 u8 has_fbc:1; 156 u8 has_pipe_cxsr:1; 157 u8 has_hotplug:1; 158 u8 cursor_needs_physical:1; 159 u8 has_overlay:1; 160 u8 overlay_needs_physical:1; 161 u8 supports_tv:1; 162 u8 has_bsd_ring:1; 163 u8 has_blt_ring:1; 164 u8 has_llc:1; 165}; 166 167#define I915_PPGTT_PD_ENTRIES 512 168#define I915_PPGTT_PT_ENTRIES 1024 169struct i915_hw_ppgtt { 170 unsigned num_pd_entries; 171 vm_page_t *pt_pages; 172 uint32_t pd_offset; 173 vm_paddr_t *pt_dma_addr; 174 vm_paddr_t scratch_page_dma_addr; 175}; 176 177 178/* This must match up with the value previously used for execbuf2.rsvd1. */ 179#define DEFAULT_CONTEXT_ID 0 180struct i915_hw_context { 181 uint32_t id; 182 bool is_initialized; 183 struct drm_i915_file_private *file_priv; 184 struct intel_ring_buffer *ring; 185 struct drm_i915_gem_object *obj; 186}; 187 188enum no_fbc_reason { 189 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 190 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 191 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 192 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 193 FBC_BAD_PLANE, /* fbc not supported on plane */ 194 FBC_NOT_TILED, /* buffer not tiled */ 195 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 196 FBC_MODULE_PARAM, 197}; 198 199struct mem_block { 200 struct mem_block *next; 201 struct mem_block *prev; 202 int start; 203 int size; 204 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 205}; 206 207struct opregion_header; 208struct opregion_acpi; 209struct opregion_swsci; 210struct opregion_asle; 211 212struct intel_opregion { 213 struct opregion_header *header; 214 struct opregion_acpi *acpi; 215 struct opregion_swsci *swsci; 216 struct opregion_asle *asle; 217 void *vbt; 218 u32 *lid_state; 219}; 220#define OPREGION_SIZE (8*1024) 221 222#define I915_FENCE_REG_NONE -1 223#define I915_MAX_NUM_FENCES 16 224/* 16 fences + sign bit for FENCE_REG_NONE */ 225#define I915_MAX_NUM_FENCE_BITS 5 226 227struct drm_i915_fence_reg { 228 struct list_head lru_list; 229 struct drm_i915_gem_object *obj; 230 uint32_t setup_seqno; 231 int pin_count; 232}; 233 234struct sdvo_device_mapping { 235 u8 initialized; 236 u8 dvo_port; 237 u8 slave_addr; 238 u8 dvo_wiring; 239 u8 i2c_pin; 240 u8 ddc_pin; 241}; 242 243enum intel_pch { 244 PCH_IBX, /* Ibexpeak PCH */ 245 PCH_CPT, /* Cougarpoint PCH */ 246}; 247 248#define QUIRK_PIPEA_FORCE (1<<0) 249#define QUIRK_LVDS_SSC_DISABLE (1<<1) 250 251struct intel_fbdev; 252struct intel_fbc_work; 253 254typedef struct drm_i915_private { 255 struct drm_device *dev; 256 257 device_t *gmbus_bridge; 258 device_t *bbbus_bridge; 259 device_t *gmbus; 260 device_t *bbbus; 261 /** gmbus_sx protects against concurrent usage of the single hw gmbus 262 * controller on different i2c buses. */ 263 struct sx gmbus_sx; 264 265 int has_gem; 266 int relative_constants_mode; 267 268 drm_local_map_t *sarea; 269 drm_local_map_t *mmio_map; 270 271 /** gt_fifo_count and the subsequent register write are synchronized 272 * with dev->struct_mutex. */ 273 unsigned gt_fifo_count; 274 /** forcewake_count is protected by gt_lock */ 275 unsigned forcewake_count; 276 /** gt_lock is also taken in irq contexts. */ 277 struct mtx gt_lock; 278 279 drm_i915_sarea_t *sarea_priv; 280 /* drm_i915_ring_buffer_t ring; */ 281 struct intel_ring_buffer rings[I915_NUM_RINGS]; 282 uint32_t next_seqno; 283 284 drm_dma_handle_t *status_page_dmah; 285 void *hw_status_page; 286 dma_addr_t dma_status_page; 287 uint32_t counter; 288 unsigned int status_gfx_addr; 289 drm_local_map_t hws_map; 290 struct drm_gem_object *hws_obj; 291 292 struct drm_i915_gem_object *pwrctx; 293 struct drm_i915_gem_object *renderctx; 294 295 unsigned int cpp; 296 int back_offset; 297 int front_offset; 298 int current_page; 299 int page_flipping; 300 301 atomic_t irq_received; 302 u32 trace_irq_seqno; 303 304 /** Cached value of IER to avoid reads in updating the bitfield */ 305 u32 pipestat[2]; 306 u32 irq_mask; 307 u32 gt_irq_mask; 308 u32 pch_irq_mask; 309 struct mtx irq_lock; 310 311 u32 hotplug_supported_mask; 312 313 int tex_lru_log_granularity; 314 int allow_batchbuffer; 315 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 316 int vblank_pipe; 317 int num_pipe; 318 319 /* For hangcheck timer */ 320#define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 321 int hangcheck_count; 322 uint32_t last_acthd; 323 uint32_t last_acthd_bsd; 324 uint32_t last_acthd_blt; 325 uint32_t last_instdone; 326 uint32_t last_instdone1; 327 328 struct intel_opregion opregion; 329 330 331 /* overlay */ 332 struct intel_overlay *overlay; 333 bool sprite_scaling_enabled; 334 335 /* LVDS info */ 336 int backlight_level; /* restore backlight to this value */ 337 bool backlight_enabled; 338 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 339 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 340 341 /* Feature bits from the VBIOS */ 342 unsigned int int_tv_support:1; 343 unsigned int lvds_dither:1; 344 unsigned int lvds_vbt:1; 345 unsigned int int_crt_support:1; 346 unsigned int lvds_use_ssc:1; 347 unsigned int display_clock_mode:1; 348 int lvds_ssc_freq; 349 struct { 350 int rate; 351 int lanes; 352 int preemphasis; 353 int vswing; 354 355 bool initialized; 356 bool support; 357 int bpp; 358 struct edp_power_seq pps; 359 } edp; 360 bool no_aux_handshake; 361 362 int crt_ddc_pin; 363 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 364 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 365 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 366 367 /* PCH chipset type */ 368 enum intel_pch pch_type; 369 370 /* Display functions */ 371 struct drm_i915_display_funcs display; 372 373 unsigned long quirks; 374 375 /* Register state */ 376 bool modeset_on_lid; 377 u8 saveLBB; 378 u32 saveDSPACNTR; 379 u32 saveDSPBCNTR; 380 u32 saveDSPARB; 381 u32 saveHWS; 382 u32 savePIPEACONF; 383 u32 savePIPEBCONF; 384 u32 savePIPEASRC; 385 u32 savePIPEBSRC; 386 u32 saveFPA0; 387 u32 saveFPA1; 388 u32 saveDPLL_A; 389 u32 saveDPLL_A_MD; 390 u32 saveHTOTAL_A; 391 u32 saveHBLANK_A; 392 u32 saveHSYNC_A; 393 u32 saveVTOTAL_A; 394 u32 saveVBLANK_A; 395 u32 saveVSYNC_A; 396 u32 saveBCLRPAT_A; 397 u32 saveTRANSACONF; 398 u32 saveTRANS_HTOTAL_A; 399 u32 saveTRANS_HBLANK_A; 400 u32 saveTRANS_HSYNC_A; 401 u32 saveTRANS_VTOTAL_A; 402 u32 saveTRANS_VBLANK_A; 403 u32 saveTRANS_VSYNC_A; 404 u32 savePIPEASTAT; 405 u32 saveDSPASTRIDE; 406 u32 saveDSPASIZE; 407 u32 saveDSPAPOS; 408 u32 saveDSPAADDR; 409 u32 saveDSPASURF; 410 u32 saveDSPATILEOFF; 411 u32 savePFIT_PGM_RATIOS; 412 u32 saveBLC_HIST_CTL; 413 u32 saveBLC_PWM_CTL; 414 u32 saveBLC_PWM_CTL2; 415 u32 saveBLC_CPU_PWM_CTL; 416 u32 saveBLC_CPU_PWM_CTL2; 417 u32 saveFPB0; 418 u32 saveFPB1; 419 u32 saveDPLL_B; 420 u32 saveDPLL_B_MD; 421 u32 saveHTOTAL_B; 422 u32 saveHBLANK_B; 423 u32 saveHSYNC_B; 424 u32 saveVTOTAL_B; 425 u32 saveVBLANK_B; 426 u32 saveVSYNC_B; 427 u32 saveBCLRPAT_B; 428 u32 saveTRANSBCONF; 429 u32 saveTRANS_HTOTAL_B; 430 u32 saveTRANS_HBLANK_B; 431 u32 saveTRANS_HSYNC_B; 432 u32 saveTRANS_VTOTAL_B; 433 u32 saveTRANS_VBLANK_B; 434 u32 saveTRANS_VSYNC_B; 435 u32 savePIPEBSTAT; 436 u32 saveDSPBSTRIDE; 437 u32 saveDSPBSIZE; 438 u32 saveDSPBPOS; 439 u32 saveDSPBADDR; 440 u32 saveDSPBSURF; 441 u32 saveDSPBTILEOFF; 442 u32 saveVGA0; 443 u32 saveVGA1; 444 u32 saveVGA_PD; 445 u32 saveVGACNTRL; 446 u32 saveADPA; 447 u32 saveLVDS; 448 u32 savePP_ON_DELAYS; 449 u32 savePP_OFF_DELAYS; 450 u32 saveDVOA; 451 u32 saveDVOB; 452 u32 saveDVOC; 453 u32 savePP_ON; 454 u32 savePP_OFF; 455 u32 savePP_CONTROL; 456 u32 savePP_DIVISOR; 457 u32 savePFIT_CONTROL; 458 u32 save_palette_a[256]; 459 u32 save_palette_b[256]; 460 u32 saveDPFC_CB_BASE; 461 u32 saveFBC_CFB_BASE; 462 u32 saveFBC_LL_BASE; 463 u32 saveFBC_CONTROL; 464 u32 saveFBC_CONTROL2; 465 u32 saveIER; 466 u32 saveIIR; 467 u32 saveIMR; 468 u32 saveDEIER; 469 u32 saveDEIMR; 470 u32 saveGTIER; 471 u32 saveGTIMR; 472 u32 saveFDI_RXA_IMR; 473 u32 saveFDI_RXB_IMR; 474 u32 saveCACHE_MODE_0; 475 u32 saveMI_ARB_STATE; 476 u32 saveSWF0[16]; 477 u32 saveSWF1[16]; 478 u32 saveSWF2[3]; 479 u8 saveMSR; 480 u8 saveSR[8]; 481 u8 saveGR[25]; 482 u8 saveAR_INDEX; 483 u8 saveAR[21]; 484 u8 saveDACMASK; 485 u8 saveCR[37]; 486 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 487 u32 saveCURACNTR; 488 u32 saveCURAPOS; 489 u32 saveCURABASE; 490 u32 saveCURBCNTR; 491 u32 saveCURBPOS; 492 u32 saveCURBBASE; 493 u32 saveCURSIZE; 494 u32 saveDP_B; 495 u32 saveDP_C; 496 u32 saveDP_D; 497 u32 savePIPEA_GMCH_DATA_M; 498 u32 savePIPEB_GMCH_DATA_M; 499 u32 savePIPEA_GMCH_DATA_N; 500 u32 savePIPEB_GMCH_DATA_N; 501 u32 savePIPEA_DP_LINK_M; 502 u32 savePIPEB_DP_LINK_M; 503 u32 savePIPEA_DP_LINK_N; 504 u32 savePIPEB_DP_LINK_N; 505 u32 saveFDI_RXA_CTL; 506 u32 saveFDI_TXA_CTL; 507 u32 saveFDI_RXB_CTL; 508 u32 saveFDI_TXB_CTL; 509 u32 savePFA_CTL_1; 510 u32 savePFB_CTL_1; 511 u32 savePFA_WIN_SZ; 512 u32 savePFB_WIN_SZ; 513 u32 savePFA_WIN_POS; 514 u32 savePFB_WIN_POS; 515 u32 savePCH_DREF_CONTROL; 516 u32 saveDISP_ARB_CTL; 517 u32 savePIPEA_DATA_M1; 518 u32 savePIPEA_DATA_N1; 519 u32 savePIPEA_LINK_M1; 520 u32 savePIPEA_LINK_N1; 521 u32 savePIPEB_DATA_M1; 522 u32 savePIPEB_DATA_N1; 523 u32 savePIPEB_LINK_M1; 524 u32 savePIPEB_LINK_N1; 525 u32 saveMCHBAR_RENDER_STANDBY; 526 u32 savePCH_PORT_HOTPLUG; 527 528 struct { 529 /** Memory allocator for GTT stolen memory */ 530 struct drm_mm stolen; 531 /** Memory allocator for GTT */ 532 struct drm_mm gtt_space; 533 /** List of all objects in gtt_space. Used to restore gtt 534 * mappings on resume */ 535 struct list_head gtt_list; 536 537 /** Usable portion of the GTT for GEM */ 538 unsigned long gtt_start; 539 unsigned long gtt_mappable_end; 540 unsigned long gtt_end; 541 542 /** PPGTT used for aliasing the PPGTT with the GTT */ 543 struct i915_hw_ppgtt *aliasing_ppgtt; 544 545 /** 546 * List of objects currently involved in rendering from the 547 * ringbuffer. 548 * 549 * Includes buffers having the contents of their GPU caches 550 * flushed, not necessarily primitives. last_rendering_seqno 551 * represents when the rendering involved will be completed. 552 * 553 * A reference is held on the buffer while on this list. 554 */ 555 struct list_head active_list; 556 557 /** 558 * List of objects which are not in the ringbuffer but which 559 * still have a write_domain which needs to be flushed before 560 * unbinding. 561 * 562 * A reference is held on the buffer while on this list. 563 */ 564 struct list_head flushing_list; 565 566 /** 567 * LRU list of objects which are not in the ringbuffer and 568 * are ready to unbind, but are still in the GTT. 569 * 570 * last_rendering_seqno is 0 while an object is in this list. 571 * 572 * A reference is not held on the buffer while on this list, 573 * as merely being GTT-bound shouldn't prevent its being 574 * freed, and we'll pull it off the list in the free path. 575 */ 576 struct list_head inactive_list; 577 578 /** 579 * LRU list of objects which are not in the ringbuffer but 580 * are still pinned in the GTT. 581 */ 582 struct list_head pinned_list; 583 584 /** LRU list of objects with fence regs on them. */ 585 struct list_head fence_list; 586 587 /** 588 * List of objects currently pending being freed. 589 * 590 * These objects are no longer in use, but due to a signal 591 * we were prevented from freeing them at the appointed time. 592 */ 593 struct list_head deferred_free_list; 594 595 /** 596 * We leave the user IRQ off as much as possible, 597 * but this means that requests will finish and never 598 * be retired once the system goes idle. Set a timer to 599 * fire periodically while the ring is running. When it 600 * fires, go retire requests. 601 */ 602 struct timeout_task retire_task; 603 604 /** 605 * Are we in a non-interruptible section of code like 606 * modesetting? 607 */ 608 bool interruptible; 609 610 uint32_t next_gem_seqno; 611 612 /** 613 * Waiting sequence number, if any 614 */ 615 uint32_t waiting_gem_seqno; 616 617 /** 618 * Last seq seen at irq time 619 */ 620 uint32_t irq_gem_seqno; 621 622 /** 623 * Flag if the X Server, and thus DRM, is not currently in 624 * control of the device. 625 * 626 * This is set between LeaveVT and EnterVT. It needs to be 627 * replaced with a semaphore. It also needs to be 628 * transitioned away from for kernel modesetting. 629 */ 630 int suspended; 631 632 /** 633 * Flag if the hardware appears to be wedged. 634 * 635 * This is set when attempts to idle the device timeout. 636 * It prevents command submission from occuring and makes 637 * every pending request fail 638 */ 639 int wedged; 640 641 /** Bit 6 swizzling required for X tiling */ 642 uint32_t bit_6_swizzle_x; 643 /** Bit 6 swizzling required for Y tiling */ 644 uint32_t bit_6_swizzle_y; 645 646 /* storage for physical objects */ 647 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 648 649 /* accounting, useful for userland debugging */ 650 size_t gtt_total; 651 size_t mappable_gtt_total; 652 size_t object_memory; 653 u32 object_count; 654 655 struct intel_gtt gtt; 656 eventhandler_tag i915_lowmem; 657 } mm; 658 659 const struct intel_device_info *info; 660 661 struct sdvo_device_mapping sdvo_mappings[2]; 662 /* indicate whether the LVDS_BORDER should be enabled or not */ 663 unsigned int lvds_border_bits; 664 /* Panel fitter placement and size for Ironlake+ */ 665 u32 pch_pf_pos, pch_pf_size; 666 667 struct drm_crtc *plane_to_crtc_mapping[3]; 668 struct drm_crtc *pipe_to_crtc_mapping[3]; 669 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 670 bool flip_pending_is_done; 671 672 /* Reclocking support */ 673 bool render_reclock_avail; 674 bool lvds_downclock_avail; 675 /* indicates the reduced downclock for LVDS*/ 676 int lvds_downclock; 677 struct task idle_task; 678 struct callout idle_callout; 679 bool busy; 680 u16 orig_clock; 681 int child_dev_num; 682 struct child_device_config *child_dev; 683 struct drm_connector *int_lvds_connector; 684 struct drm_connector *int_edp_connector; 685 686 device_t bridge_dev; 687 bool mchbar_need_disable; 688 int mch_res_rid; 689 struct resource *mch_res; 690 691 struct mtx rps_lock; 692 u32 pm_iir; 693 struct task rps_task; 694 695 u8 cur_delay; 696 u8 min_delay; 697 u8 max_delay; 698 u8 fmax; 699 u8 fstart; 700 701 u64 last_count1; 702 unsigned long last_time1; 703 unsigned long chipset_power; 704 u64 last_count2; 705 struct timespec last_time2; 706 unsigned long gfx_power; 707 int c_m; 708 int r_t; 709 u8 corr; 710 struct mtx *mchdev_lock; 711 712 enum no_fbc_reason no_fbc_reason; 713 714 unsigned int stop_rings; 715 716 unsigned long cfb_size; 717 unsigned int cfb_fb; 718 int cfb_plane; 719 int cfb_y; 720 struct intel_fbc_work *fbc_work; 721 722 unsigned int fsb_freq, mem_freq, is_ddr3; 723 724 struct taskqueue *tq; 725 struct task error_task; 726 struct task hotplug_task; 727 int error_completion; 728 struct mtx error_completion_lock; 729 struct drm_i915_error_state *first_error; 730 struct mtx error_lock; 731 struct callout hangcheck_timer; 732 733 unsigned long last_gpu_reset; 734 735 struct intel_fbdev *fbdev; 736 737 struct drm_property *broadcast_rgb_property; 738 struct drm_property *force_audio_property; 739 740 bool hw_contexts_disabled; 741 uint32_t hw_context_size; 742} drm_i915_private_t; 743 744/* Iterate over initialised rings */ 745#define for_each_ring(ring__, dev_priv__, i__) \ 746 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 747 if (((ring__) = &(dev_priv__)->rings[(i__)]), intel_ring_initialized((ring__))) 748 749enum hdmi_force_audio { 750 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 751 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 752 HDMI_AUDIO_AUTO, /* trust EDID */ 753 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 754}; 755 756enum i915_cache_level { 757 I915_CACHE_NONE, 758 I915_CACHE_LLC, 759 I915_CACHE_LLC_MLC, /* gen6+ */ 760}; 761 762enum intel_chip_family { 763 CHIP_I8XX = 0x01, 764 CHIP_I9XX = 0x02, 765 CHIP_I915 = 0x04, 766 CHIP_I965 = 0x08, 767}; 768 769/** driver private structure attached to each drm_gem_object */ 770struct drm_i915_gem_object { 771 struct drm_gem_object base; 772 773 /** Current space allocated to this object in the GTT, if any. */ 774 struct drm_mm_node *gtt_space; 775 struct list_head gtt_list; 776 /** This object's place on the active/flushing/inactive lists */ 777 struct list_head ring_list; 778 struct list_head mm_list; 779 /** This object's place on GPU write list */ 780 struct list_head gpu_write_list; 781 /** This object's place in the batchbuffer or on the eviction list */ 782 struct list_head exec_list; 783 784 /** 785 * This is set if the object is on the active or flushing lists 786 * (has pending rendering), and is not set if it's on inactive (ready 787 * to be unbound). 788 */ 789 unsigned int active:1; 790 791 /** 792 * This is set if the object has been written to since last bound 793 * to the GTT 794 */ 795 unsigned int dirty:1; 796 797 /** 798 * This is set if the object has been written to since the last 799 * GPU flush. 800 */ 801 unsigned int pending_gpu_write:1; 802 803 /** 804 * Fence register bits (if any) for this object. Will be set 805 * as needed when mapped into the GTT. 806 * Protected by dev->struct_mutex. 807 */ 808 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 809 810 /** 811 * Advice: are the backing pages purgeable? 812 */ 813 unsigned int madv:2; 814 815 /** 816 * Current tiling mode for the object. 817 */ 818 unsigned int tiling_mode:2; 819 unsigned int tiling_changed:1; 820 821 /** How many users have pinned this object in GTT space. The following 822 * users can each hold at most one reference: pwrite/pread, pin_ioctl 823 * (via user_pin_count), execbuffer (objects are not allowed multiple 824 * times for the same batchbuffer), and the framebuffer code. When 825 * switching/pageflipping, the framebuffer code has at most two buffers 826 * pinned per crtc. 827 * 828 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 829 * bits with absolutely no headroom. So use 4 bits. */ 830 unsigned int pin_count:4; 831#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 832 833 /** 834 * Is the object at the current location in the gtt mappable and 835 * fenceable? Used to avoid costly recalculations. 836 */ 837 unsigned int map_and_fenceable:1; 838 839 /** 840 * Whether the current gtt mapping needs to be mappable (and isn't just 841 * mappable by accident). Track pin and fault separate for a more 842 * accurate mappable working set. 843 */ 844 unsigned int fault_mappable:1; 845 unsigned int pin_mappable:1; 846 847 /* 848 * Is the GPU currently using a fence to access this buffer, 849 */ 850 unsigned int pending_fenced_gpu_access:1; 851 unsigned int fenced_gpu_access:1; 852 853 unsigned int cache_level:2; 854 855 unsigned int has_aliasing_ppgtt_mapping:1; 856 unsigned int has_global_gtt_mapping:1; 857 858 vm_page_t *pages; 859 860 /** 861 * DMAR support 862 */ 863 struct sglist *sg_list; 864 865 /** 866 * Used for performing relocations during execbuffer insertion. 867 */ 868 LIST_ENTRY(drm_i915_gem_object) exec_node; 869 unsigned long exec_handle; 870 struct drm_i915_gem_exec_object2 *exec_entry; 871 872 /** 873 * Current offset of the object in GTT space. 874 * 875 * This is the same as gtt_space->start 876 */ 877 uint32_t gtt_offset; 878 879 /** Breadcrumb of last rendering to the buffer. */ 880 uint32_t last_rendering_seqno; 881 struct intel_ring_buffer *ring; 882 883 /** Breadcrumb of last fenced GPU access to the buffer. */ 884 uint32_t last_fenced_seqno; 885 struct intel_ring_buffer *last_fenced_ring; 886 887 /** Current tiling stride for the object, if it's tiled. */ 888 uint32_t stride; 889 890 /** Record of address bit 17 of each page at last unbind. */ 891 unsigned long *bit_17; 892 893 /** 894 * If present, while GEM_DOMAIN_CPU is in the read domain this array 895 * flags which individual pages are valid. 896 */ 897 uint8_t *page_cpu_valid; 898 899 /** User space pin count and filp owning the pin */ 900 uint32_t user_pin_count; 901 struct drm_file *pin_filp; 902 903 /** for phy allocated objects */ 904 struct drm_i915_gem_phys_object *phys_obj; 905 906 /** 907 * Number of crtcs where this object is currently the fb, but 908 * will be page flipped away on the next vblank. When it 909 * reaches 0, dev_priv->pending_flip_queue will be woken up. 910 */ 911 int pending_flip; 912}; 913 914#define to_intel_bo(x) __containerof(x, struct drm_i915_gem_object, base) 915 916/** 917 * Request queue structure. 918 * 919 * The request queue allows us to note sequence numbers that have been emitted 920 * and may be associated with active buffers to be retired. 921 * 922 * By keeping this list, we can avoid having to do questionable 923 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 924 * an emission time with seqnos for tracking how far ahead of the GPU we are. 925 */ 926struct drm_i915_gem_request { 927 /** On Which ring this request was generated */ 928 struct intel_ring_buffer *ring; 929 930 /** GEM sequence number associated with this request. */ 931 uint32_t seqno; 932 933 /** Postion in the ringbuffer of the end of the request */ 934 u32 tail; 935 936 /** Time at which this request was emitted, in jiffies. */ 937 unsigned long emitted_jiffies; 938 939 /** global list entry for this request */ 940 struct list_head list; 941 942 struct drm_i915_file_private *file_priv; 943 /** file_priv list entry for this request */ 944 struct list_head client_list; 945}; 946 947struct drm_i915_file_private { 948 struct { 949 struct list_head request_list; 950 struct mtx lck; 951 } mm; 952 struct drm_gem_names context_idr; 953}; 954 955struct drm_i915_error_state { 956 u32 eir; 957 u32 pgtbl_er; 958 u32 pipestat[I915_MAX_PIPES]; 959 u32 tail[I915_NUM_RINGS]; 960 u32 head[I915_NUM_RINGS]; 961 u32 ipeir[I915_NUM_RINGS]; 962 u32 ipehr[I915_NUM_RINGS]; 963 u32 instdone[I915_NUM_RINGS]; 964 u32 acthd[I915_NUM_RINGS]; 965 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 966 /* our own tracking of ring head and tail */ 967 u32 cpu_ring_head[I915_NUM_RINGS]; 968 u32 cpu_ring_tail[I915_NUM_RINGS]; 969 u32 error; /* gen6+ */ 970 u32 instpm[I915_NUM_RINGS]; 971 u32 instps[I915_NUM_RINGS]; 972 u32 instdone1; 973 u32 seqno[I915_NUM_RINGS]; 974 u64 bbaddr; 975 u32 fault_reg[I915_NUM_RINGS]; 976 u32 done_reg; 977 u32 faddr[I915_NUM_RINGS]; 978 u64 fence[I915_MAX_NUM_FENCES]; 979 struct timeval time; 980 struct drm_i915_error_ring { 981 struct drm_i915_error_object { 982 int page_count; 983 u32 gtt_offset; 984 u32 *pages[0]; 985 } *ringbuffer, *batchbuffer; 986 struct drm_i915_error_request { 987 long jiffies; 988 u32 seqno; 989 u32 tail; 990 } *requests; 991 int num_requests; 992 } ring[I915_NUM_RINGS]; 993 struct drm_i915_error_buffer { 994 u32 size; 995 u32 name; 996 u32 seqno; 997 u32 gtt_offset; 998 u32 read_domains; 999 u32 write_domain; 1000 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 1001 s32 pinned:2; 1002 u32 tiling:2; 1003 u32 dirty:1; 1004 u32 purgeable:1; 1005 s32 ring:4; 1006 u32 cache_level:2; 1007 } *active_bo, *pinned_bo; 1008 u32 active_bo_count, pinned_bo_count; 1009 struct intel_overlay_error_state *overlay; 1010 struct intel_display_error_state *display; 1011}; 1012 1013/** 1014 * RC6 is a special power stage which allows the GPU to enter an very 1015 * low-voltage mode when idle, using down to 0V while at this stage. This 1016 * stage is entered automatically when the GPU is idle when RC6 support is 1017 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1018 * 1019 * There are different RC6 modes available in Intel GPU, which differentiate 1020 * among each other with the latency required to enter and leave RC6 and 1021 * voltage consumed by the GPU in different states. 1022 * 1023 * The combination of the following flags define which states GPU is allowed 1024 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1025 * RC6pp is deepest RC6. Their support by hardware varies according to the 1026 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1027 * which brings the most power savings; deeper states save more power, but 1028 * require higher latency to switch to and wake up. 1029 */ 1030#define INTEL_RC6_ENABLE (1<<0) 1031#define INTEL_RC6p_ENABLE (1<<1) 1032#define INTEL_RC6pp_ENABLE (1<<2) 1033 1034extern int intel_iommu_enabled; 1035extern struct drm_ioctl_desc i915_ioctls[]; 1036extern struct drm_driver_info i915_driver_info; 1037extern struct cdev_pager_ops i915_gem_pager_ops; 1038extern unsigned int i915_fbpercrtc; 1039extern int i915_panel_ignore_lid; 1040extern unsigned int i915_powersave; 1041extern int i915_semaphores; 1042extern unsigned int i915_lvds_downclock; 1043extern int i915_panel_use_ssc; 1044extern int i915_vbt_sdvo_panel_type; 1045extern int i915_enable_rc6; 1046extern int i915_enable_fbc; 1047extern int i915_enable_ppgtt; 1048extern int i915_enable_hangcheck; 1049 1050const struct intel_device_info *i915_get_device_id(int device); 1051 1052extern int intel_gpu_reset(struct drm_device *dev); 1053int i915_reset(struct drm_device *dev); 1054 1055/* i915_debug.c */ 1056int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1057 struct sysctl_oid *top); 1058void i915_sysctl_cleanup(struct drm_device *dev); 1059 1060 /* i915_dma.c */ 1061int i915_batchbuffer(struct drm_device *dev, void *data, 1062 struct drm_file *file_priv); 1063int i915_cmdbuffer(struct drm_device *dev, void *data, 1064 struct drm_file *file_priv); 1065int i915_getparam(struct drm_device *dev, void *data, 1066 struct drm_file *file_priv); 1067extern void i915_kernel_lost_context(struct drm_device * dev); 1068extern int i915_driver_load(struct drm_device *, unsigned long flags); 1069extern int i915_driver_unload(struct drm_device *); 1070extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1071extern void i915_driver_lastclose(struct drm_device * dev); 1072extern void i915_driver_preclose(struct drm_device *dev, 1073 struct drm_file *file_priv); 1074extern void i915_driver_postclose(struct drm_device *dev, 1075 struct drm_file *file_priv); 1076extern int i915_driver_device_is_agp(struct drm_device * dev); 1077extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1078 unsigned long arg); 1079extern int i915_emit_box(struct drm_device *dev, 1080 struct drm_clip_rect __user *boxes, 1081 int i, int DR1, int DR4); 1082int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1083 int DR1, int DR4); 1084 1085unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1086unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1087void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1088unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1089unsigned long i915_read_mch_val(void); 1090bool i915_gpu_raise(void); 1091bool i915_gpu_lower(void); 1092bool i915_gpu_busy(void); 1093bool i915_gpu_turbo_disable(void); 1094 1095/* i915_irq.c */ 1096extern int i915_irq_emit(struct drm_device *dev, void *data, 1097 struct drm_file *file_priv); 1098extern int i915_irq_wait(struct drm_device *dev, void *data, 1099 struct drm_file *file_priv); 1100 1101extern void intel_irq_init(struct drm_device *dev); 1102 1103extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1104 struct drm_file *file_priv); 1105extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1106 struct drm_file *file_priv); 1107extern int i915_vblank_swap(struct drm_device *dev, void *data, 1108 struct drm_file *file_priv); 1109void intel_enable_asle(struct drm_device *dev); 1110void i915_hangcheck_elapsed(void *context); 1111void i915_handle_error(struct drm_device *dev, bool wedged); 1112 1113void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1114void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1115 1116void i915_destroy_error_state(struct drm_device *dev); 1117 1118/* i915_gem.c */ 1119int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1120 uint32_t *handle_p); 1121int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1122 struct drm_file *file_priv); 1123int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1124 struct drm_file *file_priv); 1125int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1126 struct drm_file *file_priv); 1127int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1128 struct drm_file *file_priv); 1129int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1130 struct drm_file *file_priv); 1131int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1132 struct drm_file *file_priv); 1133int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1134 struct drm_file *file_priv); 1135int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1136 struct drm_file *file_priv); 1137int i915_gem_execbuffer(struct drm_device *dev, void *data, 1138 struct drm_file *file_priv); 1139int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1140 struct drm_file *file_priv); 1141int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1142 struct drm_file *file_priv); 1143int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1144 struct drm_file *file_priv); 1145int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1146 struct drm_file *file_priv); 1147int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1148 struct drm_file *file_priv); 1149int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1150 struct drm_file *file_priv); 1151int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1152 struct drm_file *file_priv); 1153int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1154 struct drm_file *file_priv); 1155int i915_gem_set_tiling(struct drm_device *dev, void *data, 1156 struct drm_file *file_priv); 1157int i915_gem_get_tiling(struct drm_device *dev, void *data, 1158 struct drm_file *file_priv); 1159int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1160 struct drm_file *file_priv); 1161void i915_gem_load(struct drm_device *dev); 1162void i915_gem_unload(struct drm_device *dev); 1163int i915_gem_init_object(struct drm_gem_object *obj); 1164void i915_gem_free_object(struct drm_gem_object *obj); 1165int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1166 bool map_and_fenceable); 1167void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1168int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1169void i915_gem_lastclose(struct drm_device *dev); 1170uint32_t i915_get_gem_seqno(struct drm_device *dev); 1171 1172static inline void 1173i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1174{ 1175 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1176 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1177 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1178 } 1179} 1180 1181static inline void 1182i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1183{ 1184 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1185 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1186 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1187 } 1188} 1189 1190void i915_gem_retire_requests(struct drm_device *dev); 1191void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1192void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1193struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1194 size_t size); 1195int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1196 unsigned long mappable_end, unsigned long end); 1197uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1198 uint32_t size, int tiling_mode); 1199int i915_mutex_lock_interruptible(struct drm_device *dev); 1200int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1201 bool write); 1202int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1203 u32 alignment, struct intel_ring_buffer *pipelined); 1204int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1205int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1206 uint32_t invalidate_domains, uint32_t flush_domains); 1207void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1208int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1209int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1210int i915_gem_idle(struct drm_device *dev); 1211int i915_gem_init_hw(struct drm_device *dev); 1212void i915_gem_init_swizzling(struct drm_device *dev); 1213void i915_gem_init_ppgtt(struct drm_device *dev); 1214void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1215int i915_gpu_idle(struct drm_device *dev, bool do_retire); 1216void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1217 struct intel_ring_buffer *ring, uint32_t seqno); 1218int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1219 struct drm_i915_gem_request *request); 1220int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1221 struct intel_ring_buffer *pipelined); 1222void i915_gem_reset(struct drm_device *dev); 1223int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1224 bool do_retire); 1225int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1226int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1227 uint64_t *phys); 1228void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1229int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1230 enum i915_cache_level cache_level); 1231 1232/* i915_gem_context.c */ 1233void i915_gem_context_init(struct drm_device *dev); 1234void i915_gem_context_fini(struct drm_device *dev); 1235void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1236int i915_switch_context(struct intel_ring_buffer *ring, 1237 struct drm_file *file, int to_id); 1238int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1239 struct drm_file *file); 1240int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1241 struct drm_file *file); 1242 1243void i915_gem_free_all_phys_object(struct drm_device *dev); 1244void i915_gem_detach_phys_object(struct drm_device *dev, 1245 struct drm_i915_gem_object *obj); 1246int i915_gem_attach_phys_object(struct drm_device *dev, 1247 struct drm_i915_gem_object *obj, int id, int align); 1248 1249int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1250 struct drm_mode_create_dumb *args); 1251int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1252 uint32_t handle, uint64_t *offset); 1253int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1254 uint32_t handle); 1255 1256/* i915_gem_tiling.c */ 1257void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1258void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1259void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1260 1261/* i915_gem_evict.c */ 1262int i915_gem_evict_something(struct drm_device *dev, int min_size, 1263 unsigned alignment, bool mappable); 1264int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1265int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1266 1267/* i915_suspend.c */ 1268extern int i915_save_state(struct drm_device *dev); 1269extern int i915_restore_state(struct drm_device *dev); 1270 1271/* intel_iic.c */ 1272extern int intel_setup_gmbus(struct drm_device *dev); 1273extern void intel_teardown_gmbus(struct drm_device *dev); 1274extern void intel_gmbus_set_speed(device_t idev, int speed); 1275extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1276extern void intel_iic_reset(struct drm_device *dev); 1277 1278/* intel_opregion.c */ 1279int intel_opregion_setup(struct drm_device *dev); 1280extern int intel_opregion_init(struct drm_device *dev); 1281extern void intel_opregion_fini(struct drm_device *dev); 1282extern void opregion_asle_intr(struct drm_device *dev); 1283extern void opregion_enable_asle(struct drm_device *dev); 1284 1285/* i915_gem_gtt.c */ 1286int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1287void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1288void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1289 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1290void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1291 struct drm_i915_gem_object *obj); 1292 1293void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1294int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1295void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1296void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1297 enum i915_cache_level cache_level); 1298 1299/* modesetting */ 1300extern void intel_modeset_init(struct drm_device *dev); 1301extern void intel_modeset_gem_init(struct drm_device *dev); 1302extern void intel_modeset_cleanup(struct drm_device *dev); 1303extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1304extern bool intel_fbc_enabled(struct drm_device *dev); 1305extern void intel_disable_fbc(struct drm_device *dev); 1306extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1307extern void ironlake_init_pch_refclk(struct drm_device *dev); 1308extern void ironlake_enable_rc6(struct drm_device *dev); 1309extern void gen6_set_rps(struct drm_device *dev, u8 val); 1310extern void intel_detect_pch(struct drm_device *dev); 1311extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1312 1313extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1314extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1315extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1316extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1317 1318extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1319 struct drm_device *dev); 1320extern void intel_overlay_print_error_state(struct sbuf *m, 1321 struct intel_overlay_error_state *error); 1322extern struct intel_display_error_state *intel_display_capture_error_state( 1323 struct drm_device *dev); 1324extern void intel_display_print_error_state(struct sbuf *m, 1325 struct drm_device *dev, struct intel_display_error_state *error); 1326 1327static inline void 1328trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1329{ 1330 1331 CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val); 1332} 1333 1334/* On SNB platform, before reading ring registers forcewake bit 1335 * must be set to prevent GT core from power down and stale values being 1336 * returned. 1337 */ 1338void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1339void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1340int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1341 1342/* We give fast paths for the really cool registers */ 1343#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1344 (((dev_priv)->info->gen >= 6) && \ 1345 ((reg) < 0x40000) && \ 1346 ((reg) != FORCEWAKE)) 1347 1348#define __i915_read(x, y) \ 1349 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1350 1351__i915_read(8, 8) 1352__i915_read(16, 16) 1353__i915_read(32, 32) 1354__i915_read(64, 64) 1355#undef __i915_read 1356 1357#define __i915_write(x, y) \ 1358 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1359 1360__i915_write(8, 8) 1361__i915_write(16, 16) 1362__i915_write(32, 32) 1363__i915_write(64, 64) 1364#undef __i915_write 1365 1366#define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1367#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1368 1369#define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1370#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1371#define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1372#define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1373 1374#define I915_READ(reg) i915_read32(dev_priv, (reg)) 1375#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1376#define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1377#define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1378 1379#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1380#define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1381 1382#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1383#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1384 1385#define I915_VERBOSE 0 1386 1387#define LP_RING(d) (&((struct drm_i915_private *)(d))->rings[RCS]) 1388 1389#define BEGIN_LP_RING(n) \ 1390 intel_ring_begin(LP_RING(dev_priv), (n)) 1391 1392#define OUT_RING(x) \ 1393 intel_ring_emit(LP_RING(dev_priv), x) 1394 1395#define ADVANCE_LP_RING() \ 1396 intel_ring_advance(LP_RING(dev_priv)) 1397 1398#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1399 if (LP_RING(dev->dev_private)->obj == NULL) \ 1400 LOCK_TEST_WITH_RETURN(dev, file); \ 1401} while (0) 1402 1403/** 1404 * Reads a dword out of the status page, which is written to from the command 1405 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1406 * MI_STORE_DATA_IMM. 1407 * 1408 * The following dwords have a reserved meaning: 1409 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1410 * 0x04: ring 0 head pointer 1411 * 0x05: ring 1 head pointer (915-class) 1412 * 0x06: ring 2 head pointer (915-class) 1413 * 0x10-0x1b: Context status DWords (GM45) 1414 * 0x1f: Last written status offset. (GM45) 1415 * 1416 * The area from dword 0x20 to 0x3ff is available for driver usage. 1417 */ 1418#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1419#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1420#define I915_GEM_HWS_INDEX 0x20 1421#define I915_BREADCRUMB_INDEX 0x21 1422 1423#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1424 1425#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1426#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1427#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1428#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1429#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1430#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1431#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1432#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1433#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1434#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1435#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1436#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1437#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1438#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1439#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1440#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1441#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1442#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1443#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1444#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1445 1446/* XXXKIB LEGACY */ 1447#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1448 (dev)->pci_device == 0x2982 || \ 1449 (dev)->pci_device == 0x2992 || \ 1450 (dev)->pci_device == 0x29A2 || \ 1451 (dev)->pci_device == 0x2A02 || \ 1452 (dev)->pci_device == 0x2A12 || \ 1453 (dev)->pci_device == 0x2A42 || \ 1454 (dev)->pci_device == 0x2E02 || \ 1455 (dev)->pci_device == 0x2E12 || \ 1456 (dev)->pci_device == 0x2E22 || \ 1457 (dev)->pci_device == 0x2E32) 1458 1459#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1460 1461#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1462#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1463#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1464 1465#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1466 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1467/* XXXKIB LEGACY END */ 1468 1469#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1470#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1471#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1472#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1473#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1474#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1475 1476#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1477#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1478#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1479#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1480 1481#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1482#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1483 1484#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1485#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1486 1487/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1488 * rows, which changed the alignment requirements and fence programming. 1489 */ 1490#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1491 IS_I915GM(dev))) 1492#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1493#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1494#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1495#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1496#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1497#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1498/* dsparb controlled by hw only */ 1499#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1500 1501#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1502#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1503#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1504 1505#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1506#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1507 1508#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1509#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1510#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1511 1512#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1513 1514static inline bool 1515i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1516{ 1517 1518 return ((int32_t)(seq1 - seq2) >= 0); 1519} 1520 1521u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1522 1523#endif 1524