drm_edid.h revision 280369
1/* 2 * Copyright �� 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * $FreeBSD: stable/10/sys/dev/drm2/drm_edid.h 280369 2015-03-23 13:38:33Z kib $ 24 */ 25#ifndef __DRM_EDID_H__ 26#define __DRM_EDID_H__ 27 28#include <sys/types.h> 29#include <dev/drm2/drmP.h> 30 31#define EDID_LENGTH 128 32#define DDC_ADDR 0x50 33 34#define CEA_EXT 0x02 35#define VTB_EXT 0x10 36#define DI_EXT 0x40 37#define LS_EXT 0x50 38#define MI_EXT 0x60 39 40struct est_timings { 41 u8 t1; 42 u8 t2; 43 u8 mfg_rsvd; 44} __attribute__((packed)); 45 46/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 47#define EDID_TIMING_ASPECT_SHIFT 6 48#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 49 50/* need to add 60 */ 51#define EDID_TIMING_VFREQ_SHIFT 0 52#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 53 54struct std_timing { 55 u8 hsize; /* need to multiply by 8 then add 248 */ 56 u8 vfreq_aspect; 57} __attribute__((packed)); 58 59#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 60#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 61#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 62#define DRM_EDID_PT_STEREO (1 << 5) 63#define DRM_EDID_PT_INTERLACED (1 << 7) 64 65/* If detailed data is pixel timing */ 66struct detailed_pixel_timing { 67 u8 hactive_lo; 68 u8 hblank_lo; 69 u8 hactive_hblank_hi; 70 u8 vactive_lo; 71 u8 vblank_lo; 72 u8 vactive_vblank_hi; 73 u8 hsync_offset_lo; 74 u8 hsync_pulse_width_lo; 75 u8 vsync_offset_pulse_width_lo; 76 u8 hsync_vsync_offset_pulse_width_hi; 77 u8 width_mm_lo; 78 u8 height_mm_lo; 79 u8 width_height_mm_hi; 80 u8 hborder; 81 u8 vborder; 82 u8 misc; 83} __attribute__((packed)); 84 85/* If it's not pixel timing, it'll be one of the below */ 86struct detailed_data_string { 87 u8 str[13]; 88} __attribute__((packed)); 89 90struct detailed_data_monitor_range { 91 u8 min_vfreq; 92 u8 max_vfreq; 93 u8 min_hfreq_khz; 94 u8 max_hfreq_khz; 95 u8 pixel_clock_mhz; /* need to multiply by 10 */ 96 u8 flags; 97 union { 98 struct { 99 u8 reserved; 100 u8 hfreq_start_khz; /* need to multiply by 2 */ 101 u8 c; /* need to divide by 2 */ 102 u16 m; 103 u8 k; 104 u8 j; /* need to divide by 2 */ 105 } __attribute__((packed)) gtf2; 106 struct { 107 u8 version; 108 u8 data1; /* high 6 bits: extra clock resolution */ 109 u8 data2; /* plus low 2 of above: max hactive */ 110 u8 supported_aspects; 111 u8 flags; /* preferred aspect and blanking support */ 112 u8 supported_scalings; 113 u8 preferred_refresh; 114 } __attribute__((packed)) cvt; 115 } formula; 116} __attribute__((packed)); 117 118struct detailed_data_wpindex { 119 u8 white_yx_lo; /* Lower 2 bits each */ 120 u8 white_x_hi; 121 u8 white_y_hi; 122 u8 gamma; /* need to divide by 100 then add 1 */ 123} __attribute__((packed)); 124 125struct detailed_data_color_point { 126 u8 windex1; 127 u8 wpindex1[3]; 128 u8 windex2; 129 u8 wpindex2[3]; 130} __attribute__((packed)); 131 132struct cvt_timing { 133 u8 code[3]; 134} __attribute__((packed)); 135 136struct detailed_non_pixel { 137 u8 pad1; 138 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 139 fb=color point data, fa=standard timing data, 140 f9=undefined, f8=mfg. reserved */ 141 u8 pad2; 142 union { 143 struct detailed_data_string str; 144 struct detailed_data_monitor_range range; 145 struct detailed_data_wpindex color; 146 struct std_timing timings[6]; 147 struct cvt_timing cvt[4]; 148 } data; 149} __attribute__((packed)); 150 151#define EDID_DETAIL_EST_TIMINGS 0xf7 152#define EDID_DETAIL_CVT_3BYTE 0xf8 153#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 154#define EDID_DETAIL_STD_MODES 0xfa 155#define EDID_DETAIL_MONITOR_CPDATA 0xfb 156#define EDID_DETAIL_MONITOR_NAME 0xfc 157#define EDID_DETAIL_MONITOR_RANGE 0xfd 158#define EDID_DETAIL_MONITOR_STRING 0xfe 159#define EDID_DETAIL_MONITOR_SERIAL 0xff 160 161struct detailed_timing { 162 u16 pixel_clock; /* need to multiply by 10 KHz */ 163 union { 164 struct detailed_pixel_timing pixel_data; 165 struct detailed_non_pixel other_data; 166 } data; 167} __attribute__((packed)); 168 169#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 170#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 171#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 172#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 173#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 174#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 175#define DRM_EDID_INPUT_DIGITAL (1 << 7) 176#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 177#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 178#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 179#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 180#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 181#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 182#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 183#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 184#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 185#define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 186#define DRM_EDID_DIGITAL_TYPE_DVI (1) 187#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 188#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 189#define DRM_EDID_DIGITAL_TYPE_MDDI (4) 190#define DRM_EDID_DIGITAL_TYPE_DP (5) 191 192#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 193#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 194#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 195#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 196/* If digital */ 197#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 198#define DRM_EDID_FEATURE_RGB (0 << 3) 199#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 200#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 201#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 202 203#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 204#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 205#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 206 207struct edid { 208 u8 header[8]; 209 /* Vendor & product info */ 210 u8 mfg_id[2]; 211 u8 prod_code[2]; 212 u32 serial; /* FIXME: byte order */ 213 u8 mfg_week; 214 u8 mfg_year; 215 /* EDID version */ 216 u8 version; 217 u8 revision; 218 /* Display info: */ 219 u8 input; 220 u8 width_cm; 221 u8 height_cm; 222 u8 gamma; 223 u8 features; 224 /* Color characteristics */ 225 u8 red_green_lo; 226 u8 black_white_lo; 227 u8 red_x; 228 u8 red_y; 229 u8 green_x; 230 u8 green_y; 231 u8 blue_x; 232 u8 blue_y; 233 u8 white_x; 234 u8 white_y; 235 /* Est. timings and mfg rsvd timings*/ 236 struct est_timings established_timings; 237 /* Standard timings 1-8*/ 238 struct std_timing standard_timings[8]; 239 /* Detailing timings 1-4 */ 240 struct detailed_timing detailed_timings[4]; 241 /* Number of 128 byte ext. blocks */ 242 u8 extensions; 243 /* Checksum */ 244 u8 checksum; 245} __attribute__((packed)); 246 247#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 248 249struct drm_encoder; 250struct drm_connector; 251struct drm_display_mode; 252void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 253int drm_av_sync_delay(struct drm_connector *connector, 254 struct drm_display_mode *mode); 255struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 256 struct drm_display_mode *mode); 257 258#endif /* __DRM_EDID_H__ */ 259