t5fw_cfg_uwire.txt revision 286895
1# Chelsio T5 Factory Default configuration file. 2# 3# Copyright (C) 2010-2015 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 4-port T5-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 4 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 8 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 10000 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 95 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 96 97 # SGE_THROTTLE_CONTROL 98 bar2throttlecount = 500 # bar2throttlecount in us 99 100 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 101 102 103 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if 104 # SGE_VFIFO_SIZE is not set, then 105 # firmware will set it up in function 106 # of number of egress queues used 107 108 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch 109 # threshold set to queue depth 110 # minus 128-entries for FL and HP 111 # queues, and 0xfff for LP which 112 # prompts the firmware to set it up 113 # in function of egress queues 114 # used 115 116 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which 117 # prompts the firmware to set it up in 118 # function of number of egress queues 119 # used 120 121 # enable TP_OUT_CONFIG.IPIDSPLITMODE 122 reg[0x7d04] = 0x00010000/0x00010000 123 124 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 125 126 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 127 # filter control: compact, fcoemask 128 # server sram : srvrsram 129 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 130 # protocol, tos, vlan, vnic_id, port, fcoe 131 # valid filterModes are described the Terminator 5 Data Book 132 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 133 134 # filter tuples enforced in LE active region (equal to or subset of filterMode) 135 filterMask = protocol, fcoe 136 137 # Percentage of dynamic memory (in either the EDRAM or external MEM) 138 # to use for TP RX payload 139 tp_pmrx = 30 140 141 # TP RX payload page size 142 tp_pmrx_pagesize = 64K 143 144 # TP number of RX channels 145 tp_nrxch = 0 # 0 (auto) = 1 146 147 # Percentage of dynamic memory (in either the EDRAM or external MEM) 148 # to use for TP TX payload 149 tp_pmtx = 50 150 151 # TP TX payload page size 152 tp_pmtx_pagesize = 64K 153 154 # TP number of TX channels 155 tp_ntxch = 0 # 0 (auto) = equal number of ports 156 157 # TP OFLD MTUs 158 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 159 160 # TP_GLOBAL_CONFIG 161 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 162 163 # TP_PC_CONFIG 164 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 165 166 # TP_PARA_REG0 167 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 168 169 # ULPRX iSCSI Page Sizes 170 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 171 172 # LE_DB_CONFIG 173 reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable 174 175 # MC configuration 176 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 177 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC 178 179# Some "definitions" to make the rest of this a bit more readable. We support 180# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 181# per function per port ... 182# 183# NMSIX = 1088 # available MSI-X Vectors 184# NVI = 128 # available Virtual Interfaces 185# NMPSTCAM = 336 # MPS TCAM entries 186# 187# NPORTS = 4 # ports 188# NCPUS = 8 # CPUs we want to support scalably 189# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 190 191# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 192# PF" which many OS Drivers will use to manage most or all functions. 193# 194# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 195# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 196# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 197# will be specified as the "Ingress Queue Asynchronous Destination Index." 198# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 199# than or equal to the number of Ingress Queues ... 200# 201# NVI_NIC = 4 # NIC access to NPORTS 202# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 203# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 204# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 205# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 206# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 207# 208# NVI_OFLD = 0 # Offload uses NIC function to access ports 209# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 210# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 211# NEQ_OFLD = 16 # Offload Egress Queues (FL) 212# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 213# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 214# 215# NVI_RDMA = 0 # RDMA uses NIC function to access ports 216# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 217# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 218# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 219# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 220# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 221# 222# NEQ_WD = 128 # Wire Direct TX Queues and FLs 223# NETHCTRL_WD = 64 # Wire Direct TX Queues 224# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 225# 226# NVI_ISCSI = 4 # ISCSI access to NPORTS 227# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 228# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 229# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 230# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 231# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 232# 233# NVI_FCOE = 4 # FCOE access to NPORTS 234# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 235# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 236# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 237# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 238# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 239 240# Two extra Ingress Queues per function for Firmware Events and Forwarded 241# Interrupts, and two extra interrupts per function for Firmware Events (or a 242# Forwarded Interrupt Queue) and General Interrupts per function. 243# 244# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 245# # Forwarded Interrupts 246# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 247# # General Interrupts 248 249# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 250# their interrupts forwarded to another set of Forwarded Interrupt Queues. 251# 252# NVI_HYPERV = 16 # VMs we want to support 253# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 254# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 255# NEQ_HYPERV = 32 # VIQs Free Lists 256# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 257# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 258 259# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 260# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 261# 262# NVI_UNIFIED = 28 263# NFLIQ_UNIFIED = 106 264# NETHCTRL_UNIFIED = 32 265# NEQ_UNIFIED = 124 266# NMPSTCAM_UNIFIED = 40 267# 268# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 269# that up to 128 to make sure the Unified PF doesn't run out of resources. 270# 271# NMSIX_UNIFIED = 128 272# 273# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 274# which is 34 but they're probably safe with 32. 275# 276# NMSIX_STORAGE = 32 277 278# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 279# associated with it. Thus, the MSI-X Vector allocations we give to the 280# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 281# provision many more Virtual Functions than we can if the UnifiedPF were 282# one of PF0-3. 283# 284 285# All of the below PCI-E parameters are actually stored in various *_init.txt 286# files. We include them below essentially as comments. 287# 288# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 289# ports 0-3. 290# 291# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 292# 293# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 294# storage applications across all four possible ports. 295# 296# Additionally, since the UnifiedPF isn't one of the per-port Physical 297# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 298# different PCI Device IDs which will allow Unified and Per-Port Drivers 299# to directly select the type of Physical Function to which they wish to be 300# attached. 301# 302# Note that the actual values used for the PCI-E Intelectual Property will be 303# 1 less than those below since that's the way it "counts" things. For 304# readability, we use the number we actually mean ... 305# 306# PF0_INT = 8 # NCPUS 307# PF1_INT = 8 # NCPUS 308# PF2_INT = 8 # NCPUS 309# PF3_INT = 8 # NCPUS 310# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 311# 312# PF4_INT = 128 # NMSIX_UNIFIED 313# PF5_INT = 32 # NMSIX_STORAGE 314# PF6_INT = 32 # NMSIX_STORAGE 315# PF7_INT = 0 # Nothing Assigned 316# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 317# 318# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 319# 320# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 321# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 322# 323# NVF = 16 324 325 326# For those OSes which manage different ports on different PFs, we need 327# only enough resources to support a single port's NIC application functions 328# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 329# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 330# managed on the "storage PFs" (see below). 331# 332[function "0"] 333 nvf = 16 # NVF on this function 334 wx_caps = all # write/execute permissions for all commands 335 r_caps = all # read permissions for all commands 336 nvi = 1 # 1 port 337 niqflint = 8 # NCPUS "Queue Sets" 338 nethctrl = 8 # NCPUS "Queue Sets" 339 neq = 16 # niqflint + nethctrl Egress Queues 340 nexactf = 8 # number of exact MPSTCAM MAC filters 341 cmask = all # access to all channels 342 pmask = 0x1 # access to only one port 343 344 345[function "1"] 346 nvf = 16 # NVF on this function 347 wx_caps = all # write/execute permissions for all commands 348 r_caps = all # read permissions for all commands 349 nvi = 1 # 1 port 350 niqflint = 8 # NCPUS "Queue Sets" 351 nethctrl = 8 # NCPUS "Queue Sets" 352 neq = 16 # niqflint + nethctrl Egress Queues 353 nexactf = 8 # number of exact MPSTCAM MAC filters 354 cmask = all # access to all channels 355 pmask = 0x2 # access to only one port 356 357 358[function "2"] 359 nvf = 16 # NVF on this function 360 wx_caps = all # write/execute permissions for all commands 361 r_caps = all # read permissions for all commands 362 nvi = 1 # 1 port 363 niqflint = 8 # NCPUS "Queue Sets" 364 nethctrl = 8 # NCPUS "Queue Sets" 365 neq = 16 # niqflint + nethctrl Egress Queues 366 nexactf = 8 # number of exact MPSTCAM MAC filters 367 cmask = all # access to all channels 368 pmask = 0x4 # access to only one port 369 370 371[function "3"] 372 nvf = 16 # NVF on this function 373 wx_caps = all # write/execute permissions for all commands 374 r_caps = all # read permissions for all commands 375 nvi = 1 # 1 port 376 niqflint = 8 # NCPUS "Queue Sets" 377 nethctrl = 8 # NCPUS "Queue Sets" 378 neq = 16 # niqflint + nethctrl Egress Queues 379 nexactf = 8 # number of exact MPSTCAM MAC filters 380 cmask = all # access to all channels 381 pmask = 0x8 # access to only one port 382 383 384# Some OS Drivers manage all application functions for all ports via PF4. 385# Thus we need to provide a large number of resources here. For Egress 386# Queues we need to account for both TX Queues as well as Free List Queues 387# (because the host is responsible for producing Free List Buffers for the 388# hardware to consume). 389# 390[function "4"] 391 wx_caps = all # write/execute permissions for all commands 392 r_caps = all # read permissions for all commands 393 nvi = 28 # NVI_UNIFIED 394 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 395 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 396 neq = 256 # NEQ_UNIFIED + NEQ_WD 397 nqpcq = 12288 398 nexactf = 40 # NMPSTCAM_UNIFIED 399 cmask = all # access to all channels 400 pmask = all # access to all four ports ... 401 nethofld = 1024 # number of user mode ethernet flow contexts 402 nroute = 32 # number of routing region entries 403 nclip = 32 # number of clip region entries 404 nfilter = 496 # number of filter region entries 405 nserver = 496 # number of server region entries 406 nhash = 12288 # number of hash region entries 407 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif 408 tp_l2t = 3072 409 tp_ddp = 2 410 tp_ddp_iscsi = 2 411 tp_stag = 2 412 tp_pbl = 5 413 tp_rq = 7 414 415 416# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 417# need to have Virtual Interfaces on each of the four ports with up to NCPUS 418# "Queue Sets" each. 419# 420[function "5"] 421 wx_caps = all # write/execute permissions for all commands 422 r_caps = all # read permissions for all commands 423 nvi = 4 # NPORTS 424 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 425 nethctrl = 32 # NPORTS*NCPUS 426 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 427 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 428 cmask = all # access to all channels 429 pmask = all # access to all four ports ... 430 nserver = 16 431 nhash = 2048 432 tp_l2t = 1020 433 protocol = iscsi_initiator_fofld 434 tp_ddp_iscsi = 2 435 iscsi_ntask = 2048 436 iscsi_nsess = 2048 437 iscsi_nconn_per_session = 1 438 iscsi_ninitiator_instance = 64 439 440 441[function "6"] 442 wx_caps = all # write/execute permissions for all commands 443 r_caps = all # read permissions for all commands 444 nvi = 4 # NPORTS 445 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 446 nethctrl = 32 # NPORTS*NCPUS 447 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 448 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 449 # which is OK since < MIN(SUM PF0..3, PF4) 450 # and we never load PF0..3 and PF4 concurrently 451 cmask = all # access to all channels 452 pmask = all # access to all four ports ... 453 nhash = 2048 454 tp_l2t = 4 455 protocol = fcoe_initiator 456 tp_ddp = 2 457 fcoe_nfcf = 16 458 fcoe_nvnp = 32 459 fcoe_nssn = 1024 460 fcoe_nfcb = 256 461 462 463# The following function, 1023, is not an actual PCIE function but is used to 464# configure and reserve firmware internal resources that come from the global 465# resource pool. 466# 467[function "1023"] 468 wx_caps = all # write/execute permissions for all commands 469 r_caps = all # read permissions for all commands 470 nvi = 4 # NVI_UNIFIED 471 cmask = all # access to all channels 472 pmask = all # access to all four ports ... 473 nexactf = 8 # NPORTS + DCBX + 474 nfilter = 16 # number of filter region entries 475 476 477# For Virtual functions, we only allow NIC functionality and we only allow 478# access to one port (1 << PF). Note that because of limitations in the 479# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 480# and GTS registers, the number of Ingress and Egress Queues must be a power 481# of 2. 482# 483[function "0/*"] # NVF 484 wx_caps = 0x82 # DMAQ | VF 485 r_caps = 0x86 # DMAQ | VF | PORT 486 nvi = 1 # 1 port 487 niqflint = 4 # 2 "Queue Sets" + NXIQ 488 nethctrl = 2 # 2 "Queue Sets" 489 neq = 4 # 2 "Queue Sets" * 2 490 nexactf = 4 491 cmask = all # access to all channels 492 pmask = 0x1 # access to only one port ... 493 494 495[function "1/*"] # NVF 496 wx_caps = 0x82 # DMAQ | VF 497 r_caps = 0x86 # DMAQ | VF | PORT 498 nvi = 1 # 1 port 499 niqflint = 4 # 2 "Queue Sets" + NXIQ 500 nethctrl = 2 # 2 "Queue Sets" 501 neq = 4 # 2 "Queue Sets" * 2 502 nexactf = 4 503 cmask = all # access to all channels 504 pmask = 0x2 # access to only one port ... 505 506 507[function "2/*"] # NVF 508 wx_caps = 0x82 # DMAQ | VF 509 r_caps = 0x86 # DMAQ | VF | PORT 510 nvi = 1 # 1 port 511 niqflint = 4 # 2 "Queue Sets" + NXIQ 512 nethctrl = 2 # 2 "Queue Sets" 513 neq = 4 # 2 "Queue Sets" * 2 514 nexactf = 4 515 cmask = all # access to all channels 516 pmask = 0x4 # access to only one port ... 517 518 519[function "3/*"] # NVF 520 wx_caps = 0x82 # DMAQ | VF 521 r_caps = 0x86 # DMAQ | VF | PORT 522 nvi = 1 # 1 port 523 niqflint = 4 # 2 "Queue Sets" + NXIQ 524 nethctrl = 2 # 2 "Queue Sets" 525 neq = 4 # 2 "Queue Sets" * 2 526 nexactf = 4 527 cmask = all # access to all channels 528 pmask = 0x8 # access to only one port ... 529 530 531# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 532# for packets from the wire as well as the loopback path of the L2 switch. The 533# folling params control how the buffer memory is distributed and the L2 flow 534# control settings: 535# 536# bg_mem: %-age of mem to use for port/buffer group 537# lpbk_mem: %-age of port/bg mem to use for loopback 538# hwm: high watermark; bytes available when starting to send pause 539# frames (in units of 0.1 MTU) 540# lwm: low watermark; bytes remaining when sending 'unpause' frame 541# (in inuits of 0.1 MTU) 542# dwm: minimum delta between high and low watermark (in units of 100 543# Bytes) 544# 545[port "0"] 546 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 547 bg_mem = 25 548 lpbk_mem = 25 549 hwm = 30 550 lwm = 15 551 dwm = 30 552 dcb_app_tlv[0] = 0x8906, ethertype, 3 553 dcb_app_tlv[1] = 0x8914, ethertype, 3 554 dcb_app_tlv[2] = 3260, socketnum, 5 555 556 557[port "1"] 558 dcb = ppp, dcbx 559 bg_mem = 25 560 lpbk_mem = 25 561 hwm = 30 562 lwm = 15 563 dwm = 30 564 dcb_app_tlv[0] = 0x8906, ethertype, 3 565 dcb_app_tlv[1] = 0x8914, ethertype, 3 566 dcb_app_tlv[2] = 3260, socketnum, 5 567 568 569[port "2"] 570 dcb = ppp, dcbx 571 bg_mem = 25 572 lpbk_mem = 25 573 hwm = 30 574 lwm = 15 575 dwm = 30 576 dcb_app_tlv[0] = 0x8906, ethertype, 3 577 dcb_app_tlv[1] = 0x8914, ethertype, 3 578 dcb_app_tlv[2] = 3260, socketnum, 5 579 580 581[port "3"] 582 dcb = ppp, dcbx 583 bg_mem = 25 584 lpbk_mem = 25 585 hwm = 30 586 lwm = 15 587 dwm = 30 588 dcb_app_tlv[0] = 0x8906, ethertype, 3 589 dcb_app_tlv[1] = 0x8914, ethertype, 3 590 dcb_app_tlv[2] = 3260, socketnum, 5 591 592 593[fini] 594 version = 0x1425001c 595 checksum = 0xb1c3ae38 596 597# Total resources used by above allocations: 598# Virtual Interfaces: 104 599# Ingress Queues/w Free Lists and Interrupts: 526 600# Egress Queues: 702 601# MPS TCAM Entries: 336 602# MSI-X Vectors: 736 603# Virtual Functions: 64 604# 605# $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt 286895 2015-08-18 18:54:45Z np $ 606# 607