t4fw_interface.h revision 311507 
1/*-
2 * Copyright (c) 2012-2016 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 311507 2017-01-06 08:44:47Z np $
27 *
28 */
29
30#ifndef _T4FW_INTERFACE_H_
31#define _T4FW_INTERFACE_H_
32
33/******************************************************************************
34 *   R E T U R N   V A L U E S
35 ********************************/
36
37enum fw_retval {
38	FW_SUCCESS		= 0,	/* completed sucessfully */
39	FW_EPERM		= 1,	/* operation not permitted */
40	FW_ENOENT		= 2,	/* no such file or directory */
41	FW_EIO			= 5,	/* input/output error; hw bad */
42	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
43	FW_EAGAIN		= 11,	/* try again */
44	FW_ENOMEM		= 12,	/* out of memory */
45	FW_EFAULT		= 14,	/* bad address; fw bad */
46	FW_EBUSY		= 16,	/* resource busy */
47	FW_EEXIST		= 17,	/* file exists */
48	FW_ENODEV		= 19,	/* no such device */
49	FW_EINVAL		= 22,	/* invalid argument */
50	FW_ENOSPC		= 28,	/* no space left on device */
51	FW_ENOSYS		= 38,	/* functionality not implemented */
52	FW_ENODATA		= 61,	/* no data available */
53	FW_EPROTO		= 71,	/* protocol error */
54	FW_EADDRINUSE		= 98,	/* address already in use */
55	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
56	FW_ENETDOWN		= 100,	/* network is down */
57	FW_ENETUNREACH		= 101,	/* network is unreachable */
58	FW_ENOBUFS		= 105,	/* no buffer space available */
59	FW_ETIMEDOUT		= 110,	/* timeout */
60	FW_EINPROGRESS		= 115,	/* fw internal */
61	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
62	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
63	FW_SCSI_ABORTED		= 130,	/* */
64	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
65	FW_ERR_LINK_DOWN	= 132,	/* */
66	FW_RDEV_NOT_READY	= 133,	/* */
67	FW_ERR_RDEV_LOST	= 134,	/* */
68	FW_ERR_RDEV_LOGO	= 135,	/* */
69	FW_FCOE_NO_XCHG		= 136,	/* */
70	FW_SCSI_RSP_ERR		= 137,	/* */
71	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
72	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
73	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
74	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
75	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
76};
77
78/******************************************************************************
79 *   M E M O R Y   T Y P E s
80 ******************************/
81
82enum fw_memtype {
83	FW_MEMTYPE_EDC0		= 0x0,
84	FW_MEMTYPE_EDC1		= 0x1,
85	FW_MEMTYPE_EXTMEM	= 0x2,
86	FW_MEMTYPE_FLASH	= 0x4,
87	FW_MEMTYPE_INTERNAL	= 0x5,
88	FW_MEMTYPE_EXTMEM1	= 0x6,
89};
90
91/******************************************************************************
92 *   W O R K   R E Q U E S T s
93 ********************************/
94
95enum fw_wr_opcodes {
96	FW_FRAG_WR		= 0x1d,
97	FW_FILTER_WR		= 0x02,
98	FW_ULPTX_WR		= 0x04,
99	FW_TP_WR		= 0x05,
100	FW_ETH_TX_PKT_WR	= 0x08,
101	FW_ETH_TX_PKT2_WR	= 0x44,
102	FW_ETH_TX_PKTS_WR	= 0x09,
103	FW_ETH_TX_EO_WR		= 0x1c,
104	FW_EQ_FLUSH_WR		= 0x1b,
105	FW_OFLD_CONNECTION_WR	= 0x2f,
106	FW_FLOWC_WR		= 0x0a,
107	FW_OFLD_TX_DATA_WR	= 0x0b,
108	FW_CMD_WR		= 0x10,
109	FW_ETH_TX_PKT_VM_WR	= 0x11,
110	FW_RI_RES_WR		= 0x0c,
111	FW_RI_RDMA_WRITE_WR	= 0x14,
112	FW_RI_SEND_WR		= 0x15,
113	FW_RI_RDMA_READ_WR	= 0x16,
114	FW_RI_RECV_WR		= 0x17,
115	FW_RI_BIND_MW_WR	= 0x18,
116	FW_RI_FR_NSMR_WR	= 0x19,
117	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
118	FW_RI_INV_LSTAG_WR	= 0x1a,
119	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
120	FW_RI_ATOMIC_WR		= 0x16,
121	FW_RI_WR		= 0x0d,
122	FW_CHNET_IFCONF_WR	= 0x6b,
123	FW_RDEV_WR		= 0x38,
124	FW_FOISCSI_NODE_WR	= 0x60,
125	FW_FOISCSI_CTRL_WR	= 0x6a,
126	FW_FOISCSI_CHAP_WR	= 0x6c,
127	FW_FCOE_ELS_CT_WR	= 0x30,
128	FW_SCSI_WRITE_WR	= 0x31,
129	FW_SCSI_READ_WR		= 0x32,
130	FW_SCSI_CMD_WR		= 0x33,
131	FW_SCSI_ABRT_CLS_WR	= 0x34,
132	FW_SCSI_TGT_ACC_WR	= 0x35,
133	FW_SCSI_TGT_XMIT_WR	= 0x36,
134	FW_SCSI_TGT_RSP_WR	= 0x37,
135	FW_POFCOE_TCB_WR	= 0x42,
136	FW_POFCOE_ULPTX_WR	= 0x43,
137	FW_ISCSI_TX_DATA_WR	= 0x45,
138	FW_PTP_TX_PKT_WR        = 0x46,
139	FW_TLSTX_DATA_WR	= 0x68,
140	FW_TLS_KEYCTX_TX_WR	= 0x69,
141	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
142	FW_COiSCSI_TGT_WR	= 0x70,
143	FW_COiSCSI_TGT_CONN_WR	= 0x71,
144	FW_COiSCSI_TGT_XMIT_WR	= 0x72,
145	FW_ISNS_WR		= 0x75,
146	FW_ISNS_XMIT_WR		= 0x76,
147	FW_LASTC2E_WR		= 0x80
148};
149
150/*
151 * Generic work request header flit0
152 */
153struct fw_wr_hdr {
154	__be32 hi;
155	__be32 lo;
156};
157
158/*	work request opcode (hi)
159 */
160#define S_FW_WR_OP		24
161#define M_FW_WR_OP		0xff
162#define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
163#define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
164
165/*	atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
166 */
167#define S_FW_WR_ATOMIC		23
168#define M_FW_WR_ATOMIC		0x1
169#define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
170#define G_FW_WR_ATOMIC(x)	\
171    (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
172#define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
173
174/*	flush flag (hi) - firmware flushes flushable work request buffered
175 *			      in the flow context.
176 */
177#define S_FW_WR_FLUSH     22
178#define M_FW_WR_FLUSH     0x1
179#define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
180#define G_FW_WR_FLUSH(x)  \
181    (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
182#define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
183
184/*	completion flag (hi) - firmware generates a cpl_fw6_ack
185 */
186#define S_FW_WR_COMPL     21
187#define M_FW_WR_COMPL     0x1
188#define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
189#define G_FW_WR_COMPL(x)  \
190    (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
191#define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
192
193
194/*	work request immediate data lengh (hi)
195 */
196#define S_FW_WR_IMMDLEN	0
197#define M_FW_WR_IMMDLEN	0xff
198#define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
199#define G_FW_WR_IMMDLEN(x)	\
200    (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
201
202/*	egress queue status update to associated ingress queue entry (lo)
203 */
204#define S_FW_WR_EQUIQ		31
205#define M_FW_WR_EQUIQ		0x1
206#define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
207#define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
208#define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
209
210/*	egress queue status update to egress queue status entry (lo)
211 */
212#define S_FW_WR_EQUEQ		30
213#define M_FW_WR_EQUEQ		0x1
214#define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
215#define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
216#define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
217
218/*	flow context identifier (lo)
219 */
220#define S_FW_WR_FLOWID		8
221#define M_FW_WR_FLOWID		0xfffff
222#define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
223#define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
224
225/*	length in units of 16-bytes (lo)
226 */
227#define S_FW_WR_LEN16		0
228#define M_FW_WR_LEN16		0xff
229#define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
230#define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
231
232struct fw_frag_wr {
233	__be32 op_to_fragoff16;
234	__be32 flowid_len16;
235	__be64 r4;
236};
237
238#define S_FW_FRAG_WR_EOF	15
239#define M_FW_FRAG_WR_EOF	0x1
240#define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
241#define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
242#define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
243
244#define S_FW_FRAG_WR_FRAGOFF16		8
245#define M_FW_FRAG_WR_FRAGOFF16		0x7f
246#define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
247#define G_FW_FRAG_WR_FRAGOFF16(x)	\
248    (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
249
250/* valid filter configurations for compressed tuple
251 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
252 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
253 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
254 * OV - Outer VLAN/VNIC_ID,
255*/
256#define HW_TPL_FR_MT_M_E_P_FC		0x3C3
257#define HW_TPL_FR_MT_M_PR_T_FC		0x3B3
258#define HW_TPL_FR_MT_M_IV_P_FC		0x38B
259#define HW_TPL_FR_MT_M_OV_P_FC		0x387
260#define HW_TPL_FR_MT_E_PR_T		0x370
261#define HW_TPL_FR_MT_E_PR_P_FC		0X363
262#define HW_TPL_FR_MT_E_T_P_FC		0X353
263#define HW_TPL_FR_MT_PR_IV_P_FC		0X32B
264#define HW_TPL_FR_MT_PR_OV_P_FC		0X327
265#define HW_TPL_FR_MT_T_IV_P_FC		0X31B
266#define HW_TPL_FR_MT_T_OV_P_FC		0X317
267#define HW_TPL_FR_M_E_PR_FC		0X2E1
268#define HW_TPL_FR_M_E_T_FC		0X2D1
269#define HW_TPL_FR_M_PR_IV_FC		0X2A9
270#define HW_TPL_FR_M_PR_OV_FC		0X2A5
271#define HW_TPL_FR_M_T_IV_FC		0X299
272#define HW_TPL_FR_M_T_OV_FC		0X295
273#define HW_TPL_FR_E_PR_T_P		0X272
274#define HW_TPL_FR_E_PR_T_FC		0X271
275#define HW_TPL_FR_E_IV_FC		0X249
276#define HW_TPL_FR_E_OV_FC		0X245
277#define HW_TPL_FR_PR_T_IV_FC		0X239
278#define HW_TPL_FR_PR_T_OV_FC		0X235
279#define HW_TPL_FR_IV_OV_FC		0X20D
280#define HW_TPL_MT_M_E_PR		0X1E0
281#define HW_TPL_MT_M_E_T			0X1D0
282#define HW_TPL_MT_E_PR_T_FC		0X171
283#define HW_TPL_MT_E_IV			0X148
284#define HW_TPL_MT_E_OV			0X144
285#define HW_TPL_MT_PR_T_IV		0X138
286#define HW_TPL_MT_PR_T_OV		0X134
287#define HW_TPL_M_E_PR_P			0X0E2
288#define HW_TPL_M_E_T_P			0X0D2
289#define HW_TPL_E_PR_T_P_FC		0X073
290#define HW_TPL_E_IV_P			0X04A
291#define HW_TPL_E_OV_P			0X046
292#define HW_TPL_PR_T_IV_P		0X03A
293#define HW_TPL_PR_T_OV_P		0X036
294
295/* filter wr reply code in cookie in CPL_SET_TCB_RPL */
296enum fw_filter_wr_cookie {
297	FW_FILTER_WR_SUCCESS,
298	FW_FILTER_WR_FLT_ADDED,
299	FW_FILTER_WR_FLT_DELETED,
300	FW_FILTER_WR_SMT_TBL_FULL,
301	FW_FILTER_WR_EINVAL,
302};
303
304struct fw_filter_wr {
305	__be32 op_pkd;
306	__be32 len16_pkd;
307	__be64 r3;
308	__be32 tid_to_iq;
309	__be32 del_filter_to_l2tix;
310	__be16 ethtype;
311	__be16 ethtypem;
312	__u8   frag_to_ovlan_vldm;
313	__u8   smac_sel;
314	__be16 rx_chan_rx_rpl_iq;
315	__be32 maci_to_matchtypem;
316	__u8   ptcl;
317	__u8   ptclm;
318	__u8   ttyp;
319	__u8   ttypm;
320	__be16 ivlan;
321	__be16 ivlanm;
322	__be16 ovlan;
323	__be16 ovlanm;
324	__u8   lip[16];
325	__u8   lipm[16];
326	__u8   fip[16];
327	__u8   fipm[16];
328	__be16 lp;
329	__be16 lpm;
330	__be16 fp;
331	__be16 fpm;
332	__be16 r7;
333	__u8   sma[6];
334};
335
336#define S_FW_FILTER_WR_TID	12
337#define M_FW_FILTER_WR_TID	0xfffff
338#define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
339#define G_FW_FILTER_WR_TID(x)	\
340    (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
341
342#define S_FW_FILTER_WR_RQTYPE		11
343#define M_FW_FILTER_WR_RQTYPE		0x1
344#define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
345#define G_FW_FILTER_WR_RQTYPE(x)	\
346    (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
347#define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
348
349#define S_FW_FILTER_WR_NOREPLY		10
350#define M_FW_FILTER_WR_NOREPLY		0x1
351#define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
352#define G_FW_FILTER_WR_NOREPLY(x)	\
353    (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
354#define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
355
356#define S_FW_FILTER_WR_IQ	0
357#define M_FW_FILTER_WR_IQ	0x3ff
358#define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
359#define G_FW_FILTER_WR_IQ(x)	\
360    (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
361
362#define S_FW_FILTER_WR_DEL_FILTER	31
363#define M_FW_FILTER_WR_DEL_FILTER	0x1
364#define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
365#define G_FW_FILTER_WR_DEL_FILTER(x)	\
366    (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
367#define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
368
369#define S_FW_FILTER_WR_RPTTID		25
370#define M_FW_FILTER_WR_RPTTID		0x1
371#define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
372#define G_FW_FILTER_WR_RPTTID(x)	\
373    (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
374#define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
375
376#define S_FW_FILTER_WR_DROP	24
377#define M_FW_FILTER_WR_DROP	0x1
378#define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
379#define G_FW_FILTER_WR_DROP(x)	\
380    (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
381#define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
382
383#define S_FW_FILTER_WR_DIRSTEER		23
384#define M_FW_FILTER_WR_DIRSTEER		0x1
385#define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
386#define G_FW_FILTER_WR_DIRSTEER(x)	\
387    (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
388#define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
389
390#define S_FW_FILTER_WR_MASKHASH		22
391#define M_FW_FILTER_WR_MASKHASH		0x1
392#define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
393#define G_FW_FILTER_WR_MASKHASH(x)	\
394    (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
395#define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
396
397#define S_FW_FILTER_WR_DIRSTEERHASH	21
398#define M_FW_FILTER_WR_DIRSTEERHASH	0x1
399#define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
400#define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
401    (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
402#define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
403
404#define S_FW_FILTER_WR_LPBK	20
405#define M_FW_FILTER_WR_LPBK	0x1
406#define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
407#define G_FW_FILTER_WR_LPBK(x)	\
408    (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
409#define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
410
411#define S_FW_FILTER_WR_DMAC	19
412#define M_FW_FILTER_WR_DMAC	0x1
413#define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
414#define G_FW_FILTER_WR_DMAC(x)	\
415    (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
416#define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
417
418#define S_FW_FILTER_WR_SMAC	18
419#define M_FW_FILTER_WR_SMAC	0x1
420#define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
421#define G_FW_FILTER_WR_SMAC(x)	\
422    (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
423#define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
424
425#define S_FW_FILTER_WR_INSVLAN		17
426#define M_FW_FILTER_WR_INSVLAN		0x1
427#define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
428#define G_FW_FILTER_WR_INSVLAN(x)	\
429    (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
430#define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
431
432#define S_FW_FILTER_WR_RMVLAN		16
433#define M_FW_FILTER_WR_RMVLAN		0x1
434#define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
435#define G_FW_FILTER_WR_RMVLAN(x)	\
436    (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
437#define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
438
439#define S_FW_FILTER_WR_HITCNTS		15
440#define M_FW_FILTER_WR_HITCNTS		0x1
441#define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
442#define G_FW_FILTER_WR_HITCNTS(x)	\
443    (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
444#define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
445
446#define S_FW_FILTER_WR_TXCHAN		13
447#define M_FW_FILTER_WR_TXCHAN		0x3
448#define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
449#define G_FW_FILTER_WR_TXCHAN(x)	\
450    (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
451
452#define S_FW_FILTER_WR_PRIO	12
453#define M_FW_FILTER_WR_PRIO	0x1
454#define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
455#define G_FW_FILTER_WR_PRIO(x)	\
456    (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
457#define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
458
459#define S_FW_FILTER_WR_L2TIX	0
460#define M_FW_FILTER_WR_L2TIX	0xfff
461#define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
462#define G_FW_FILTER_WR_L2TIX(x)	\
463    (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
464
465#define S_FW_FILTER_WR_FRAG	7
466#define M_FW_FILTER_WR_FRAG	0x1
467#define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
468#define G_FW_FILTER_WR_FRAG(x)	\
469    (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
470#define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
471
472#define S_FW_FILTER_WR_FRAGM	6
473#define M_FW_FILTER_WR_FRAGM	0x1
474#define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
475#define G_FW_FILTER_WR_FRAGM(x)	\
476    (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
477#define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
478
479#define S_FW_FILTER_WR_IVLAN_VLD	5
480#define M_FW_FILTER_WR_IVLAN_VLD	0x1
481#define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
482#define G_FW_FILTER_WR_IVLAN_VLD(x)	\
483    (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
484#define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
485
486#define S_FW_FILTER_WR_OVLAN_VLD	4
487#define M_FW_FILTER_WR_OVLAN_VLD	0x1
488#define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
489#define G_FW_FILTER_WR_OVLAN_VLD(x)	\
490    (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
491#define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
492
493#define S_FW_FILTER_WR_IVLAN_VLDM	3
494#define M_FW_FILTER_WR_IVLAN_VLDM	0x1
495#define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
496#define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
497    (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
498#define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
499
500#define S_FW_FILTER_WR_OVLAN_VLDM	2
501#define M_FW_FILTER_WR_OVLAN_VLDM	0x1
502#define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
503#define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
504    (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
505#define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
506
507#define S_FW_FILTER_WR_RX_CHAN		15
508#define M_FW_FILTER_WR_RX_CHAN		0x1
509#define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
510#define G_FW_FILTER_WR_RX_CHAN(x)	\
511    (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
512#define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
513
514#define S_FW_FILTER_WR_RX_RPL_IQ	0
515#define M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
516#define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
517#define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
518    (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
519
520#define S_FW_FILTER_WR_MACI	23
521#define M_FW_FILTER_WR_MACI	0x1ff
522#define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
523#define G_FW_FILTER_WR_MACI(x)	\
524    (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
525
526#define S_FW_FILTER_WR_MACIM	14
527#define M_FW_FILTER_WR_MACIM	0x1ff
528#define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
529#define G_FW_FILTER_WR_MACIM(x)	\
530    (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
531
532#define S_FW_FILTER_WR_FCOE	13
533#define M_FW_FILTER_WR_FCOE	0x1
534#define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
535#define G_FW_FILTER_WR_FCOE(x)	\
536    (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
537#define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
538
539#define S_FW_FILTER_WR_FCOEM	12
540#define M_FW_FILTER_WR_FCOEM	0x1
541#define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
542#define G_FW_FILTER_WR_FCOEM(x)	\
543    (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
544#define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
545
546#define S_FW_FILTER_WR_PORT	9
547#define M_FW_FILTER_WR_PORT	0x7
548#define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
549#define G_FW_FILTER_WR_PORT(x)	\
550    (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
551
552#define S_FW_FILTER_WR_PORTM	6
553#define M_FW_FILTER_WR_PORTM	0x7
554#define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
555#define G_FW_FILTER_WR_PORTM(x)	\
556    (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
557
558#define S_FW_FILTER_WR_MATCHTYPE	3
559#define M_FW_FILTER_WR_MATCHTYPE	0x7
560#define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
561#define G_FW_FILTER_WR_MATCHTYPE(x)	\
562    (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
563
564#define S_FW_FILTER_WR_MATCHTYPEM	0
565#define M_FW_FILTER_WR_MATCHTYPEM	0x7
566#define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
567#define G_FW_FILTER_WR_MATCHTYPEM(x)	\
568    (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
569
570struct fw_ulptx_wr {
571	__be32 op_to_compl;
572	__be32 flowid_len16;
573	__u64  cookie;
574};
575
576struct fw_tp_wr {
577	__be32 op_to_immdlen;
578	__be32 flowid_len16;
579	__u64  cookie;
580};
581
582struct fw_eth_tx_pkt_wr {
583	__be32 op_immdlen;
584	__be32 equiq_to_len16;
585	__be64 r3;
586};
587
588#define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
589#define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
590#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
591#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
592    (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
593
594struct fw_eth_tx_pkt2_wr {
595	__be32 op_immdlen;
596	__be32 equiq_to_len16;
597	__be32 r3;
598	__be32 L4ChkDisable_to_IpHdrLen;
599};
600
601#define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
602#define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
603#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
604#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
605    (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
606
607#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
608#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
609#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
610    ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
611#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
612    (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
613     M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
614#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
615    V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
616
617#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
618#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
619#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
620    ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
621#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
622    (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
623     M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
624#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
625    V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
626
627#define S_FW_ETH_TX_PKT2_WR_IVLAN	28
628#define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
629#define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
630#define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
631    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
632#define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
633
634#define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
635#define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
636#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
637#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
638    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
639
640#define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
641#define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
642#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
643#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
644    (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
645
646#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
647#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
648#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
649#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
650    (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
651
652struct fw_eth_tx_pkts_wr {
653	__be32 op_pkd;
654	__be32 equiq_to_len16;
655	__be32 r3;
656	__be16 plen;
657	__u8   npkt;
658	__u8   type;
659};
660
661#define S_FW_PTP_TX_PKT_WR_IMMDLEN      0
662#define M_FW_PTP_TX_PKT_WR_IMMDLEN      0x1ff
663#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
664#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x)   \
665    (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
666
667struct fw_eth_tx_pkt_ptp_wr {
668	__be32 op_immdlen;
669	__be32 equiq_to_len16;
670	__be64 r3;
671};
672
673enum fw_eth_tx_eo_type {
674	FW_ETH_TX_EO_TYPE_UDPSEG,
675	FW_ETH_TX_EO_TYPE_TCPSEG,
676	FW_ETH_TX_EO_TYPE_NVGRESEG,
677	FW_ETH_TX_EO_TYPE_VXLANSEG,
678	FW_ETH_TX_EO_TYPE_GENEVESEG,
679};
680
681struct fw_eth_tx_eo_wr {
682	__be32 op_immdlen;
683	__be32 equiq_to_len16;
684	__be64 r3;
685	union fw_eth_tx_eo {
686		struct fw_eth_tx_eo_udpseg {
687			__u8   type;
688			__u8   ethlen;
689			__be16 iplen;
690			__u8   udplen;
691			__u8   rtplen;
692			__be16 r4;
693			__be16 mss;
694			__be16 schedpktsize;
695			__be32 plen;
696		} udpseg;
697		struct fw_eth_tx_eo_tcpseg {
698			__u8   type;
699			__u8   ethlen;
700			__be16 iplen;
701			__u8   tcplen;
702			__u8   tsclk_tsoff;
703			__be16 r4;
704			__be16 mss;
705			__be16 r5;
706			__be32 plen;
707		} tcpseg;
708		struct fw_eth_tx_eo_nvgreseg {
709			__u8   type;
710			__u8   iphdroffout;
711			__be16 grehdroff;
712			__be16 iphdroffin;
713			__be16 tcphdroffin;
714			__be16 mss;
715			__be16 r4;
716			__be32 plen;
717		} nvgreseg;
718		struct fw_eth_tx_eo_vxlanseg {
719			__u8   type;
720			__u8   iphdroffout;
721			__be16 vxlanhdroff;
722			__be16 iphdroffin;
723			__be16 tcphdroffin;
724			__be16 mss;
725			__be16 r4;
726			__be32 plen;
727
728		} vxlanseg;
729		struct fw_eth_tx_eo_geneveseg {
730			__u8   type;
731			__u8   iphdroffout;
732			__be16 genevehdroff;
733			__be16 iphdroffin;
734			__be16 tcphdroffin;
735			__be16 mss;
736			__be16 r4;
737			__be32 plen;
738		} geneveseg;
739	} u;
740};
741
742#define S_FW_ETH_TX_EO_WR_IMMDLEN	0
743#define M_FW_ETH_TX_EO_WR_IMMDLEN	0x1ff
744#define V_FW_ETH_TX_EO_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
745#define G_FW_ETH_TX_EO_WR_IMMDLEN(x)	\
746    (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
747
748#define S_FW_ETH_TX_EO_WR_TSCLK		6
749#define M_FW_ETH_TX_EO_WR_TSCLK		0x3
750#define V_FW_ETH_TX_EO_WR_TSCLK(x)	((x) << S_FW_ETH_TX_EO_WR_TSCLK)
751#define G_FW_ETH_TX_EO_WR_TSCLK(x)	\
752    (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
753
754#define S_FW_ETH_TX_EO_WR_TSOFF		0
755#define M_FW_ETH_TX_EO_WR_TSOFF		0x3f
756#define V_FW_ETH_TX_EO_WR_TSOFF(x)	((x) << S_FW_ETH_TX_EO_WR_TSOFF)
757#define G_FW_ETH_TX_EO_WR_TSOFF(x)	\
758    (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
759
760struct fw_eq_flush_wr {
761	__u8   opcode;
762	__u8   r1[3];
763	__be32 equiq_to_len16;
764	__be64 r3;
765};
766
767struct fw_ofld_connection_wr {
768	__be32 op_compl;
769	__be32 len16_pkd;
770	__u64  cookie;
771	__be64 r2;
772	__be64 r3;
773	struct fw_ofld_connection_le {
774		__be32 version_cpl;
775		__be32 filter;
776		__be32 r1;
777		__be16 lport;
778		__be16 pport;
779		union fw_ofld_connection_leip {
780			struct fw_ofld_connection_le_ipv4 {
781				__be32 pip;
782				__be32 lip;
783				__be64 r0;
784				__be64 r1;
785				__be64 r2;
786			} ipv4;
787			struct fw_ofld_connection_le_ipv6 {
788				__be64 pip_hi;
789				__be64 pip_lo;
790				__be64 lip_hi;
791				__be64 lip_lo;
792			} ipv6;
793		} u;
794	} le;
795	struct fw_ofld_connection_tcb {
796		__be32 t_state_to_astid;
797		__be16 cplrxdataack_cplpassacceptrpl;
798		__be16 rcv_adv;
799		__be32 rcv_nxt;
800		__be32 tx_max;
801		__be64 opt0;
802		__be32 opt2;
803		__be32 r1;
804		__be64 r2;
805		__be64 r3;
806	} tcb;
807};
808
809#define S_FW_OFLD_CONNECTION_WR_VERSION		31
810#define M_FW_OFLD_CONNECTION_WR_VERSION		0x1
811#define V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
812    ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
813#define G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
814    (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
815     M_FW_OFLD_CONNECTION_WR_VERSION)
816#define F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
817
818#define S_FW_OFLD_CONNECTION_WR_CPL	30
819#define M_FW_OFLD_CONNECTION_WR_CPL	0x1
820#define V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
821#define G_FW_OFLD_CONNECTION_WR_CPL(x)	\
822    (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
823#define F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
824
825#define S_FW_OFLD_CONNECTION_WR_T_STATE		28
826#define M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
827#define V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
828    ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
829#define G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
830    (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
831     M_FW_OFLD_CONNECTION_WR_T_STATE)
832
833#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
834#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
835#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
836    ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
837#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
838    (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
839     M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
840
841#define S_FW_OFLD_CONNECTION_WR_ASTID		0
842#define M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
843#define V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
844    ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
845#define G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
846    (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
847
848#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
849#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
850#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
851    ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
852#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
853    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
854     M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
855#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
856    V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
857
858#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
859#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
860#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
861    ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
862#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
863    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
864     M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
865#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
866    V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
867
868enum fw_flowc_mnem_tcpstate {
869	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0, /* illegal */
870	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1, /* illegal */
871	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2, /* illegal */
872	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
873	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
874	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
875	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6, /* haven't gotten ACK for FIN and
876					      * will resend FIN - equiv ESTAB
877					      */
878	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7, /* haven't gotten ACK for FIN and
879					      * will resend FIN but have
880					      * received FIN
881					      */
882	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8, /* haven't gotten ACK for FIN and
883					      * will resend FIN but have
884					      * received FIN
885					      */
886	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9, /* sent FIN and got FIN + ACK,
887					      * waiting for FIN
888					      */
889	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10, /* not expected */
890};
891
892enum fw_flowc_mnem_eostate {
893	FW_FLOWC_MNEM_EOSTATE_CLOSED	= 0, /* illegal */
894	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
895	FW_FLOWC_MNEM_EOSTATE_CLOSING	= 2, /* graceful close, after sending
896					      * outstanding payload
897					      */
898	FW_FLOWC_MNEM_EOSTATE_ABORTING	= 3, /* immediate close, after
899					      * discarding outstanding payload
900					      */
901};
902
903enum fw_flowc_mnem {
904	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
905	FW_FLOWC_MNEM_CH		= 1,
906	FW_FLOWC_MNEM_PORT		= 2,
907	FW_FLOWC_MNEM_IQID		= 3,
908	FW_FLOWC_MNEM_SNDNXT		= 4,
909	FW_FLOWC_MNEM_RCVNXT		= 5,
910	FW_FLOWC_MNEM_SNDBUF		= 6,
911	FW_FLOWC_MNEM_MSS		= 7,
912	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
913	FW_FLOWC_MNEM_TCPSTATE		= 9,
914	FW_FLOWC_MNEM_EOSTATE		= 10,
915	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
916	FW_FLOWC_MNEM_DCBPRIO		= 12,
917	FW_FLOWC_MNEM_SND_SCALE		= 13,
918	FW_FLOWC_MNEM_RCV_SCALE		= 14,
919	FW_FLOWC_MNEM_ULP_MODE		= 15,
920	FW_FLOWC_MNEM_MAX		= 16,
921};
922
923struct fw_flowc_mnemval {
924	__u8   mnemonic;
925	__u8   r4[3];
926	__be32 val;
927};
928
929struct fw_flowc_wr {
930	__be32 op_to_nparams;
931	__be32 flowid_len16;
932#ifndef C99_NOT_SUPPORTED
933	struct fw_flowc_mnemval mnemval[0];
934#endif
935};
936
937#define S_FW_FLOWC_WR_NPARAMS		0
938#define M_FW_FLOWC_WR_NPARAMS		0xff
939#define V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
940#define G_FW_FLOWC_WR_NPARAMS(x)	\
941    (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
942
943struct fw_ofld_tx_data_wr {
944	__be32 op_to_immdlen;
945	__be32 flowid_len16;
946	__be32 plen;
947	__be32 lsodisable_to_flags;
948};
949
950#define S_FW_OFLD_TX_DATA_WR_LSODISABLE		31
951#define M_FW_OFLD_TX_DATA_WR_LSODISABLE		0x1
952#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
953    ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
954#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
955    (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
956     M_FW_OFLD_TX_DATA_WR_LSODISABLE)
957#define F_FW_OFLD_TX_DATA_WR_LSODISABLE	V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
958
959#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD		30
960#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD		0x1
961#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
962    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
963#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
964    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
965#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD	V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
966
967#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	29
968#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	0x1
969#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
970    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
971#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
972    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
973     M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
974#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	\
975    V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
976
977#define S_FW_OFLD_TX_DATA_WR_FLAGS	0
978#define M_FW_OFLD_TX_DATA_WR_FLAGS	0xfffffff
979#define V_FW_OFLD_TX_DATA_WR_FLAGS(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
980#define G_FW_OFLD_TX_DATA_WR_FLAGS(x)	\
981    (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
982
983
984/* Use fw_ofld_tx_data_wr structure */
985#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI		10
986#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI		0x3fffff
987#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
988    ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
989#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
990    (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
991
992#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	9
993#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	0x1
994#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
995    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
996#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
997    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
998     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
999#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	\
1000    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1001
1002#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	8
1003#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	0x1
1004#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1005    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1006#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1007    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1008     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1009#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	\
1010    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1011
1012#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		7
1013#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		0x1
1014#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1015    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1016#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1017    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1018     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1019#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC	\
1020    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1021
1022#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		6
1023#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		0x1
1024#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1025    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1026#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1027    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1028     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1029#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC	\
1030    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1031
1032#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0
1033#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0x3f
1034#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1035    ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1036#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1037    (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1038
1039struct fw_cmd_wr {
1040	__be32 op_dma;
1041	__be32 len16_pkd;
1042	__be64 cookie_daddr;
1043};
1044
1045#define S_FW_CMD_WR_DMA		17
1046#define M_FW_CMD_WR_DMA		0x1
1047#define V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
1048#define G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1049#define F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
1050
1051struct fw_eth_tx_pkt_vm_wr {
1052	__be32 op_immdlen;
1053	__be32 equiq_to_len16;
1054	__be32 r3[2];
1055	__u8   ethmacdst[6];
1056	__u8   ethmacsrc[6];
1057	__be16 ethtype;
1058	__be16 vlantci;
1059};
1060
1061/******************************************************************************
1062 *   R I   W O R K   R E Q U E S T s
1063 **************************************/
1064
1065enum fw_ri_wr_opcode {
1066	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
1067	FW_RI_READ_REQ			= 0x1,
1068	FW_RI_READ_RESP			= 0x2,
1069	FW_RI_SEND			= 0x3,
1070	FW_RI_SEND_WITH_INV		= 0x4,
1071	FW_RI_SEND_WITH_SE		= 0x5,
1072	FW_RI_SEND_WITH_SE_INV		= 0x6,
1073	FW_RI_TERMINATE			= 0x7,
1074	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
1075	FW_RI_BIND_MW			= 0x9,
1076	FW_RI_FAST_REGISTER		= 0xa,
1077	FW_RI_LOCAL_INV			= 0xb,
1078	FW_RI_QP_MODIFY			= 0xc,
1079	FW_RI_BYPASS			= 0xd,
1080	FW_RI_RECEIVE			= 0xe,
1081#if 0
1082	FW_RI_SEND_IMMEDIATE		= 0x8,
1083	FW_RI_SEND_IMMEDIATE_WITH_SE	= 0x9,
1084	FW_RI_ATOMIC_REQUEST		= 0xa,
1085	FW_RI_ATOMIC_RESPONSE		= 0xb,
1086
1087	FW_RI_BIND_MW			= 0xc, /* CHELSIO RI specific ... */
1088	FW_RI_FAST_REGISTER		= 0xd,
1089	FW_RI_LOCAL_INV			= 0xe,
1090#endif
1091	FW_RI_SGE_EC_CR_RETURN		= 0xf
1092};
1093
1094enum fw_ri_wr_flags {
1095	FW_RI_COMPLETION_FLAG		= 0x01,
1096	FW_RI_NOTIFICATION_FLAG		= 0x02,
1097	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
1098	FW_RI_READ_FENCE_FLAG		= 0x08,
1099	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
1100	FW_RI_RDMA_READ_INVALIDATE	= 0x20
1101};
1102
1103enum fw_ri_mpa_attrs {
1104	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
1105	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
1106	FW_RI_MPA_CRC_ENABLE		= 0x04,
1107	FW_RI_MPA_IETF_ENABLE		= 0x08
1108};
1109
1110enum fw_ri_qp_caps {
1111	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
1112	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
1113	FW_RI_QP_BIND_ENABLE		= 0x04,
1114	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
1115	FW_RI_QP_STAG0_ENABLE		= 0x10,
1116	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1117};
1118
1119enum fw_ri_addr_type {
1120	FW_RI_ZERO_BASED_TO		= 0x00,
1121	FW_RI_VA_BASED_TO		= 0x01
1122};
1123
1124enum fw_ri_mem_perms {
1125	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
1126	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
1127	FW_RI_MEM_ACCESS_REM		= 0x03,
1128	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
1129	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
1130	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
1131};
1132
1133enum fw_ri_stag_type {
1134	FW_RI_STAG_NSMR			= 0x00,
1135	FW_RI_STAG_SMR			= 0x01,
1136	FW_RI_STAG_MW			= 0x02,
1137	FW_RI_STAG_MW_RELAXED		= 0x03
1138};
1139
1140enum fw_ri_data_op {
1141	FW_RI_DATA_IMMD			= 0x81,
1142	FW_RI_DATA_DSGL			= 0x82,
1143	FW_RI_DATA_ISGL			= 0x83
1144};
1145
1146enum fw_ri_sgl_depth {
1147	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
1148	FW_RI_SGL_DEPTH_MAX_RQ		= 4
1149};
1150
1151enum fw_ri_cqe_err {
1152	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
1153	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
1154	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
1155	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
1156	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
1157	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
1158	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
1159	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1160	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1161	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
1162	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1163	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B, /* pbl address out of bound : software error */
1164	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
1165	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
1166	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
1167	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
1168	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
1169	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
1170	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
1171	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
1172	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
1173	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
1174	FW_RI_CQE_ERR_MO		= 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1175	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
1176	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
1177	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
1178	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E, /*  RQE address out of bound : software error */
1179	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F  /* internel error (opcode mismatch) */
1180
1181};
1182
1183struct fw_ri_dsge_pair {
1184	__be32	len[2];
1185	__be64	addr[2];
1186};
1187
1188struct fw_ri_dsgl {
1189	__u8	op;
1190	__u8	r1;
1191	__be16	nsge;
1192	__be32	len0;
1193	__be64	addr0;
1194#ifndef C99_NOT_SUPPORTED
1195	struct fw_ri_dsge_pair sge[0];
1196#endif
1197};
1198
1199struct fw_ri_sge {
1200	__be32 stag;
1201	__be32 len;
1202	__be64 to;
1203};
1204
1205struct fw_ri_isgl {
1206	__u8	op;
1207	__u8	r1;
1208	__be16	nsge;
1209	__be32	r2;
1210#ifndef C99_NOT_SUPPORTED
1211	struct fw_ri_sge sge[0];
1212#endif
1213};
1214
1215struct fw_ri_immd {
1216	__u8	op;
1217	__u8	r1;
1218	__be16	r2;
1219	__be32	immdlen;
1220#ifndef C99_NOT_SUPPORTED
1221	__u8	data[0];
1222#endif
1223};
1224
1225struct fw_ri_tpte {
1226	__be32 valid_to_pdid;
1227	__be32 locread_to_qpid;
1228	__be32 nosnoop_pbladdr;
1229	__be32 len_lo;
1230	__be32 va_hi;
1231	__be32 va_lo_fbo;
1232	__be32 dca_mwbcnt_pstag;
1233	__be32 len_hi;
1234};
1235
1236#define S_FW_RI_TPTE_VALID		31
1237#define M_FW_RI_TPTE_VALID		0x1
1238#define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
1239#define G_FW_RI_TPTE_VALID(x)		\
1240    (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1241#define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1242
1243#define S_FW_RI_TPTE_STAGKEY		23
1244#define M_FW_RI_TPTE_STAGKEY		0xff
1245#define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1246#define G_FW_RI_TPTE_STAGKEY(x)		\
1247    (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1248
1249#define S_FW_RI_TPTE_STAGSTATE		22
1250#define M_FW_RI_TPTE_STAGSTATE		0x1
1251#define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1252#define G_FW_RI_TPTE_STAGSTATE(x)	\
1253    (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1254#define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1255
1256#define S_FW_RI_TPTE_STAGTYPE		20
1257#define M_FW_RI_TPTE_STAGTYPE		0x3
1258#define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1259#define G_FW_RI_TPTE_STAGTYPE(x)	\
1260    (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1261
1262#define S_FW_RI_TPTE_PDID		0
1263#define M_FW_RI_TPTE_PDID		0xfffff
1264#define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1265#define G_FW_RI_TPTE_PDID(x)		\
1266    (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1267
1268#define S_FW_RI_TPTE_PERM		28
1269#define M_FW_RI_TPTE_PERM		0xf
1270#define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1271#define G_FW_RI_TPTE_PERM(x)		\
1272    (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1273
1274#define S_FW_RI_TPTE_REMINVDIS		27
1275#define M_FW_RI_TPTE_REMINVDIS		0x1
1276#define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1277#define G_FW_RI_TPTE_REMINVDIS(x)	\
1278    (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1279#define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1280
1281#define S_FW_RI_TPTE_ADDRTYPE		26
1282#define M_FW_RI_TPTE_ADDRTYPE		1
1283#define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1284#define G_FW_RI_TPTE_ADDRTYPE(x)	\
1285    (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1286#define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1287
1288#define S_FW_RI_TPTE_MWBINDEN		25
1289#define M_FW_RI_TPTE_MWBINDEN		0x1
1290#define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1291#define G_FW_RI_TPTE_MWBINDEN(x)	\
1292    (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1293#define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1294
1295#define S_FW_RI_TPTE_PS			20
1296#define M_FW_RI_TPTE_PS			0x1f
1297#define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1298#define G_FW_RI_TPTE_PS(x)		\
1299    (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1300
1301#define S_FW_RI_TPTE_QPID		0
1302#define M_FW_RI_TPTE_QPID		0xfffff
1303#define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1304#define G_FW_RI_TPTE_QPID(x)		\
1305    (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1306
1307#define S_FW_RI_TPTE_NOSNOOP		31
1308#define M_FW_RI_TPTE_NOSNOOP		0x1
1309#define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1310#define G_FW_RI_TPTE_NOSNOOP(x)		\
1311    (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1312#define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1313
1314#define S_FW_RI_TPTE_PBLADDR		0
1315#define M_FW_RI_TPTE_PBLADDR		0x1fffffff
1316#define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1317#define G_FW_RI_TPTE_PBLADDR(x)		\
1318    (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1319
1320#define S_FW_RI_TPTE_DCA		24
1321#define M_FW_RI_TPTE_DCA		0x1f
1322#define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1323#define G_FW_RI_TPTE_DCA(x)		\
1324    (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1325
1326#define S_FW_RI_TPTE_MWBCNT_PSTAG	0
1327#define M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
1328#define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1329    ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1330#define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1331    (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1332
1333enum fw_ri_cqe_rxtx {
1334	FW_RI_CQE_RXTX_RX = 0x0,
1335	FW_RI_CQE_RXTX_TX = 0x1,
1336};
1337
1338struct fw_ri_cqe {
1339	union fw_ri_rxtx {
1340		struct fw_ri_scqe {
1341		__be32	qpid_n_stat_rxtx_type;
1342		__be32	plen;
1343		__be32	stag;
1344		__be32	wrid;
1345		} scqe;
1346		struct fw_ri_rcqe {
1347		__be32	qpid_n_stat_rxtx_type;
1348		__be32	plen;
1349		__be32	stag;
1350		__be32	msn;
1351		} rcqe;
1352	} u;
1353};
1354
1355#define S_FW_RI_CQE_QPID      12
1356#define M_FW_RI_CQE_QPID      0xfffff
1357#define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1358#define G_FW_RI_CQE_QPID(x)   \
1359    (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1360
1361#define S_FW_RI_CQE_NOTIFY    10
1362#define M_FW_RI_CQE_NOTIFY    0x1
1363#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1364#define G_FW_RI_CQE_NOTIFY(x) \
1365    (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1366
1367#define S_FW_RI_CQE_STATUS    5
1368#define M_FW_RI_CQE_STATUS    0x1f
1369#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1370#define G_FW_RI_CQE_STATUS(x) \
1371    (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1372
1373
1374#define S_FW_RI_CQE_RXTX      4
1375#define M_FW_RI_CQE_RXTX      0x1
1376#define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1377#define G_FW_RI_CQE_RXTX(x)   \
1378    (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1379
1380#define S_FW_RI_CQE_TYPE      0
1381#define M_FW_RI_CQE_TYPE      0xf
1382#define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1383#define G_FW_RI_CQE_TYPE(x)   \
1384    (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1385
1386enum fw_ri_res_type {
1387	FW_RI_RES_TYPE_SQ,
1388	FW_RI_RES_TYPE_RQ,
1389	FW_RI_RES_TYPE_CQ,
1390	FW_RI_RES_TYPE_SRQ,
1391};
1392
1393enum fw_ri_res_op {
1394	FW_RI_RES_OP_WRITE,
1395	FW_RI_RES_OP_RESET,
1396};
1397
1398struct fw_ri_res {
1399	union fw_ri_restype {
1400		struct fw_ri_res_sqrq {
1401			__u8   restype;
1402			__u8   op;
1403			__be16 r3;
1404			__be32 eqid;
1405			__be32 r4[2];
1406			__be32 fetchszm_to_iqid;
1407			__be32 dcaen_to_eqsize;
1408			__be64 eqaddr;
1409		} sqrq;
1410		struct fw_ri_res_cq {
1411			__u8   restype;
1412			__u8   op;
1413			__be16 r3;
1414			__be32 iqid;
1415			__be32 r4[2];
1416			__be32 iqandst_to_iqandstindex;
1417			__be16 iqdroprss_to_iqesize;
1418			__be16 iqsize;
1419			__be64 iqaddr;
1420			__be32 iqns_iqro;
1421			__be32 r6_lo;
1422			__be64 r7;
1423		} cq;
1424		struct fw_ri_res_srq {
1425			__u8   restype;
1426			__u8   op;
1427			__be16 r3;
1428			__be32 eqid;
1429			__be32 r4[2];
1430			__be32 fetchszm_to_iqid;
1431			__be32 dcaen_to_eqsize;
1432			__be64 eqaddr;
1433			__be32 srqid;
1434			__be32 pdid;
1435			__be32 hwsrqsize;
1436			__be32 hwsrqaddr;
1437		} srq;
1438	} u;
1439};
1440
1441struct fw_ri_res_wr {
1442	__be32 op_nres;
1443	__be32 len16_pkd;
1444	__u64  cookie;
1445#ifndef C99_NOT_SUPPORTED
1446	struct fw_ri_res res[0];
1447#endif
1448};
1449
1450#define S_FW_RI_RES_WR_NRES	0
1451#define M_FW_RI_RES_WR_NRES	0xff
1452#define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1453#define G_FW_RI_RES_WR_NRES(x)	\
1454    (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1455
1456#define S_FW_RI_RES_WR_FETCHSZM		26
1457#define M_FW_RI_RES_WR_FETCHSZM		0x1
1458#define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1459#define G_FW_RI_RES_WR_FETCHSZM(x)	\
1460    (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1461#define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1462
1463#define S_FW_RI_RES_WR_STATUSPGNS	25
1464#define M_FW_RI_RES_WR_STATUSPGNS	0x1
1465#define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1466#define G_FW_RI_RES_WR_STATUSPGNS(x)	\
1467    (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1468#define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1469
1470#define S_FW_RI_RES_WR_STATUSPGRO	24
1471#define M_FW_RI_RES_WR_STATUSPGRO	0x1
1472#define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1473#define G_FW_RI_RES_WR_STATUSPGRO(x)	\
1474    (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1475#define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
1476
1477#define S_FW_RI_RES_WR_FETCHNS		23
1478#define M_FW_RI_RES_WR_FETCHNS		0x1
1479#define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
1480#define G_FW_RI_RES_WR_FETCHNS(x)	\
1481    (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1482#define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
1483
1484#define S_FW_RI_RES_WR_FETCHRO		22
1485#define M_FW_RI_RES_WR_FETCHRO		0x1
1486#define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
1487#define G_FW_RI_RES_WR_FETCHRO(x)	\
1488    (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1489#define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
1490
1491#define S_FW_RI_RES_WR_HOSTFCMODE	20
1492#define M_FW_RI_RES_WR_HOSTFCMODE	0x3
1493#define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1494#define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
1495    (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1496
1497#define S_FW_RI_RES_WR_CPRIO	19
1498#define M_FW_RI_RES_WR_CPRIO	0x1
1499#define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
1500#define G_FW_RI_RES_WR_CPRIO(x)	\
1501    (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1502#define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
1503
1504#define S_FW_RI_RES_WR_ONCHIP		18
1505#define M_FW_RI_RES_WR_ONCHIP		0x1
1506#define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
1507#define G_FW_RI_RES_WR_ONCHIP(x)	\
1508    (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1509#define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
1510
1511#define S_FW_RI_RES_WR_PCIECHN		16
1512#define M_FW_RI_RES_WR_PCIECHN		0x3
1513#define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
1514#define G_FW_RI_RES_WR_PCIECHN(x)	\
1515    (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1516
1517#define S_FW_RI_RES_WR_IQID	0
1518#define M_FW_RI_RES_WR_IQID	0xffff
1519#define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
1520#define G_FW_RI_RES_WR_IQID(x)	\
1521    (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1522
1523#define S_FW_RI_RES_WR_DCAEN	31
1524#define M_FW_RI_RES_WR_DCAEN	0x1
1525#define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
1526#define G_FW_RI_RES_WR_DCAEN(x)	\
1527    (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1528#define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
1529
1530#define S_FW_RI_RES_WR_DCACPU		26
1531#define M_FW_RI_RES_WR_DCACPU		0x1f
1532#define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
1533#define G_FW_RI_RES_WR_DCACPU(x)	\
1534    (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1535
1536#define S_FW_RI_RES_WR_FBMIN	23
1537#define M_FW_RI_RES_WR_FBMIN	0x7
1538#define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
1539#define G_FW_RI_RES_WR_FBMIN(x)	\
1540    (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1541
1542#define S_FW_RI_RES_WR_FBMAX	20
1543#define M_FW_RI_RES_WR_FBMAX	0x7
1544#define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
1545#define G_FW_RI_RES_WR_FBMAX(x)	\
1546    (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1547
1548#define S_FW_RI_RES_WR_CIDXFTHRESHO	19
1549#define M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
1550#define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1551#define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
1552    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1553#define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1554
1555#define S_FW_RI_RES_WR_CIDXFTHRESH	16
1556#define M_FW_RI_RES_WR_CIDXFTHRESH	0x7
1557#define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1558#define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
1559    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1560
1561#define S_FW_RI_RES_WR_EQSIZE		0
1562#define M_FW_RI_RES_WR_EQSIZE		0xffff
1563#define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
1564#define G_FW_RI_RES_WR_EQSIZE(x)	\
1565    (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1566
1567#define S_FW_RI_RES_WR_IQANDST		15
1568#define M_FW_RI_RES_WR_IQANDST		0x1
1569#define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
1570#define G_FW_RI_RES_WR_IQANDST(x)	\
1571    (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1572#define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
1573
1574#define S_FW_RI_RES_WR_IQANUS		14
1575#define M_FW_RI_RES_WR_IQANUS		0x1
1576#define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
1577#define G_FW_RI_RES_WR_IQANUS(x)	\
1578    (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1579#define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
1580
1581#define S_FW_RI_RES_WR_IQANUD		12
1582#define M_FW_RI_RES_WR_IQANUD		0x3
1583#define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
1584#define G_FW_RI_RES_WR_IQANUD(x)	\
1585    (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1586
1587#define S_FW_RI_RES_WR_IQANDSTINDEX	0
1588#define M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
1589#define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1590#define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
1591    (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1592
1593#define S_FW_RI_RES_WR_IQDROPRSS	15
1594#define M_FW_RI_RES_WR_IQDROPRSS	0x1
1595#define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
1596#define G_FW_RI_RES_WR_IQDROPRSS(x)	\
1597    (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1598#define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
1599
1600#define S_FW_RI_RES_WR_IQGTSMODE	14
1601#define M_FW_RI_RES_WR_IQGTSMODE	0x1
1602#define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
1603#define G_FW_RI_RES_WR_IQGTSMODE(x)	\
1604    (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1605#define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
1606
1607#define S_FW_RI_RES_WR_IQPCIECH		12
1608#define M_FW_RI_RES_WR_IQPCIECH		0x3
1609#define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
1610#define G_FW_RI_RES_WR_IQPCIECH(x)	\
1611    (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1612
1613#define S_FW_RI_RES_WR_IQDCAEN		11
1614#define M_FW_RI_RES_WR_IQDCAEN		0x1
1615#define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
1616#define G_FW_RI_RES_WR_IQDCAEN(x)	\
1617    (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1618#define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
1619
1620#define S_FW_RI_RES_WR_IQDCACPU		6
1621#define M_FW_RI_RES_WR_IQDCACPU		0x1f
1622#define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
1623#define G_FW_RI_RES_WR_IQDCACPU(x)	\
1624    (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1625
1626#define S_FW_RI_RES_WR_IQINTCNTTHRESH		4
1627#define M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
1628#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1629    ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1630#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1631    (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1632
1633#define S_FW_RI_RES_WR_IQO	3
1634#define M_FW_RI_RES_WR_IQO	0x1
1635#define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
1636#define G_FW_RI_RES_WR_IQO(x)	\
1637    (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1638#define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
1639
1640#define S_FW_RI_RES_WR_IQCPRIO		2
1641#define M_FW_RI_RES_WR_IQCPRIO		0x1
1642#define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
1643#define G_FW_RI_RES_WR_IQCPRIO(x)	\
1644    (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1645#define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
1646
1647#define S_FW_RI_RES_WR_IQESIZE		0
1648#define M_FW_RI_RES_WR_IQESIZE		0x3
1649#define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
1650#define G_FW_RI_RES_WR_IQESIZE(x)	\
1651    (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1652
1653#define S_FW_RI_RES_WR_IQNS	31
1654#define M_FW_RI_RES_WR_IQNS	0x1
1655#define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
1656#define G_FW_RI_RES_WR_IQNS(x)	\
1657    (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1658#define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
1659
1660#define S_FW_RI_RES_WR_IQRO	30
1661#define M_FW_RI_RES_WR_IQRO	0x1
1662#define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
1663#define G_FW_RI_RES_WR_IQRO(x)	\
1664    (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1665#define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
1666
1667struct fw_ri_rdma_write_wr {
1668	__u8   opcode;
1669	__u8   flags;
1670	__u16  wrid;
1671	__u8   r1[3];
1672	__u8   len16;
1673	__be64 r2;
1674	__be32 plen;
1675	__be32 stag_sink;
1676	__be64 to_sink;
1677#ifndef C99_NOT_SUPPORTED
1678	union {
1679		struct fw_ri_immd immd_src[0];
1680		struct fw_ri_isgl isgl_src[0];
1681	} u;
1682#endif
1683};
1684
1685struct fw_ri_send_wr {
1686	__u8   opcode;
1687	__u8   flags;
1688	__u16  wrid;
1689	__u8   r1[3];
1690	__u8   len16;
1691	__be32 sendop_pkd;
1692	__be32 stag_inv;
1693	__be32 plen;
1694	__be32 r3;
1695	__be64 r4;
1696#ifndef C99_NOT_SUPPORTED
1697	union {
1698		struct fw_ri_immd immd_src[0];
1699		struct fw_ri_isgl isgl_src[0];
1700	} u;
1701#endif
1702};
1703
1704#define S_FW_RI_SEND_WR_SENDOP		0
1705#define M_FW_RI_SEND_WR_SENDOP		0xf
1706#define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
1707#define G_FW_RI_SEND_WR_SENDOP(x)	\
1708    (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1709
1710struct fw_ri_rdma_read_wr {
1711	__u8   opcode;
1712	__u8   flags;
1713	__u16  wrid;
1714	__u8   r1[3];
1715	__u8   len16;
1716	__be64 r2;
1717	__be32 stag_sink;
1718	__be32 to_sink_hi;
1719	__be32 to_sink_lo;
1720	__be32 plen;
1721	__be32 stag_src;
1722	__be32 to_src_hi;
1723	__be32 to_src_lo;
1724	__be32 r5;
1725};
1726
1727struct fw_ri_recv_wr {
1728	__u8   opcode;
1729	__u8   r1;
1730	__u16  wrid;
1731	__u8   r2[3];
1732	__u8   len16;
1733	struct fw_ri_isgl isgl;
1734};
1735
1736struct fw_ri_bind_mw_wr {
1737	__u8   opcode;
1738	__u8   flags;
1739	__u16  wrid;
1740	__u8   r1[3];
1741	__u8   len16;
1742	__u8   qpbinde_to_dcacpu;
1743	__u8   pgsz_shift;
1744	__u8   addr_type;
1745	__u8   mem_perms;
1746	__be32 stag_mr;
1747	__be32 stag_mw;
1748	__be32 r3;
1749	__be64 len_mw;
1750	__be64 va_fbo;
1751	__be64 r4;
1752};
1753
1754#define S_FW_RI_BIND_MW_WR_QPBINDE	6
1755#define M_FW_RI_BIND_MW_WR_QPBINDE	0x1
1756#define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1757#define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
1758    (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1759#define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1760
1761#define S_FW_RI_BIND_MW_WR_NS		5
1762#define M_FW_RI_BIND_MW_WR_NS		0x1
1763#define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
1764#define G_FW_RI_BIND_MW_WR_NS(x)	\
1765    (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1766#define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
1767
1768#define S_FW_RI_BIND_MW_WR_DCACPU	0
1769#define M_FW_RI_BIND_MW_WR_DCACPU	0x1f
1770#define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1771#define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
1772    (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1773
1774struct fw_ri_fr_nsmr_wr {
1775	__u8   opcode;
1776	__u8   flags;
1777	__u16  wrid;
1778	__u8   r1[3];
1779	__u8   len16;
1780	__u8   qpbinde_to_dcacpu;
1781	__u8   pgsz_shift;
1782	__u8   addr_type;
1783	__u8   mem_perms;
1784	__be32 stag;
1785	__be32 len_hi;
1786	__be32 len_lo;
1787	__be32 va_hi;
1788	__be32 va_lo_fbo;
1789};
1790
1791#define S_FW_RI_FR_NSMR_WR_QPBINDE	6
1792#define M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
1793#define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1794#define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
1795    (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1796#define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1797
1798#define S_FW_RI_FR_NSMR_WR_NS		5
1799#define M_FW_RI_FR_NSMR_WR_NS		0x1
1800#define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
1801#define G_FW_RI_FR_NSMR_WR_NS(x)	\
1802    (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1803#define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
1804
1805#define S_FW_RI_FR_NSMR_WR_DCACPU	0
1806#define M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
1807#define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1808#define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
1809    (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1810
1811struct fw_ri_fr_nsmr_tpte_wr {
1812	__u8   opcode;
1813	__u8   flags;
1814	__u16  wrid;
1815	__u8   r1[3];
1816	__u8   len16;
1817	__be32 r2;
1818	__be32 stag;
1819	struct fw_ri_tpte tpte;
1820	__be64 pbl[2];
1821};
1822
1823struct fw_ri_inv_lstag_wr {
1824	__u8   opcode;
1825	__u8   flags;
1826	__u16  wrid;
1827	__u8   r1[3];
1828	__u8   len16;
1829	__be32 r2;
1830	__be32 stag_inv;
1831};
1832
1833struct fw_ri_send_immediate_wr {
1834	__u8   opcode;
1835	__u8   flags;
1836	__u16  wrid;
1837	__u8   r1[3];
1838	__u8   len16;
1839	__be32 sendimmop_pkd;
1840	__be32 r3;
1841	__be32 plen;
1842	__be32 r4;
1843	__be64 r5;
1844#ifndef C99_NOT_SUPPORTED
1845	struct fw_ri_immd immd_src[0];
1846#endif
1847};
1848
1849#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
1850#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
1851#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1852    ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1853#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1854    (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1855     M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1856
1857enum fw_ri_atomic_op {
1858	FW_RI_ATOMIC_OP_FETCHADD,
1859	FW_RI_ATOMIC_OP_SWAP,
1860	FW_RI_ATOMIC_OP_CMDSWAP,
1861};
1862
1863struct fw_ri_atomic_wr {
1864	__u8   opcode;
1865	__u8   flags;
1866	__u16  wrid;
1867	__u8   r1[3];
1868	__u8   len16;
1869	__be32 atomicop_pkd;
1870	__be64 r3;
1871	__be32 aopcode_pkd;
1872	__be32 reqid;
1873	__be32 stag;
1874	__be32 to_hi;
1875	__be32 to_lo;
1876	__be32 addswap_data_hi;
1877	__be32 addswap_data_lo;
1878	__be32 addswap_mask_hi;
1879	__be32 addswap_mask_lo;
1880	__be32 compare_data_hi;
1881	__be32 compare_data_lo;
1882	__be32 compare_mask_hi;
1883	__be32 compare_mask_lo;
1884	__be32 r5;
1885};
1886
1887#define S_FW_RI_ATOMIC_WR_ATOMICOP	0
1888#define M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
1889#define V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1890#define G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
1891    (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1892
1893#define S_FW_RI_ATOMIC_WR_AOPCODE	0
1894#define M_FW_RI_ATOMIC_WR_AOPCODE	0xf
1895#define V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1896#define G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
1897    (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1898
1899enum fw_ri_type {
1900	FW_RI_TYPE_INIT,
1901	FW_RI_TYPE_FINI,
1902	FW_RI_TYPE_TERMINATE
1903};
1904
1905enum fw_ri_init_p2ptype {
1906	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
1907	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
1908	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
1909	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
1910	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
1911	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
1912	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
1913};
1914
1915enum fw_ri_init_rqeqid_srq {
1916	FW_RI_INIT_RQEQID_SRQ			= 1 << 31,
1917};
1918
1919struct fw_ri_wr {
1920	__be32 op_compl;
1921	__be32 flowid_len16;
1922	__u64  cookie;
1923	union fw_ri {
1924		struct fw_ri_init {
1925			__u8   type;
1926			__u8   mpareqbit_p2ptype;
1927			__u8   r4[2];
1928			__u8   mpa_attrs;
1929			__u8   qp_caps;
1930			__be16 nrqe;
1931			__be32 pdid;
1932			__be32 qpid;
1933			__be32 sq_eqid;
1934			__be32 rq_eqid;
1935			__be32 scqid;
1936			__be32 rcqid;
1937			__be32 ord_max;
1938			__be32 ird_max;
1939			__be32 iss;
1940			__be32 irs;
1941			__be32 hwrqsize;
1942			__be32 hwrqaddr;
1943			__be64 r5;
1944			union fw_ri_init_p2p {
1945				struct fw_ri_rdma_write_wr write;
1946				struct fw_ri_rdma_read_wr read;
1947				struct fw_ri_send_wr send;
1948			} u;
1949		} init;
1950		struct fw_ri_fini {
1951			__u8   type;
1952			__u8   r3[7];
1953			__be64 r4;
1954		} fini;
1955		struct fw_ri_terminate {
1956			__u8   type;
1957			__u8   r3[3];
1958			__be32 immdlen;
1959			__u8   termmsg[40];
1960		} terminate;
1961	} u;
1962};
1963
1964#define S_FW_RI_WR_MPAREQBIT	7
1965#define M_FW_RI_WR_MPAREQBIT	0x1
1966#define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
1967#define G_FW_RI_WR_MPAREQBIT(x)	\
1968    (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
1969#define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
1970
1971#define S_FW_RI_WR_0BRRBIT	6
1972#define M_FW_RI_WR_0BRRBIT	0x1
1973#define V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
1974#define G_FW_RI_WR_0BRRBIT(x)	\
1975    (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
1976#define F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
1977
1978#define S_FW_RI_WR_P2PTYPE	0
1979#define M_FW_RI_WR_P2PTYPE	0xf
1980#define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
1981#define G_FW_RI_WR_P2PTYPE(x)	\
1982    (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
1983
1984/******************************************************************************
1985 *  F O i S C S I   W O R K R E Q U E S T s
1986 *********************************************/
1987
1988#define	FW_FOISCSI_NAME_MAX_LEN		224
1989#define	FW_FOISCSI_ALIAS_MAX_LEN	224
1990#define FW_FOISCSI_CHAP_SEC_MAX_LEN	128
1991#define	FW_FOISCSI_INIT_NODE_MAX	8
1992
1993enum fw_chnet_ifconf_wr_subop {
1994	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
1995
1996	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
1997	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
1998
1999	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2000	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2001
2002	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2003	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2004
2005	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2006	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2007
2008	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2009	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2010
2011	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2012	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2013
2014	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2015	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2016
2017	FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2018	FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2019	FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2020
2021	FW_CHNET_IFCONF_WR_SUBOP_MAX,
2022};
2023
2024struct fw_chnet_ifconf_wr {
2025	__be32 op_compl;
2026	__be32 flowid_len16;
2027	__be64 cookie;
2028	__be32 if_flowid;
2029	__u8   idx;
2030	__u8   subop;
2031	__u8   retval;
2032	__u8   r2;
2033	__be64 r3;
2034	struct fw_chnet_ifconf_params {
2035		__be32 r0;
2036		__be16 vlanid;
2037		__be16 mtu;
2038		union fw_chnet_ifconf_addr_type {
2039			struct fw_chnet_ifconf_ipv4 {
2040				__be32 addr;
2041				__be32 mask;
2042				__be32 router;
2043				__be32 r0;
2044				__be64 r1;
2045			} ipv4;
2046			struct fw_chnet_ifconf_ipv6 {
2047				__u8   prefix_len;
2048				__u8   r0;
2049				__be16 r1;
2050				__be32 r2;
2051				__be64 addr_hi;
2052				__be64 addr_lo;
2053				__be64 router_hi;
2054				__be64 router_lo;
2055			} ipv6;
2056		} in_attr;
2057	} param;
2058};
2059
2060enum fw_foiscsi_node_type {
2061	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2062	FW_FOISCSI_NODE_TYPE_TARGET,
2063};
2064
2065enum fw_foiscsi_session_type {
2066	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2067	FW_FOISCSI_SESSION_TYPE_NORMAL,
2068};
2069
2070enum fw_foiscsi_auth_policy {
2071	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2072	FW_FOISCSI_AUTH_POLICY_MUTUAL,
2073};
2074
2075enum fw_foiscsi_auth_method {
2076	FW_FOISCSI_AUTH_METHOD_NONE = 0,
2077	FW_FOISCSI_AUTH_METHOD_CHAP,
2078	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2079	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2080};
2081
2082enum fw_foiscsi_digest_type {
2083	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2084	FW_FOISCSI_DIGEST_TYPE_CRC32,
2085	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2086	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2087};
2088
2089enum fw_foiscsi_wr_subop {
2090	FW_FOISCSI_WR_SUBOP_ADD = 1,
2091	FW_FOISCSI_WR_SUBOP_DEL = 2,
2092	FW_FOISCSI_WR_SUBOP_MOD = 4,
2093};
2094
2095enum fw_foiscsi_ctrl_state {
2096	FW_FOISCSI_CTRL_STATE_FREE = 0,
2097	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2098	FW_FOISCSI_CTRL_STATE_FAILED,
2099	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2100	FW_FOISCSI_CTRL_STATE_REDIRECT,
2101};
2102
2103struct fw_rdev_wr {
2104	__be32 op_to_immdlen;
2105	__be32 alloc_to_len16;
2106	__be64 cookie;
2107	__u8   protocol;
2108	__u8   event_cause;
2109	__u8   cur_state;
2110	__u8   prev_state;
2111	__be32 flags_to_assoc_flowid;
2112	union rdev_entry {
2113		struct fcoe_rdev_entry {
2114			__be32 flowid;
2115			__u8   protocol;
2116			__u8   event_cause;
2117			__u8   flags;
2118			__u8   rjt_reason;
2119			__u8   cur_login_st;
2120			__u8   prev_login_st;
2121			__be16 rcv_fr_sz;
2122			__u8   rd_xfer_rdy_to_rport_type;
2123			__u8   vft_to_qos;
2124			__u8   org_proc_assoc_to_acc_rsp_code;
2125			__u8   enh_disc_to_tgt;
2126			__u8   wwnn[8];
2127			__u8   wwpn[8];
2128			__be16 iqid;
2129			__u8   fc_oui[3];
2130			__u8   r_id[3];
2131		} fcoe_rdev;
2132		struct iscsi_rdev_entry {
2133			__be32 flowid;
2134			__u8   protocol;
2135			__u8   event_cause;
2136			__u8   flags;
2137			__u8   r3;
2138			__be16 iscsi_opts;
2139			__be16 tcp_opts;
2140			__be16 ip_opts;
2141			__be16 max_rcv_len;
2142			__be16 max_snd_len;
2143			__be16 first_brst_len;
2144			__be16 max_brst_len;
2145			__be16 r4;
2146			__be16 def_time2wait;
2147			__be16 def_time2ret;
2148			__be16 nop_out_intrvl;
2149			__be16 non_scsi_to;
2150			__be16 isid;
2151			__be16 tsid;
2152			__be16 port;
2153			__be16 tpgt;
2154			__u8   r5[6];
2155			__be16 iqid;
2156		} iscsi_rdev;
2157	} u;
2158};
2159
2160#define S_FW_RDEV_WR_IMMDLEN	0
2161#define M_FW_RDEV_WR_IMMDLEN	0xff
2162#define V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
2163#define G_FW_RDEV_WR_IMMDLEN(x)	\
2164    (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2165
2166#define S_FW_RDEV_WR_ALLOC	31
2167#define M_FW_RDEV_WR_ALLOC	0x1
2168#define V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
2169#define G_FW_RDEV_WR_ALLOC(x)	\
2170    (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2171#define F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
2172
2173#define S_FW_RDEV_WR_FREE	30
2174#define M_FW_RDEV_WR_FREE	0x1
2175#define V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
2176#define G_FW_RDEV_WR_FREE(x)	\
2177    (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2178#define F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
2179
2180#define S_FW_RDEV_WR_MODIFY	29
2181#define M_FW_RDEV_WR_MODIFY	0x1
2182#define V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
2183#define G_FW_RDEV_WR_MODIFY(x)	\
2184    (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2185#define F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
2186
2187#define S_FW_RDEV_WR_FLOWID	8
2188#define M_FW_RDEV_WR_FLOWID	0xfffff
2189#define V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
2190#define G_FW_RDEV_WR_FLOWID(x)	\
2191    (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2192
2193#define S_FW_RDEV_WR_LEN16	0
2194#define M_FW_RDEV_WR_LEN16	0xff
2195#define V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
2196#define G_FW_RDEV_WR_LEN16(x)	\
2197    (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2198
2199#define S_FW_RDEV_WR_FLAGS	24
2200#define M_FW_RDEV_WR_FLAGS	0xff
2201#define V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
2202#define G_FW_RDEV_WR_FLAGS(x)	\
2203    (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2204
2205#define S_FW_RDEV_WR_GET_NEXT		20
2206#define M_FW_RDEV_WR_GET_NEXT		0xf
2207#define V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
2208#define G_FW_RDEV_WR_GET_NEXT(x)	\
2209    (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2210
2211#define S_FW_RDEV_WR_ASSOC_FLOWID	0
2212#define M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
2213#define V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2214#define G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
2215    (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2216
2217#define S_FW_RDEV_WR_RJT	7
2218#define M_FW_RDEV_WR_RJT	0x1
2219#define V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
2220#define G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2221#define F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
2222
2223#define S_FW_RDEV_WR_REASON	0
2224#define M_FW_RDEV_WR_REASON	0x7f
2225#define V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
2226#define G_FW_RDEV_WR_REASON(x)	\
2227    (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2228
2229#define S_FW_RDEV_WR_RD_XFER_RDY	7
2230#define M_FW_RDEV_WR_RD_XFER_RDY	0x1
2231#define V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2232#define G_FW_RDEV_WR_RD_XFER_RDY(x)	\
2233    (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2234#define F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
2235
2236#define S_FW_RDEV_WR_WR_XFER_RDY	6
2237#define M_FW_RDEV_WR_WR_XFER_RDY	0x1
2238#define V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2239#define G_FW_RDEV_WR_WR_XFER_RDY(x)	\
2240    (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2241#define F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
2242
2243#define S_FW_RDEV_WR_FC_SP	5
2244#define M_FW_RDEV_WR_FC_SP	0x1
2245#define V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
2246#define G_FW_RDEV_WR_FC_SP(x)	\
2247    (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2248#define F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
2249
2250#define S_FW_RDEV_WR_RPORT_TYPE		0
2251#define M_FW_RDEV_WR_RPORT_TYPE		0x1f
2252#define V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
2253#define G_FW_RDEV_WR_RPORT_TYPE(x)	\
2254    (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2255
2256#define S_FW_RDEV_WR_VFT	7
2257#define M_FW_RDEV_WR_VFT	0x1
2258#define V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
2259#define G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2260#define F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
2261
2262#define S_FW_RDEV_WR_NPIV	6
2263#define M_FW_RDEV_WR_NPIV	0x1
2264#define V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
2265#define G_FW_RDEV_WR_NPIV(x)	\
2266    (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2267#define F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
2268
2269#define S_FW_RDEV_WR_CLASS	4
2270#define M_FW_RDEV_WR_CLASS	0x3
2271#define V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
2272#define G_FW_RDEV_WR_CLASS(x)	\
2273    (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2274
2275#define S_FW_RDEV_WR_SEQ_DEL	3
2276#define M_FW_RDEV_WR_SEQ_DEL	0x1
2277#define V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
2278#define G_FW_RDEV_WR_SEQ_DEL(x)	\
2279    (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2280#define F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
2281
2282#define S_FW_RDEV_WR_PRIO_PREEMP	2
2283#define M_FW_RDEV_WR_PRIO_PREEMP	0x1
2284#define V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2285#define G_FW_RDEV_WR_PRIO_PREEMP(x)	\
2286    (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2287#define F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
2288
2289#define S_FW_RDEV_WR_PREF	1
2290#define M_FW_RDEV_WR_PREF	0x1
2291#define V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
2292#define G_FW_RDEV_WR_PREF(x)	\
2293    (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2294#define F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
2295
2296#define S_FW_RDEV_WR_QOS	0
2297#define M_FW_RDEV_WR_QOS	0x1
2298#define V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
2299#define G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2300#define F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
2301
2302#define S_FW_RDEV_WR_ORG_PROC_ASSOC	7
2303#define M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
2304#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2305#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
2306    (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2307#define F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2308
2309#define S_FW_RDEV_WR_RSP_PROC_ASSOC	6
2310#define M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
2311#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2312#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
2313    (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2314#define F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2315
2316#define S_FW_RDEV_WR_IMAGE_PAIR		5
2317#define M_FW_RDEV_WR_IMAGE_PAIR		0x1
2318#define V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2319#define G_FW_RDEV_WR_IMAGE_PAIR(x)	\
2320    (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2321#define F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
2322
2323#define S_FW_RDEV_WR_ACC_RSP_CODE	0
2324#define M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
2325#define V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2326#define G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
2327    (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2328
2329#define S_FW_RDEV_WR_ENH_DISC		7
2330#define M_FW_RDEV_WR_ENH_DISC		0x1
2331#define V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
2332#define G_FW_RDEV_WR_ENH_DISC(x)	\
2333    (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2334#define F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
2335
2336#define S_FW_RDEV_WR_REC	6
2337#define M_FW_RDEV_WR_REC	0x1
2338#define V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
2339#define G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2340#define F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
2341
2342#define S_FW_RDEV_WR_TASK_RETRY_ID	5
2343#define M_FW_RDEV_WR_TASK_RETRY_ID	0x1
2344#define V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2345#define G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
2346    (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2347#define F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2348
2349#define S_FW_RDEV_WR_RETRY	4
2350#define M_FW_RDEV_WR_RETRY	0x1
2351#define V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
2352#define G_FW_RDEV_WR_RETRY(x)	\
2353    (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2354#define F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
2355
2356#define S_FW_RDEV_WR_CONF_CMPL		3
2357#define M_FW_RDEV_WR_CONF_CMPL		0x1
2358#define V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
2359#define G_FW_RDEV_WR_CONF_CMPL(x)	\
2360    (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2361#define F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
2362
2363#define S_FW_RDEV_WR_DATA_OVLY		2
2364#define M_FW_RDEV_WR_DATA_OVLY		0x1
2365#define V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
2366#define G_FW_RDEV_WR_DATA_OVLY(x)	\
2367    (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2368#define F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
2369
2370#define S_FW_RDEV_WR_INI	1
2371#define M_FW_RDEV_WR_INI	0x1
2372#define V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
2373#define G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2374#define F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
2375
2376#define S_FW_RDEV_WR_TGT	0
2377#define M_FW_RDEV_WR_TGT	0x1
2378#define V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
2379#define G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2380#define F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
2381
2382struct fw_foiscsi_node_wr {
2383	__be32 op_to_immdlen;
2384	__be32 flowid_len16;
2385	__u64  cookie;
2386	__u8   subop;
2387	__u8   status;
2388	__u8   alias_len;
2389	__u8   iqn_len;
2390	__be32 node_flowid;
2391	__be16 nodeid;
2392	__be16 login_retry;
2393	__be16 retry_timeout;
2394	__be16 r3;
2395	__u8   iqn[224];
2396	__u8   alias[224];
2397};
2398
2399#define S_FW_FOISCSI_NODE_WR_IMMDLEN	0
2400#define M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
2401#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2402#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
2403    (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2404
2405struct fw_foiscsi_ctrl_wr {
2406	__be32 op_compl;
2407	__be32 flowid_len16;
2408	__u64  cookie;
2409	__u8   subop;
2410	__u8   status;
2411	__u8   ctrl_state;
2412	__u8   io_state;
2413	__be32 node_id;
2414	__be32 ctrl_id;
2415	__be32 io_id;
2416	struct fw_foiscsi_sess_attr {
2417		__be32 sess_type_to_erl;
2418		__be16 max_conn;
2419		__be16 max_r2t;
2420		__be16 time2wait;
2421		__be16 time2retain;
2422		__be32 max_burst;
2423		__be32 first_burst;
2424		__be32 r1;
2425	} sess_attr;
2426	struct fw_foiscsi_conn_attr {
2427		__be32 hdigest_to_ddp_pgsz;
2428		__be32 max_rcv_dsl;
2429		__be32 ping_tmo;
2430		__be16 dst_port;
2431		__be16 src_port;
2432		union fw_foiscsi_conn_attr_addr {
2433			struct fw_foiscsi_conn_attr_ipv6 {
2434				__be64 dst_addr[2];
2435				__be64 src_addr[2];
2436			} ipv6_addr;
2437			struct fw_foiscsi_conn_attr_ipv4 {
2438				__be32 dst_addr;
2439				__be32 src_addr;
2440			} ipv4_addr;
2441		} u;
2442	} conn_attr;
2443	__u8   tgt_name_len;
2444	__u8   r3[7];
2445	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2446};
2447
2448#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
2449#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
2450#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2451    ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2452#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2453    (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2454
2455#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
2456#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
2457#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2458    ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2459#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2460    (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2461     M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2462#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
2463    V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2464
2465#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
2466#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
2467#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2468    ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2469#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2470    (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2471     M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2472#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
2473    V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2474
2475#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
2476#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
2477#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2478    ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2479#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2480    (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2481     M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2482#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
2483    V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2484
2485#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
2486#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
2487#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2488    ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2489#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2490    (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2491     M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2492#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
2493    V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2494
2495#define S_FW_FOISCSI_CTRL_WR_ERL	24
2496#define M_FW_FOISCSI_CTRL_WR_ERL	0x3
2497#define V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2498#define G_FW_FOISCSI_CTRL_WR_ERL(x)	\
2499    (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2500
2501#define S_FW_FOISCSI_CTRL_WR_HDIGEST	30
2502#define M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
2503#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2504#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
2505    (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2506
2507#define S_FW_FOISCSI_CTRL_WR_DDIGEST	28
2508#define M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
2509#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2510#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
2511    (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2512
2513#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
2514#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
2515#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2516    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2517#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2518    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2519     M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2520
2521#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
2522#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
2523#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2524    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2525#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2526    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2527     M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2528
2529#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
2530#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
2531#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2532    ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2533#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2534    (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2535
2536#define S_FW_FOISCSI_CTRL_WR_IPV6	20
2537#define M_FW_FOISCSI_CTRL_WR_IPV6	0x1
2538#define V_FW_FOISCSI_CTRL_WR_IPV6(x)	((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2539#define G_FW_FOISCSI_CTRL_WR_IPV6(x)	\
2540    (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2541#define F_FW_FOISCSI_CTRL_WR_IPV6	V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2542
2543struct fw_foiscsi_chap_wr {
2544	__be32 op_compl;
2545	__be32 flowid_len16;
2546	__u64  cookie;
2547	__u8   status;
2548	__u8   id_len;
2549	__u8   sec_len;
2550	__u8   node_type;
2551	__be16 node_id;
2552	__u8   r3[2];
2553	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
2554	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2555};
2556
2557/******************************************************************************
2558 *  C O i S C S I  W O R K R E Q U E S T S
2559 ********************************************/
2560
2561enum fw_chnet_addr_type {
2562	FW_CHNET_ADDD_TYPE_NONE = 0,
2563	FW_CHNET_ADDR_TYPE_IPV4,
2564	FW_CHNET_ADDR_TYPE_IPV6,
2565};
2566
2567enum fw_msg_wr_type {
2568	FW_MSG_WR_TYPE_RPL = 0,
2569	FW_MSG_WR_TYPE_ERR,
2570	FW_MSG_WR_TYPE_PLD,
2571};
2572
2573struct fw_coiscsi_tgt_wr {
2574	__be32 op_compl;
2575	__be32 flowid_len16;
2576	__u64  cookie;
2577	__u8   subop;
2578	__u8   status;
2579	__be16 r4;
2580	__be32 flags;
2581	struct fw_coiscsi_tgt_conn_attr {
2582		__be32 in_tid;
2583		__be16 in_port;
2584		__u8   in_type;
2585		__u8   r6;
2586		union fw_coiscsi_tgt_conn_attr_addr {
2587			struct fw_coiscsi_tgt_conn_attr_in_addr {
2588				__be32 addr;
2589				__be32 r7;
2590				__be32 r8[2];
2591			} in_addr;
2592			struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2593				__be64 addr[2];
2594			} in_addr6;
2595		} u;
2596	} conn_attr;
2597};
2598
2599struct fw_coiscsi_tgt_conn_wr {
2600	__be32 op_compl;
2601	__be32 flowid_len16;
2602	__u64  cookie;
2603	__u8   subop;
2604	__u8   status;
2605	__be16 iq_id;
2606	__be32 in_stid;
2607	__be32 io_id;
2608	__be32 flags;
2609	struct fw_coiscsi_tgt_conn_tcp {
2610		__be16 in_sport;
2611		__be16 in_dport;
2612		__be32 r4;
2613		union fw_coiscsi_tgt_conn_tcp_addr {
2614			struct fw_coiscsi_tgt_conn_tcp_in_addr {
2615				__be32 saddr;
2616				__be32 daddr;
2617			} in_addr;
2618			struct fw_coiscsi_tgt_conn_tcp_in_addr6 {
2619				__be64 saddr[2];
2620				__be64 daddr[2];
2621			} in_addr6;
2622		} u;
2623	} conn_tcp;
2624	struct fw_coiscsi_tgt_conn_iscsi {
2625		__be32 hdigest_to_ddp_pgsz;
2626		__be32 tgt_id;
2627		__be16 max_r2t;
2628		__be16 r5;
2629		__be32 max_burst;
2630		__be32 max_rdsl;
2631		__be32 max_tdsl;
2632		__be32 nxt_sn;
2633		__be32 r6;
2634	} conn_iscsi;
2635};
2636
2637struct fw_coiscsi_tgt_xmit_wr {
2638	__be32 op_to_immdlen;
2639	__be32 flowid_len16;
2640	__be64 cookie;
2641	__be16 iq_id;
2642	__be16 r4;
2643	__be32 datasn;
2644	__be32 t_xfer_len;
2645	__be32 flags;
2646	__be32 tag;
2647	__be32 tidx;
2648	__be32 r5[2];
2649};
2650
2651#define S_FW_COiSCSI_TGT_XMIT_WR_DDGST		23
2652#define M_FW_COiSCSI_TGT_XMIT_WR_DDGST		0x1
2653#define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2654    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2655#define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2656    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2657#define F_FW_COiSCSI_TGT_XMIT_WR_DDGST	V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
2658
2659#define S_FW_COiSCSI_TGT_XMIT_WR_HDGST		22
2660#define M_FW_COiSCSI_TGT_XMIT_WR_HDGST		0x1
2661#define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2662    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2663#define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2664    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2665#define F_FW_COiSCSI_TGT_XMIT_WR_HDGST	V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
2666
2667#define S_FW_COiSCSI_TGT_XMIT_WR_DDP	20
2668#define M_FW_COiSCSI_TGT_XMIT_WR_DDP	0x1
2669#define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
2670#define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	\
2671    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
2672#define F_FW_COiSCSI_TGT_XMIT_WR_DDP	V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
2673
2674#define S_FW_COiSCSI_TGT_XMIT_WR_ABORT		19
2675#define M_FW_COiSCSI_TGT_XMIT_WR_ABORT		0x1
2676#define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2677    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2678#define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2679    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2680#define F_FW_COiSCSI_TGT_XMIT_WR_ABORT	V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U)
2681
2682#define S_FW_COiSCSI_TGT_XMIT_WR_FINAL		18
2683#define M_FW_COiSCSI_TGT_XMIT_WR_FINAL		0x1
2684#define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2685    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2686#define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2687    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2688#define F_FW_COiSCSI_TGT_XMIT_WR_FINAL	V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U)
2689
2690#define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN		16
2691#define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN		0x3
2692#define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2693    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2694#define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2695    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \
2696     M_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2697
2698#define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0
2699#define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0xff
2700#define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2701    ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2702#define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2703    (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
2704     M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2705
2706struct fw_isns_wr {
2707	__be32 op_compl;
2708	__be32 flowid_len16;
2709	__u64  cookie;
2710	__u8   subop;
2711	__u8   status;
2712	__be16 iq_id;
2713	__be32 r4;
2714	struct fw_tcp_conn_attr {
2715		__be32 in_tid;
2716		__be16 in_port;
2717		__u8   in_type;
2718		__u8   r6;
2719		union fw_tcp_conn_attr_addr {
2720			struct fw_tcp_conn_attr_in_addr {
2721				__be32 addr;
2722				__be32 r7;
2723				__be32 r8[2];
2724			} in_addr;
2725			struct fw_tcp_conn_attr_in_addr6 {
2726				__be64 addr[2];
2727			} in_addr6;
2728		} u;
2729	} conn_attr;
2730};
2731
2732struct fw_isns_xmit_wr {
2733	__be32 op_to_immdlen;
2734	__be32 flowid_len16;
2735	__be64 cookie;
2736	__be16 iq_id;
2737	__be16 r4;
2738	__be32 xfer_len;
2739	__be64 r5;
2740};
2741
2742#define S_FW_ISNS_XMIT_WR_IMMDLEN	0
2743#define M_FW_ISNS_XMIT_WR_IMMDLEN	0xff
2744#define V_FW_ISNS_XMIT_WR_IMMDLEN(x)	((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
2745#define G_FW_ISNS_XMIT_WR_IMMDLEN(x)	\
2746    (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
2747
2748/******************************************************************************
2749 *  F O F C O E   W O R K R E Q U E S T s
2750 *******************************************/
2751
2752struct fw_fcoe_els_ct_wr {
2753	__be32 op_immdlen;
2754	__be32 flowid_len16;
2755	__be64 cookie;
2756	__be16 iqid;
2757	__u8   tmo_val;
2758	__u8   els_ct_type;
2759	__u8   ctl_pri;
2760	__u8   cp_en_class;
2761	__be16 xfer_cnt;
2762	__u8   fl_to_sp;
2763	__u8   l_id[3];
2764	__u8   r5;
2765	__u8   r_id[3];
2766	__be64 rsp_dmaaddr;
2767	__be32 rsp_dmalen;
2768	__be32 r6;
2769};
2770
2771#define S_FW_FCOE_ELS_CT_WR_OPCODE	24
2772#define M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
2773#define V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2774#define G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
2775    (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2776
2777#define S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
2778#define M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
2779#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2780#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
2781    (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2782
2783#define S_FW_FCOE_ELS_CT_WR_FLOWID	8
2784#define M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
2785#define V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2786#define G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
2787    (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2788
2789#define S_FW_FCOE_ELS_CT_WR_LEN16	0
2790#define M_FW_FCOE_ELS_CT_WR_LEN16	0xff
2791#define V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2792#define G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
2793    (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2794
2795#define S_FW_FCOE_ELS_CT_WR_CP_EN	6
2796#define M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
2797#define V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2798#define G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
2799    (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2800
2801#define S_FW_FCOE_ELS_CT_WR_CLASS	4
2802#define M_FW_FCOE_ELS_CT_WR_CLASS	0x3
2803#define V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2804#define G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
2805    (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2806
2807#define S_FW_FCOE_ELS_CT_WR_FL		2
2808#define M_FW_FCOE_ELS_CT_WR_FL		0x1
2809#define V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
2810#define G_FW_FCOE_ELS_CT_WR_FL(x)	\
2811    (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2812#define F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
2813
2814#define S_FW_FCOE_ELS_CT_WR_NPIV	1
2815#define M_FW_FCOE_ELS_CT_WR_NPIV	0x1
2816#define V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2817#define G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
2818    (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2819#define F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2820
2821#define S_FW_FCOE_ELS_CT_WR_SP		0
2822#define M_FW_FCOE_ELS_CT_WR_SP		0x1
2823#define V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
2824#define G_FW_FCOE_ELS_CT_WR_SP(x)	\
2825    (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2826#define F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
2827
2828/******************************************************************************
2829 *  S C S I   W O R K R E Q U E S T s   (FOiSCSI and FCOE unified data path)
2830 *****************************************************************************/
2831
2832struct fw_scsi_write_wr {
2833	__be32 op_immdlen;
2834	__be32 flowid_len16;
2835	__be64 cookie;
2836	__be16 iqid;
2837	__u8   tmo_val;
2838	__u8   use_xfer_cnt;
2839	union fw_scsi_write_priv {
2840		struct fcoe_write_priv {
2841			__u8   ctl_pri;
2842			__u8   cp_en_class;
2843			__u8   r3_lo[2];
2844		} fcoe;
2845		struct iscsi_write_priv {
2846			__u8   r3[4];
2847		} iscsi;
2848	} u;
2849	__be32 xfer_cnt;
2850	__be32 ini_xfer_cnt;
2851	__be64 rsp_dmaaddr;
2852	__be32 rsp_dmalen;
2853	__be32 r4;
2854};
2855
2856#define S_FW_SCSI_WRITE_WR_OPCODE	24
2857#define M_FW_SCSI_WRITE_WR_OPCODE	0xff
2858#define V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2859#define G_FW_SCSI_WRITE_WR_OPCODE(x)	\
2860    (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2861
2862#define S_FW_SCSI_WRITE_WR_IMMDLEN	0
2863#define M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
2864#define V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2865#define G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
2866    (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2867
2868#define S_FW_SCSI_WRITE_WR_FLOWID	8
2869#define M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
2870#define V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2871#define G_FW_SCSI_WRITE_WR_FLOWID(x)	\
2872    (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2873
2874#define S_FW_SCSI_WRITE_WR_LEN16	0
2875#define M_FW_SCSI_WRITE_WR_LEN16	0xff
2876#define V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
2877#define G_FW_SCSI_WRITE_WR_LEN16(x)	\
2878    (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2879
2880#define S_FW_SCSI_WRITE_WR_CP_EN	6
2881#define M_FW_SCSI_WRITE_WR_CP_EN	0x3
2882#define V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2883#define G_FW_SCSI_WRITE_WR_CP_EN(x)	\
2884    (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2885
2886#define S_FW_SCSI_WRITE_WR_CLASS	4
2887#define M_FW_SCSI_WRITE_WR_CLASS	0x3
2888#define V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
2889#define G_FW_SCSI_WRITE_WR_CLASS(x)	\
2890    (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2891
2892struct fw_scsi_read_wr {
2893	__be32 op_immdlen;
2894	__be32 flowid_len16;
2895	__be64 cookie;
2896	__be16 iqid;
2897	__u8   tmo_val;
2898	__u8   use_xfer_cnt;
2899	union fw_scsi_read_priv {
2900		struct fcoe_read_priv {
2901			__u8   ctl_pri;
2902			__u8   cp_en_class;
2903			__u8   r3_lo[2];
2904		} fcoe;
2905		struct iscsi_read_priv {
2906			__u8   r3[4];
2907		} iscsi;
2908	} u;
2909	__be32 xfer_cnt;
2910	__be32 ini_xfer_cnt;
2911	__be64 rsp_dmaaddr;
2912	__be32 rsp_dmalen;
2913	__be32 r4;
2914};
2915
2916#define S_FW_SCSI_READ_WR_OPCODE	24
2917#define M_FW_SCSI_READ_WR_OPCODE	0xff
2918#define V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
2919#define G_FW_SCSI_READ_WR_OPCODE(x)	\
2920    (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2921
2922#define S_FW_SCSI_READ_WR_IMMDLEN	0
2923#define M_FW_SCSI_READ_WR_IMMDLEN	0xff
2924#define V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2925#define G_FW_SCSI_READ_WR_IMMDLEN(x)	\
2926    (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2927
2928#define S_FW_SCSI_READ_WR_FLOWID	8
2929#define M_FW_SCSI_READ_WR_FLOWID	0xfffff
2930#define V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
2931#define G_FW_SCSI_READ_WR_FLOWID(x)	\
2932    (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2933
2934#define S_FW_SCSI_READ_WR_LEN16		0
2935#define M_FW_SCSI_READ_WR_LEN16		0xff
2936#define V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
2937#define G_FW_SCSI_READ_WR_LEN16(x)	\
2938    (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2939
2940#define S_FW_SCSI_READ_WR_CP_EN		6
2941#define M_FW_SCSI_READ_WR_CP_EN		0x3
2942#define V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
2943#define G_FW_SCSI_READ_WR_CP_EN(x)	\
2944    (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
2945
2946#define S_FW_SCSI_READ_WR_CLASS		4
2947#define M_FW_SCSI_READ_WR_CLASS		0x3
2948#define V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
2949#define G_FW_SCSI_READ_WR_CLASS(x)	\
2950    (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
2951
2952struct fw_scsi_cmd_wr {
2953	__be32 op_immdlen;
2954	__be32 flowid_len16;
2955	__be64 cookie;
2956	__be16 iqid;
2957	__u8   tmo_val;
2958	__u8   r3;
2959	union fw_scsi_cmd_priv {
2960		struct fcoe_cmd_priv {
2961			__u8   ctl_pri;
2962			__u8   cp_en_class;
2963			__u8   r4_lo[2];
2964		} fcoe;
2965		struct iscsi_cmd_priv {
2966			__u8   r4[4];
2967		} iscsi;
2968	} u;
2969	__u8   r5[8];
2970	__be64 rsp_dmaaddr;
2971	__be32 rsp_dmalen;
2972	__be32 r6;
2973};
2974
2975#define S_FW_SCSI_CMD_WR_OPCODE		24
2976#define M_FW_SCSI_CMD_WR_OPCODE		0xff
2977#define V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
2978#define G_FW_SCSI_CMD_WR_OPCODE(x)	\
2979    (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
2980
2981#define S_FW_SCSI_CMD_WR_IMMDLEN	0
2982#define M_FW_SCSI_CMD_WR_IMMDLEN	0xff
2983#define V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
2984#define G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
2985    (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
2986
2987#define S_FW_SCSI_CMD_WR_FLOWID		8
2988#define M_FW_SCSI_CMD_WR_FLOWID		0xfffff
2989#define V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
2990#define G_FW_SCSI_CMD_WR_FLOWID(x)	\
2991    (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
2992
2993#define S_FW_SCSI_CMD_WR_LEN16		0
2994#define M_FW_SCSI_CMD_WR_LEN16		0xff
2995#define V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
2996#define G_FW_SCSI_CMD_WR_LEN16(x)	\
2997    (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
2998
2999#define S_FW_SCSI_CMD_WR_CP_EN		6
3000#define M_FW_SCSI_CMD_WR_CP_EN		0x3
3001#define V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
3002#define G_FW_SCSI_CMD_WR_CP_EN(x)	\
3003    (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3004
3005#define S_FW_SCSI_CMD_WR_CLASS		4
3006#define M_FW_SCSI_CMD_WR_CLASS		0x3
3007#define V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
3008#define G_FW_SCSI_CMD_WR_CLASS(x)	\
3009    (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3010
3011struct fw_scsi_abrt_cls_wr {
3012	__be32 op_immdlen;
3013	__be32 flowid_len16;
3014	__be64 cookie;
3015	__be16 iqid;
3016	__u8   tmo_val;
3017	__u8   sub_opcode_to_chk_all_io;
3018	__u8   r3[4];
3019	__be64 t_cookie;
3020};
3021
3022#define S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
3023#define M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
3024#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3025#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
3026    (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3027
3028#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
3029#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
3030#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
3031    ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3032#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
3033    (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3034
3035#define S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
3036#define M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
3037#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3038#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
3039    (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3040
3041#define S_FW_SCSI_ABRT_CLS_WR_LEN16	0
3042#define M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
3043#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3044#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
3045    (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3046
3047#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
3048#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
3049#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
3050    ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3051#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
3052    (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3053     M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3054
3055#define S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
3056#define M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
3057#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3058#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
3059    (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3060#define F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3061
3062#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
3063#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
3064#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
3065    ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3066#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
3067    (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3068     M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3069#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
3070    V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3071
3072struct fw_scsi_tgt_acc_wr {
3073	__be32 op_immdlen;
3074	__be32 flowid_len16;
3075	__be64 cookie;
3076	__be16 iqid;
3077	__u8   r3;
3078	__u8   use_burst_len;
3079	union fw_scsi_tgt_acc_priv {
3080		struct fcoe_tgt_acc_priv {
3081			__u8   ctl_pri;
3082			__u8   cp_en_class;
3083			__u8   r4_lo[2];
3084		} fcoe;
3085		struct iscsi_tgt_acc_priv {
3086			__u8   r4[4];
3087		} iscsi;
3088	} u;
3089	__be32 burst_len;
3090	__be32 rel_off;
3091	__be64 r5;
3092	__be32 r6;
3093	__be32 tot_xfer_len;
3094};
3095
3096#define S_FW_SCSI_TGT_ACC_WR_OPCODE	24
3097#define M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
3098#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3099#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
3100    (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3101
3102#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
3103#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
3104#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3105#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
3106    (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3107
3108#define S_FW_SCSI_TGT_ACC_WR_FLOWID	8
3109#define M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
3110#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3111#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
3112    (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3113
3114#define S_FW_SCSI_TGT_ACC_WR_LEN16	0
3115#define M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
3116#define V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3117#define G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
3118    (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3119
3120#define S_FW_SCSI_TGT_ACC_WR_CP_EN	6
3121#define M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
3122#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3123#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
3124    (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3125
3126#define S_FW_SCSI_TGT_ACC_WR_CLASS	4
3127#define M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
3128#define V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3129#define G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
3130    (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3131
3132struct fw_scsi_tgt_xmit_wr {
3133	__be32 op_immdlen;
3134	__be32 flowid_len16;
3135	__be64 cookie;
3136	__be16 iqid;
3137	__u8   auto_rsp;
3138	__u8   use_xfer_cnt;
3139	union fw_scsi_tgt_xmit_priv {
3140		struct fcoe_tgt_xmit_priv {
3141			__u8   ctl_pri;
3142			__u8   cp_en_class;
3143			__u8   r3_lo[2];
3144		} fcoe;
3145		struct iscsi_tgt_xmit_priv {
3146			__u8   r3[4];
3147		} iscsi;
3148	} u;
3149	__be32 xfer_cnt;
3150	__be32 r4;
3151	__be64 r5;
3152	__be32 r6;
3153	__be32 tot_xfer_len;
3154};
3155
3156#define S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
3157#define M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
3158#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3159#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
3160    (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3161
3162#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
3163#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
3164#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3165    ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3166#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3167    (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3168
3169#define S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
3170#define M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
3171#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3172#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
3173    (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3174
3175#define S_FW_SCSI_TGT_XMIT_WR_LEN16	0
3176#define M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
3177#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3178#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
3179    (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3180
3181#define S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
3182#define M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
3183#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3184#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
3185    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3186
3187#define S_FW_SCSI_TGT_XMIT_WR_CLASS	4
3188#define M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
3189#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3190#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
3191    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3192
3193struct fw_scsi_tgt_rsp_wr {
3194	__be32 op_immdlen;
3195	__be32 flowid_len16;
3196	__be64 cookie;
3197	__be16 iqid;
3198	__u8   r3[2];
3199	union fw_scsi_tgt_rsp_priv {
3200		struct fcoe_tgt_rsp_priv {
3201			__u8   ctl_pri;
3202			__u8   cp_en_class;
3203			__u8   r4_lo[2];
3204		} fcoe;
3205		struct iscsi_tgt_rsp_priv {
3206			__u8   r4[4];
3207		} iscsi;
3208	} u;
3209	__u8   r5[8];
3210};
3211
3212#define S_FW_SCSI_TGT_RSP_WR_OPCODE	24
3213#define M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
3214#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3215#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
3216    (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3217
3218#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
3219#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
3220#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3221#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
3222    (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3223
3224#define S_FW_SCSI_TGT_RSP_WR_FLOWID	8
3225#define M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
3226#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3227#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
3228    (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3229
3230#define S_FW_SCSI_TGT_RSP_WR_LEN16	0
3231#define M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
3232#define V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3233#define G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
3234    (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3235
3236#define S_FW_SCSI_TGT_RSP_WR_CP_EN	6
3237#define M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
3238#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3239#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
3240    (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3241
3242#define S_FW_SCSI_TGT_RSP_WR_CLASS	4
3243#define M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
3244#define V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3245#define G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
3246    (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3247
3248struct fw_pofcoe_tcb_wr {
3249	__be32 op_compl;
3250	__be32 equiq_to_len16;
3251	__be32 r4;
3252	__be32 xfer_len;
3253	__be32 tid_to_port;
3254	__be16 x_id;
3255	__be16 vlan_id;
3256	__be64 cookie;
3257	__be32 s_id;
3258	__be32 d_id;
3259	__be32 tag;
3260	__be16 r6;
3261	__be16 iqid;
3262};
3263
3264#define S_FW_POFCOE_TCB_WR_TID		12
3265#define M_FW_POFCOE_TCB_WR_TID		0xfffff
3266#define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
3267#define G_FW_POFCOE_TCB_WR_TID(x)	\
3268    (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3269
3270#define S_FW_POFCOE_TCB_WR_ALLOC	4
3271#define M_FW_POFCOE_TCB_WR_ALLOC	0x1
3272#define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3273#define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
3274    (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3275#define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
3276
3277#define S_FW_POFCOE_TCB_WR_FREE		3
3278#define M_FW_POFCOE_TCB_WR_FREE		0x1
3279#define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
3280#define G_FW_POFCOE_TCB_WR_FREE(x)	\
3281    (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3282#define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
3283
3284#define S_FW_POFCOE_TCB_WR_PORT		0
3285#define M_FW_POFCOE_TCB_WR_PORT		0x7
3286#define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
3287#define G_FW_POFCOE_TCB_WR_PORT(x)	\
3288    (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3289
3290struct fw_pofcoe_ulptx_wr {
3291	__be32 op_pkd;
3292	__be32 equiq_to_len16;
3293	__u64  cookie;
3294};
3295
3296/*******************************************************************
3297 *  T10 DIF related definition
3298 *******************************************************************/
3299struct fw_tx_pi_header {
3300	__be16 op_to_inline;
3301	__u8   pi_interval_tag_type;
3302	__u8   num_pi;
3303	__be32 pi_start4_pi_end4;
3304	__u8   tag_gen_enabled_pkd;
3305	__u8   num_pi_dsg;
3306	__be16 app_tag;
3307	__be32 ref_tag;
3308};
3309
3310#define S_FW_TX_PI_HEADER_OP	8
3311#define M_FW_TX_PI_HEADER_OP	0xff
3312#define V_FW_TX_PI_HEADER_OP(x)	((x) << S_FW_TX_PI_HEADER_OP)
3313#define G_FW_TX_PI_HEADER_OP(x)	\
3314    (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3315
3316#define S_FW_TX_PI_HEADER_ULPTXMORE	7
3317#define M_FW_TX_PI_HEADER_ULPTXMORE	0x1
3318#define V_FW_TX_PI_HEADER_ULPTXMORE(x)	((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3319#define G_FW_TX_PI_HEADER_ULPTXMORE(x)	\
3320    (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3321#define F_FW_TX_PI_HEADER_ULPTXMORE	V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3322
3323#define S_FW_TX_PI_HEADER_PI_CONTROL	4
3324#define M_FW_TX_PI_HEADER_PI_CONTROL	0x7
3325#define V_FW_TX_PI_HEADER_PI_CONTROL(x)	((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3326#define G_FW_TX_PI_HEADER_PI_CONTROL(x)	\
3327    (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3328
3329#define S_FW_TX_PI_HEADER_GUARD_TYPE	2
3330#define M_FW_TX_PI_HEADER_GUARD_TYPE	0x1
3331#define V_FW_TX_PI_HEADER_GUARD_TYPE(x)	((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3332#define G_FW_TX_PI_HEADER_GUARD_TYPE(x)	\
3333    (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3334#define F_FW_TX_PI_HEADER_GUARD_TYPE	V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3335
3336#define S_FW_TX_PI_HEADER_VALIDATE	1
3337#define M_FW_TX_PI_HEADER_VALIDATE	0x1
3338#define V_FW_TX_PI_HEADER_VALIDATE(x)	((x) << S_FW_TX_PI_HEADER_VALIDATE)
3339#define G_FW_TX_PI_HEADER_VALIDATE(x)	\
3340    (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3341#define F_FW_TX_PI_HEADER_VALIDATE	V_FW_TX_PI_HEADER_VALIDATE(1U)
3342
3343#define S_FW_TX_PI_HEADER_INLINE	0
3344#define M_FW_TX_PI_HEADER_INLINE	0x1
3345#define V_FW_TX_PI_HEADER_INLINE(x)	((x) << S_FW_TX_PI_HEADER_INLINE)
3346#define G_FW_TX_PI_HEADER_INLINE(x)	\
3347    (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3348#define F_FW_TX_PI_HEADER_INLINE	V_FW_TX_PI_HEADER_INLINE(1U)
3349
3350#define S_FW_TX_PI_HEADER_PI_INTERVAL		7
3351#define M_FW_TX_PI_HEADER_PI_INTERVAL		0x1
3352#define V_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
3353    ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3354#define G_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
3355    (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3356#define F_FW_TX_PI_HEADER_PI_INTERVAL	V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3357
3358#define S_FW_TX_PI_HEADER_TAG_TYPE	5
3359#define M_FW_TX_PI_HEADER_TAG_TYPE	0x3
3360#define V_FW_TX_PI_HEADER_TAG_TYPE(x)	((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3361#define G_FW_TX_PI_HEADER_TAG_TYPE(x)	\
3362    (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3363
3364#define S_FW_TX_PI_HEADER_PI_START4	22
3365#define M_FW_TX_PI_HEADER_PI_START4	0x3ff
3366#define V_FW_TX_PI_HEADER_PI_START4(x)	((x) << S_FW_TX_PI_HEADER_PI_START4)
3367#define G_FW_TX_PI_HEADER_PI_START4(x)	\
3368    (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3369
3370#define S_FW_TX_PI_HEADER_PI_END4	0
3371#define M_FW_TX_PI_HEADER_PI_END4	0x3fffff
3372#define V_FW_TX_PI_HEADER_PI_END4(x)	((x) << S_FW_TX_PI_HEADER_PI_END4)
3373#define G_FW_TX_PI_HEADER_PI_END4(x)	\
3374    (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3375
3376#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED	6
3377#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED	0x3
3378#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
3379    ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3380#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
3381    (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3382     M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3383
3384enum fw_pi_error_type {
3385	FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3386};
3387
3388struct fw_pi_error {
3389	__be32 err_type_pkd;
3390	__be32 flowid_len16;
3391	__be16 r2;
3392	__be16 app_tag;
3393	__be32 ref_tag;
3394	__be32  pisc[4];
3395};
3396
3397#define S_FW_PI_ERROR_ERR_TYPE		24
3398#define M_FW_PI_ERROR_ERR_TYPE		0xff
3399#define V_FW_PI_ERROR_ERR_TYPE(x)	((x) << S_FW_PI_ERROR_ERR_TYPE)
3400#define G_FW_PI_ERROR_ERR_TYPE(x)	\
3401    (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3402
3403struct fw_tlstx_data_wr {
3404        __be32 op_to_immdlen;
3405        __be32 flowid_len16;
3406        __be32 plen;
3407        __be32 lsodisable_to_flags;
3408        __be32 r5;
3409        __be32 ctxloc_to_exp;
3410        __be16 mfs;
3411        __be16 adjustedplen_pkd;
3412        __be16 expinplenmax_pkd;
3413        __u8   pdusinplenmax_pkd;
3414        __u8   r10;
3415};
3416
3417#define S_FW_TLSTX_DATA_WR_OPCODE       24
3418#define M_FW_TLSTX_DATA_WR_OPCODE       0xff
3419#define V_FW_TLSTX_DATA_WR_OPCODE(x)    ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3420#define G_FW_TLSTX_DATA_WR_OPCODE(x)    \
3421    (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3422
3423#define S_FW_TLSTX_DATA_WR_COMPL        21
3424#define M_FW_TLSTX_DATA_WR_COMPL        0x1
3425#define V_FW_TLSTX_DATA_WR_COMPL(x)     ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3426#define G_FW_TLSTX_DATA_WR_COMPL(x)     \
3427    (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3428#define F_FW_TLSTX_DATA_WR_COMPL        V_FW_TLSTX_DATA_WR_COMPL(1U)
3429
3430#define S_FW_TLSTX_DATA_WR_IMMDLEN      0
3431#define M_FW_TLSTX_DATA_WR_IMMDLEN      0xff
3432#define V_FW_TLSTX_DATA_WR_IMMDLEN(x)   ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3433#define G_FW_TLSTX_DATA_WR_IMMDLEN(x)   \
3434    (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3435
3436#define S_FW_TLSTX_DATA_WR_FLOWID       8
3437#define M_FW_TLSTX_DATA_WR_FLOWID       0xfffff
3438#define V_FW_TLSTX_DATA_WR_FLOWID(x)    ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3439#define G_FW_TLSTX_DATA_WR_FLOWID(x)    \
3440    (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3441
3442#define S_FW_TLSTX_DATA_WR_LEN16        0
3443#define M_FW_TLSTX_DATA_WR_LEN16        0xff
3444#define V_FW_TLSTX_DATA_WR_LEN16(x)     ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3445#define G_FW_TLSTX_DATA_WR_LEN16(x)     \
3446    (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3447
3448#define S_FW_TLSTX_DATA_WR_LSODISABLE   31
3449#define M_FW_TLSTX_DATA_WR_LSODISABLE   0x1
3450#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3451    ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3452#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3453    (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3454#define F_FW_TLSTX_DATA_WR_LSODISABLE   V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3455
3456#define S_FW_TLSTX_DATA_WR_ALIGNPLD     30
3457#define M_FW_TLSTX_DATA_WR_ALIGNPLD     0x1
3458#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x)  ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3459#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x)  \
3460    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3461#define F_FW_TLSTX_DATA_WR_ALIGNPLD     V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3462
3463#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3464#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3465#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3466    ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3467#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3468    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3469     M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3470#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3471
3472#define S_FW_TLSTX_DATA_WR_FLAGS        0
3473#define M_FW_TLSTX_DATA_WR_FLAGS        0xfffffff
3474#define V_FW_TLSTX_DATA_WR_FLAGS(x)     ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3475#define G_FW_TLSTX_DATA_WR_FLAGS(x)     \
3476    (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3477
3478#define S_FW_TLSTX_DATA_WR_CTXLOC       30
3479#define M_FW_TLSTX_DATA_WR_CTXLOC       0x3
3480#define V_FW_TLSTX_DATA_WR_CTXLOC(x)    ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3481#define G_FW_TLSTX_DATA_WR_CTXLOC(x)    \
3482    (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3483
3484#define S_FW_TLSTX_DATA_WR_IVDSGL       29
3485#define M_FW_TLSTX_DATA_WR_IVDSGL       0x1
3486#define V_FW_TLSTX_DATA_WR_IVDSGL(x)    ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3487#define G_FW_TLSTX_DATA_WR_IVDSGL(x)    \
3488    (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3489#define F_FW_TLSTX_DATA_WR_IVDSGL       V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3490
3491#define S_FW_TLSTX_DATA_WR_KEYSIZE      24
3492#define M_FW_TLSTX_DATA_WR_KEYSIZE      0x1f
3493#define V_FW_TLSTX_DATA_WR_KEYSIZE(x)   ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3494#define G_FW_TLSTX_DATA_WR_KEYSIZE(x)   \
3495    (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3496
3497#define S_FW_TLSTX_DATA_WR_NUMIVS       14
3498#define M_FW_TLSTX_DATA_WR_NUMIVS       0xff
3499#define V_FW_TLSTX_DATA_WR_NUMIVS(x)    ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3500#define G_FW_TLSTX_DATA_WR_NUMIVS(x)    \
3501    (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3502
3503#define S_FW_TLSTX_DATA_WR_EXP          0
3504#define M_FW_TLSTX_DATA_WR_EXP          0x3fff
3505#define V_FW_TLSTX_DATA_WR_EXP(x)       ((x) << S_FW_TLSTX_DATA_WR_EXP)
3506#define G_FW_TLSTX_DATA_WR_EXP(x)       \
3507    (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3508
3509#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3510#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3511#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3512    ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3513#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3514    (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3515     M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3516
3517#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3518#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3519#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3520    ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3521#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3522    (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3523     M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3524
3525#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3526#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3527#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3528    ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3529#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3530    (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3531     M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3532
3533struct fw_tls_keyctx_tx_wr {
3534        __be32 op_to_compl;
3535        __be32 flowid_len16;
3536        union fw_key_ctx {
3537                struct fw_tx_keyctx_hdr {
3538                        __u8   ctxlen;
3539                        __u8   r2;
3540                        __be16 dualck_to_txvalid;
3541                        __u8   txsalt[4];
3542                        __be64 r5;
3543                } txhdr;
3544                struct fw_rx_keyctx_hdr {
3545                        __u8   flitcnt_hmacctrl;
3546                        __u8   protover_ciphmode;
3547                        __u8   authmode_to_rxvalid;
3548                        __u8   ivpresent_to_rxmk_size;
3549                        __u8   rxsalt[4];
3550                        __be64 ivinsert_to_authinsrt;
3551                } rxhdr;
3552                struct fw_keyctx_clear {
3553                        __be32 tx_key;
3554                        __be32 rx_key;
3555                } kctx_clr;
3556        } u;
3557        struct keys {
3558                __u8   edkey[32];
3559                __u8   ipad[64];
3560                __u8   opad[64];
3561        } keys;
3562        __u8   reneg_to_write_rx;
3563        __u8   protocol;
3564        __be16 mfs;
3565        __be32 ftid;
3566};
3567
3568#define S_FW_TLS_KEYCTX_TX_WR_OPCODE    24
3569#define M_FW_TLS_KEYCTX_TX_WR_OPCODE    0xff
3570#define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE)
3571#define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \
3572    (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE)
3573
3574#define S_FW_TLS_KEYCTX_TX_WR_ATOMIC    23
3575#define M_FW_TLS_KEYCTX_TX_WR_ATOMIC    0x1
3576#define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3577#define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \
3578    (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3579#define F_FW_TLS_KEYCTX_TX_WR_ATOMIC    V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U)
3580
3581#define S_FW_TLS_KEYCTX_TX_WR_FLUSH     22
3582#define M_FW_TLS_KEYCTX_TX_WR_FLUSH     0x1
3583#define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH)
3584#define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x)  \
3585    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH)
3586#define F_FW_TLS_KEYCTX_TX_WR_FLUSH     V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U)
3587
3588#define S_FW_TLS_KEYCTX_TX_WR_COMPL     21
3589#define M_FW_TLS_KEYCTX_TX_WR_COMPL     0x1
3590#define V_FW_TLS_KEYCTX_TX_WR_COMPL(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL)
3591#define G_FW_TLS_KEYCTX_TX_WR_COMPL(x)  \
3592    (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL)
3593#define F_FW_TLS_KEYCTX_TX_WR_COMPL     V_FW_TLS_KEYCTX_TX_WR_COMPL(1U)
3594
3595#define S_FW_TLS_KEYCTX_TX_WR_FLOWID    8
3596#define M_FW_TLS_KEYCTX_TX_WR_FLOWID    0xfffff
3597#define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID)
3598#define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \
3599    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID)
3600
3601#define S_FW_TLS_KEYCTX_TX_WR_LEN16     0
3602#define M_FW_TLS_KEYCTX_TX_WR_LEN16     0xff
3603#define V_FW_TLS_KEYCTX_TX_WR_LEN16(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16)
3604#define G_FW_TLS_KEYCTX_TX_WR_LEN16(x)  \
3605    (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16)
3606
3607#define S_FW_TLS_KEYCTX_TX_WR_DUALCK    12
3608#define M_FW_TLS_KEYCTX_TX_WR_DUALCK    0x1
3609#define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK)
3610#define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \
3611    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK)
3612#define F_FW_TLS_KEYCTX_TX_WR_DUALCK    V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U)
3613
3614#define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11
3615#define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1
3616#define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3617    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3618#define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3619    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \
3620     M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3621#define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \
3622    V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U)
3623
3624#define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10
3625#define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1
3626#define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3627    ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3628#define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3629    (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \
3630     M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3631#define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \
3632    V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U)
3633
3634#define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6
3635#define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf
3636#define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3637    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3638#define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3639    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \
3640     M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3641
3642#define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2
3643#define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf
3644#define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3645    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3646#define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3647    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \
3648     M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3649
3650#define S_FW_TLS_KEYCTX_TX_WR_TXVALID   0
3651#define M_FW_TLS_KEYCTX_TX_WR_TXVALID   0x1
3652#define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3653    ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID)
3654#define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3655    (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID)
3656#define F_FW_TLS_KEYCTX_TX_WR_TXVALID   V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U)
3657
3658#define S_FW_TLS_KEYCTX_TX_WR_FLITCNT   3
3659#define M_FW_TLS_KEYCTX_TX_WR_FLITCNT   0x1f
3660#define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3661    ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3662#define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3663    (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3664
3665#define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0
3666#define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL  0x7
3667#define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3668    ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3669#define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3670    (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3671
3672#define S_FW_TLS_KEYCTX_TX_WR_PROTOVER  4
3673#define M_FW_TLS_KEYCTX_TX_WR_PROTOVER  0xf
3674#define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3675    ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3676#define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3677    (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3678
3679#define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0
3680#define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE  0xf
3681#define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3682    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3683#define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3684    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3685
3686#define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE  4
3687#define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE  0xf
3688#define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3689    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3690#define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3691    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3692
3693#define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3
3694#define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1
3695#define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3696    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3697#define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3698    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \
3699     M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3700#define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \
3701    V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U)
3702
3703#define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1
3704#define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3
3705#define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3706    ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3707#define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3708    (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \
3709     M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3710
3711#define S_FW_TLS_KEYCTX_TX_WR_RXVALID   0
3712#define M_FW_TLS_KEYCTX_TX_WR_RXVALID   0x1
3713#define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3714    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID)
3715#define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3716    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID)
3717#define F_FW_TLS_KEYCTX_TX_WR_RXVALID   V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U)
3718
3719#define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7
3720#define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1
3721#define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3722    ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3723#define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3724    (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \
3725     M_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3726#define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U)
3727
3728#define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6
3729#define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1
3730#define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3731    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3732#define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3733    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \
3734     M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3735#define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \
3736    V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U)
3737
3738#define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3
3739#define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
3740#define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3741    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3742#define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3743    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \
3744     M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3745
3746#define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0
3747#define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7
3748#define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3749    ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3750#define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3751    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \
3752     M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3753
3754#define S_FW_TLS_KEYCTX_TX_WR_IVINSERT  55
3755#define M_FW_TLS_KEYCTX_TX_WR_IVINSERT  0x1ffULL
3756#define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3757    ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3758#define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3759    (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3760
3761#define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47
3762#define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL
3763#define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3764    ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3765#define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3766    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \
3767     M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3768
3769#define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39
3770#define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL
3771#define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3772    ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3773#define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3774    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \
3775     M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3776
3777#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30
3778#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL
3779#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3780    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3781#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3782    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \
3783     M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3784
3785#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23
3786#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f
3787#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3788    ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3789#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3790    (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \
3791     M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3792
3793#define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14
3794#define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff
3795#define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3796    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3797#define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3798    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \
3799     M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3800
3801#define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7
3802#define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f
3803#define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3804    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3805#define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3806    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \
3807     M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3808
3809#define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0
3810#define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f
3811#define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3812    ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3813#define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3814    (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \
3815     M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3816
3817#define S_FW_TLS_KEYCTX_TX_WR_RENEG     4
3818#define M_FW_TLS_KEYCTX_TX_WR_RENEG     0x1
3819#define V_FW_TLS_KEYCTX_TX_WR_RENEG(x)  ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG)
3820#define G_FW_TLS_KEYCTX_TX_WR_RENEG(x)  \
3821    (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG)
3822#define F_FW_TLS_KEYCTX_TX_WR_RENEG     V_FW_TLS_KEYCTX_TX_WR_RENEG(1U)
3823
3824#define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3
3825#define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1
3826#define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3827    ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3828#define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3829    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \
3830     M_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3831#define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U)
3832
3833#define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2
3834#define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1
3835#define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3836    ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3837#define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3838    (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \
3839     M_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3840#define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U)
3841
3842#define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX  1
3843#define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX  0x1
3844#define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3845    ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3846#define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3847    (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3848#define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX  V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U)
3849
3850#define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0
3851#define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX  0x1
3852#define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3853    ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3854#define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3855    (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3856#define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX  V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U)
3857
3858struct fw_crypto_lookaside_wr {
3859        __be32 op_to_cctx_size;
3860        __be32 len16_pkd;
3861        __be32 session_id;
3862        __be32 rx_chid_to_rx_q_id;
3863        __be32 key_addr;
3864        __be32 pld_size_hash_size;
3865        __be64 cookie;
3866};
3867
3868#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3869#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3870#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3871    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3872#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3873    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3874     M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3875
3876#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3877#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
3878#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3879    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3880#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3881    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
3882     M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3883#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
3884
3885#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
3886#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
3887#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3888    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3889#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3890    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
3891     M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3892
3893#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
3894#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
3895#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3896    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3897#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3898    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
3899     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3900
3901#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
3902#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
3903#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3904    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3905#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3906    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
3907     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3908
3909#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
3910#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
3911#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3912    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3913#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3914    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
3915     M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3916
3917#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
3918#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
3919#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3920    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3921#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3922    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
3923     M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3924
3925#define S_FW_CRYPTO_LOOKASIDE_WR_LCB  27
3926#define M_FW_CRYPTO_LOOKASIDE_WR_LCB  0x3
3927#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3928    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
3929#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3930    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
3931
3932#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
3933#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
3934#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3935    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3936#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3937    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
3938     M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3939
3940#define S_FW_CRYPTO_LOOKASIDE_WR_IV   23
3941#define M_FW_CRYPTO_LOOKASIDE_WR_IV   0x3
3942#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
3943    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
3944#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
3945    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
3946
3947#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX  15
3948#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX  0xff
3949#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
3950	((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
3951#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
3952	(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
3953	  M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
3954
3955#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
3956#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
3957#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
3958    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
3959#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
3960    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
3961     M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
3962
3963#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
3964#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
3965#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
3966    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
3967#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
3968    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
3969     M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
3970
3971#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
3972#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
3973#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
3974    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
3975#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
3976    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
3977     M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
3978
3979#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
3980#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
3981#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
3982    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
3983#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
3984    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
3985     M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
3986
3987/******************************************************************************
3988 *  C O M M A N D s
3989 *********************/
3990
3991/*
3992 * The maximum length of time, in miliseconds, that we expect any firmware
3993 * command to take to execute and return a reply to the host.  The RESET
3994 * and INITIALIZE commands can take a fair amount of time to execute but
3995 * most execute in far less time than this maximum.  This constant is used
3996 * by host software to determine how long to wait for a firmware command
3997 * reply before declaring the firmware as dead/unreachable ...
3998 */
3999#define FW_CMD_MAX_TIMEOUT	10000
4000
4001/*
4002 * If a host driver does a HELLO and discovers that there's already a MASTER
4003 * selected, we may have to wait for that MASTER to finish issuing RESET,
4004 * configuration and INITIALIZE commands.  Also, there's a possibility that
4005 * our own HELLO may get lost if it happens right as the MASTER is issuign a
4006 * RESET command, so we need to be willing to make a few retries of our HELLO.
4007 */
4008#define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
4009#define FW_CMD_HELLO_RETRIES	3
4010
4011enum fw_cmd_opcodes {
4012	FW_LDST_CMD                    = 0x01,
4013	FW_RESET_CMD                   = 0x03,
4014	FW_HELLO_CMD                   = 0x04,
4015	FW_BYE_CMD                     = 0x05,
4016	FW_INITIALIZE_CMD              = 0x06,
4017	FW_CAPS_CONFIG_CMD             = 0x07,
4018	FW_PARAMS_CMD                  = 0x08,
4019	FW_PFVF_CMD                    = 0x09,
4020	FW_IQ_CMD                      = 0x10,
4021	FW_EQ_MNGT_CMD                 = 0x11,
4022	FW_EQ_ETH_CMD                  = 0x12,
4023	FW_EQ_CTRL_CMD                 = 0x13,
4024	FW_EQ_OFLD_CMD                 = 0x21,
4025	FW_VI_CMD                      = 0x14,
4026	FW_VI_MAC_CMD                  = 0x15,
4027	FW_VI_RXMODE_CMD               = 0x16,
4028	FW_VI_ENABLE_CMD               = 0x17,
4029	FW_VI_STATS_CMD                = 0x1a,
4030	FW_ACL_MAC_CMD                 = 0x18,
4031	FW_ACL_VLAN_CMD                = 0x19,
4032	FW_PORT_CMD                    = 0x1b,
4033	FW_PORT_STATS_CMD              = 0x1c,
4034	FW_PORT_LB_STATS_CMD           = 0x1d,
4035	FW_PORT_TRACE_CMD              = 0x1e,
4036	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
4037	FW_RSS_IND_TBL_CMD             = 0x20,
4038	FW_RSS_GLB_CONFIG_CMD          = 0x22,
4039	FW_RSS_VI_CONFIG_CMD           = 0x23,
4040	FW_SCHED_CMD                   = 0x24,
4041	FW_DEVLOG_CMD                  = 0x25,
4042	FW_WATCHDOG_CMD                = 0x27,
4043	FW_CLIP_CMD                    = 0x28,
4044	FW_CHNET_IFACE_CMD             = 0x26,
4045	FW_FCOE_RES_INFO_CMD           = 0x31,
4046	FW_FCOE_LINK_CMD               = 0x32,
4047	FW_FCOE_VNP_CMD                = 0x33,
4048	FW_FCOE_SPARAMS_CMD            = 0x35,
4049	FW_FCOE_STATS_CMD              = 0x37,
4050	FW_FCOE_FCF_CMD                = 0x38,
4051	FW_DCB_IEEE_CMD		       = 0x3a,
4052	FW_DIAG_CMD		       = 0x3d,
4053	FW_PTP_CMD                     = 0x3e,
4054	FW_LASTC2E_CMD                 = 0x40,
4055	FW_ERROR_CMD                   = 0x80,
4056	FW_DEBUG_CMD                   = 0x81,
4057};
4058
4059enum fw_cmd_cap {
4060	FW_CMD_CAP_PF                  = 0x01,
4061	FW_CMD_CAP_DMAQ                = 0x02,
4062	FW_CMD_CAP_PORT                = 0x04,
4063	FW_CMD_CAP_PORTPROMISC         = 0x08,
4064	FW_CMD_CAP_PORTSTATS           = 0x10,
4065	FW_CMD_CAP_VF                  = 0x80,
4066};
4067
4068/*
4069 * Generic command header flit0
4070 */
4071struct fw_cmd_hdr {
4072	__be32 hi;
4073	__be32 lo;
4074};
4075
4076#define S_FW_CMD_OP		24
4077#define M_FW_CMD_OP		0xff
4078#define V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
4079#define G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
4080
4081#define S_FW_CMD_REQUEST	23
4082#define M_FW_CMD_REQUEST	0x1
4083#define V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
4084#define G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
4085#define F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
4086
4087#define S_FW_CMD_READ		22
4088#define M_FW_CMD_READ		0x1
4089#define V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
4090#define G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
4091#define F_FW_CMD_READ		V_FW_CMD_READ(1U)
4092
4093#define S_FW_CMD_WRITE		21
4094#define M_FW_CMD_WRITE		0x1
4095#define V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
4096#define G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
4097#define F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
4098
4099#define S_FW_CMD_EXEC		20
4100#define M_FW_CMD_EXEC		0x1
4101#define V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
4102#define G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
4103#define F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
4104
4105#define S_FW_CMD_RAMASK		20
4106#define M_FW_CMD_RAMASK		0xf
4107#define V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
4108#define G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
4109
4110#define S_FW_CMD_RETVAL		8
4111#define M_FW_CMD_RETVAL		0xff
4112#define V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
4113#define G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
4114
4115#define S_FW_CMD_LEN16		0
4116#define M_FW_CMD_LEN16		0xff
4117#define V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
4118#define G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
4119
4120#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
4121
4122/*
4123 *	address spaces
4124 */
4125enum fw_ldst_addrspc {
4126	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
4127	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
4128	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
4129	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
4130	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
4131	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
4132	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
4133	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
4134	FW_LDST_ADDRSPC_MDIO      = 0x0018,
4135	FW_LDST_ADDRSPC_MPS       = 0x0020,
4136	FW_LDST_ADDRSPC_FUNC      = 0x0028,
4137	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
4138	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
4139	FW_LDST_ADDRSPC_LE	  = 0x0030,
4140	FW_LDST_ADDRSPC_I2C       = 0x0038,
4141	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
4142	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
4143	FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,
4144	FW_LDST_ADDRSPC_CIM_Q	  = 0x0048,
4145};
4146
4147/*
4148 *	MDIO VSC8634 register access control field
4149 */
4150enum fw_ldst_mdio_vsc8634_aid {
4151	FW_LDST_MDIO_VS_STANDARD,
4152	FW_LDST_MDIO_VS_EXTENDED,
4153	FW_LDST_MDIO_VS_GPIO
4154};
4155
4156enum fw_ldst_mps_fid {
4157	FW_LDST_MPS_ATRB,
4158	FW_LDST_MPS_RPLC
4159};
4160
4161enum fw_ldst_func_access_ctl {
4162	FW_LDST_FUNC_ACC_CTL_VIID,
4163	FW_LDST_FUNC_ACC_CTL_FID
4164};
4165
4166enum fw_ldst_func_mod_index {
4167	FW_LDST_FUNC_MPS
4168};
4169
4170struct fw_ldst_cmd {
4171	__be32 op_to_addrspace;
4172	__be32 cycles_to_len16;
4173	union fw_ldst {
4174		struct fw_ldst_addrval {
4175			__be32 addr;
4176			__be32 val;
4177		} addrval;
4178		struct fw_ldst_idctxt {
4179			__be32 physid;
4180			__be32 msg_ctxtflush;
4181			__be32 ctxt_data7;
4182			__be32 ctxt_data6;
4183			__be32 ctxt_data5;
4184			__be32 ctxt_data4;
4185			__be32 ctxt_data3;
4186			__be32 ctxt_data2;
4187			__be32 ctxt_data1;
4188			__be32 ctxt_data0;
4189		} idctxt;
4190		struct fw_ldst_mdio {
4191			__be16 paddr_mmd;
4192			__be16 raddr;
4193			__be16 vctl;
4194			__be16 rval;
4195		} mdio;
4196		struct fw_ldst_cim_rq {
4197			__u8   req_first64[8];
4198			__u8   req_second64[8];
4199			__u8   resp_first64[8];
4200			__u8   resp_second64[8];
4201			__be32 r3[2];
4202		} cim_rq;
4203		union fw_ldst_mps {
4204			struct fw_ldst_mps_rplc {
4205				__be16 fid_idx;
4206				__be16 rplcpf_pkd;
4207				__be32 rplc255_224;
4208				__be32 rplc223_192;
4209				__be32 rplc191_160;
4210				__be32 rplc159_128;
4211				__be32 rplc127_96;
4212				__be32 rplc95_64;
4213				__be32 rplc63_32;
4214				__be32 rplc31_0;
4215			} rplc;
4216			struct fw_ldst_mps_atrb {
4217				__be16 fid_mpsid;
4218				__be16 r2[3];
4219				__be32 r3[2];
4220				__be32 r4;
4221				__be32 atrb;
4222				__be16 vlan[16];
4223			} atrb;
4224		} mps;
4225		struct fw_ldst_func {
4226			__u8   access_ctl;
4227			__u8   mod_index;
4228			__be16 ctl_id;
4229			__be32 offset;
4230			__be64 data0;
4231			__be64 data1;
4232		} func;
4233		struct fw_ldst_pcie {
4234			__u8   ctrl_to_fn;
4235			__u8   bnum;
4236			__u8   r;
4237			__u8   ext_r;
4238			__u8   select_naccess;
4239			__u8   pcie_fn;
4240			__be16 nset_pkd;
4241			__be32 data[12];
4242		} pcie;
4243		struct fw_ldst_i2c_deprecated {
4244			__u8   pid_pkd;
4245			__u8   base;
4246			__u8   boffset;
4247			__u8   data;
4248			__be32 r9;
4249		} i2c_deprecated;
4250		struct fw_ldst_i2c {
4251			__u8   pid;
4252			__u8   did;
4253			__u8   boffset;
4254			__u8   blen;
4255			__be32 r9;
4256			__u8   data[48];
4257		} i2c;
4258		struct fw_ldst_le {
4259			__be32 index;
4260			__be32 r9;
4261			__u8   val[33];
4262			__u8   r11[7];
4263		} le;
4264	} u;
4265};
4266
4267#define S_FW_LDST_CMD_ADDRSPACE		0
4268#define M_FW_LDST_CMD_ADDRSPACE		0xff
4269#define V_FW_LDST_CMD_ADDRSPACE(x)	((x) << S_FW_LDST_CMD_ADDRSPACE)
4270#define G_FW_LDST_CMD_ADDRSPACE(x)	\
4271    (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4272
4273#define S_FW_LDST_CMD_CYCLES		16
4274#define M_FW_LDST_CMD_CYCLES		0xffff
4275#define V_FW_LDST_CMD_CYCLES(x)		((x) << S_FW_LDST_CMD_CYCLES)
4276#define G_FW_LDST_CMD_CYCLES(x)		\
4277    (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4278
4279#define S_FW_LDST_CMD_MSG		31
4280#define M_FW_LDST_CMD_MSG		0x1
4281#define V_FW_LDST_CMD_MSG(x)		((x) << S_FW_LDST_CMD_MSG)
4282#define G_FW_LDST_CMD_MSG(x)		\
4283    (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4284#define F_FW_LDST_CMD_MSG		V_FW_LDST_CMD_MSG(1U)
4285
4286#define S_FW_LDST_CMD_CTXTFLUSH		30
4287#define M_FW_LDST_CMD_CTXTFLUSH		0x1
4288#define V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
4289#define G_FW_LDST_CMD_CTXTFLUSH(x)	\
4290    (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4291#define F_FW_LDST_CMD_CTXTFLUSH		V_FW_LDST_CMD_CTXTFLUSH(1U)
4292
4293#define S_FW_LDST_CMD_PADDR		8
4294#define M_FW_LDST_CMD_PADDR		0x1f
4295#define V_FW_LDST_CMD_PADDR(x)		((x) << S_FW_LDST_CMD_PADDR)
4296#define G_FW_LDST_CMD_PADDR(x)		\
4297    (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4298
4299#define S_FW_LDST_CMD_MMD		0
4300#define M_FW_LDST_CMD_MMD		0x1f
4301#define V_FW_LDST_CMD_MMD(x)		((x) << S_FW_LDST_CMD_MMD)
4302#define G_FW_LDST_CMD_MMD(x)		\
4303    (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4304
4305#define S_FW_LDST_CMD_FID		15
4306#define M_FW_LDST_CMD_FID		0x1
4307#define V_FW_LDST_CMD_FID(x)		((x) << S_FW_LDST_CMD_FID)
4308#define G_FW_LDST_CMD_FID(x)		\
4309    (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4310#define F_FW_LDST_CMD_FID		V_FW_LDST_CMD_FID(1U)
4311
4312#define S_FW_LDST_CMD_IDX		0
4313#define M_FW_LDST_CMD_IDX		0x7fff
4314#define V_FW_LDST_CMD_IDX(x)		((x) << S_FW_LDST_CMD_IDX)
4315#define G_FW_LDST_CMD_IDX(x)		\
4316    (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4317
4318#define S_FW_LDST_CMD_RPLCPF		0
4319#define M_FW_LDST_CMD_RPLCPF		0xff
4320#define V_FW_LDST_CMD_RPLCPF(x)		((x) << S_FW_LDST_CMD_RPLCPF)
4321#define G_FW_LDST_CMD_RPLCPF(x)		\
4322    (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4323
4324#define S_FW_LDST_CMD_MPSID		0
4325#define M_FW_LDST_CMD_MPSID		0x7fff
4326#define V_FW_LDST_CMD_MPSID(x)		((x) << S_FW_LDST_CMD_MPSID)
4327#define G_FW_LDST_CMD_MPSID(x)		\
4328    (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4329
4330#define S_FW_LDST_CMD_CTRL		7
4331#define M_FW_LDST_CMD_CTRL		0x1
4332#define V_FW_LDST_CMD_CTRL(x)		((x) << S_FW_LDST_CMD_CTRL)
4333#define G_FW_LDST_CMD_CTRL(x)		\
4334    (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4335#define F_FW_LDST_CMD_CTRL		V_FW_LDST_CMD_CTRL(1U)
4336
4337#define S_FW_LDST_CMD_LC		4
4338#define M_FW_LDST_CMD_LC		0x1
4339#define V_FW_LDST_CMD_LC(x)		((x) << S_FW_LDST_CMD_LC)
4340#define G_FW_LDST_CMD_LC(x)		\
4341    (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4342#define F_FW_LDST_CMD_LC		V_FW_LDST_CMD_LC(1U)
4343
4344#define S_FW_LDST_CMD_AI		3
4345#define M_FW_LDST_CMD_AI		0x1
4346#define V_FW_LDST_CMD_AI(x)		((x) << S_FW_LDST_CMD_AI)
4347#define G_FW_LDST_CMD_AI(x)		\
4348    (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4349#define F_FW_LDST_CMD_AI		V_FW_LDST_CMD_AI(1U)
4350
4351#define S_FW_LDST_CMD_FN		0
4352#define M_FW_LDST_CMD_FN		0x7
4353#define V_FW_LDST_CMD_FN(x)		((x) << S_FW_LDST_CMD_FN)
4354#define G_FW_LDST_CMD_FN(x)		\
4355    (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4356
4357#define S_FW_LDST_CMD_SELECT		4
4358#define M_FW_LDST_CMD_SELECT		0xf
4359#define V_FW_LDST_CMD_SELECT(x)		((x) << S_FW_LDST_CMD_SELECT)
4360#define G_FW_LDST_CMD_SELECT(x)		\
4361    (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4362
4363#define S_FW_LDST_CMD_NACCESS		0
4364#define M_FW_LDST_CMD_NACCESS		0xf
4365#define V_FW_LDST_CMD_NACCESS(x)	((x) << S_FW_LDST_CMD_NACCESS)
4366#define G_FW_LDST_CMD_NACCESS(x)	\
4367    (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4368
4369#define S_FW_LDST_CMD_NSET		14
4370#define M_FW_LDST_CMD_NSET		0x3
4371#define V_FW_LDST_CMD_NSET(x)		((x) << S_FW_LDST_CMD_NSET)
4372#define G_FW_LDST_CMD_NSET(x)		\
4373    (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4374
4375#define S_FW_LDST_CMD_PID		6
4376#define M_FW_LDST_CMD_PID		0x3
4377#define V_FW_LDST_CMD_PID(x)		((x) << S_FW_LDST_CMD_PID)
4378#define G_FW_LDST_CMD_PID(x)		\
4379    (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4380
4381struct fw_reset_cmd {
4382	__be32 op_to_write;
4383	__be32 retval_len16;
4384	__be32 val;
4385	__be32 halt_pkd;
4386};
4387
4388#define S_FW_RESET_CMD_HALT		31
4389#define M_FW_RESET_CMD_HALT		0x1
4390#define V_FW_RESET_CMD_HALT(x)		((x) << S_FW_RESET_CMD_HALT)
4391#define G_FW_RESET_CMD_HALT(x)		\
4392    (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4393#define F_FW_RESET_CMD_HALT		V_FW_RESET_CMD_HALT(1U)
4394
4395enum {
4396	FW_HELLO_CMD_STAGE_OS		= 0,
4397	FW_HELLO_CMD_STAGE_PREOS0	= 1,
4398	FW_HELLO_CMD_STAGE_PREOS1	= 2,
4399	FW_HELLO_CMD_STAGE_POSTOS	= 3,
4400};
4401
4402struct fw_hello_cmd {
4403	__be32 op_to_write;
4404	__be32 retval_len16;
4405	__be32 err_to_clearinit;
4406	__be32 fwrev;
4407};
4408
4409#define S_FW_HELLO_CMD_ERR		31
4410#define M_FW_HELLO_CMD_ERR		0x1
4411#define V_FW_HELLO_CMD_ERR(x)		((x) << S_FW_HELLO_CMD_ERR)
4412#define G_FW_HELLO_CMD_ERR(x)		\
4413    (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4414#define F_FW_HELLO_CMD_ERR		V_FW_HELLO_CMD_ERR(1U)
4415
4416#define S_FW_HELLO_CMD_INIT		30
4417#define M_FW_HELLO_CMD_INIT		0x1
4418#define V_FW_HELLO_CMD_INIT(x)		((x) << S_FW_HELLO_CMD_INIT)
4419#define G_FW_HELLO_CMD_INIT(x)		\
4420    (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4421#define F_FW_HELLO_CMD_INIT		V_FW_HELLO_CMD_INIT(1U)
4422
4423#define S_FW_HELLO_CMD_MASTERDIS	29
4424#define M_FW_HELLO_CMD_MASTERDIS	0x1
4425#define V_FW_HELLO_CMD_MASTERDIS(x)	((x) << S_FW_HELLO_CMD_MASTERDIS)
4426#define G_FW_HELLO_CMD_MASTERDIS(x)	\
4427    (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4428#define F_FW_HELLO_CMD_MASTERDIS	V_FW_HELLO_CMD_MASTERDIS(1U)
4429
4430#define S_FW_HELLO_CMD_MASTERFORCE	28
4431#define M_FW_HELLO_CMD_MASTERFORCE	0x1
4432#define V_FW_HELLO_CMD_MASTERFORCE(x)	((x) << S_FW_HELLO_CMD_MASTERFORCE)
4433#define G_FW_HELLO_CMD_MASTERFORCE(x)	\
4434    (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4435#define F_FW_HELLO_CMD_MASTERFORCE	V_FW_HELLO_CMD_MASTERFORCE(1U)
4436
4437#define S_FW_HELLO_CMD_MBMASTER		24
4438#define M_FW_HELLO_CMD_MBMASTER		0xf
4439#define V_FW_HELLO_CMD_MBMASTER(x)	((x) << S_FW_HELLO_CMD_MBMASTER)
4440#define G_FW_HELLO_CMD_MBMASTER(x)	\
4441    (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4442
4443#define S_FW_HELLO_CMD_MBASYNCNOTINT	23
4444#define M_FW_HELLO_CMD_MBASYNCNOTINT	0x1
4445#define V_FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4446#define G_FW_HELLO_CMD_MBASYNCNOTINT(x)	\
4447    (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4448#define F_FW_HELLO_CMD_MBASYNCNOTINT	V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4449
4450#define S_FW_HELLO_CMD_MBASYNCNOT	20
4451#define M_FW_HELLO_CMD_MBASYNCNOT	0x7
4452#define V_FW_HELLO_CMD_MBASYNCNOT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4453#define G_FW_HELLO_CMD_MBASYNCNOT(x)	\
4454    (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4455
4456#define S_FW_HELLO_CMD_STAGE		17
4457#define M_FW_HELLO_CMD_STAGE		0x7
4458#define V_FW_HELLO_CMD_STAGE(x)		((x) << S_FW_HELLO_CMD_STAGE)
4459#define G_FW_HELLO_CMD_STAGE(x)		\
4460    (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4461
4462#define S_FW_HELLO_CMD_CLEARINIT	16
4463#define M_FW_HELLO_CMD_CLEARINIT	0x1
4464#define V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
4465#define G_FW_HELLO_CMD_CLEARINIT(x)	\
4466    (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4467#define F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
4468
4469struct fw_bye_cmd {
4470	__be32 op_to_write;
4471	__be32 retval_len16;
4472	__be64 r3;
4473};
4474
4475struct fw_initialize_cmd {
4476	__be32 op_to_write;
4477	__be32 retval_len16;
4478	__be64 r3;
4479};
4480
4481enum fw_caps_config_hm {
4482	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
4483	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
4484	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
4485	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
4486	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
4487	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
4488	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
4489	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
4490	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
4491	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
4492	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
4493	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
4494	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
4495	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
4496	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
4497	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
4498	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
4499	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
4500	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
4501	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
4502	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
4503	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
4504	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
4505	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
4506};
4507
4508/*
4509 * The VF Register Map.
4510 *
4511 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4512 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4513 * the Slice to Module Map Table (see below) in the Physical Function Register
4514 * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4515 * and Offset registers in the PF Register Map.  The MBDATA base address is
4516 * quite constrained as it determines the Mailbox Data addresses for both PFs
4517 * and VFs, and therefore must fit in both the VF and PF Register Maps without
4518 * overlapping other registers.
4519 */
4520#define FW_T4VF_SGE_BASE_ADDR      0x0000
4521#define FW_T4VF_MPS_BASE_ADDR      0x0100
4522#define FW_T4VF_PL_BASE_ADDR       0x0200
4523#define FW_T4VF_MBDATA_BASE_ADDR   0x0240
4524#define FW_T6VF_MBDATA_BASE_ADDR   0x0280 /* aligned to mbox size 128B */
4525#define FW_T4VF_CIM_BASE_ADDR      0x0300
4526
4527#define FW_T4VF_REGMAP_START       0x0000
4528#define FW_T4VF_REGMAP_SIZE        0x0400
4529
4530enum fw_caps_config_nbm {
4531	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
4532	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
4533};
4534
4535enum fw_caps_config_link {
4536	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
4537	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
4538	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
4539};
4540
4541enum fw_caps_config_switch {
4542	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
4543	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
4544};
4545
4546enum fw_caps_config_nic {
4547	FW_CAPS_CONFIG_NIC		= 0x00000001,
4548	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
4549	FW_CAPS_CONFIG_NIC_IDS		= 0x00000004,
4550	FW_CAPS_CONFIG_NIC_UM		= 0x00000008,
4551	FW_CAPS_CONFIG_NIC_UM_ISGL	= 0x00000010,
4552	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
4553	FW_CAPS_CONFIG_NIC_ETHOFLD	= 0x00000040,
4554};
4555
4556enum fw_caps_config_toe {
4557	FW_CAPS_CONFIG_TOE		= 0x00000001,
4558};
4559
4560enum fw_caps_config_rdma {
4561	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
4562	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
4563};
4564
4565enum fw_caps_config_iscsi {
4566	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4567	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4568	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4569	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4570	FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4571	FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4572	FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4573	FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4574	FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4575};
4576
4577enum fw_caps_config_crypto {
4578	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4579	FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4580};
4581
4582enum fw_caps_config_fcoe {
4583	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
4584	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
4585	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
4586	FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4587	FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,
4588};
4589
4590enum fw_memtype_cf {
4591	FW_MEMTYPE_CF_EDC0		= FW_MEMTYPE_EDC0,
4592	FW_MEMTYPE_CF_EDC1		= FW_MEMTYPE_EDC1,
4593	FW_MEMTYPE_CF_EXTMEM		= FW_MEMTYPE_EXTMEM,
4594	FW_MEMTYPE_CF_FLASH		= FW_MEMTYPE_FLASH,
4595	FW_MEMTYPE_CF_INTERNAL		= FW_MEMTYPE_INTERNAL,
4596	FW_MEMTYPE_CF_EXTMEM1		= FW_MEMTYPE_EXTMEM1,
4597};
4598
4599struct fw_caps_config_cmd {
4600	__be32 op_to_write;
4601	__be32 cfvalid_to_len16;
4602	__be32 r2;
4603	__be32 hwmbitmap;
4604	__be16 nbmcaps;
4605	__be16 linkcaps;
4606	__be16 switchcaps;
4607	__be16 r3;
4608	__be16 niccaps;
4609	__be16 toecaps;
4610	__be16 rdmacaps;
4611	__be16 cryptocaps;
4612	__be16 iscsicaps;
4613	__be16 fcoecaps;
4614	__be32 cfcsum;
4615	__be32 finiver;
4616	__be32 finicsum;
4617};
4618
4619#define S_FW_CAPS_CONFIG_CMD_CFVALID	27
4620#define M_FW_CAPS_CONFIG_CMD_CFVALID	0x1
4621#define V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4622#define G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
4623    (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4624#define F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4625
4626#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF	24
4627#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF	0x7
4628#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4629    ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4630#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4631    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4632     M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4633
4634#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4635#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4636#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4637    ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4638#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4639    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4640     M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4641
4642/*
4643 * params command mnemonics
4644 */
4645enum fw_params_mnem {
4646	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
4647	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
4648	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
4649	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
4650	FW_PARAMS_MNEM_CHNET		= 5,	/* chnet params */
4651	FW_PARAMS_MNEM_LAST
4652};
4653
4654/*
4655 * device parameters
4656 */
4657enum fw_params_param_dev {
4658	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
4659	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
4660	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
4661						 * allocated by the device's
4662						 * Lookup Engine
4663						 */
4664	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4665	FW_PARAMS_PARAM_DEV_INTFVER_NIC	= 0x04,
4666	FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4667	FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4668	FW_PARAMS_PARAM_DEV_INTFVER_RI	= 0x07,
4669	FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4670	FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4671	FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4672	FW_PARAMS_PARAM_DEV_FWREV	= 0x0B,
4673	FW_PARAMS_PARAM_DEV_TPREV	= 0x0C,
4674	FW_PARAMS_PARAM_DEV_CF		= 0x0D,
4675	FW_PARAMS_PARAM_DEV_BYPASS	= 0x0E,
4676	FW_PARAMS_PARAM_DEV_PHYFW	= 0x0F,
4677	FW_PARAMS_PARAM_DEV_LOAD	= 0x10,
4678	FW_PARAMS_PARAM_DEV_DIAG	= 0x11,
4679	FW_PARAMS_PARAM_DEV_UCLK	= 0x12, /* uP clock in khz */
4680	FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4681						 */
4682	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4683						 */
4684	FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4685	FW_PARAMS_PARAM_DEV_MCINIT	= 0x16,
4686	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4687	FW_PARAMS_PARAM_DEV_FWCACHE	= 0x18,
4688	FW_PARAMS_PARAM_DEV_RSSINFO	= 0x19,
4689	FW_PARAMS_PARAM_DEV_SCFGREV	= 0x1A,
4690	FW_PARAMS_PARAM_DEV_VPDREV	= 0x1B,
4691	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
4692};
4693
4694/*
4695 * dev bypass parameters; actions and modes
4696 */
4697enum fw_params_param_dev_bypass {
4698
4699	/* actions
4700	 */
4701	FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4702	FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4703
4704	/* modes
4705	 */
4706	FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4707	FW_PARAMS_PARAM_DEV_BYPASS_DROP	= 0x1,
4708	FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4709};
4710
4711enum fw_params_param_dev_phyfw {
4712	FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4713	FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4714};
4715
4716enum fw_params_param_dev_diag {
4717	FW_PARAM_DEV_DIAG_TMP		= 0x00,
4718	FW_PARAM_DEV_DIAG_VDD		= 0x01,
4719};
4720
4721enum fw_params_param_dev_fwcache {
4722	FW_PARAM_DEV_FWCACHE_FLUSH	= 0x00,
4723	FW_PARAM_DEV_FWCACHE_FLUSHINV	= 0x01,
4724};
4725
4726/*
4727 * physical and virtual function parameters
4728 */
4729enum fw_params_param_pfvf {
4730	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
4731	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4732	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4733	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4734	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4735	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4736	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4737	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4738	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4739	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4740	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4741	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4742	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4743	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4744	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4745	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4746	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
4747	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4748	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
4749	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4750	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4751	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4752	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
4753	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
4754	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
4755	FW_PARAMS_PARAM_PFVF_SRQ_START	= 0x19,
4756	FW_PARAMS_PARAM_PFVF_SRQ_END	= 0x1A,
4757	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4758	FW_PARAMS_PARAM_PFVF_VIID	= 0x24,
4759	FW_PARAMS_PARAM_PFVF_CPMASK	= 0x25,
4760	FW_PARAMS_PARAM_PFVF_OCQ_START	= 0x26,
4761	FW_PARAMS_PARAM_PFVF_OCQ_END	= 0x27,
4762	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
4763	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4764	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4765	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
4766	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
4767	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4768	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4769	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4770	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4771	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4772	FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4773	FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4774	FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4775        FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4776	FW_PARAMS_PARAM_PFVF_RAWF_START	= 0x36,
4777	FW_PARAMS_PARAM_PFVF_RAWF_END	= 0x37,
4778	FW_PARAMS_PARAM_PFVF_RSSKEYINFO	= 0x38,
4779};
4780
4781/*
4782 * dma queue parameters
4783 */
4784enum fw_params_param_dmaq {
4785	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4786	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4787	FW_PARAMS_PARAM_DMAQ_IQ_INTIDX	= 0x02,
4788	FW_PARAMS_PARAM_DMAQ_IQ_DCA	= 0x03,
4789	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4790	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4791	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4792	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4793	FW_PARAMS_PARAM_DMAQ_EQ_DCA	= 0x14,
4794	FW_PARAMS_PARAM_DMAQ_CONM_CTXT	= 0x20,
4795	FW_PARAMS_PARAM_DMAQ_FLM_DCA	= 0x30
4796};
4797
4798/*
4799 * chnet parameters
4800 */
4801enum fw_params_param_chnet {
4802	FW_PARAMS_PARAM_CHNET_FLAGS		= 0x00,
4803};
4804
4805enum fw_params_param_chnet_flags {
4806	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6	= 0x1,
4807	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD	= 0x2,
4808	FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
4809};
4810
4811#define S_FW_PARAMS_MNEM	24
4812#define M_FW_PARAMS_MNEM	0xff
4813#define V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
4814#define G_FW_PARAMS_MNEM(x)	\
4815    (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
4816
4817#define S_FW_PARAMS_PARAM_X	16
4818#define M_FW_PARAMS_PARAM_X	0xff
4819#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
4820#define G_FW_PARAMS_PARAM_X(x) \
4821    (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
4822
4823#define S_FW_PARAMS_PARAM_Y	8
4824#define M_FW_PARAMS_PARAM_Y	0xff
4825#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
4826#define G_FW_PARAMS_PARAM_Y(x) \
4827    (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
4828
4829#define S_FW_PARAMS_PARAM_Z	0
4830#define M_FW_PARAMS_PARAM_Z	0xff
4831#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
4832#define G_FW_PARAMS_PARAM_Z(x) \
4833    (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
4834
4835#define S_FW_PARAMS_PARAM_XYZ	0
4836#define M_FW_PARAMS_PARAM_XYZ	0xffffff
4837#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
4838#define G_FW_PARAMS_PARAM_XYZ(x) \
4839    (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
4840
4841#define S_FW_PARAMS_PARAM_YZ	0
4842#define M_FW_PARAMS_PARAM_YZ	0xffff
4843#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
4844#define G_FW_PARAMS_PARAM_YZ(x) \
4845    (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
4846
4847#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
4848#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
4849#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4850    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4851#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4852    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
4853	M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4854
4855#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
4856#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
4857#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4858    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4859#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4860    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
4861	M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4862
4863#define S_FW_PARAMS_PARAM_DMAQ_DCA_ST	0
4864#define M_FW_PARAMS_PARAM_DMAQ_DCA_ST	0x7ff
4865#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4866    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4867#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4868    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4869
4870struct fw_params_cmd {
4871	__be32 op_to_vfn;
4872	__be32 retval_len16;
4873	struct fw_params_param {
4874		__be32 mnem;
4875		__be32 val;
4876	} param[7];
4877};
4878
4879#define S_FW_PARAMS_CMD_PFN		8
4880#define M_FW_PARAMS_CMD_PFN		0x7
4881#define V_FW_PARAMS_CMD_PFN(x)		((x) << S_FW_PARAMS_CMD_PFN)
4882#define G_FW_PARAMS_CMD_PFN(x)		\
4883    (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
4884
4885#define S_FW_PARAMS_CMD_VFN		0
4886#define M_FW_PARAMS_CMD_VFN		0xff
4887#define V_FW_PARAMS_CMD_VFN(x)		((x) << S_FW_PARAMS_CMD_VFN)
4888#define G_FW_PARAMS_CMD_VFN(x)		\
4889    (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
4890
4891struct fw_pfvf_cmd {
4892	__be32 op_to_vfn;
4893	__be32 retval_len16;
4894	__be32 niqflint_niq;
4895	__be32 type_to_neq;
4896	__be32 tc_to_nexactf;
4897	__be32 r_caps_to_nethctrl;
4898	__be16 nricq;
4899	__be16 nriqp;
4900	__be32 r4;
4901};
4902
4903#define S_FW_PFVF_CMD_PFN		8
4904#define M_FW_PFVF_CMD_PFN		0x7
4905#define V_FW_PFVF_CMD_PFN(x)		((x) << S_FW_PFVF_CMD_PFN)
4906#define G_FW_PFVF_CMD_PFN(x)		\
4907    (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
4908
4909#define S_FW_PFVF_CMD_VFN		0
4910#define M_FW_PFVF_CMD_VFN		0xff
4911#define V_FW_PFVF_CMD_VFN(x)		((x) << S_FW_PFVF_CMD_VFN)
4912#define G_FW_PFVF_CMD_VFN(x)		\
4913    (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
4914
4915#define S_FW_PFVF_CMD_NIQFLINT		20
4916#define M_FW_PFVF_CMD_NIQFLINT		0xfff
4917#define V_FW_PFVF_CMD_NIQFLINT(x)	((x) << S_FW_PFVF_CMD_NIQFLINT)
4918#define G_FW_PFVF_CMD_NIQFLINT(x)	\
4919    (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
4920
4921#define S_FW_PFVF_CMD_NIQ		0
4922#define M_FW_PFVF_CMD_NIQ		0xfffff
4923#define V_FW_PFVF_CMD_NIQ(x)		((x) << S_FW_PFVF_CMD_NIQ)
4924#define G_FW_PFVF_CMD_NIQ(x)		\
4925    (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
4926
4927#define S_FW_PFVF_CMD_TYPE		31
4928#define M_FW_PFVF_CMD_TYPE		0x1
4929#define V_FW_PFVF_CMD_TYPE(x)		((x) << S_FW_PFVF_CMD_TYPE)
4930#define G_FW_PFVF_CMD_TYPE(x)		\
4931    (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
4932#define F_FW_PFVF_CMD_TYPE		V_FW_PFVF_CMD_TYPE(1U)
4933
4934#define S_FW_PFVF_CMD_CMASK		24
4935#define M_FW_PFVF_CMD_CMASK		0xf
4936#define V_FW_PFVF_CMD_CMASK(x)		((x) << S_FW_PFVF_CMD_CMASK)
4937#define G_FW_PFVF_CMD_CMASK(x)		\
4938    (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
4939
4940#define S_FW_PFVF_CMD_PMASK		20
4941#define M_FW_PFVF_CMD_PMASK		0xf
4942#define V_FW_PFVF_CMD_PMASK(x)		((x) << S_FW_PFVF_CMD_PMASK)
4943#define G_FW_PFVF_CMD_PMASK(x)		\
4944    (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
4945
4946#define S_FW_PFVF_CMD_NEQ		0
4947#define M_FW_PFVF_CMD_NEQ		0xfffff
4948#define V_FW_PFVF_CMD_NEQ(x)		((x) << S_FW_PFVF_CMD_NEQ)
4949#define G_FW_PFVF_CMD_NEQ(x)		\
4950    (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
4951
4952#define S_FW_PFVF_CMD_TC		24
4953#define M_FW_PFVF_CMD_TC		0xff
4954#define V_FW_PFVF_CMD_TC(x)		((x) << S_FW_PFVF_CMD_TC)
4955#define G_FW_PFVF_CMD_TC(x)		\
4956    (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
4957
4958#define S_FW_PFVF_CMD_NVI		16
4959#define M_FW_PFVF_CMD_NVI		0xff
4960#define V_FW_PFVF_CMD_NVI(x)		((x) << S_FW_PFVF_CMD_NVI)
4961#define G_FW_PFVF_CMD_NVI(x)		\
4962    (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
4963
4964#define S_FW_PFVF_CMD_NEXACTF		0
4965#define M_FW_PFVF_CMD_NEXACTF		0xffff
4966#define V_FW_PFVF_CMD_NEXACTF(x)	((x) << S_FW_PFVF_CMD_NEXACTF)
4967#define G_FW_PFVF_CMD_NEXACTF(x)	\
4968    (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
4969
4970#define S_FW_PFVF_CMD_R_CAPS		24
4971#define M_FW_PFVF_CMD_R_CAPS		0xff
4972#define V_FW_PFVF_CMD_R_CAPS(x)		((x) << S_FW_PFVF_CMD_R_CAPS)
4973#define G_FW_PFVF_CMD_R_CAPS(x)		\
4974    (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
4975
4976#define S_FW_PFVF_CMD_WX_CAPS		16
4977#define M_FW_PFVF_CMD_WX_CAPS		0xff
4978#define V_FW_PFVF_CMD_WX_CAPS(x)	((x) << S_FW_PFVF_CMD_WX_CAPS)
4979#define G_FW_PFVF_CMD_WX_CAPS(x)	\
4980    (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
4981
4982#define S_FW_PFVF_CMD_NETHCTRL		0
4983#define M_FW_PFVF_CMD_NETHCTRL		0xffff
4984#define V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
4985#define G_FW_PFVF_CMD_NETHCTRL(x)	\
4986    (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
4987
4988/*
4989 *	ingress queue type; the first 1K ingress queues can have associated 0,
4990 *	1 or 2 free lists and an interrupt, all other ingress queues lack these
4991 *	capabilities
4992 */
4993enum fw_iq_type {
4994	FW_IQ_TYPE_FL_INT_CAP,
4995	FW_IQ_TYPE_NO_FL_INT_CAP
4996};
4997
4998struct fw_iq_cmd {
4999	__be32 op_to_vfn;
5000	__be32 alloc_to_len16;
5001	__be16 physiqid;
5002	__be16 iqid;
5003	__be16 fl0id;
5004	__be16 fl1id;
5005	__be32 type_to_iqandstindex;
5006	__be16 iqdroprss_to_iqesize;
5007	__be16 iqsize;
5008	__be64 iqaddr;
5009	__be32 iqns_to_fl0congen;
5010	__be16 fl0dcaen_to_fl0cidxfthresh;
5011	__be16 fl0size;
5012	__be64 fl0addr;
5013	__be32 fl1cngchmap_to_fl1congen;
5014	__be16 fl1dcaen_to_fl1cidxfthresh;
5015	__be16 fl1size;
5016	__be64 fl1addr;
5017};
5018
5019#define S_FW_IQ_CMD_PFN			8
5020#define M_FW_IQ_CMD_PFN			0x7
5021#define V_FW_IQ_CMD_PFN(x)		((x) << S_FW_IQ_CMD_PFN)
5022#define G_FW_IQ_CMD_PFN(x)		\
5023    (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
5024
5025#define S_FW_IQ_CMD_VFN			0
5026#define M_FW_IQ_CMD_VFN			0xff
5027#define V_FW_IQ_CMD_VFN(x)		((x) << S_FW_IQ_CMD_VFN)
5028#define G_FW_IQ_CMD_VFN(x)		\
5029    (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
5030
5031#define S_FW_IQ_CMD_ALLOC		31
5032#define M_FW_IQ_CMD_ALLOC		0x1
5033#define V_FW_IQ_CMD_ALLOC(x)		((x) << S_FW_IQ_CMD_ALLOC)
5034#define G_FW_IQ_CMD_ALLOC(x)		\
5035    (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
5036#define F_FW_IQ_CMD_ALLOC		V_FW_IQ_CMD_ALLOC(1U)
5037
5038#define S_FW_IQ_CMD_FREE		30
5039#define M_FW_IQ_CMD_FREE		0x1
5040#define V_FW_IQ_CMD_FREE(x)		((x) << S_FW_IQ_CMD_FREE)
5041#define G_FW_IQ_CMD_FREE(x)		\
5042    (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
5043#define F_FW_IQ_CMD_FREE		V_FW_IQ_CMD_FREE(1U)
5044
5045#define S_FW_IQ_CMD_MODIFY		29
5046#define M_FW_IQ_CMD_MODIFY		0x1
5047#define V_FW_IQ_CMD_MODIFY(x)		((x) << S_FW_IQ_CMD_MODIFY)
5048#define G_FW_IQ_CMD_MODIFY(x)		\
5049    (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
5050#define F_FW_IQ_CMD_MODIFY		V_FW_IQ_CMD_MODIFY(1U)
5051
5052#define S_FW_IQ_CMD_IQSTART		28
5053#define M_FW_IQ_CMD_IQSTART		0x1
5054#define V_FW_IQ_CMD_IQSTART(x)		((x) << S_FW_IQ_CMD_IQSTART)
5055#define G_FW_IQ_CMD_IQSTART(x)		\
5056    (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
5057#define F_FW_IQ_CMD_IQSTART		V_FW_IQ_CMD_IQSTART(1U)
5058
5059#define S_FW_IQ_CMD_IQSTOP		27
5060#define M_FW_IQ_CMD_IQSTOP		0x1
5061#define V_FW_IQ_CMD_IQSTOP(x)		((x) << S_FW_IQ_CMD_IQSTOP)
5062#define G_FW_IQ_CMD_IQSTOP(x)		\
5063    (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
5064#define F_FW_IQ_CMD_IQSTOP		V_FW_IQ_CMD_IQSTOP(1U)
5065
5066#define S_FW_IQ_CMD_TYPE		29
5067#define M_FW_IQ_CMD_TYPE		0x7
5068#define V_FW_IQ_CMD_TYPE(x)		((x) << S_FW_IQ_CMD_TYPE)
5069#define G_FW_IQ_CMD_TYPE(x)		\
5070    (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
5071
5072#define S_FW_IQ_CMD_IQASYNCH		28
5073#define M_FW_IQ_CMD_IQASYNCH		0x1
5074#define V_FW_IQ_CMD_IQASYNCH(x)		((x) << S_FW_IQ_CMD_IQASYNCH)
5075#define G_FW_IQ_CMD_IQASYNCH(x)		\
5076    (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
5077#define F_FW_IQ_CMD_IQASYNCH		V_FW_IQ_CMD_IQASYNCH(1U)
5078
5079#define S_FW_IQ_CMD_VIID		16
5080#define M_FW_IQ_CMD_VIID		0xfff
5081#define V_FW_IQ_CMD_VIID(x)		((x) << S_FW_IQ_CMD_VIID)
5082#define G_FW_IQ_CMD_VIID(x)		\
5083    (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
5084
5085#define S_FW_IQ_CMD_IQANDST		15
5086#define M_FW_IQ_CMD_IQANDST		0x1
5087#define V_FW_IQ_CMD_IQANDST(x)		((x) << S_FW_IQ_CMD_IQANDST)
5088#define G_FW_IQ_CMD_IQANDST(x)		\
5089    (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
5090#define F_FW_IQ_CMD_IQANDST		V_FW_IQ_CMD_IQANDST(1U)
5091
5092#define S_FW_IQ_CMD_IQANUS		14
5093#define M_FW_IQ_CMD_IQANUS		0x1
5094#define V_FW_IQ_CMD_IQANUS(x)		((x) << S_FW_IQ_CMD_IQANUS)
5095#define G_FW_IQ_CMD_IQANUS(x)		\
5096    (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
5097#define F_FW_IQ_CMD_IQANUS		V_FW_IQ_CMD_IQANUS(1U)
5098
5099#define S_FW_IQ_CMD_IQANUD		12
5100#define M_FW_IQ_CMD_IQANUD		0x3
5101#define V_FW_IQ_CMD_IQANUD(x)		((x) << S_FW_IQ_CMD_IQANUD)
5102#define G_FW_IQ_CMD_IQANUD(x)		\
5103    (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
5104
5105#define S_FW_IQ_CMD_IQANDSTINDEX	0
5106#define M_FW_IQ_CMD_IQANDSTINDEX	0xfff
5107#define V_FW_IQ_CMD_IQANDSTINDEX(x)	((x) << S_FW_IQ_CMD_IQANDSTINDEX)
5108#define G_FW_IQ_CMD_IQANDSTINDEX(x)	\
5109    (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
5110
5111#define S_FW_IQ_CMD_IQDROPRSS		15
5112#define M_FW_IQ_CMD_IQDROPRSS		0x1
5113#define V_FW_IQ_CMD_IQDROPRSS(x)	((x) << S_FW_IQ_CMD_IQDROPRSS)
5114#define G_FW_IQ_CMD_IQDROPRSS(x)	\
5115    (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
5116#define F_FW_IQ_CMD_IQDROPRSS		V_FW_IQ_CMD_IQDROPRSS(1U)
5117
5118#define S_FW_IQ_CMD_IQGTSMODE		14
5119#define M_FW_IQ_CMD_IQGTSMODE		0x1
5120#define V_FW_IQ_CMD_IQGTSMODE(x)	((x) << S_FW_IQ_CMD_IQGTSMODE)
5121#define G_FW_IQ_CMD_IQGTSMODE(x)	\
5122    (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
5123#define F_FW_IQ_CMD_IQGTSMODE		V_FW_IQ_CMD_IQGTSMODE(1U)
5124
5125#define S_FW_IQ_CMD_IQPCIECH		12
5126#define M_FW_IQ_CMD_IQPCIECH		0x3
5127#define V_FW_IQ_CMD_IQPCIECH(x)		((x) << S_FW_IQ_CMD_IQPCIECH)
5128#define G_FW_IQ_CMD_IQPCIECH(x)		\
5129    (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
5130
5131#define S_FW_IQ_CMD_IQDCAEN		11
5132#define M_FW_IQ_CMD_IQDCAEN		0x1
5133#define V_FW_IQ_CMD_IQDCAEN(x)		((x) << S_FW_IQ_CMD_IQDCAEN)
5134#define G_FW_IQ_CMD_IQDCAEN(x)		\
5135    (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
5136#define F_FW_IQ_CMD_IQDCAEN		V_FW_IQ_CMD_IQDCAEN(1U)
5137
5138#define S_FW_IQ_CMD_IQDCACPU		6
5139#define M_FW_IQ_CMD_IQDCACPU		0x1f
5140#define V_FW_IQ_CMD_IQDCACPU(x)		((x) << S_FW_IQ_CMD_IQDCACPU)
5141#define G_FW_IQ_CMD_IQDCACPU(x)		\
5142    (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
5143
5144#define S_FW_IQ_CMD_IQINTCNTTHRESH	4
5145#define M_FW_IQ_CMD_IQINTCNTTHRESH	0x3
5146#define V_FW_IQ_CMD_IQINTCNTTHRESH(x)	((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
5147#define G_FW_IQ_CMD_IQINTCNTTHRESH(x)	\
5148    (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
5149
5150#define S_FW_IQ_CMD_IQO			3
5151#define M_FW_IQ_CMD_IQO			0x1
5152#define V_FW_IQ_CMD_IQO(x)		((x) << S_FW_IQ_CMD_IQO)
5153#define G_FW_IQ_CMD_IQO(x)		\
5154    (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
5155#define F_FW_IQ_CMD_IQO			V_FW_IQ_CMD_IQO(1U)
5156
5157#define S_FW_IQ_CMD_IQCPRIO		2
5158#define M_FW_IQ_CMD_IQCPRIO		0x1
5159#define V_FW_IQ_CMD_IQCPRIO(x)		((x) << S_FW_IQ_CMD_IQCPRIO)
5160#define G_FW_IQ_CMD_IQCPRIO(x)		\
5161    (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
5162#define F_FW_IQ_CMD_IQCPRIO		V_FW_IQ_CMD_IQCPRIO(1U)
5163
5164#define S_FW_IQ_CMD_IQESIZE		0
5165#define M_FW_IQ_CMD_IQESIZE		0x3
5166#define V_FW_IQ_CMD_IQESIZE(x)		((x) << S_FW_IQ_CMD_IQESIZE)
5167#define G_FW_IQ_CMD_IQESIZE(x)		\
5168    (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
5169
5170#define S_FW_IQ_CMD_IQNS		31
5171#define M_FW_IQ_CMD_IQNS		0x1
5172#define V_FW_IQ_CMD_IQNS(x)		((x) << S_FW_IQ_CMD_IQNS)
5173#define G_FW_IQ_CMD_IQNS(x)		\
5174    (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
5175#define F_FW_IQ_CMD_IQNS		V_FW_IQ_CMD_IQNS(1U)
5176
5177#define S_FW_IQ_CMD_IQRO		30
5178#define M_FW_IQ_CMD_IQRO		0x1
5179#define V_FW_IQ_CMD_IQRO(x)		((x) << S_FW_IQ_CMD_IQRO)
5180#define G_FW_IQ_CMD_IQRO(x)		\
5181    (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
5182#define F_FW_IQ_CMD_IQRO		V_FW_IQ_CMD_IQRO(1U)
5183
5184#define S_FW_IQ_CMD_IQFLINTIQHSEN	28
5185#define M_FW_IQ_CMD_IQFLINTIQHSEN	0x3
5186#define V_FW_IQ_CMD_IQFLINTIQHSEN(x)	((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
5187#define G_FW_IQ_CMD_IQFLINTIQHSEN(x)	\
5188    (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5189
5190#define S_FW_IQ_CMD_IQFLINTCONGEN	27
5191#define M_FW_IQ_CMD_IQFLINTCONGEN	0x1
5192#define V_FW_IQ_CMD_IQFLINTCONGEN(x)	((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5193#define G_FW_IQ_CMD_IQFLINTCONGEN(x)	\
5194    (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5195#define F_FW_IQ_CMD_IQFLINTCONGEN	V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5196
5197#define S_FW_IQ_CMD_IQFLINTISCSIC	26
5198#define M_FW_IQ_CMD_IQFLINTISCSIC	0x1
5199#define V_FW_IQ_CMD_IQFLINTISCSIC(x)	((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5200#define G_FW_IQ_CMD_IQFLINTISCSIC(x)	\
5201    (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5202#define F_FW_IQ_CMD_IQFLINTISCSIC	V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5203
5204#define S_FW_IQ_CMD_FL0CNGCHMAP		20
5205#define M_FW_IQ_CMD_FL0CNGCHMAP		0xf
5206#define V_FW_IQ_CMD_FL0CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5207#define G_FW_IQ_CMD_FL0CNGCHMAP(x)	\
5208    (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5209
5210#define S_FW_IQ_CMD_FL0CONGDROP		16
5211#define M_FW_IQ_CMD_FL0CONGDROP		0x1
5212#define V_FW_IQ_CMD_FL0CONGDROP(x)	((x) << S_FW_IQ_CMD_FL0CONGDROP)
5213#define G_FW_IQ_CMD_FL0CONGDROP(x)	\
5214    (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5215#define F_FW_IQ_CMD_FL0CONGDROP		V_FW_IQ_CMD_FL0CONGDROP(1U)
5216
5217#define S_FW_IQ_CMD_FL0CACHELOCK	15
5218#define M_FW_IQ_CMD_FL0CACHELOCK	0x1
5219#define V_FW_IQ_CMD_FL0CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5220#define G_FW_IQ_CMD_FL0CACHELOCK(x)	\
5221    (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5222#define F_FW_IQ_CMD_FL0CACHELOCK	V_FW_IQ_CMD_FL0CACHELOCK(1U)
5223
5224#define S_FW_IQ_CMD_FL0DBP		14
5225#define M_FW_IQ_CMD_FL0DBP		0x1
5226#define V_FW_IQ_CMD_FL0DBP(x)		((x) << S_FW_IQ_CMD_FL0DBP)
5227#define G_FW_IQ_CMD_FL0DBP(x)		\
5228    (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5229#define F_FW_IQ_CMD_FL0DBP		V_FW_IQ_CMD_FL0DBP(1U)
5230
5231#define S_FW_IQ_CMD_FL0DATANS		13
5232#define M_FW_IQ_CMD_FL0DATANS		0x1
5233#define V_FW_IQ_CMD_FL0DATANS(x)	((x) << S_FW_IQ_CMD_FL0DATANS)
5234#define G_FW_IQ_CMD_FL0DATANS(x)	\
5235    (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5236#define F_FW_IQ_CMD_FL0DATANS		V_FW_IQ_CMD_FL0DATANS(1U)
5237
5238#define S_FW_IQ_CMD_FL0DATARO		12
5239#define M_FW_IQ_CMD_FL0DATARO		0x1
5240#define V_FW_IQ_CMD_FL0DATARO(x)	((x) << S_FW_IQ_CMD_FL0DATARO)
5241#define G_FW_IQ_CMD_FL0DATARO(x)	\
5242    (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5243#define F_FW_IQ_CMD_FL0DATARO		V_FW_IQ_CMD_FL0DATARO(1U)
5244
5245#define S_FW_IQ_CMD_FL0CONGCIF		11
5246#define M_FW_IQ_CMD_FL0CONGCIF		0x1
5247#define V_FW_IQ_CMD_FL0CONGCIF(x)	((x) << S_FW_IQ_CMD_FL0CONGCIF)
5248#define G_FW_IQ_CMD_FL0CONGCIF(x)	\
5249    (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5250#define F_FW_IQ_CMD_FL0CONGCIF		V_FW_IQ_CMD_FL0CONGCIF(1U)
5251
5252#define S_FW_IQ_CMD_FL0ONCHIP		10
5253#define M_FW_IQ_CMD_FL0ONCHIP		0x1
5254#define V_FW_IQ_CMD_FL0ONCHIP(x)	((x) << S_FW_IQ_CMD_FL0ONCHIP)
5255#define G_FW_IQ_CMD_FL0ONCHIP(x)	\
5256    (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5257#define F_FW_IQ_CMD_FL0ONCHIP		V_FW_IQ_CMD_FL0ONCHIP(1U)
5258
5259#define S_FW_IQ_CMD_FL0STATUSPGNS	9
5260#define M_FW_IQ_CMD_FL0STATUSPGNS	0x1
5261#define V_FW_IQ_CMD_FL0STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5262#define G_FW_IQ_CMD_FL0STATUSPGNS(x)	\
5263    (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5264#define F_FW_IQ_CMD_FL0STATUSPGNS	V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5265
5266#define S_FW_IQ_CMD_FL0STATUSPGRO	8
5267#define M_FW_IQ_CMD_FL0STATUSPGRO	0x1
5268#define V_FW_IQ_CMD_FL0STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5269#define G_FW_IQ_CMD_FL0STATUSPGRO(x)	\
5270    (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5271#define F_FW_IQ_CMD_FL0STATUSPGRO	V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5272
5273#define S_FW_IQ_CMD_FL0FETCHNS		7
5274#define M_FW_IQ_CMD_FL0FETCHNS		0x1
5275#define V_FW_IQ_CMD_FL0FETCHNS(x)	((x) << S_FW_IQ_CMD_FL0FETCHNS)
5276#define G_FW_IQ_CMD_FL0FETCHNS(x)	\
5277    (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5278#define F_FW_IQ_CMD_FL0FETCHNS		V_FW_IQ_CMD_FL0FETCHNS(1U)
5279
5280#define S_FW_IQ_CMD_FL0FETCHRO		6
5281#define M_FW_IQ_CMD_FL0FETCHRO		0x1
5282#define V_FW_IQ_CMD_FL0FETCHRO(x)	((x) << S_FW_IQ_CMD_FL0FETCHRO)
5283#define G_FW_IQ_CMD_FL0FETCHRO(x)	\
5284    (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5285#define F_FW_IQ_CMD_FL0FETCHRO		V_FW_IQ_CMD_FL0FETCHRO(1U)
5286
5287#define S_FW_IQ_CMD_FL0HOSTFCMODE	4
5288#define M_FW_IQ_CMD_FL0HOSTFCMODE	0x3
5289#define V_FW_IQ_CMD_FL0HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5290#define G_FW_IQ_CMD_FL0HOSTFCMODE(x)	\
5291    (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5292
5293#define S_FW_IQ_CMD_FL0CPRIO		3
5294#define M_FW_IQ_CMD_FL0CPRIO		0x1
5295#define V_FW_IQ_CMD_FL0CPRIO(x)		((x) << S_FW_IQ_CMD_FL0CPRIO)
5296#define G_FW_IQ_CMD_FL0CPRIO(x)		\
5297    (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5298#define F_FW_IQ_CMD_FL0CPRIO		V_FW_IQ_CMD_FL0CPRIO(1U)
5299
5300#define S_FW_IQ_CMD_FL0PADEN		2
5301#define M_FW_IQ_CMD_FL0PADEN		0x1
5302#define V_FW_IQ_CMD_FL0PADEN(x)		((x) << S_FW_IQ_CMD_FL0PADEN)
5303#define G_FW_IQ_CMD_FL0PADEN(x)		\
5304    (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5305#define F_FW_IQ_CMD_FL0PADEN		V_FW_IQ_CMD_FL0PADEN(1U)
5306
5307#define S_FW_IQ_CMD_FL0PACKEN		1
5308#define M_FW_IQ_CMD_FL0PACKEN		0x1
5309#define V_FW_IQ_CMD_FL0PACKEN(x)	((x) << S_FW_IQ_CMD_FL0PACKEN)
5310#define G_FW_IQ_CMD_FL0PACKEN(x)	\
5311    (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5312#define F_FW_IQ_CMD_FL0PACKEN		V_FW_IQ_CMD_FL0PACKEN(1U)
5313
5314#define S_FW_IQ_CMD_FL0CONGEN		0
5315#define M_FW_IQ_CMD_FL0CONGEN		0x1
5316#define V_FW_IQ_CMD_FL0CONGEN(x)	((x) << S_FW_IQ_CMD_FL0CONGEN)
5317#define G_FW_IQ_CMD_FL0CONGEN(x)	\
5318    (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5319#define F_FW_IQ_CMD_FL0CONGEN		V_FW_IQ_CMD_FL0CONGEN(1U)
5320
5321#define S_FW_IQ_CMD_FL0DCAEN		15
5322#define M_FW_IQ_CMD_FL0DCAEN		0x1
5323#define V_FW_IQ_CMD_FL0DCAEN(x)		((x) << S_FW_IQ_CMD_FL0DCAEN)
5324#define G_FW_IQ_CMD_FL0DCAEN(x)		\
5325    (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5326#define F_FW_IQ_CMD_FL0DCAEN		V_FW_IQ_CMD_FL0DCAEN(1U)
5327
5328#define S_FW_IQ_CMD_FL0DCACPU		10
5329#define M_FW_IQ_CMD_FL0DCACPU		0x1f
5330#define V_FW_IQ_CMD_FL0DCACPU(x)	((x) << S_FW_IQ_CMD_FL0DCACPU)
5331#define G_FW_IQ_CMD_FL0DCACPU(x)	\
5332    (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5333
5334#define S_FW_IQ_CMD_FL0FBMIN		7
5335#define M_FW_IQ_CMD_FL0FBMIN		0x7
5336#define V_FW_IQ_CMD_FL0FBMIN(x)		((x) << S_FW_IQ_CMD_FL0FBMIN)
5337#define G_FW_IQ_CMD_FL0FBMIN(x)		\
5338    (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5339
5340#define S_FW_IQ_CMD_FL0FBMAX		4
5341#define M_FW_IQ_CMD_FL0FBMAX		0x7
5342#define V_FW_IQ_CMD_FL0FBMAX(x)		((x) << S_FW_IQ_CMD_FL0FBMAX)
5343#define G_FW_IQ_CMD_FL0FBMAX(x)		\
5344    (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5345
5346#define S_FW_IQ_CMD_FL0CIDXFTHRESHO	3
5347#define M_FW_IQ_CMD_FL0CIDXFTHRESHO	0x1
5348#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5349#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	\
5350    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5351#define F_FW_IQ_CMD_FL0CIDXFTHRESHO	V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5352
5353#define S_FW_IQ_CMD_FL0CIDXFTHRESH	0
5354#define M_FW_IQ_CMD_FL0CIDXFTHRESH	0x7
5355#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5356#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x)	\
5357    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5358
5359#define S_FW_IQ_CMD_FL1CNGCHMAP		20
5360#define M_FW_IQ_CMD_FL1CNGCHMAP		0xf
5361#define V_FW_IQ_CMD_FL1CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5362#define G_FW_IQ_CMD_FL1CNGCHMAP(x)	\
5363    (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5364
5365#define S_FW_IQ_CMD_FL1CONGDROP		16
5366#define M_FW_IQ_CMD_FL1CONGDROP		0x1
5367#define V_FW_IQ_CMD_FL1CONGDROP(x)	((x) << S_FW_IQ_CMD_FL1CONGDROP)
5368#define G_FW_IQ_CMD_FL1CONGDROP(x)	\
5369    (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5370#define F_FW_IQ_CMD_FL1CONGDROP		V_FW_IQ_CMD_FL1CONGDROP(1U)
5371
5372#define S_FW_IQ_CMD_FL1CACHELOCK	15
5373#define M_FW_IQ_CMD_FL1CACHELOCK	0x1
5374#define V_FW_IQ_CMD_FL1CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5375#define G_FW_IQ_CMD_FL1CACHELOCK(x)	\
5376    (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5377#define F_FW_IQ_CMD_FL1CACHELOCK	V_FW_IQ_CMD_FL1CACHELOCK(1U)
5378
5379#define S_FW_IQ_CMD_FL1DBP		14
5380#define M_FW_IQ_CMD_FL1DBP		0x1
5381#define V_FW_IQ_CMD_FL1DBP(x)		((x) << S_FW_IQ_CMD_FL1DBP)
5382#define G_FW_IQ_CMD_FL1DBP(x)		\
5383    (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5384#define F_FW_IQ_CMD_FL1DBP		V_FW_IQ_CMD_FL1DBP(1U)
5385
5386#define S_FW_IQ_CMD_FL1DATANS		13
5387#define M_FW_IQ_CMD_FL1DATANS		0x1
5388#define V_FW_IQ_CMD_FL1DATANS(x)	((x) << S_FW_IQ_CMD_FL1DATANS)
5389#define G_FW_IQ_CMD_FL1DATANS(x)	\
5390    (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5391#define F_FW_IQ_CMD_FL1DATANS		V_FW_IQ_CMD_FL1DATANS(1U)
5392
5393#define S_FW_IQ_CMD_FL1DATARO		12
5394#define M_FW_IQ_CMD_FL1DATARO		0x1
5395#define V_FW_IQ_CMD_FL1DATARO(x)	((x) << S_FW_IQ_CMD_FL1DATARO)
5396#define G_FW_IQ_CMD_FL1DATARO(x)	\
5397    (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5398#define F_FW_IQ_CMD_FL1DATARO		V_FW_IQ_CMD_FL1DATARO(1U)
5399
5400#define S_FW_IQ_CMD_FL1CONGCIF		11
5401#define M_FW_IQ_CMD_FL1CONGCIF		0x1
5402#define V_FW_IQ_CMD_FL1CONGCIF(x)	((x) << S_FW_IQ_CMD_FL1CONGCIF)
5403#define G_FW_IQ_CMD_FL1CONGCIF(x)	\
5404    (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5405#define F_FW_IQ_CMD_FL1CONGCIF		V_FW_IQ_CMD_FL1CONGCIF(1U)
5406
5407#define S_FW_IQ_CMD_FL1ONCHIP		10
5408#define M_FW_IQ_CMD_FL1ONCHIP		0x1
5409#define V_FW_IQ_CMD_FL1ONCHIP(x)	((x) << S_FW_IQ_CMD_FL1ONCHIP)
5410#define G_FW_IQ_CMD_FL1ONCHIP(x)	\
5411    (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5412#define F_FW_IQ_CMD_FL1ONCHIP		V_FW_IQ_CMD_FL1ONCHIP(1U)
5413
5414#define S_FW_IQ_CMD_FL1STATUSPGNS	9
5415#define M_FW_IQ_CMD_FL1STATUSPGNS	0x1
5416#define V_FW_IQ_CMD_FL1STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5417#define G_FW_IQ_CMD_FL1STATUSPGNS(x)	\
5418    (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5419#define F_FW_IQ_CMD_FL1STATUSPGNS	V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5420
5421#define S_FW_IQ_CMD_FL1STATUSPGRO	8
5422#define M_FW_IQ_CMD_FL1STATUSPGRO	0x1
5423#define V_FW_IQ_CMD_FL1STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5424#define G_FW_IQ_CMD_FL1STATUSPGRO(x)	\
5425    (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5426#define F_FW_IQ_CMD_FL1STATUSPGRO	V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5427
5428#define S_FW_IQ_CMD_FL1FETCHNS		7
5429#define M_FW_IQ_CMD_FL1FETCHNS		0x1
5430#define V_FW_IQ_CMD_FL1FETCHNS(x)	((x) << S_FW_IQ_CMD_FL1FETCHNS)
5431#define G_FW_IQ_CMD_FL1FETCHNS(x)	\
5432    (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5433#define F_FW_IQ_CMD_FL1FETCHNS		V_FW_IQ_CMD_FL1FETCHNS(1U)
5434
5435#define S_FW_IQ_CMD_FL1FETCHRO		6
5436#define M_FW_IQ_CMD_FL1FETCHRO		0x1
5437#define V_FW_IQ_CMD_FL1FETCHRO(x)	((x) << S_FW_IQ_CMD_FL1FETCHRO)
5438#define G_FW_IQ_CMD_FL1FETCHRO(x)	\
5439    (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5440#define F_FW_IQ_CMD_FL1FETCHRO		V_FW_IQ_CMD_FL1FETCHRO(1U)
5441
5442#define S_FW_IQ_CMD_FL1HOSTFCMODE	4
5443#define M_FW_IQ_CMD_FL1HOSTFCMODE	0x3
5444#define V_FW_IQ_CMD_FL1HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5445#define G_FW_IQ_CMD_FL1HOSTFCMODE(x)	\
5446    (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5447
5448#define S_FW_IQ_CMD_FL1CPRIO		3
5449#define M_FW_IQ_CMD_FL1CPRIO		0x1
5450#define V_FW_IQ_CMD_FL1CPRIO(x)		((x) << S_FW_IQ_CMD_FL1CPRIO)
5451#define G_FW_IQ_CMD_FL1CPRIO(x)		\
5452    (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5453#define F_FW_IQ_CMD_FL1CPRIO		V_FW_IQ_CMD_FL1CPRIO(1U)
5454
5455#define S_FW_IQ_CMD_FL1PADEN		2
5456#define M_FW_IQ_CMD_FL1PADEN		0x1
5457#define V_FW_IQ_CMD_FL1PADEN(x)		((x) << S_FW_IQ_CMD_FL1PADEN)
5458#define G_FW_IQ_CMD_FL1PADEN(x)		\
5459    (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5460#define F_FW_IQ_CMD_FL1PADEN		V_FW_IQ_CMD_FL1PADEN(1U)
5461
5462#define S_FW_IQ_CMD_FL1PACKEN		1
5463#define M_FW_IQ_CMD_FL1PACKEN		0x1
5464#define V_FW_IQ_CMD_FL1PACKEN(x)	((x) << S_FW_IQ_CMD_FL1PACKEN)
5465#define G_FW_IQ_CMD_FL1PACKEN(x)	\
5466    (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5467#define F_FW_IQ_CMD_FL1PACKEN		V_FW_IQ_CMD_FL1PACKEN(1U)
5468
5469#define S_FW_IQ_CMD_FL1CONGEN		0
5470#define M_FW_IQ_CMD_FL1CONGEN		0x1
5471#define V_FW_IQ_CMD_FL1CONGEN(x)	((x) << S_FW_IQ_CMD_FL1CONGEN)
5472#define G_FW_IQ_CMD_FL1CONGEN(x)	\
5473    (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5474#define F_FW_IQ_CMD_FL1CONGEN		V_FW_IQ_CMD_FL1CONGEN(1U)
5475
5476#define S_FW_IQ_CMD_FL1DCAEN		15
5477#define M_FW_IQ_CMD_FL1DCAEN		0x1
5478#define V_FW_IQ_CMD_FL1DCAEN(x)		((x) << S_FW_IQ_CMD_FL1DCAEN)
5479#define G_FW_IQ_CMD_FL1DCAEN(x)		\
5480    (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5481#define F_FW_IQ_CMD_FL1DCAEN		V_FW_IQ_CMD_FL1DCAEN(1U)
5482
5483#define S_FW_IQ_CMD_FL1DCACPU		10
5484#define M_FW_IQ_CMD_FL1DCACPU		0x1f
5485#define V_FW_IQ_CMD_FL1DCACPU(x)	((x) << S_FW_IQ_CMD_FL1DCACPU)
5486#define G_FW_IQ_CMD_FL1DCACPU(x)	\
5487    (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5488
5489#define S_FW_IQ_CMD_FL1FBMIN		7
5490#define M_FW_IQ_CMD_FL1FBMIN		0x7
5491#define V_FW_IQ_CMD_FL1FBMIN(x)		((x) << S_FW_IQ_CMD_FL1FBMIN)
5492#define G_FW_IQ_CMD_FL1FBMIN(x)		\
5493    (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5494
5495#define S_FW_IQ_CMD_FL1FBMAX		4
5496#define M_FW_IQ_CMD_FL1FBMAX		0x7
5497#define V_FW_IQ_CMD_FL1FBMAX(x)		((x) << S_FW_IQ_CMD_FL1FBMAX)
5498#define G_FW_IQ_CMD_FL1FBMAX(x)		\
5499    (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5500
5501#define S_FW_IQ_CMD_FL1CIDXFTHRESHO	3
5502#define M_FW_IQ_CMD_FL1CIDXFTHRESHO	0x1
5503#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5504#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	\
5505    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5506#define F_FW_IQ_CMD_FL1CIDXFTHRESHO	V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5507
5508#define S_FW_IQ_CMD_FL1CIDXFTHRESH	0
5509#define M_FW_IQ_CMD_FL1CIDXFTHRESH	0x7
5510#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5511#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x)	\
5512    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5513
5514struct fw_eq_mngt_cmd {
5515	__be32 op_to_vfn;
5516	__be32 alloc_to_len16;
5517	__be32 cmpliqid_eqid;
5518	__be32 physeqid_pkd;
5519	__be32 fetchszm_to_iqid;
5520	__be32 dcaen_to_eqsize;
5521	__be64 eqaddr;
5522};
5523
5524#define S_FW_EQ_MNGT_CMD_PFN		8
5525#define M_FW_EQ_MNGT_CMD_PFN		0x7
5526#define V_FW_EQ_MNGT_CMD_PFN(x)		((x) << S_FW_EQ_MNGT_CMD_PFN)
5527#define G_FW_EQ_MNGT_CMD_PFN(x)		\
5528    (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5529
5530#define S_FW_EQ_MNGT_CMD_VFN		0
5531#define M_FW_EQ_MNGT_CMD_VFN		0xff
5532#define V_FW_EQ_MNGT_CMD_VFN(x)		((x) << S_FW_EQ_MNGT_CMD_VFN)
5533#define G_FW_EQ_MNGT_CMD_VFN(x)		\
5534    (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5535
5536#define S_FW_EQ_MNGT_CMD_ALLOC		31
5537#define M_FW_EQ_MNGT_CMD_ALLOC		0x1
5538#define V_FW_EQ_MNGT_CMD_ALLOC(x)	((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5539#define G_FW_EQ_MNGT_CMD_ALLOC(x)	\
5540    (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5541#define F_FW_EQ_MNGT_CMD_ALLOC		V_FW_EQ_MNGT_CMD_ALLOC(1U)
5542
5543#define S_FW_EQ_MNGT_CMD_FREE		30
5544#define M_FW_EQ_MNGT_CMD_FREE		0x1
5545#define V_FW_EQ_MNGT_CMD_FREE(x)	((x) << S_FW_EQ_MNGT_CMD_FREE)
5546#define G_FW_EQ_MNGT_CMD_FREE(x)	\
5547    (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5548#define F_FW_EQ_MNGT_CMD_FREE		V_FW_EQ_MNGT_CMD_FREE(1U)
5549
5550#define S_FW_EQ_MNGT_CMD_MODIFY		29
5551#define M_FW_EQ_MNGT_CMD_MODIFY		0x1
5552#define V_FW_EQ_MNGT_CMD_MODIFY(x)	((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5553#define G_FW_EQ_MNGT_CMD_MODIFY(x)	\
5554    (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5555#define F_FW_EQ_MNGT_CMD_MODIFY		V_FW_EQ_MNGT_CMD_MODIFY(1U)
5556
5557#define S_FW_EQ_MNGT_CMD_EQSTART	28
5558#define M_FW_EQ_MNGT_CMD_EQSTART	0x1
5559#define V_FW_EQ_MNGT_CMD_EQSTART(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5560#define G_FW_EQ_MNGT_CMD_EQSTART(x)	\
5561    (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5562#define F_FW_EQ_MNGT_CMD_EQSTART	V_FW_EQ_MNGT_CMD_EQSTART(1U)
5563
5564#define S_FW_EQ_MNGT_CMD_EQSTOP		27
5565#define M_FW_EQ_MNGT_CMD_EQSTOP		0x1
5566#define V_FW_EQ_MNGT_CMD_EQSTOP(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5567#define G_FW_EQ_MNGT_CMD_EQSTOP(x)	\
5568    (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5569#define F_FW_EQ_MNGT_CMD_EQSTOP		V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5570
5571#define S_FW_EQ_MNGT_CMD_CMPLIQID	20
5572#define M_FW_EQ_MNGT_CMD_CMPLIQID	0xfff
5573#define V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5574#define G_FW_EQ_MNGT_CMD_CMPLIQID(x)	\
5575    (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5576
5577#define S_FW_EQ_MNGT_CMD_EQID		0
5578#define M_FW_EQ_MNGT_CMD_EQID		0xfffff
5579#define V_FW_EQ_MNGT_CMD_EQID(x)	((x) << S_FW_EQ_MNGT_CMD_EQID)
5580#define G_FW_EQ_MNGT_CMD_EQID(x)	\
5581    (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5582
5583#define S_FW_EQ_MNGT_CMD_PHYSEQID	0
5584#define M_FW_EQ_MNGT_CMD_PHYSEQID	0xfffff
5585#define V_FW_EQ_MNGT_CMD_PHYSEQID(x)	((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5586#define G_FW_EQ_MNGT_CMD_PHYSEQID(x)	\
5587    (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5588
5589#define S_FW_EQ_MNGT_CMD_FETCHSZM	26
5590#define M_FW_EQ_MNGT_CMD_FETCHSZM	0x1
5591#define V_FW_EQ_MNGT_CMD_FETCHSZM(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5592#define G_FW_EQ_MNGT_CMD_FETCHSZM(x)	\
5593    (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5594#define F_FW_EQ_MNGT_CMD_FETCHSZM	V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5595
5596#define S_FW_EQ_MNGT_CMD_STATUSPGNS	25
5597#define M_FW_EQ_MNGT_CMD_STATUSPGNS	0x1
5598#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5599#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x)	\
5600    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5601#define F_FW_EQ_MNGT_CMD_STATUSPGNS	V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5602
5603#define S_FW_EQ_MNGT_CMD_STATUSPGRO	24
5604#define M_FW_EQ_MNGT_CMD_STATUSPGRO	0x1
5605#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5606#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x)	\
5607    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5608#define F_FW_EQ_MNGT_CMD_STATUSPGRO	V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5609
5610#define S_FW_EQ_MNGT_CMD_FETCHNS	23
5611#define M_FW_EQ_MNGT_CMD_FETCHNS	0x1
5612#define V_FW_EQ_MNGT_CMD_FETCHNS(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5613#define G_FW_EQ_MNGT_CMD_FETCHNS(x)	\
5614    (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5615#define F_FW_EQ_MNGT_CMD_FETCHNS	V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5616
5617#define S_FW_EQ_MNGT_CMD_FETCHRO	22
5618#define M_FW_EQ_MNGT_CMD_FETCHRO	0x1
5619#define V_FW_EQ_MNGT_CMD_FETCHRO(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5620#define G_FW_EQ_MNGT_CMD_FETCHRO(x)	\
5621    (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5622#define F_FW_EQ_MNGT_CMD_FETCHRO	V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5623
5624#define S_FW_EQ_MNGT_CMD_HOSTFCMODE	20
5625#define M_FW_EQ_MNGT_CMD_HOSTFCMODE	0x3
5626#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5627#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	\
5628    (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5629
5630#define S_FW_EQ_MNGT_CMD_CPRIO		19
5631#define M_FW_EQ_MNGT_CMD_CPRIO		0x1
5632#define V_FW_EQ_MNGT_CMD_CPRIO(x)	((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5633#define G_FW_EQ_MNGT_CMD_CPRIO(x)	\
5634    (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5635#define F_FW_EQ_MNGT_CMD_CPRIO		V_FW_EQ_MNGT_CMD_CPRIO(1U)
5636
5637#define S_FW_EQ_MNGT_CMD_ONCHIP		18
5638#define M_FW_EQ_MNGT_CMD_ONCHIP		0x1
5639#define V_FW_EQ_MNGT_CMD_ONCHIP(x)	((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5640#define G_FW_EQ_MNGT_CMD_ONCHIP(x)	\
5641    (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5642#define F_FW_EQ_MNGT_CMD_ONCHIP		V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5643
5644#define S_FW_EQ_MNGT_CMD_PCIECHN	16
5645#define M_FW_EQ_MNGT_CMD_PCIECHN	0x3
5646#define V_FW_EQ_MNGT_CMD_PCIECHN(x)	((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5647#define G_FW_EQ_MNGT_CMD_PCIECHN(x)	\
5648    (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5649
5650#define S_FW_EQ_MNGT_CMD_IQID		0
5651#define M_FW_EQ_MNGT_CMD_IQID		0xffff
5652#define V_FW_EQ_MNGT_CMD_IQID(x)	((x) << S_FW_EQ_MNGT_CMD_IQID)
5653#define G_FW_EQ_MNGT_CMD_IQID(x)	\
5654    (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5655
5656#define S_FW_EQ_MNGT_CMD_DCAEN		31
5657#define M_FW_EQ_MNGT_CMD_DCAEN		0x1
5658#define V_FW_EQ_MNGT_CMD_DCAEN(x)	((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5659#define G_FW_EQ_MNGT_CMD_DCAEN(x)	\
5660    (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5661#define F_FW_EQ_MNGT_CMD_DCAEN		V_FW_EQ_MNGT_CMD_DCAEN(1U)
5662
5663#define S_FW_EQ_MNGT_CMD_DCACPU		26
5664#define M_FW_EQ_MNGT_CMD_DCACPU		0x1f
5665#define V_FW_EQ_MNGT_CMD_DCACPU(x)	((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5666#define G_FW_EQ_MNGT_CMD_DCACPU(x)	\
5667    (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5668
5669#define S_FW_EQ_MNGT_CMD_FBMIN		23
5670#define M_FW_EQ_MNGT_CMD_FBMIN		0x7
5671#define V_FW_EQ_MNGT_CMD_FBMIN(x)	((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5672#define G_FW_EQ_MNGT_CMD_FBMIN(x)	\
5673    (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5674
5675#define S_FW_EQ_MNGT_CMD_FBMAX		20
5676#define M_FW_EQ_MNGT_CMD_FBMAX		0x7
5677#define V_FW_EQ_MNGT_CMD_FBMAX(x)	((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5678#define G_FW_EQ_MNGT_CMD_FBMAX(x)	\
5679    (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5680
5681#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO	19
5682#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO	0x1
5683#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5684    ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5685#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5686    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5687#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5688
5689#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH	16
5690#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH	0x7
5691#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5692#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	\
5693    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5694
5695#define S_FW_EQ_MNGT_CMD_EQSIZE		0
5696#define M_FW_EQ_MNGT_CMD_EQSIZE		0xffff
5697#define V_FW_EQ_MNGT_CMD_EQSIZE(x)	((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5698#define G_FW_EQ_MNGT_CMD_EQSIZE(x)	\
5699    (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5700
5701struct fw_eq_eth_cmd {
5702	__be32 op_to_vfn;
5703	__be32 alloc_to_len16;
5704	__be32 eqid_pkd;
5705	__be32 physeqid_pkd;
5706	__be32 fetchszm_to_iqid;
5707	__be32 dcaen_to_eqsize;
5708	__be64 eqaddr;
5709	__be32 autoequiqe_to_viid;
5710	__be32 r8_lo;
5711	__be64 r9;
5712};
5713
5714#define S_FW_EQ_ETH_CMD_PFN		8
5715#define M_FW_EQ_ETH_CMD_PFN		0x7
5716#define V_FW_EQ_ETH_CMD_PFN(x)		((x) << S_FW_EQ_ETH_CMD_PFN)
5717#define G_FW_EQ_ETH_CMD_PFN(x)		\
5718    (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5719
5720#define S_FW_EQ_ETH_CMD_VFN		0
5721#define M_FW_EQ_ETH_CMD_VFN		0xff
5722#define V_FW_EQ_ETH_CMD_VFN(x)		((x) << S_FW_EQ_ETH_CMD_VFN)
5723#define G_FW_EQ_ETH_CMD_VFN(x)		\
5724    (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5725
5726#define S_FW_EQ_ETH_CMD_ALLOC		31
5727#define M_FW_EQ_ETH_CMD_ALLOC		0x1
5728#define V_FW_EQ_ETH_CMD_ALLOC(x)	((x) << S_FW_EQ_ETH_CMD_ALLOC)
5729#define G_FW_EQ_ETH_CMD_ALLOC(x)	\
5730    (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5731#define F_FW_EQ_ETH_CMD_ALLOC		V_FW_EQ_ETH_CMD_ALLOC(1U)
5732
5733#define S_FW_EQ_ETH_CMD_FREE		30
5734#define M_FW_EQ_ETH_CMD_FREE		0x1
5735#define V_FW_EQ_ETH_CMD_FREE(x)		((x) << S_FW_EQ_ETH_CMD_FREE)
5736#define G_FW_EQ_ETH_CMD_FREE(x)		\
5737    (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5738#define F_FW_EQ_ETH_CMD_FREE		V_FW_EQ_ETH_CMD_FREE(1U)
5739
5740#define S_FW_EQ_ETH_CMD_MODIFY		29
5741#define M_FW_EQ_ETH_CMD_MODIFY		0x1
5742#define V_FW_EQ_ETH_CMD_MODIFY(x)	((x) << S_FW_EQ_ETH_CMD_MODIFY)
5743#define G_FW_EQ_ETH_CMD_MODIFY(x)	\
5744    (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5745#define F_FW_EQ_ETH_CMD_MODIFY		V_FW_EQ_ETH_CMD_MODIFY(1U)
5746
5747#define S_FW_EQ_ETH_CMD_EQSTART		28
5748#define M_FW_EQ_ETH_CMD_EQSTART		0x1
5749#define V_FW_EQ_ETH_CMD_EQSTART(x)	((x) << S_FW_EQ_ETH_CMD_EQSTART)
5750#define G_FW_EQ_ETH_CMD_EQSTART(x)	\
5751    (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5752#define F_FW_EQ_ETH_CMD_EQSTART		V_FW_EQ_ETH_CMD_EQSTART(1U)
5753
5754#define S_FW_EQ_ETH_CMD_EQSTOP		27
5755#define M_FW_EQ_ETH_CMD_EQSTOP		0x1
5756#define V_FW_EQ_ETH_CMD_EQSTOP(x)	((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5757#define G_FW_EQ_ETH_CMD_EQSTOP(x)	\
5758    (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5759#define F_FW_EQ_ETH_CMD_EQSTOP		V_FW_EQ_ETH_CMD_EQSTOP(1U)
5760
5761#define S_FW_EQ_ETH_CMD_EQID		0
5762#define M_FW_EQ_ETH_CMD_EQID		0xfffff
5763#define V_FW_EQ_ETH_CMD_EQID(x)		((x) << S_FW_EQ_ETH_CMD_EQID)
5764#define G_FW_EQ_ETH_CMD_EQID(x)		\
5765    (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5766
5767#define S_FW_EQ_ETH_CMD_PHYSEQID	0
5768#define M_FW_EQ_ETH_CMD_PHYSEQID	0xfffff
5769#define V_FW_EQ_ETH_CMD_PHYSEQID(x)	((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5770#define G_FW_EQ_ETH_CMD_PHYSEQID(x)	\
5771    (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5772
5773#define S_FW_EQ_ETH_CMD_FETCHSZM	26
5774#define M_FW_EQ_ETH_CMD_FETCHSZM	0x1
5775#define V_FW_EQ_ETH_CMD_FETCHSZM(x)	((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5776#define G_FW_EQ_ETH_CMD_FETCHSZM(x)	\
5777    (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5778#define F_FW_EQ_ETH_CMD_FETCHSZM	V_FW_EQ_ETH_CMD_FETCHSZM(1U)
5779
5780#define S_FW_EQ_ETH_CMD_STATUSPGNS	25
5781#define M_FW_EQ_ETH_CMD_STATUSPGNS	0x1
5782#define V_FW_EQ_ETH_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
5783#define G_FW_EQ_ETH_CMD_STATUSPGNS(x)	\
5784    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
5785#define F_FW_EQ_ETH_CMD_STATUSPGNS	V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
5786
5787#define S_FW_EQ_ETH_CMD_STATUSPGRO	24
5788#define M_FW_EQ_ETH_CMD_STATUSPGRO	0x1
5789#define V_FW_EQ_ETH_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
5790#define G_FW_EQ_ETH_CMD_STATUSPGRO(x)	\
5791    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
5792#define F_FW_EQ_ETH_CMD_STATUSPGRO	V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
5793
5794#define S_FW_EQ_ETH_CMD_FETCHNS		23
5795#define M_FW_EQ_ETH_CMD_FETCHNS		0x1
5796#define V_FW_EQ_ETH_CMD_FETCHNS(x)	((x) << S_FW_EQ_ETH_CMD_FETCHNS)
5797#define G_FW_EQ_ETH_CMD_FETCHNS(x)	\
5798    (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
5799#define F_FW_EQ_ETH_CMD_FETCHNS		V_FW_EQ_ETH_CMD_FETCHNS(1U)
5800
5801#define S_FW_EQ_ETH_CMD_FETCHRO		22
5802#define M_FW_EQ_ETH_CMD_FETCHRO		0x1
5803#define V_FW_EQ_ETH_CMD_FETCHRO(x)	((x) << S_FW_EQ_ETH_CMD_FETCHRO)
5804#define G_FW_EQ_ETH_CMD_FETCHRO(x)	\
5805    (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
5806#define F_FW_EQ_ETH_CMD_FETCHRO		V_FW_EQ_ETH_CMD_FETCHRO(1U)
5807
5808#define S_FW_EQ_ETH_CMD_HOSTFCMODE	20
5809#define M_FW_EQ_ETH_CMD_HOSTFCMODE	0x3
5810#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
5811#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)	\
5812    (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
5813
5814#define S_FW_EQ_ETH_CMD_CPRIO		19
5815#define M_FW_EQ_ETH_CMD_CPRIO		0x1
5816#define V_FW_EQ_ETH_CMD_CPRIO(x)	((x) << S_FW_EQ_ETH_CMD_CPRIO)
5817#define G_FW_EQ_ETH_CMD_CPRIO(x)	\
5818    (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
5819#define F_FW_EQ_ETH_CMD_CPRIO		V_FW_EQ_ETH_CMD_CPRIO(1U)
5820
5821#define S_FW_EQ_ETH_CMD_ONCHIP		18
5822#define M_FW_EQ_ETH_CMD_ONCHIP		0x1
5823#define V_FW_EQ_ETH_CMD_ONCHIP(x)	((x) << S_FW_EQ_ETH_CMD_ONCHIP)
5824#define G_FW_EQ_ETH_CMD_ONCHIP(x)	\
5825    (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
5826#define F_FW_EQ_ETH_CMD_ONCHIP		V_FW_EQ_ETH_CMD_ONCHIP(1U)
5827
5828#define S_FW_EQ_ETH_CMD_PCIECHN		16
5829#define M_FW_EQ_ETH_CMD_PCIECHN		0x3
5830#define V_FW_EQ_ETH_CMD_PCIECHN(x)	((x) << S_FW_EQ_ETH_CMD_PCIECHN)
5831#define G_FW_EQ_ETH_CMD_PCIECHN(x)	\
5832    (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
5833
5834#define S_FW_EQ_ETH_CMD_IQID		0
5835#define M_FW_EQ_ETH_CMD_IQID		0xffff
5836#define V_FW_EQ_ETH_CMD_IQID(x)		((x) << S_FW_EQ_ETH_CMD_IQID)
5837#define G_FW_EQ_ETH_CMD_IQID(x)		\
5838    (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
5839
5840#define S_FW_EQ_ETH_CMD_DCAEN		31
5841#define M_FW_EQ_ETH_CMD_DCAEN		0x1
5842#define V_FW_EQ_ETH_CMD_DCAEN(x)	((x) << S_FW_EQ_ETH_CMD_DCAEN)
5843#define G_FW_EQ_ETH_CMD_DCAEN(x)	\
5844    (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
5845#define F_FW_EQ_ETH_CMD_DCAEN		V_FW_EQ_ETH_CMD_DCAEN(1U)
5846
5847#define S_FW_EQ_ETH_CMD_DCACPU		26
5848#define M_FW_EQ_ETH_CMD_DCACPU		0x1f
5849#define V_FW_EQ_ETH_CMD_DCACPU(x)	((x) << S_FW_EQ_ETH_CMD_DCACPU)
5850#define G_FW_EQ_ETH_CMD_DCACPU(x)	\
5851    (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
5852
5853#define S_FW_EQ_ETH_CMD_FBMIN		23
5854#define M_FW_EQ_ETH_CMD_FBMIN		0x7
5855#define V_FW_EQ_ETH_CMD_FBMIN(x)	((x) << S_FW_EQ_ETH_CMD_FBMIN)
5856#define G_FW_EQ_ETH_CMD_FBMIN(x)	\
5857    (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
5858
5859#define S_FW_EQ_ETH_CMD_FBMAX		20
5860#define M_FW_EQ_ETH_CMD_FBMAX		0x7
5861#define V_FW_EQ_ETH_CMD_FBMAX(x)	((x) << S_FW_EQ_ETH_CMD_FBMAX)
5862#define G_FW_EQ_ETH_CMD_FBMAX(x)	\
5863    (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
5864
5865#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO	19
5866#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO	0x1
5867#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5868#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	\
5869    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5870#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
5871
5872#define S_FW_EQ_ETH_CMD_CIDXFTHRESH	16
5873#define M_FW_EQ_ETH_CMD_CIDXFTHRESH	0x7
5874#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
5875#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	\
5876    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
5877
5878#define S_FW_EQ_ETH_CMD_EQSIZE		0
5879#define M_FW_EQ_ETH_CMD_EQSIZE		0xffff
5880#define V_FW_EQ_ETH_CMD_EQSIZE(x)	((x) << S_FW_EQ_ETH_CMD_EQSIZE)
5881#define G_FW_EQ_ETH_CMD_EQSIZE(x)	\
5882    (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
5883
5884#define S_FW_EQ_ETH_CMD_AUTOEQUIQE	31
5885#define M_FW_EQ_ETH_CMD_AUTOEQUIQE	0x1
5886#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
5887#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	\
5888    (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
5889#define F_FW_EQ_ETH_CMD_AUTOEQUIQE	V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
5890
5891#define S_FW_EQ_ETH_CMD_AUTOEQUEQE	30
5892#define M_FW_EQ_ETH_CMD_AUTOEQUEQE	0x1
5893#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
5894#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	\
5895    (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
5896#define F_FW_EQ_ETH_CMD_AUTOEQUEQE	V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
5897
5898#define S_FW_EQ_ETH_CMD_VIID		16
5899#define M_FW_EQ_ETH_CMD_VIID		0xfff
5900#define V_FW_EQ_ETH_CMD_VIID(x)		((x) << S_FW_EQ_ETH_CMD_VIID)
5901#define G_FW_EQ_ETH_CMD_VIID(x)		\
5902    (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
5903
5904struct fw_eq_ctrl_cmd {
5905	__be32 op_to_vfn;
5906	__be32 alloc_to_len16;
5907	__be32 cmpliqid_eqid;
5908	__be32 physeqid_pkd;
5909	__be32 fetchszm_to_iqid;
5910	__be32 dcaen_to_eqsize;
5911	__be64 eqaddr;
5912};
5913
5914#define S_FW_EQ_CTRL_CMD_PFN		8
5915#define M_FW_EQ_CTRL_CMD_PFN		0x7
5916#define V_FW_EQ_CTRL_CMD_PFN(x)		((x) << S_FW_EQ_CTRL_CMD_PFN)
5917#define G_FW_EQ_CTRL_CMD_PFN(x)		\
5918    (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
5919
5920#define S_FW_EQ_CTRL_CMD_VFN		0
5921#define M_FW_EQ_CTRL_CMD_VFN		0xff
5922#define V_FW_EQ_CTRL_CMD_VFN(x)		((x) << S_FW_EQ_CTRL_CMD_VFN)
5923#define G_FW_EQ_CTRL_CMD_VFN(x)		\
5924    (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
5925
5926#define S_FW_EQ_CTRL_CMD_ALLOC		31
5927#define M_FW_EQ_CTRL_CMD_ALLOC		0x1
5928#define V_FW_EQ_CTRL_CMD_ALLOC(x)	((x) << S_FW_EQ_CTRL_CMD_ALLOC)
5929#define G_FW_EQ_CTRL_CMD_ALLOC(x)	\
5930    (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
5931#define F_FW_EQ_CTRL_CMD_ALLOC		V_FW_EQ_CTRL_CMD_ALLOC(1U)
5932
5933#define S_FW_EQ_CTRL_CMD_FREE		30
5934#define M_FW_EQ_CTRL_CMD_FREE		0x1
5935#define V_FW_EQ_CTRL_CMD_FREE(x)	((x) << S_FW_EQ_CTRL_CMD_FREE)
5936#define G_FW_EQ_CTRL_CMD_FREE(x)	\
5937    (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
5938#define F_FW_EQ_CTRL_CMD_FREE		V_FW_EQ_CTRL_CMD_FREE(1U)
5939
5940#define S_FW_EQ_CTRL_CMD_MODIFY		29
5941#define M_FW_EQ_CTRL_CMD_MODIFY		0x1
5942#define V_FW_EQ_CTRL_CMD_MODIFY(x)	((x) << S_FW_EQ_CTRL_CMD_MODIFY)
5943#define G_FW_EQ_CTRL_CMD_MODIFY(x)	\
5944    (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
5945#define F_FW_EQ_CTRL_CMD_MODIFY		V_FW_EQ_CTRL_CMD_MODIFY(1U)
5946
5947#define S_FW_EQ_CTRL_CMD_EQSTART	28
5948#define M_FW_EQ_CTRL_CMD_EQSTART	0x1
5949#define V_FW_EQ_CTRL_CMD_EQSTART(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTART)
5950#define G_FW_EQ_CTRL_CMD_EQSTART(x)	\
5951    (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
5952#define F_FW_EQ_CTRL_CMD_EQSTART	V_FW_EQ_CTRL_CMD_EQSTART(1U)
5953
5954#define S_FW_EQ_CTRL_CMD_EQSTOP		27
5955#define M_FW_EQ_CTRL_CMD_EQSTOP		0x1
5956#define V_FW_EQ_CTRL_CMD_EQSTOP(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
5957#define G_FW_EQ_CTRL_CMD_EQSTOP(x)	\
5958    (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
5959#define F_FW_EQ_CTRL_CMD_EQSTOP		V_FW_EQ_CTRL_CMD_EQSTOP(1U)
5960
5961#define S_FW_EQ_CTRL_CMD_CMPLIQID	20
5962#define M_FW_EQ_CTRL_CMD_CMPLIQID	0xfff
5963#define V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
5964#define G_FW_EQ_CTRL_CMD_CMPLIQID(x)	\
5965    (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
5966
5967#define S_FW_EQ_CTRL_CMD_EQID		0
5968#define M_FW_EQ_CTRL_CMD_EQID		0xfffff
5969#define V_FW_EQ_CTRL_CMD_EQID(x)	((x) << S_FW_EQ_CTRL_CMD_EQID)
5970#define G_FW_EQ_CTRL_CMD_EQID(x)	\
5971    (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
5972
5973#define S_FW_EQ_CTRL_CMD_PHYSEQID	0
5974#define M_FW_EQ_CTRL_CMD_PHYSEQID	0xfffff
5975#define V_FW_EQ_CTRL_CMD_PHYSEQID(x)	((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
5976#define G_FW_EQ_CTRL_CMD_PHYSEQID(x)	\
5977    (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
5978
5979#define S_FW_EQ_CTRL_CMD_FETCHSZM	26
5980#define M_FW_EQ_CTRL_CMD_FETCHSZM	0x1
5981#define V_FW_EQ_CTRL_CMD_FETCHSZM(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
5982#define G_FW_EQ_CTRL_CMD_FETCHSZM(x)	\
5983    (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
5984#define F_FW_EQ_CTRL_CMD_FETCHSZM	V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
5985
5986#define S_FW_EQ_CTRL_CMD_STATUSPGNS	25
5987#define M_FW_EQ_CTRL_CMD_STATUSPGNS	0x1
5988#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
5989#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x)	\
5990    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
5991#define F_FW_EQ_CTRL_CMD_STATUSPGNS	V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
5992
5993#define S_FW_EQ_CTRL_CMD_STATUSPGRO	24
5994#define M_FW_EQ_CTRL_CMD_STATUSPGRO	0x1
5995#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
5996#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x)	\
5997    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
5998#define F_FW_EQ_CTRL_CMD_STATUSPGRO	V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
5999
6000#define S_FW_EQ_CTRL_CMD_FETCHNS	23
6001#define M_FW_EQ_CTRL_CMD_FETCHNS	0x1
6002#define V_FW_EQ_CTRL_CMD_FETCHNS(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
6003#define G_FW_EQ_CTRL_CMD_FETCHNS(x)	\
6004    (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
6005#define F_FW_EQ_CTRL_CMD_FETCHNS	V_FW_EQ_CTRL_CMD_FETCHNS(1U)
6006
6007#define S_FW_EQ_CTRL_CMD_FETCHRO	22
6008#define M_FW_EQ_CTRL_CMD_FETCHRO	0x1
6009#define V_FW_EQ_CTRL_CMD_FETCHRO(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
6010#define G_FW_EQ_CTRL_CMD_FETCHRO(x)	\
6011    (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
6012#define F_FW_EQ_CTRL_CMD_FETCHRO	V_FW_EQ_CTRL_CMD_FETCHRO(1U)
6013
6014#define S_FW_EQ_CTRL_CMD_HOSTFCMODE	20
6015#define M_FW_EQ_CTRL_CMD_HOSTFCMODE	0x3
6016#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
6017#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	\
6018    (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
6019
6020#define S_FW_EQ_CTRL_CMD_CPRIO		19
6021#define M_FW_EQ_CTRL_CMD_CPRIO		0x1
6022#define V_FW_EQ_CTRL_CMD_CPRIO(x)	((x) << S_FW_EQ_CTRL_CMD_CPRIO)
6023#define G_FW_EQ_CTRL_CMD_CPRIO(x)	\
6024    (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
6025#define F_FW_EQ_CTRL_CMD_CPRIO		V_FW_EQ_CTRL_CMD_CPRIO(1U)
6026
6027#define S_FW_EQ_CTRL_CMD_ONCHIP		18
6028#define M_FW_EQ_CTRL_CMD_ONCHIP		0x1
6029#define V_FW_EQ_CTRL_CMD_ONCHIP(x)	((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
6030#define G_FW_EQ_CTRL_CMD_ONCHIP(x)	\
6031    (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
6032#define F_FW_EQ_CTRL_CMD_ONCHIP		V_FW_EQ_CTRL_CMD_ONCHIP(1U)
6033
6034#define S_FW_EQ_CTRL_CMD_PCIECHN	16
6035#define M_FW_EQ_CTRL_CMD_PCIECHN	0x3
6036#define V_FW_EQ_CTRL_CMD_PCIECHN(x)	((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
6037#define G_FW_EQ_CTRL_CMD_PCIECHN(x)	\
6038    (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
6039
6040#define S_FW_EQ_CTRL_CMD_IQID		0
6041#define M_FW_EQ_CTRL_CMD_IQID		0xffff
6042#define V_FW_EQ_CTRL_CMD_IQID(x)	((x) << S_FW_EQ_CTRL_CMD_IQID)
6043#define G_FW_EQ_CTRL_CMD_IQID(x)	\
6044    (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
6045
6046#define S_FW_EQ_CTRL_CMD_DCAEN		31
6047#define M_FW_EQ_CTRL_CMD_DCAEN		0x1
6048#define V_FW_EQ_CTRL_CMD_DCAEN(x)	((x) << S_FW_EQ_CTRL_CMD_DCAEN)
6049#define G_FW_EQ_CTRL_CMD_DCAEN(x)	\
6050    (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
6051#define F_FW_EQ_CTRL_CMD_DCAEN		V_FW_EQ_CTRL_CMD_DCAEN(1U)
6052
6053#define S_FW_EQ_CTRL_CMD_DCACPU		26
6054#define M_FW_EQ_CTRL_CMD_DCACPU		0x1f
6055#define V_FW_EQ_CTRL_CMD_DCACPU(x)	((x) << S_FW_EQ_CTRL_CMD_DCACPU)
6056#define G_FW_EQ_CTRL_CMD_DCACPU(x)	\
6057    (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
6058
6059#define S_FW_EQ_CTRL_CMD_FBMIN		23
6060#define M_FW_EQ_CTRL_CMD_FBMIN		0x7
6061#define V_FW_EQ_CTRL_CMD_FBMIN(x)	((x) << S_FW_EQ_CTRL_CMD_FBMIN)
6062#define G_FW_EQ_CTRL_CMD_FBMIN(x)	\
6063    (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
6064
6065#define S_FW_EQ_CTRL_CMD_FBMAX		20
6066#define M_FW_EQ_CTRL_CMD_FBMAX		0x7
6067#define V_FW_EQ_CTRL_CMD_FBMAX(x)	((x) << S_FW_EQ_CTRL_CMD_FBMAX)
6068#define G_FW_EQ_CTRL_CMD_FBMAX(x)	\
6069    (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
6070
6071#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO	19
6072#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO	0x1
6073#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6074    ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6075#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6076    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6077#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
6078
6079#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH	16
6080#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH	0x7
6081#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6082#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	\
6083    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6084
6085#define S_FW_EQ_CTRL_CMD_EQSIZE		0
6086#define M_FW_EQ_CTRL_CMD_EQSIZE		0xffff
6087#define V_FW_EQ_CTRL_CMD_EQSIZE(x)	((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
6088#define G_FW_EQ_CTRL_CMD_EQSIZE(x)	\
6089    (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
6090
6091struct fw_eq_ofld_cmd {
6092	__be32 op_to_vfn;
6093	__be32 alloc_to_len16;
6094	__be32 eqid_pkd;
6095	__be32 physeqid_pkd;
6096	__be32 fetchszm_to_iqid;
6097	__be32 dcaen_to_eqsize;
6098	__be64 eqaddr;
6099};
6100
6101#define S_FW_EQ_OFLD_CMD_PFN		8
6102#define M_FW_EQ_OFLD_CMD_PFN		0x7
6103#define V_FW_EQ_OFLD_CMD_PFN(x)		((x) << S_FW_EQ_OFLD_CMD_PFN)
6104#define G_FW_EQ_OFLD_CMD_PFN(x)		\
6105    (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
6106
6107#define S_FW_EQ_OFLD_CMD_VFN		0
6108#define M_FW_EQ_OFLD_CMD_VFN		0xff
6109#define V_FW_EQ_OFLD_CMD_VFN(x)		((x) << S_FW_EQ_OFLD_CMD_VFN)
6110#define G_FW_EQ_OFLD_CMD_VFN(x)		\
6111    (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
6112
6113#define S_FW_EQ_OFLD_CMD_ALLOC		31
6114#define M_FW_EQ_OFLD_CMD_ALLOC		0x1
6115#define V_FW_EQ_OFLD_CMD_ALLOC(x)	((x) << S_FW_EQ_OFLD_CMD_ALLOC)
6116#define G_FW_EQ_OFLD_CMD_ALLOC(x)	\
6117    (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
6118#define F_FW_EQ_OFLD_CMD_ALLOC		V_FW_EQ_OFLD_CMD_ALLOC(1U)
6119
6120#define S_FW_EQ_OFLD_CMD_FREE		30
6121#define M_FW_EQ_OFLD_CMD_FREE		0x1
6122#define V_FW_EQ_OFLD_CMD_FREE(x)	((x) << S_FW_EQ_OFLD_CMD_FREE)
6123#define G_FW_EQ_OFLD_CMD_FREE(x)	\
6124    (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
6125#define F_FW_EQ_OFLD_CMD_FREE		V_FW_EQ_OFLD_CMD_FREE(1U)
6126
6127#define S_FW_EQ_OFLD_CMD_MODIFY		29
6128#define M_FW_EQ_OFLD_CMD_MODIFY		0x1
6129#define V_FW_EQ_OFLD_CMD_MODIFY(x)	((x) << S_FW_EQ_OFLD_CMD_MODIFY)
6130#define G_FW_EQ_OFLD_CMD_MODIFY(x)	\
6131    (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
6132#define F_FW_EQ_OFLD_CMD_MODIFY		V_FW_EQ_OFLD_CMD_MODIFY(1U)
6133
6134#define S_FW_EQ_OFLD_CMD_EQSTART	28
6135#define M_FW_EQ_OFLD_CMD_EQSTART	0x1
6136#define V_FW_EQ_OFLD_CMD_EQSTART(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTART)
6137#define G_FW_EQ_OFLD_CMD_EQSTART(x)	\
6138    (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
6139#define F_FW_EQ_OFLD_CMD_EQSTART	V_FW_EQ_OFLD_CMD_EQSTART(1U)
6140
6141#define S_FW_EQ_OFLD_CMD_EQSTOP		27
6142#define M_FW_EQ_OFLD_CMD_EQSTOP		0x1
6143#define V_FW_EQ_OFLD_CMD_EQSTOP(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
6144#define G_FW_EQ_OFLD_CMD_EQSTOP(x)	\
6145    (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
6146#define F_FW_EQ_OFLD_CMD_EQSTOP		V_FW_EQ_OFLD_CMD_EQSTOP(1U)
6147
6148#define S_FW_EQ_OFLD_CMD_EQID		0
6149#define M_FW_EQ_OFLD_CMD_EQID		0xfffff
6150#define V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
6151#define G_FW_EQ_OFLD_CMD_EQID(x)	\
6152    (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
6153
6154#define S_FW_EQ_OFLD_CMD_PHYSEQID	0
6155#define M_FW_EQ_OFLD_CMD_PHYSEQID	0xfffff
6156#define V_FW_EQ_OFLD_CMD_PHYSEQID(x)	((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
6157#define G_FW_EQ_OFLD_CMD_PHYSEQID(x)	\
6158    (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
6159
6160#define S_FW_EQ_OFLD_CMD_FETCHSZM	26
6161#define M_FW_EQ_OFLD_CMD_FETCHSZM	0x1
6162#define V_FW_EQ_OFLD_CMD_FETCHSZM(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
6163#define G_FW_EQ_OFLD_CMD_FETCHSZM(x)	\
6164    (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
6165#define F_FW_EQ_OFLD_CMD_FETCHSZM	V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
6166
6167#define S_FW_EQ_OFLD_CMD_STATUSPGNS	25
6168#define M_FW_EQ_OFLD_CMD_STATUSPGNS	0x1
6169#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
6170#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x)	\
6171    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
6172#define F_FW_EQ_OFLD_CMD_STATUSPGNS	V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
6173
6174#define S_FW_EQ_OFLD_CMD_STATUSPGRO	24
6175#define M_FW_EQ_OFLD_CMD_STATUSPGRO	0x1
6176#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
6177#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x)	\
6178    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
6179#define F_FW_EQ_OFLD_CMD_STATUSPGRO	V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
6180
6181#define S_FW_EQ_OFLD_CMD_FETCHNS	23
6182#define M_FW_EQ_OFLD_CMD_FETCHNS	0x1
6183#define V_FW_EQ_OFLD_CMD_FETCHNS(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
6184#define G_FW_EQ_OFLD_CMD_FETCHNS(x)	\
6185    (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
6186#define F_FW_EQ_OFLD_CMD_FETCHNS	V_FW_EQ_OFLD_CMD_FETCHNS(1U)
6187
6188#define S_FW_EQ_OFLD_CMD_FETCHRO	22
6189#define M_FW_EQ_OFLD_CMD_FETCHRO	0x1
6190#define V_FW_EQ_OFLD_CMD_FETCHRO(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6191#define G_FW_EQ_OFLD_CMD_FETCHRO(x)	\
6192    (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6193#define F_FW_EQ_OFLD_CMD_FETCHRO	V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6194
6195#define S_FW_EQ_OFLD_CMD_HOSTFCMODE	20
6196#define M_FW_EQ_OFLD_CMD_HOSTFCMODE	0x3
6197#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6198#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	\
6199    (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6200
6201#define S_FW_EQ_OFLD_CMD_CPRIO		19
6202#define M_FW_EQ_OFLD_CMD_CPRIO		0x1
6203#define V_FW_EQ_OFLD_CMD_CPRIO(x)	((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6204#define G_FW_EQ_OFLD_CMD_CPRIO(x)	\
6205    (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6206#define F_FW_EQ_OFLD_CMD_CPRIO		V_FW_EQ_OFLD_CMD_CPRIO(1U)
6207
6208#define S_FW_EQ_OFLD_CMD_ONCHIP		18
6209#define M_FW_EQ_OFLD_CMD_ONCHIP		0x1
6210#define V_FW_EQ_OFLD_CMD_ONCHIP(x)	((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6211#define G_FW_EQ_OFLD_CMD_ONCHIP(x)	\
6212    (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6213#define F_FW_EQ_OFLD_CMD_ONCHIP		V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6214
6215#define S_FW_EQ_OFLD_CMD_PCIECHN	16
6216#define M_FW_EQ_OFLD_CMD_PCIECHN	0x3
6217#define V_FW_EQ_OFLD_CMD_PCIECHN(x)	((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6218#define G_FW_EQ_OFLD_CMD_PCIECHN(x)	\
6219    (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6220
6221#define S_FW_EQ_OFLD_CMD_IQID		0
6222#define M_FW_EQ_OFLD_CMD_IQID		0xffff
6223#define V_FW_EQ_OFLD_CMD_IQID(x)	((x) << S_FW_EQ_OFLD_CMD_IQID)
6224#define G_FW_EQ_OFLD_CMD_IQID(x)	\
6225    (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6226
6227#define S_FW_EQ_OFLD_CMD_DCAEN		31
6228#define M_FW_EQ_OFLD_CMD_DCAEN		0x1
6229#define V_FW_EQ_OFLD_CMD_DCAEN(x)	((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6230#define G_FW_EQ_OFLD_CMD_DCAEN(x)	\
6231    (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6232#define F_FW_EQ_OFLD_CMD_DCAEN		V_FW_EQ_OFLD_CMD_DCAEN(1U)
6233
6234#define S_FW_EQ_OFLD_CMD_DCACPU		26
6235#define M_FW_EQ_OFLD_CMD_DCACPU		0x1f
6236#define V_FW_EQ_OFLD_CMD_DCACPU(x)	((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6237#define G_FW_EQ_OFLD_CMD_DCACPU(x)	\
6238    (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6239
6240#define S_FW_EQ_OFLD_CMD_FBMIN		23
6241#define M_FW_EQ_OFLD_CMD_FBMIN		0x7
6242#define V_FW_EQ_OFLD_CMD_FBMIN(x)	((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6243#define G_FW_EQ_OFLD_CMD_FBMIN(x)	\
6244    (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6245
6246#define S_FW_EQ_OFLD_CMD_FBMAX		20
6247#define M_FW_EQ_OFLD_CMD_FBMAX		0x7
6248#define V_FW_EQ_OFLD_CMD_FBMAX(x)	((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6249#define G_FW_EQ_OFLD_CMD_FBMAX(x)	\
6250    (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6251
6252#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO	19
6253#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO	0x1
6254#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6255    ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6256#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6257    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6258#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6259
6260#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH	16
6261#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH	0x7
6262#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6263#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	\
6264    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6265
6266#define S_FW_EQ_OFLD_CMD_EQSIZE		0
6267#define M_FW_EQ_OFLD_CMD_EQSIZE		0xffff
6268#define V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6269#define G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
6270    (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6271
6272/* Macros for VIID parsing:
6273   VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6274#define S_FW_VIID_PFN		8
6275#define M_FW_VIID_PFN		0x7
6276#define V_FW_VIID_PFN(x)	((x) << S_FW_VIID_PFN)
6277#define G_FW_VIID_PFN(x)	(((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6278
6279#define S_FW_VIID_VIVLD		7
6280#define M_FW_VIID_VIVLD		0x1
6281#define V_FW_VIID_VIVLD(x)	((x) << S_FW_VIID_VIVLD)
6282#define G_FW_VIID_VIVLD(x)	(((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6283
6284#define S_FW_VIID_VIN		0
6285#define M_FW_VIID_VIN		0x7F
6286#define V_FW_VIID_VIN(x)	((x) << S_FW_VIID_VIN)
6287#define G_FW_VIID_VIN(x)	(((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6288
6289enum fw_vi_func {
6290	FW_VI_FUNC_ETH,
6291	FW_VI_FUNC_OFLD,
6292	FW_VI_FUNC_IWARP,
6293	FW_VI_FUNC_OPENISCSI,
6294	FW_VI_FUNC_OPENFCOE,
6295	FW_VI_FUNC_FOISCSI,
6296	FW_VI_FUNC_FOFCOE,
6297	FW_VI_FUNC_FW,
6298};
6299
6300struct fw_vi_cmd {
6301	__be32 op_to_vfn;
6302	__be32 alloc_to_len16;
6303	__be16 type_to_viid;
6304	__u8   mac[6];
6305	__u8   portid_pkd;
6306	__u8   nmac;
6307	__u8   nmac0[6];
6308	__be16 norss_rsssize;
6309	__u8   nmac1[6];
6310	__be16 idsiiq_pkd;
6311	__u8   nmac2[6];
6312	__be16 idseiq_pkd;
6313	__u8   nmac3[6];
6314	__be64 r9;
6315	__be64 r10;
6316};
6317
6318#define S_FW_VI_CMD_PFN			8
6319#define M_FW_VI_CMD_PFN			0x7
6320#define V_FW_VI_CMD_PFN(x)		((x) << S_FW_VI_CMD_PFN)
6321#define G_FW_VI_CMD_PFN(x)		\
6322    (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6323
6324#define S_FW_VI_CMD_VFN			0
6325#define M_FW_VI_CMD_VFN			0xff
6326#define V_FW_VI_CMD_VFN(x)		((x) << S_FW_VI_CMD_VFN)
6327#define G_FW_VI_CMD_VFN(x)		\
6328    (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6329
6330#define S_FW_VI_CMD_ALLOC		31
6331#define M_FW_VI_CMD_ALLOC		0x1
6332#define V_FW_VI_CMD_ALLOC(x)		((x) << S_FW_VI_CMD_ALLOC)
6333#define G_FW_VI_CMD_ALLOC(x)		\
6334    (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6335#define F_FW_VI_CMD_ALLOC		V_FW_VI_CMD_ALLOC(1U)
6336
6337#define S_FW_VI_CMD_FREE		30
6338#define M_FW_VI_CMD_FREE		0x1
6339#define V_FW_VI_CMD_FREE(x)		((x) << S_FW_VI_CMD_FREE)
6340#define G_FW_VI_CMD_FREE(x)		\
6341    (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6342#define F_FW_VI_CMD_FREE		V_FW_VI_CMD_FREE(1U)
6343
6344#define S_FW_VI_CMD_TYPE		15
6345#define M_FW_VI_CMD_TYPE		0x1
6346#define V_FW_VI_CMD_TYPE(x)		((x) << S_FW_VI_CMD_TYPE)
6347#define G_FW_VI_CMD_TYPE(x)		\
6348    (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6349#define F_FW_VI_CMD_TYPE		V_FW_VI_CMD_TYPE(1U)
6350
6351#define S_FW_VI_CMD_FUNC		12
6352#define M_FW_VI_CMD_FUNC		0x7
6353#define V_FW_VI_CMD_FUNC(x)		((x) << S_FW_VI_CMD_FUNC)
6354#define G_FW_VI_CMD_FUNC(x)		\
6355    (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6356
6357#define S_FW_VI_CMD_VIID		0
6358#define M_FW_VI_CMD_VIID		0xfff
6359#define V_FW_VI_CMD_VIID(x)		((x) << S_FW_VI_CMD_VIID)
6360#define G_FW_VI_CMD_VIID(x)		\
6361    (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6362
6363#define S_FW_VI_CMD_PORTID		4
6364#define M_FW_VI_CMD_PORTID		0xf
6365#define V_FW_VI_CMD_PORTID(x)		((x) << S_FW_VI_CMD_PORTID)
6366#define G_FW_VI_CMD_PORTID(x)		\
6367    (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6368
6369#define S_FW_VI_CMD_NORSS		11
6370#define M_FW_VI_CMD_NORSS		0x1
6371#define V_FW_VI_CMD_NORSS(x)		((x) << S_FW_VI_CMD_NORSS)
6372#define G_FW_VI_CMD_NORSS(x)		\
6373    (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6374#define F_FW_VI_CMD_NORSS		V_FW_VI_CMD_NORSS(1U)
6375
6376#define S_FW_VI_CMD_RSSSIZE		0
6377#define M_FW_VI_CMD_RSSSIZE		0x7ff
6378#define V_FW_VI_CMD_RSSSIZE(x)		((x) << S_FW_VI_CMD_RSSSIZE)
6379#define G_FW_VI_CMD_RSSSIZE(x)		\
6380    (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6381
6382#define S_FW_VI_CMD_IDSIIQ		0
6383#define M_FW_VI_CMD_IDSIIQ		0x3ff
6384#define V_FW_VI_CMD_IDSIIQ(x)		((x) << S_FW_VI_CMD_IDSIIQ)
6385#define G_FW_VI_CMD_IDSIIQ(x)		\
6386    (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6387
6388#define S_FW_VI_CMD_IDSEIQ		0
6389#define M_FW_VI_CMD_IDSEIQ		0x3ff
6390#define V_FW_VI_CMD_IDSEIQ(x)		((x) << S_FW_VI_CMD_IDSEIQ)
6391#define G_FW_VI_CMD_IDSEIQ(x)		\
6392    (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6393
6394/* Special VI_MAC command index ids */
6395#define FW_VI_MAC_ADD_MAC		0x3FF
6396#define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
6397#define FW_VI_MAC_MAC_BASED_FREE	0x3FD
6398
6399enum fw_vi_mac_smac {
6400	FW_VI_MAC_MPS_TCAM_ENTRY,
6401	FW_VI_MAC_MPS_TCAM_ONLY,
6402	FW_VI_MAC_SMT_ONLY,
6403	FW_VI_MAC_SMT_AND_MPSTCAM
6404};
6405
6406enum fw_vi_mac_result {
6407	FW_VI_MAC_R_SUCCESS,
6408	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6409	FW_VI_MAC_R_SMAC_FAIL,
6410	FW_VI_MAC_R_F_ACL_CHECK
6411};
6412
6413enum fw_vi_mac_entry_types {
6414	FW_VI_MAC_TYPE_EXACTMAC,
6415	FW_VI_MAC_TYPE_HASHVEC,
6416	FW_VI_MAC_TYPE_RAW,
6417};
6418
6419struct fw_vi_mac_cmd {
6420	__be32 op_to_viid;
6421	__be32 freemacs_to_len16;
6422	union fw_vi_mac {
6423		struct fw_vi_mac_exact {
6424			__be16 valid_to_idx;
6425			__u8   macaddr[6];
6426		} exact[7];
6427		struct fw_vi_mac_hash {
6428			__be64 hashvec;
6429		} hash;
6430		struct fw_vi_mac_raw {
6431			__be32 raw_idx_pkd;
6432			__be32 data0_pkd;
6433			__be32 data1[2];
6434			__be64 data0m_pkd;
6435			__be32 data1m[2];
6436		} raw;
6437	} u;
6438};
6439
6440#define S_FW_VI_MAC_CMD_VIID		0
6441#define M_FW_VI_MAC_CMD_VIID		0xfff
6442#define V_FW_VI_MAC_CMD_VIID(x)		((x) << S_FW_VI_MAC_CMD_VIID)
6443#define G_FW_VI_MAC_CMD_VIID(x)		\
6444    (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6445
6446#define S_FW_VI_MAC_CMD_FREEMACS	31
6447#define M_FW_VI_MAC_CMD_FREEMACS	0x1
6448#define V_FW_VI_MAC_CMD_FREEMACS(x)	((x) << S_FW_VI_MAC_CMD_FREEMACS)
6449#define G_FW_VI_MAC_CMD_FREEMACS(x)	\
6450    (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6451#define F_FW_VI_MAC_CMD_FREEMACS	V_FW_VI_MAC_CMD_FREEMACS(1U)
6452
6453#define S_FW_VI_MAC_CMD_ENTRY_TYPE	23
6454#define M_FW_VI_MAC_CMD_ENTRY_TYPE	0x7
6455#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)	((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6456#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x)	\
6457    (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6458
6459#define S_FW_VI_MAC_CMD_HASHUNIEN	22
6460#define M_FW_VI_MAC_CMD_HASHUNIEN	0x1
6461#define V_FW_VI_MAC_CMD_HASHUNIEN(x)	((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6462#define G_FW_VI_MAC_CMD_HASHUNIEN(x)	\
6463    (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6464#define F_FW_VI_MAC_CMD_HASHUNIEN	V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6465
6466#define S_FW_VI_MAC_CMD_VALID		15
6467#define M_FW_VI_MAC_CMD_VALID		0x1
6468#define V_FW_VI_MAC_CMD_VALID(x)	((x) << S_FW_VI_MAC_CMD_VALID)
6469#define G_FW_VI_MAC_CMD_VALID(x)	\
6470    (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6471#define F_FW_VI_MAC_CMD_VALID		V_FW_VI_MAC_CMD_VALID(1U)
6472
6473#define S_FW_VI_MAC_CMD_PRIO		12
6474#define M_FW_VI_MAC_CMD_PRIO		0x7
6475#define V_FW_VI_MAC_CMD_PRIO(x)		((x) << S_FW_VI_MAC_CMD_PRIO)
6476#define G_FW_VI_MAC_CMD_PRIO(x)		\
6477    (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6478
6479#define S_FW_VI_MAC_CMD_SMAC_RESULT	10
6480#define M_FW_VI_MAC_CMD_SMAC_RESULT	0x3
6481#define V_FW_VI_MAC_CMD_SMAC_RESULT(x)	((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6482#define G_FW_VI_MAC_CMD_SMAC_RESULT(x)	\
6483    (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6484
6485#define S_FW_VI_MAC_CMD_IDX		0
6486#define M_FW_VI_MAC_CMD_IDX		0x3ff
6487#define V_FW_VI_MAC_CMD_IDX(x)		((x) << S_FW_VI_MAC_CMD_IDX)
6488#define G_FW_VI_MAC_CMD_IDX(x)		\
6489    (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6490
6491#define S_FW_VI_MAC_CMD_RAW_IDX		16
6492#define M_FW_VI_MAC_CMD_RAW_IDX		0xffff
6493#define V_FW_VI_MAC_CMD_RAW_IDX(x)	((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6494#define G_FW_VI_MAC_CMD_RAW_IDX(x)	\
6495    (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6496
6497#define S_FW_VI_MAC_CMD_DATA0		0
6498#define M_FW_VI_MAC_CMD_DATA0		0xffff
6499#define V_FW_VI_MAC_CMD_DATA0(x)	((x) << S_FW_VI_MAC_CMD_DATA0)
6500#define G_FW_VI_MAC_CMD_DATA0(x)	\
6501    (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6502
6503/* T4 max MTU supported */
6504#define T4_MAX_MTU_SUPPORTED	9600
6505#define FW_RXMODE_MTU_NO_CHG	65535
6506
6507struct fw_vi_rxmode_cmd {
6508	__be32 op_to_viid;
6509	__be32 retval_len16;
6510	__be32 mtu_to_vlanexen;
6511	__be32 r4_lo;
6512};
6513
6514#define S_FW_VI_RXMODE_CMD_VIID		0
6515#define M_FW_VI_RXMODE_CMD_VIID		0xfff
6516#define V_FW_VI_RXMODE_CMD_VIID(x)	((x) << S_FW_VI_RXMODE_CMD_VIID)
6517#define G_FW_VI_RXMODE_CMD_VIID(x)	\
6518    (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6519
6520#define S_FW_VI_RXMODE_CMD_MTU		16
6521#define M_FW_VI_RXMODE_CMD_MTU		0xffff
6522#define V_FW_VI_RXMODE_CMD_MTU(x)	((x) << S_FW_VI_RXMODE_CMD_MTU)
6523#define G_FW_VI_RXMODE_CMD_MTU(x)	\
6524    (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6525
6526#define S_FW_VI_RXMODE_CMD_PROMISCEN	14
6527#define M_FW_VI_RXMODE_CMD_PROMISCEN	0x3
6528#define V_FW_VI_RXMODE_CMD_PROMISCEN(x)	((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6529#define G_FW_VI_RXMODE_CMD_PROMISCEN(x)	\
6530    (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6531
6532#define S_FW_VI_RXMODE_CMD_ALLMULTIEN	12
6533#define M_FW_VI_RXMODE_CMD_ALLMULTIEN	0x3
6534#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6535    ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6536#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6537    (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6538
6539#define S_FW_VI_RXMODE_CMD_BROADCASTEN	10
6540#define M_FW_VI_RXMODE_CMD_BROADCASTEN	0x3
6541#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6542    ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6543#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6544    (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6545
6546#define S_FW_VI_RXMODE_CMD_VLANEXEN	8
6547#define M_FW_VI_RXMODE_CMD_VLANEXEN	0x3
6548#define V_FW_VI_RXMODE_CMD_VLANEXEN(x)	((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6549#define G_FW_VI_RXMODE_CMD_VLANEXEN(x)	\
6550    (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6551
6552struct fw_vi_enable_cmd {
6553	__be32 op_to_viid;
6554	__be32 ien_to_len16;
6555	__be16 blinkdur;
6556	__be16 r3;
6557	__be32 r4;
6558};
6559
6560#define S_FW_VI_ENABLE_CMD_VIID		0
6561#define M_FW_VI_ENABLE_CMD_VIID		0xfff
6562#define V_FW_VI_ENABLE_CMD_VIID(x)	((x) << S_FW_VI_ENABLE_CMD_VIID)
6563#define G_FW_VI_ENABLE_CMD_VIID(x)	\
6564    (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6565
6566#define S_FW_VI_ENABLE_CMD_IEN		31
6567#define M_FW_VI_ENABLE_CMD_IEN		0x1
6568#define V_FW_VI_ENABLE_CMD_IEN(x)	((x) << S_FW_VI_ENABLE_CMD_IEN)
6569#define G_FW_VI_ENABLE_CMD_IEN(x)	\
6570    (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6571#define F_FW_VI_ENABLE_CMD_IEN		V_FW_VI_ENABLE_CMD_IEN(1U)
6572
6573#define S_FW_VI_ENABLE_CMD_EEN		30
6574#define M_FW_VI_ENABLE_CMD_EEN		0x1
6575#define V_FW_VI_ENABLE_CMD_EEN(x)	((x) << S_FW_VI_ENABLE_CMD_EEN)
6576#define G_FW_VI_ENABLE_CMD_EEN(x)	\
6577    (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6578#define F_FW_VI_ENABLE_CMD_EEN		V_FW_VI_ENABLE_CMD_EEN(1U)
6579
6580#define S_FW_VI_ENABLE_CMD_LED		29
6581#define M_FW_VI_ENABLE_CMD_LED		0x1
6582#define V_FW_VI_ENABLE_CMD_LED(x)	((x) << S_FW_VI_ENABLE_CMD_LED)
6583#define G_FW_VI_ENABLE_CMD_LED(x)	\
6584    (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6585#define F_FW_VI_ENABLE_CMD_LED		V_FW_VI_ENABLE_CMD_LED(1U)
6586
6587#define S_FW_VI_ENABLE_CMD_DCB_INFO	28
6588#define M_FW_VI_ENABLE_CMD_DCB_INFO	0x1
6589#define V_FW_VI_ENABLE_CMD_DCB_INFO(x)	((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6590#define G_FW_VI_ENABLE_CMD_DCB_INFO(x)	\
6591    (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6592#define F_FW_VI_ENABLE_CMD_DCB_INFO	V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6593
6594/* VI VF stats offset definitions */
6595#define VI_VF_NUM_STATS	16
6596enum fw_vi_stats_vf_index {
6597	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6598	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6599	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6600	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6601	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6602	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6603	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6604	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6605	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6606	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6607	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6608	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6609	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6610	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6611	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6612	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6613};
6614
6615/* VI PF stats offset definitions */
6616#define VI_PF_NUM_STATS	17
6617enum fw_vi_stats_pf_index {
6618	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6619	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6620	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6621	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6622	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6623	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6624	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6625	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6626	FW_VI_PF_STAT_RX_BYTES_IX,
6627	FW_VI_PF_STAT_RX_FRAMES_IX,
6628	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6629	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6630	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6631	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6632	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6633	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6634	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6635};
6636
6637struct fw_vi_stats_cmd {
6638	__be32 op_to_viid;
6639	__be32 retval_len16;
6640	union fw_vi_stats {
6641		struct fw_vi_stats_ctl {
6642			__be16 nstats_ix;
6643			__be16 r6;
6644			__be32 r7;
6645			__be64 stat0;
6646			__be64 stat1;
6647			__be64 stat2;
6648			__be64 stat3;
6649			__be64 stat4;
6650			__be64 stat5;
6651		} ctl;
6652		struct fw_vi_stats_pf {
6653			__be64 tx_bcast_bytes;
6654			__be64 tx_bcast_frames;
6655			__be64 tx_mcast_bytes;
6656			__be64 tx_mcast_frames;
6657			__be64 tx_ucast_bytes;
6658			__be64 tx_ucast_frames;
6659			__be64 tx_offload_bytes;
6660			__be64 tx_offload_frames;
6661			__be64 rx_pf_bytes;
6662			__be64 rx_pf_frames;
6663			__be64 rx_bcast_bytes;
6664			__be64 rx_bcast_frames;
6665			__be64 rx_mcast_bytes;
6666			__be64 rx_mcast_frames;
6667			__be64 rx_ucast_bytes;
6668			__be64 rx_ucast_frames;
6669			__be64 rx_err_frames;
6670		} pf;
6671		struct fw_vi_stats_vf {
6672			__be64 tx_bcast_bytes;
6673			__be64 tx_bcast_frames;
6674			__be64 tx_mcast_bytes;
6675			__be64 tx_mcast_frames;
6676			__be64 tx_ucast_bytes;
6677			__be64 tx_ucast_frames;
6678			__be64 tx_drop_frames;
6679			__be64 tx_offload_bytes;
6680			__be64 tx_offload_frames;
6681			__be64 rx_bcast_bytes;
6682			__be64 rx_bcast_frames;
6683			__be64 rx_mcast_bytes;
6684			__be64 rx_mcast_frames;
6685			__be64 rx_ucast_bytes;
6686			__be64 rx_ucast_frames;
6687			__be64 rx_err_frames;
6688		} vf;
6689	} u;
6690};
6691
6692#define S_FW_VI_STATS_CMD_VIID		0
6693#define M_FW_VI_STATS_CMD_VIID		0xfff
6694#define V_FW_VI_STATS_CMD_VIID(x)	((x) << S_FW_VI_STATS_CMD_VIID)
6695#define G_FW_VI_STATS_CMD_VIID(x)	\
6696    (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
6697
6698#define S_FW_VI_STATS_CMD_NSTATS	12
6699#define M_FW_VI_STATS_CMD_NSTATS	0x7
6700#define V_FW_VI_STATS_CMD_NSTATS(x)	((x) << S_FW_VI_STATS_CMD_NSTATS)
6701#define G_FW_VI_STATS_CMD_NSTATS(x)	\
6702    (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
6703
6704#define S_FW_VI_STATS_CMD_IX		0
6705#define M_FW_VI_STATS_CMD_IX		0x1f
6706#define V_FW_VI_STATS_CMD_IX(x)		((x) << S_FW_VI_STATS_CMD_IX)
6707#define G_FW_VI_STATS_CMD_IX(x)		\
6708    (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
6709
6710struct fw_acl_mac_cmd {
6711	__be32 op_to_vfn;
6712	__be32 en_to_len16;
6713	__u8   nmac;
6714	__u8   r3[7];
6715	__be16 r4;
6716	__u8   macaddr0[6];
6717	__be16 r5;
6718	__u8   macaddr1[6];
6719	__be16 r6;
6720	__u8   macaddr2[6];
6721	__be16 r7;
6722	__u8   macaddr3[6];
6723};
6724
6725#define S_FW_ACL_MAC_CMD_PFN		8
6726#define M_FW_ACL_MAC_CMD_PFN		0x7
6727#define V_FW_ACL_MAC_CMD_PFN(x)		((x) << S_FW_ACL_MAC_CMD_PFN)
6728#define G_FW_ACL_MAC_CMD_PFN(x)		\
6729    (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
6730
6731#define S_FW_ACL_MAC_CMD_VFN		0
6732#define M_FW_ACL_MAC_CMD_VFN		0xff
6733#define V_FW_ACL_MAC_CMD_VFN(x)		((x) << S_FW_ACL_MAC_CMD_VFN)
6734#define G_FW_ACL_MAC_CMD_VFN(x)		\
6735    (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
6736
6737#define S_FW_ACL_MAC_CMD_EN		31
6738#define M_FW_ACL_MAC_CMD_EN		0x1
6739#define V_FW_ACL_MAC_CMD_EN(x)		((x) << S_FW_ACL_MAC_CMD_EN)
6740#define G_FW_ACL_MAC_CMD_EN(x)		\
6741    (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
6742#define F_FW_ACL_MAC_CMD_EN		V_FW_ACL_MAC_CMD_EN(1U)
6743
6744struct fw_acl_vlan_cmd {
6745	__be32 op_to_vfn;
6746	__be32 en_to_len16;
6747	__u8   nvlan;
6748	__u8   dropnovlan_fm;
6749	__u8   r3_lo[6];
6750	__be16 vlanid[16];
6751};
6752
6753#define S_FW_ACL_VLAN_CMD_PFN		8
6754#define M_FW_ACL_VLAN_CMD_PFN		0x7
6755#define V_FW_ACL_VLAN_CMD_PFN(x)	((x) << S_FW_ACL_VLAN_CMD_PFN)
6756#define G_FW_ACL_VLAN_CMD_PFN(x)	\
6757    (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
6758
6759#define S_FW_ACL_VLAN_CMD_VFN		0
6760#define M_FW_ACL_VLAN_CMD_VFN		0xff
6761#define V_FW_ACL_VLAN_CMD_VFN(x)	((x) << S_FW_ACL_VLAN_CMD_VFN)
6762#define G_FW_ACL_VLAN_CMD_VFN(x)	\
6763    (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
6764
6765#define S_FW_ACL_VLAN_CMD_EN		31
6766#define M_FW_ACL_VLAN_CMD_EN		0x1
6767#define V_FW_ACL_VLAN_CMD_EN(x)		((x) << S_FW_ACL_VLAN_CMD_EN)
6768#define G_FW_ACL_VLAN_CMD_EN(x)		\
6769    (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
6770#define F_FW_ACL_VLAN_CMD_EN		V_FW_ACL_VLAN_CMD_EN(1U)
6771
6772#define S_FW_ACL_VLAN_CMD_DROPNOVLAN	7
6773#define M_FW_ACL_VLAN_CMD_DROPNOVLAN	0x1
6774#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
6775#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	\
6776    (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
6777#define F_FW_ACL_VLAN_CMD_DROPNOVLAN	V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
6778
6779#define S_FW_ACL_VLAN_CMD_FM		6
6780#define M_FW_ACL_VLAN_CMD_FM		0x1
6781#define V_FW_ACL_VLAN_CMD_FM(x)		((x) << S_FW_ACL_VLAN_CMD_FM)
6782#define G_FW_ACL_VLAN_CMD_FM(x)		\
6783    (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
6784#define F_FW_ACL_VLAN_CMD_FM		V_FW_ACL_VLAN_CMD_FM(1U)
6785
6786/* port capabilities bitmap */
6787enum fw_port_cap {
6788	FW_PORT_CAP_SPEED_100M		= 0x0001,
6789	FW_PORT_CAP_SPEED_1G		= 0x0002,
6790	FW_PORT_CAP_SPEED_25G		= 0x0004,
6791	FW_PORT_CAP_SPEED_10G		= 0x0008,
6792	FW_PORT_CAP_SPEED_40G		= 0x0010,
6793	FW_PORT_CAP_SPEED_100G		= 0x0020,
6794	FW_PORT_CAP_FC_RX		= 0x0040,
6795	FW_PORT_CAP_FC_TX		= 0x0080,
6796	FW_PORT_CAP_ANEG		= 0x0100,
6797	FW_PORT_CAP_MDIX		= 0x0200,
6798	FW_PORT_CAP_MDIAUTO		= 0x0400,
6799	FW_PORT_CAP_FEC_RS		= 0x0800,
6800	FW_PORT_CAP_FEC_BASER_RS	= 0x1000,
6801	FW_PORT_CAP_FEC_RESERVED	= 0x2000,
6802	FW_PORT_CAP_802_3_PAUSE		= 0x4000,
6803	FW_PORT_CAP_802_3_ASM_DIR	= 0x8000,
6804};
6805
6806#define S_FW_PORT_CAP_SPEED	0
6807#define M_FW_PORT_CAP_SPEED	0x3f
6808#define V_FW_PORT_CAP_SPEED(x)	((x) << S_FW_PORT_CAP_SPEED)
6809#define G_FW_PORT_CAP_SPEED(x) \
6810    (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
6811
6812#define S_FW_PORT_CAP_FC	6
6813#define M_FW_PORT_CAP_FC	0x3
6814#define V_FW_PORT_CAP_FC(x)	((x) << S_FW_PORT_CAP_FC)
6815#define G_FW_PORT_CAP_FC(x) \
6816    (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
6817
6818#define S_FW_PORT_CAP_ANEG	8
6819#define M_FW_PORT_CAP_ANEG	0x1
6820#define V_FW_PORT_CAP_ANEG(x)	((x) << S_FW_PORT_CAP_ANEG)
6821#define G_FW_PORT_CAP_ANEG(x) \
6822    (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
6823
6824#define S_FW_PORT_CAP_FEC	11
6825#define M_FW_PORT_CAP_FEC	0x7
6826#define V_FW_PORT_CAP_FEC(x)	((x) << S_FW_PORT_CAP_FEC)
6827#define G_FW_PORT_CAP_FEC(x) \
6828    (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
6829
6830#define S_FW_PORT_CAP_802_3	14
6831#define M_FW_PORT_CAP_802_3	0x3
6832#define V_FW_PORT_CAP_802_3(x)	((x) << S_FW_PORT_CAP_802_3)
6833#define G_FW_PORT_CAP_802_3(x) \
6834    (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
6835
6836enum fw_port_mdi {
6837	FW_PORT_CAP_MDI_UNCHANGED,
6838	FW_PORT_CAP_MDI_AUTO,
6839	FW_PORT_CAP_MDI_F_STRAIGHT,
6840	FW_PORT_CAP_MDI_F_CROSSOVER
6841};
6842
6843#define S_FW_PORT_CAP_MDI 9
6844#define M_FW_PORT_CAP_MDI 3
6845#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
6846#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
6847
6848#define S_FW_PORT_AUXLINFO_KX4	2
6849#define M_FW_PORT_AUXLINFO_KX4	0x1
6850#define V_FW_PORT_AUXLINFO_KX4(x) \
6851    ((x) << S_FW_PORT_AUXLINFO_KX4)
6852#define G_FW_PORT_AUXLINFO_KX4(x) \
6853    (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
6854#define F_FW_PORT_AUXLINFO_KX4	V_FW_PORT_AUXLINFO_KX4(1U)
6855
6856#define S_FW_PORT_AUXLINFO_KR	1
6857#define M_FW_PORT_AUXLINFO_KR	0x1
6858#define V_FW_PORT_AUXLINFO_KR(x) \
6859    ((x) << S_FW_PORT_AUXLINFO_KR)
6860#define G_FW_PORT_AUXLINFO_KR(x) \
6861    (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
6862#define F_FW_PORT_AUXLINFO_KR	V_FW_PORT_AUXLINFO_KR(1U)
6863
6864enum fw_port_action {
6865	FW_PORT_ACTION_L1_CFG		= 0x0001,
6866	FW_PORT_ACTION_L2_CFG		= 0x0002,
6867	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
6868	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
6869	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
6870	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,
6871	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,
6872	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,
6873	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
6874	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
6875	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
6876	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
6877	FW_PORT_ACTION_LPBK_SS_ASIC	= 0x0022,
6878	FW_PORT_ACTION_LPBK_WS_ASIC	= 0x0023,
6879	FW_PORT_ACTION_LPBK_WS_EXT_PHY	= 0x0025,
6880	FW_PORT_ACTION_LPBK_SS_EXT	= 0x0026,
6881	FW_PORT_ACTION_DIAGNOSTICS	= 0x0027,
6882	FW_PORT_ACTION_LPBK_SS_EXT_PHY	= 0x0028,
6883	FW_PORT_ACTION_PHY_RESET	= 0x0040,
6884	FW_PORT_ACTION_PMA_RESET	= 0x0041,
6885	FW_PORT_ACTION_PCS_RESET	= 0x0042,
6886	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
6887	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
6888	FW_PORT_ACTION_AN_RESET		= 0x0045,
6889
6890};
6891
6892enum fw_port_l2cfg_ctlbf {
6893	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
6894	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
6895	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
6896	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
6897	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
6898	FW_PORT_L2_CTLBF_TXIPG	= 0x20,
6899	FW_PORT_L2_CTLBF_MTU	= 0x40
6900};
6901
6902enum fw_dcb_app_tlv_sf {
6903	FW_DCB_APP_SF_ETHERTYPE,
6904	FW_DCB_APP_SF_SOCKET_TCP,
6905	FW_DCB_APP_SF_SOCKET_UDP,
6906	FW_DCB_APP_SF_SOCKET_ALL,
6907};
6908
6909enum fw_port_dcb_versions {
6910	FW_PORT_DCB_VER_UNKNOWN,
6911	FW_PORT_DCB_VER_CEE1D0,
6912	FW_PORT_DCB_VER_CEE1D01,
6913	FW_PORT_DCB_VER_IEEE,
6914	FW_PORT_DCB_VER_AUTO=7
6915};
6916
6917enum fw_port_dcb_cfg {
6918	FW_PORT_DCB_CFG_PG	= 0x01,
6919	FW_PORT_DCB_CFG_PFC	= 0x02,
6920	FW_PORT_DCB_CFG_APPL	= 0x04
6921};
6922
6923enum fw_port_dcb_cfg_rc {
6924	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
6925	FW_PORT_DCB_CFG_ERROR	= 0x1
6926};
6927
6928enum fw_port_dcb_type {
6929	FW_PORT_DCB_TYPE_PGID		= 0x00,
6930	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
6931	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
6932	FW_PORT_DCB_TYPE_PFC		= 0x03,
6933	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
6934	FW_PORT_DCB_TYPE_CONTROL	= 0x05,
6935};
6936
6937enum fw_port_dcb_feature_state {
6938	FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
6939	FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
6940	FW_PORT_DCB_FEATURE_STATE_ERROR	= 0x2,
6941	FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
6942};
6943
6944enum fw_port_diag_ops {
6945	FW_PORT_DIAGS_TEMP		= 0x00,
6946	FW_PORT_DIAGS_TX_POWER		= 0x01,
6947	FW_PORT_DIAGS_RX_POWER		= 0x02,
6948	FW_PORT_DIAGS_TX_DIS		= 0x03,
6949};
6950
6951struct fw_port_cmd {
6952	__be32 op_to_portid;
6953	__be32 action_to_len16;
6954	union fw_port {
6955		struct fw_port_l1cfg {
6956			__be32 rcap;
6957			__be32 r;
6958		} l1cfg;
6959		struct fw_port_l2cfg {
6960			__u8   ctlbf;
6961			__u8   ovlan3_to_ivlan0;
6962			__be16 ivlantype;
6963			__be16 txipg_force_pinfo;
6964			__be16 mtu;
6965			__be16 ovlan0mask;
6966			__be16 ovlan0type;
6967			__be16 ovlan1mask;
6968			__be16 ovlan1type;
6969			__be16 ovlan2mask;
6970			__be16 ovlan2type;
6971			__be16 ovlan3mask;
6972			__be16 ovlan3type;
6973		} l2cfg;
6974		struct fw_port_info {
6975			__be32 lstatus_to_modtype;
6976			__be16 pcap;
6977			__be16 acap;
6978			__be16 mtu;
6979			__u8   cbllen;
6980			__u8   auxlinfo;
6981			__u8   dcbxdis_pkd;
6982			__u8   r8_lo;
6983			__be16 lpacap;
6984			__be64 r9;
6985		} info;
6986		struct fw_port_diags {
6987			__u8   diagop;
6988			__u8   r[3];
6989			__be32 diagval;
6990		} diags;
6991		union fw_port_dcb {
6992			struct fw_port_dcb_pgid {
6993				__u8   type;
6994				__u8   apply_pkd;
6995				__u8   r10_lo[2];
6996				__be32 pgid;
6997				__be64 r11;
6998			} pgid;
6999			struct fw_port_dcb_pgrate {
7000				__u8   type;
7001				__u8   apply_pkd;
7002				__u8   r10_lo[5];
7003				__u8   num_tcs_supported;
7004				__u8   pgrate[8];
7005				__u8   tsa[8];
7006			} pgrate;
7007			struct fw_port_dcb_priorate {
7008				__u8   type;
7009				__u8   apply_pkd;
7010				__u8   r10_lo[6];
7011				__u8   strict_priorate[8];
7012			} priorate;
7013			struct fw_port_dcb_pfc {
7014				__u8   type;
7015				__u8   pfcen;
7016				__u8   r10[5];
7017				__u8   max_pfc_tcs;
7018				__be64 r11;
7019			} pfc;
7020			struct fw_port_app_priority {
7021				__u8   type;
7022				__u8   r10[2];
7023				__u8   idx;
7024				__u8   user_prio_map;
7025				__u8   sel_field;
7026				__be16 protocolid;
7027				__be64 r12;
7028			} app_priority;
7029			struct fw_port_dcb_control {
7030				__u8   type;
7031				__u8   all_syncd_pkd;
7032				__be16 dcb_version_to_app_state;
7033				__be32 r11;
7034				__be64 r12;
7035			} control;
7036		} dcb;
7037	} u;
7038};
7039
7040#define S_FW_PORT_CMD_READ		22
7041#define M_FW_PORT_CMD_READ		0x1
7042#define V_FW_PORT_CMD_READ(x)		((x) << S_FW_PORT_CMD_READ)
7043#define G_FW_PORT_CMD_READ(x)		\
7044    (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
7045#define F_FW_PORT_CMD_READ		V_FW_PORT_CMD_READ(1U)
7046
7047#define S_FW_PORT_CMD_PORTID		0
7048#define M_FW_PORT_CMD_PORTID		0xf
7049#define V_FW_PORT_CMD_PORTID(x)		((x) << S_FW_PORT_CMD_PORTID)
7050#define G_FW_PORT_CMD_PORTID(x)		\
7051    (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
7052
7053#define S_FW_PORT_CMD_ACTION		16
7054#define M_FW_PORT_CMD_ACTION		0xffff
7055#define V_FW_PORT_CMD_ACTION(x)		((x) << S_FW_PORT_CMD_ACTION)
7056#define G_FW_PORT_CMD_ACTION(x)		\
7057    (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
7058
7059#define S_FW_PORT_CMD_OVLAN3		7
7060#define M_FW_PORT_CMD_OVLAN3		0x1
7061#define V_FW_PORT_CMD_OVLAN3(x)		((x) << S_FW_PORT_CMD_OVLAN3)
7062#define G_FW_PORT_CMD_OVLAN3(x)		\
7063    (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
7064#define F_FW_PORT_CMD_OVLAN3		V_FW_PORT_CMD_OVLAN3(1U)
7065
7066#define S_FW_PORT_CMD_OVLAN2		6
7067#define M_FW_PORT_CMD_OVLAN2		0x1
7068#define V_FW_PORT_CMD_OVLAN2(x)		((x) << S_FW_PORT_CMD_OVLAN2)
7069#define G_FW_PORT_CMD_OVLAN2(x)		\
7070    (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
7071#define F_FW_PORT_CMD_OVLAN2		V_FW_PORT_CMD_OVLAN2(1U)
7072
7073#define S_FW_PORT_CMD_OVLAN1		5
7074#define M_FW_PORT_CMD_OVLAN1		0x1
7075#define V_FW_PORT_CMD_OVLAN1(x)		((x) << S_FW_PORT_CMD_OVLAN1)
7076#define G_FW_PORT_CMD_OVLAN1(x)		\
7077    (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
7078#define F_FW_PORT_CMD_OVLAN1		V_FW_PORT_CMD_OVLAN1(1U)
7079
7080#define S_FW_PORT_CMD_OVLAN0		4
7081#define M_FW_PORT_CMD_OVLAN0		0x1
7082#define V_FW_PORT_CMD_OVLAN0(x)		((x) << S_FW_PORT_CMD_OVLAN0)
7083#define G_FW_PORT_CMD_OVLAN0(x)		\
7084    (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7085#define F_FW_PORT_CMD_OVLAN0		V_FW_PORT_CMD_OVLAN0(1U)
7086
7087#define S_FW_PORT_CMD_IVLAN0		3
7088#define M_FW_PORT_CMD_IVLAN0		0x1
7089#define V_FW_PORT_CMD_IVLAN0(x)		((x) << S_FW_PORT_CMD_IVLAN0)
7090#define G_FW_PORT_CMD_IVLAN0(x)		\
7091    (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7092#define F_FW_PORT_CMD_IVLAN0		V_FW_PORT_CMD_IVLAN0(1U)
7093
7094#define S_FW_PORT_CMD_TXIPG		3
7095#define M_FW_PORT_CMD_TXIPG		0x1fff
7096#define V_FW_PORT_CMD_TXIPG(x)		((x) << S_FW_PORT_CMD_TXIPG)
7097#define G_FW_PORT_CMD_TXIPG(x)		\
7098    (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7099
7100#define S_FW_PORT_CMD_FORCE_PINFO	0
7101#define M_FW_PORT_CMD_FORCE_PINFO	0x1
7102#define V_FW_PORT_CMD_FORCE_PINFO(x)	((x) << S_FW_PORT_CMD_FORCE_PINFO)
7103#define G_FW_PORT_CMD_FORCE_PINFO(x)	\
7104    (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7105#define F_FW_PORT_CMD_FORCE_PINFO	V_FW_PORT_CMD_FORCE_PINFO(1U)
7106
7107#define S_FW_PORT_CMD_LSTATUS		31
7108#define M_FW_PORT_CMD_LSTATUS		0x1
7109#define V_FW_PORT_CMD_LSTATUS(x)	((x) << S_FW_PORT_CMD_LSTATUS)
7110#define G_FW_PORT_CMD_LSTATUS(x)	\
7111    (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7112#define F_FW_PORT_CMD_LSTATUS		V_FW_PORT_CMD_LSTATUS(1U)
7113
7114#define S_FW_PORT_CMD_LSPEED		24
7115#define M_FW_PORT_CMD_LSPEED		0x3f
7116#define V_FW_PORT_CMD_LSPEED(x)		((x) << S_FW_PORT_CMD_LSPEED)
7117#define G_FW_PORT_CMD_LSPEED(x)		\
7118    (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7119
7120#define S_FW_PORT_CMD_TXPAUSE		23
7121#define M_FW_PORT_CMD_TXPAUSE		0x1
7122#define V_FW_PORT_CMD_TXPAUSE(x)	((x) << S_FW_PORT_CMD_TXPAUSE)
7123#define G_FW_PORT_CMD_TXPAUSE(x)	\
7124    (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7125#define F_FW_PORT_CMD_TXPAUSE		V_FW_PORT_CMD_TXPAUSE(1U)
7126
7127#define S_FW_PORT_CMD_RXPAUSE		22
7128#define M_FW_PORT_CMD_RXPAUSE		0x1
7129#define V_FW_PORT_CMD_RXPAUSE(x)	((x) << S_FW_PORT_CMD_RXPAUSE)
7130#define G_FW_PORT_CMD_RXPAUSE(x)	\
7131    (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7132#define F_FW_PORT_CMD_RXPAUSE		V_FW_PORT_CMD_RXPAUSE(1U)
7133
7134#define S_FW_PORT_CMD_MDIOCAP		21
7135#define M_FW_PORT_CMD_MDIOCAP		0x1
7136#define V_FW_PORT_CMD_MDIOCAP(x)	((x) << S_FW_PORT_CMD_MDIOCAP)
7137#define G_FW_PORT_CMD_MDIOCAP(x)	\
7138    (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7139#define F_FW_PORT_CMD_MDIOCAP		V_FW_PORT_CMD_MDIOCAP(1U)
7140
7141#define S_FW_PORT_CMD_MDIOADDR		16
7142#define M_FW_PORT_CMD_MDIOADDR		0x1f
7143#define V_FW_PORT_CMD_MDIOADDR(x)	((x) << S_FW_PORT_CMD_MDIOADDR)
7144#define G_FW_PORT_CMD_MDIOADDR(x)	\
7145    (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7146
7147#define S_FW_PORT_CMD_LPTXPAUSE		15
7148#define M_FW_PORT_CMD_LPTXPAUSE		0x1
7149#define V_FW_PORT_CMD_LPTXPAUSE(x)	((x) << S_FW_PORT_CMD_LPTXPAUSE)
7150#define G_FW_PORT_CMD_LPTXPAUSE(x)	\
7151    (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7152#define F_FW_PORT_CMD_LPTXPAUSE		V_FW_PORT_CMD_LPTXPAUSE(1U)
7153
7154#define S_FW_PORT_CMD_LPRXPAUSE		14
7155#define M_FW_PORT_CMD_LPRXPAUSE		0x1
7156#define V_FW_PORT_CMD_LPRXPAUSE(x)	((x) << S_FW_PORT_CMD_LPRXPAUSE)
7157#define G_FW_PORT_CMD_LPRXPAUSE(x)	\
7158    (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7159#define F_FW_PORT_CMD_LPRXPAUSE		V_FW_PORT_CMD_LPRXPAUSE(1U)
7160
7161#define S_FW_PORT_CMD_PTYPE		8
7162#define M_FW_PORT_CMD_PTYPE		0x1f
7163#define V_FW_PORT_CMD_PTYPE(x)		((x) << S_FW_PORT_CMD_PTYPE)
7164#define G_FW_PORT_CMD_PTYPE(x)		\
7165    (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7166
7167#define S_FW_PORT_CMD_LINKDNRC		5
7168#define M_FW_PORT_CMD_LINKDNRC		0x7
7169#define V_FW_PORT_CMD_LINKDNRC(x)	((x) << S_FW_PORT_CMD_LINKDNRC)
7170#define G_FW_PORT_CMD_LINKDNRC(x)	\
7171    (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7172
7173#define S_FW_PORT_CMD_MODTYPE		0
7174#define M_FW_PORT_CMD_MODTYPE		0x1f
7175#define V_FW_PORT_CMD_MODTYPE(x)	((x) << S_FW_PORT_CMD_MODTYPE)
7176#define G_FW_PORT_CMD_MODTYPE(x)	\
7177    (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7178
7179#define S_FW_PORT_CMD_DCBXDIS		7
7180#define M_FW_PORT_CMD_DCBXDIS		0x1
7181#define V_FW_PORT_CMD_DCBXDIS(x)	((x) << S_FW_PORT_CMD_DCBXDIS)
7182#define G_FW_PORT_CMD_DCBXDIS(x)	\
7183    (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7184#define F_FW_PORT_CMD_DCBXDIS		V_FW_PORT_CMD_DCBXDIS(1U)
7185
7186#define S_FW_PORT_CMD_APPLY		7
7187#define M_FW_PORT_CMD_APPLY		0x1
7188#define V_FW_PORT_CMD_APPLY(x)		((x) << S_FW_PORT_CMD_APPLY)
7189#define G_FW_PORT_CMD_APPLY(x)		\
7190    (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7191#define F_FW_PORT_CMD_APPLY		V_FW_PORT_CMD_APPLY(1U)
7192
7193#define S_FW_PORT_CMD_ALL_SYNCD		7
7194#define M_FW_PORT_CMD_ALL_SYNCD		0x1
7195#define V_FW_PORT_CMD_ALL_SYNCD(x)	((x) << S_FW_PORT_CMD_ALL_SYNCD)
7196#define G_FW_PORT_CMD_ALL_SYNCD(x)	\
7197    (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7198#define F_FW_PORT_CMD_ALL_SYNCD		V_FW_PORT_CMD_ALL_SYNCD(1U)
7199
7200#define S_FW_PORT_CMD_DCB_VERSION	12
7201#define M_FW_PORT_CMD_DCB_VERSION	0x7
7202#define V_FW_PORT_CMD_DCB_VERSION(x)	((x) << S_FW_PORT_CMD_DCB_VERSION)
7203#define G_FW_PORT_CMD_DCB_VERSION(x)	\
7204    (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7205
7206#define S_FW_PORT_CMD_PFC_STATE		8
7207#define M_FW_PORT_CMD_PFC_STATE		0xf
7208#define V_FW_PORT_CMD_PFC_STATE(x)	((x) << S_FW_PORT_CMD_PFC_STATE)
7209#define G_FW_PORT_CMD_PFC_STATE(x)	\
7210    (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7211
7212#define S_FW_PORT_CMD_ETS_STATE		4
7213#define M_FW_PORT_CMD_ETS_STATE		0xf
7214#define V_FW_PORT_CMD_ETS_STATE(x)	((x) << S_FW_PORT_CMD_ETS_STATE)
7215#define G_FW_PORT_CMD_ETS_STATE(x)	\
7216    (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7217
7218#define S_FW_PORT_CMD_APP_STATE		0
7219#define M_FW_PORT_CMD_APP_STATE		0xf
7220#define V_FW_PORT_CMD_APP_STATE(x)	((x) << S_FW_PORT_CMD_APP_STATE)
7221#define G_FW_PORT_CMD_APP_STATE(x)	\
7222    (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7223
7224/*
7225 *	These are configured into the VPD and hence tools that generate
7226 *	VPD may use this enumeration.
7227 *	extPHY	#lanes	T4_I2C	extI2C	BP_Eq	BP_ANEG	Speed
7228 *
7229 *	REMEMBER:
7230 *	    Update the Common Code t4_hw.c:t4_get_port_type_description()
7231 *	    with any new Firmware Port Technology Types!
7232 */
7233enum fw_port_type {
7234	FW_PORT_TYPE_FIBER_XFI	=  0,	/* Y, 1, N, Y, N, N, 10G */
7235	FW_PORT_TYPE_FIBER_XAUI	=  1,	/* Y, 4, N, Y, N, N, 10G */
7236	FW_PORT_TYPE_BT_SGMII	=  2,	/* Y, 1, No, No, No, No, 1G/100M */
7237	FW_PORT_TYPE_BT_XFI	=  3,	/* Y, 1, No, No, No, No, 10G/1G/100M */
7238	FW_PORT_TYPE_BT_XAUI	=  4,	/* Y, 4, No, No, No, No, 10G/1G/100M */
7239	FW_PORT_TYPE_KX4	=  5,	/* No, 4, No, No, Yes, Yes, 10G */
7240	FW_PORT_TYPE_CX4	=  6,	/* No, 4, No, No, No, No, 10G */
7241	FW_PORT_TYPE_KX		=  7,	/* No, 1, No, No, Yes, No, 1G */
7242	FW_PORT_TYPE_KR		=  8,	/* No, 1, No, No, Yes, Yes, 10G */
7243	FW_PORT_TYPE_SFP	=  9,	/* No, 1, Yes, No, No, No, 10G */
7244	FW_PORT_TYPE_BP_AP	= 10,	/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7245	FW_PORT_TYPE_BP4_AP	= 11,	/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7246	FW_PORT_TYPE_QSFP_10G	= 12,	/* No, 1, Yes, No, No, No, 10G */
7247	FW_PORT_TYPE_QSA	= 13,	/* No, 1, Yes, No, No, No, 10G */
7248	FW_PORT_TYPE_QSFP	= 14,	/* No, 4, Yes, No, No, No, 40G */
7249	FW_PORT_TYPE_BP40_BA	= 15,	/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7250	FW_PORT_TYPE_KR4_100G	= 16,	/* No, 4, 100G, Backplane */
7251	FW_PORT_TYPE_CR4_QSFP	= 17,	/* No, 4, 100G */
7252	FW_PORT_TYPE_CR_QSFP	= 18,	/* No, 1, 25G Spider cable */
7253	FW_PORT_TYPE_CR2_QSFP	= 19,	/* No, 2, 50G */
7254	FW_PORT_TYPE_SFP28	= 20,	/* No, 1, 25G */
7255	FW_PORT_TYPE_KR_SFP28	= 21,	/* No, 1, 25G using Backplane */
7256	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7257};
7258
7259/* These are read from module's EEPROM and determined once the
7260   module is inserted. */
7261enum fw_port_module_type {
7262	FW_PORT_MOD_TYPE_NA		= 0x0,
7263	FW_PORT_MOD_TYPE_LR		= 0x1,
7264	FW_PORT_MOD_TYPE_SR		= 0x2,
7265	FW_PORT_MOD_TYPE_ER		= 0x3,
7266	FW_PORT_MOD_TYPE_TWINAX_PASSIVE	= 0x4,
7267	FW_PORT_MOD_TYPE_TWINAX_ACTIVE	= 0x5,
7268	FW_PORT_MOD_TYPE_LRM		= 0x6,
7269	FW_PORT_MOD_TYPE_ERROR		= M_FW_PORT_CMD_MODTYPE - 3,
7270	FW_PORT_MOD_TYPE_UNKNOWN	= M_FW_PORT_CMD_MODTYPE - 2,
7271	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
7272	FW_PORT_MOD_TYPE_NONE		= M_FW_PORT_CMD_MODTYPE
7273};
7274
7275/* used by FW and tools may use this to generate VPD */
7276enum fw_port_mod_sub_type {
7277	FW_PORT_MOD_SUB_TYPE_NA,
7278	FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7279	FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7280	FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7281	FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7282	FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7283	FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7284	FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7285	FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7286
7287	/*
7288	 * The following will never been in the VPD.  They are TWINAX cable
7289	 * lengths decoded from SFP+ module i2c PROMs.  These should almost
7290	 * certainly go somewhere else ...
7291	 */
7292	FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7293	FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7294	FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7295	FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7296};
7297
7298/* link down reason codes (3b) */
7299enum fw_port_link_dn_rc {
7300	FW_PORT_LINK_DN_RC_NONE,
7301	FW_PORT_LINK_DN_RC_REMFLT,	/* Remote fault detected */
7302	FW_PORT_LINK_DN_ANEG_F,		/* Auto-negotiation fault */
7303	FW_PORT_LINK_DN_RESERVED3,
7304	FW_PORT_LINK_DN_OVERHEAT,	/* Port overheated */
7305	FW_PORT_LINK_DN_UNKNOWN,	/* Unable to determine reason */
7306	FW_PORT_LINK_DN_RX_LOS,		/* No RX signal detected */
7307	FW_PORT_LINK_DN_RESERVED7
7308};
7309enum fw_port_stats_tx_index {
7310	FW_STAT_TX_PORT_BYTES_IX = 0,
7311	FW_STAT_TX_PORT_FRAMES_IX,
7312	FW_STAT_TX_PORT_BCAST_IX,
7313	FW_STAT_TX_PORT_MCAST_IX,
7314	FW_STAT_TX_PORT_UCAST_IX,
7315	FW_STAT_TX_PORT_ERROR_IX,
7316	FW_STAT_TX_PORT_64B_IX,
7317	FW_STAT_TX_PORT_65B_127B_IX,
7318	FW_STAT_TX_PORT_128B_255B_IX,
7319	FW_STAT_TX_PORT_256B_511B_IX,
7320	FW_STAT_TX_PORT_512B_1023B_IX,
7321	FW_STAT_TX_PORT_1024B_1518B_IX,
7322	FW_STAT_TX_PORT_1519B_MAX_IX,
7323	FW_STAT_TX_PORT_DROP_IX,
7324	FW_STAT_TX_PORT_PAUSE_IX,
7325	FW_STAT_TX_PORT_PPP0_IX,
7326	FW_STAT_TX_PORT_PPP1_IX,
7327	FW_STAT_TX_PORT_PPP2_IX,
7328	FW_STAT_TX_PORT_PPP3_IX,
7329	FW_STAT_TX_PORT_PPP4_IX,
7330	FW_STAT_TX_PORT_PPP5_IX,
7331	FW_STAT_TX_PORT_PPP6_IX,
7332	FW_STAT_TX_PORT_PPP7_IX,
7333	FW_NUM_PORT_TX_STATS
7334};
7335
7336enum fw_port_stat_rx_index {
7337	FW_STAT_RX_PORT_BYTES_IX = 0,
7338	FW_STAT_RX_PORT_FRAMES_IX,
7339	FW_STAT_RX_PORT_BCAST_IX,
7340	FW_STAT_RX_PORT_MCAST_IX,
7341	FW_STAT_RX_PORT_UCAST_IX,
7342	FW_STAT_RX_PORT_MTU_ERROR_IX,
7343	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7344	FW_STAT_RX_PORT_CRC_ERROR_IX,
7345	FW_STAT_RX_PORT_LEN_ERROR_IX,
7346	FW_STAT_RX_PORT_SYM_ERROR_IX,
7347	FW_STAT_RX_PORT_64B_IX,
7348	FW_STAT_RX_PORT_65B_127B_IX,
7349	FW_STAT_RX_PORT_128B_255B_IX,
7350	FW_STAT_RX_PORT_256B_511B_IX,
7351	FW_STAT_RX_PORT_512B_1023B_IX,
7352	FW_STAT_RX_PORT_1024B_1518B_IX,
7353	FW_STAT_RX_PORT_1519B_MAX_IX,
7354	FW_STAT_RX_PORT_PAUSE_IX,
7355	FW_STAT_RX_PORT_PPP0_IX,
7356	FW_STAT_RX_PORT_PPP1_IX,
7357	FW_STAT_RX_PORT_PPP2_IX,
7358	FW_STAT_RX_PORT_PPP3_IX,
7359	FW_STAT_RX_PORT_PPP4_IX,
7360	FW_STAT_RX_PORT_PPP5_IX,
7361	FW_STAT_RX_PORT_PPP6_IX,
7362	FW_STAT_RX_PORT_PPP7_IX,
7363	FW_STAT_RX_PORT_LESS_64B_IX,
7364        FW_STAT_RX_PORT_MAC_ERROR_IX,
7365        FW_NUM_PORT_RX_STATS
7366};
7367/* port stats */
7368#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7369                                 FW_NUM_PORT_RX_STATS)
7370
7371
7372struct fw_port_stats_cmd {
7373	__be32 op_to_portid;
7374	__be32 retval_len16;
7375	union fw_port_stats {
7376		struct fw_port_stats_ctl {
7377			__u8   nstats_bg_bm;
7378			__u8   tx_ix;
7379			__be16 r6;
7380			__be32 r7;
7381			__be64 stat0;
7382			__be64 stat1;
7383			__be64 stat2;
7384			__be64 stat3;
7385			__be64 stat4;
7386			__be64 stat5;
7387		} ctl;
7388		struct fw_port_stats_all {
7389			__be64 tx_bytes;
7390			__be64 tx_frames;
7391			__be64 tx_bcast;
7392			__be64 tx_mcast;
7393			__be64 tx_ucast;
7394			__be64 tx_error;
7395			__be64 tx_64b;
7396			__be64 tx_65b_127b;
7397			__be64 tx_128b_255b;
7398			__be64 tx_256b_511b;
7399			__be64 tx_512b_1023b;
7400			__be64 tx_1024b_1518b;
7401			__be64 tx_1519b_max;
7402			__be64 tx_drop;
7403			__be64 tx_pause;
7404			__be64 tx_ppp0;
7405			__be64 tx_ppp1;
7406			__be64 tx_ppp2;
7407			__be64 tx_ppp3;
7408			__be64 tx_ppp4;
7409			__be64 tx_ppp5;
7410			__be64 tx_ppp6;
7411			__be64 tx_ppp7;
7412			__be64 rx_bytes;
7413			__be64 rx_frames;
7414			__be64 rx_bcast;
7415			__be64 rx_mcast;
7416			__be64 rx_ucast;
7417			__be64 rx_mtu_error;
7418			__be64 rx_mtu_crc_error;
7419			__be64 rx_crc_error;
7420			__be64 rx_len_error;
7421			__be64 rx_sym_error;
7422			__be64 rx_64b;
7423			__be64 rx_65b_127b;
7424			__be64 rx_128b_255b;
7425			__be64 rx_256b_511b;
7426			__be64 rx_512b_1023b;
7427			__be64 rx_1024b_1518b;
7428			__be64 rx_1519b_max;
7429			__be64 rx_pause;
7430			__be64 rx_ppp0;
7431			__be64 rx_ppp1;
7432			__be64 rx_ppp2;
7433			__be64 rx_ppp3;
7434			__be64 rx_ppp4;
7435			__be64 rx_ppp5;
7436			__be64 rx_ppp6;
7437			__be64 rx_ppp7;
7438			__be64 rx_less_64b;
7439			__be64 rx_bg_drop;
7440			__be64 rx_bg_trunc;
7441		} all;
7442	} u;
7443};
7444
7445#define S_FW_PORT_STATS_CMD_NSTATS	4
7446#define M_FW_PORT_STATS_CMD_NSTATS	0x7
7447#define V_FW_PORT_STATS_CMD_NSTATS(x)	((x) << S_FW_PORT_STATS_CMD_NSTATS)
7448#define G_FW_PORT_STATS_CMD_NSTATS(x)	\
7449    (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
7450
7451#define S_FW_PORT_STATS_CMD_BG_BM	0
7452#define M_FW_PORT_STATS_CMD_BG_BM	0x3
7453#define V_FW_PORT_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_STATS_CMD_BG_BM)
7454#define G_FW_PORT_STATS_CMD_BG_BM(x)	\
7455    (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
7456
7457#define S_FW_PORT_STATS_CMD_TX		7
7458#define M_FW_PORT_STATS_CMD_TX		0x1
7459#define V_FW_PORT_STATS_CMD_TX(x)	((x) << S_FW_PORT_STATS_CMD_TX)
7460#define G_FW_PORT_STATS_CMD_TX(x)	\
7461    (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
7462#define F_FW_PORT_STATS_CMD_TX		V_FW_PORT_STATS_CMD_TX(1U)
7463
7464#define S_FW_PORT_STATS_CMD_IX		0
7465#define M_FW_PORT_STATS_CMD_IX		0x3f
7466#define V_FW_PORT_STATS_CMD_IX(x)	((x) << S_FW_PORT_STATS_CMD_IX)
7467#define G_FW_PORT_STATS_CMD_IX(x)	\
7468    (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
7469
7470/* port loopback stats */
7471#define FW_NUM_LB_STATS 14
7472enum fw_port_lb_stats_index {
7473	FW_STAT_LB_PORT_BYTES_IX,
7474	FW_STAT_LB_PORT_FRAMES_IX,
7475	FW_STAT_LB_PORT_BCAST_IX,
7476	FW_STAT_LB_PORT_MCAST_IX,
7477	FW_STAT_LB_PORT_UCAST_IX,
7478	FW_STAT_LB_PORT_ERROR_IX,
7479	FW_STAT_LB_PORT_64B_IX,
7480	FW_STAT_LB_PORT_65B_127B_IX,
7481	FW_STAT_LB_PORT_128B_255B_IX,
7482	FW_STAT_LB_PORT_256B_511B_IX,
7483	FW_STAT_LB_PORT_512B_1023B_IX,
7484	FW_STAT_LB_PORT_1024B_1518B_IX,
7485	FW_STAT_LB_PORT_1519B_MAX_IX,
7486	FW_STAT_LB_PORT_DROP_FRAMES_IX
7487};
7488
7489struct fw_port_lb_stats_cmd {
7490	__be32 op_to_lbport;
7491	__be32 retval_len16;
7492	union fw_port_lb_stats {
7493		struct fw_port_lb_stats_ctl {
7494			__u8   nstats_bg_bm;
7495			__u8   ix_pkd;
7496			__be16 r6;
7497			__be32 r7;
7498			__be64 stat0;
7499			__be64 stat1;
7500			__be64 stat2;
7501			__be64 stat3;
7502			__be64 stat4;
7503			__be64 stat5;
7504		} ctl;
7505		struct fw_port_lb_stats_all {
7506			__be64 tx_bytes;
7507			__be64 tx_frames;
7508			__be64 tx_bcast;
7509			__be64 tx_mcast;
7510			__be64 tx_ucast;
7511			__be64 tx_error;
7512			__be64 tx_64b;
7513			__be64 tx_65b_127b;
7514			__be64 tx_128b_255b;
7515			__be64 tx_256b_511b;
7516			__be64 tx_512b_1023b;
7517			__be64 tx_1024b_1518b;
7518			__be64 tx_1519b_max;
7519			__be64 rx_lb_drop;
7520			__be64 rx_lb_trunc;
7521		} all;
7522	} u;
7523};
7524
7525#define S_FW_PORT_LB_STATS_CMD_LBPORT	0
7526#define M_FW_PORT_LB_STATS_CMD_LBPORT	0xf
7527#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7528    ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
7529#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7530    (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
7531
7532#define S_FW_PORT_LB_STATS_CMD_NSTATS	4
7533#define M_FW_PORT_LB_STATS_CMD_NSTATS	0x7
7534#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7535    ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
7536#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7537    (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
7538
7539#define S_FW_PORT_LB_STATS_CMD_BG_BM	0
7540#define M_FW_PORT_LB_STATS_CMD_BG_BM	0x3
7541#define V_FW_PORT_LB_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
7542#define G_FW_PORT_LB_STATS_CMD_BG_BM(x)	\
7543    (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
7544
7545#define S_FW_PORT_LB_STATS_CMD_IX	0
7546#define M_FW_PORT_LB_STATS_CMD_IX	0xf
7547#define V_FW_PORT_LB_STATS_CMD_IX(x)	((x) << S_FW_PORT_LB_STATS_CMD_IX)
7548#define G_FW_PORT_LB_STATS_CMD_IX(x)	\
7549    (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
7550
7551/* Trace related defines */
7552#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
7553#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE  2560
7554
7555struct fw_port_trace_cmd {
7556	__be32 op_to_portid;
7557	__be32 retval_len16;
7558	__be16 traceen_to_pciech;
7559	__be16 qnum;
7560	__be32 r5;
7561};
7562
7563#define S_FW_PORT_TRACE_CMD_PORTID	0
7564#define M_FW_PORT_TRACE_CMD_PORTID	0xf
7565#define V_FW_PORT_TRACE_CMD_PORTID(x)	((x) << S_FW_PORT_TRACE_CMD_PORTID)
7566#define G_FW_PORT_TRACE_CMD_PORTID(x)	\
7567    (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
7568
7569#define S_FW_PORT_TRACE_CMD_TRACEEN	15
7570#define M_FW_PORT_TRACE_CMD_TRACEEN	0x1
7571#define V_FW_PORT_TRACE_CMD_TRACEEN(x)	((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
7572#define G_FW_PORT_TRACE_CMD_TRACEEN(x)	\
7573    (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
7574#define F_FW_PORT_TRACE_CMD_TRACEEN	V_FW_PORT_TRACE_CMD_TRACEEN(1U)
7575
7576#define S_FW_PORT_TRACE_CMD_FLTMODE	14
7577#define M_FW_PORT_TRACE_CMD_FLTMODE	0x1
7578#define V_FW_PORT_TRACE_CMD_FLTMODE(x)	((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
7579#define G_FW_PORT_TRACE_CMD_FLTMODE(x)	\
7580    (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
7581#define F_FW_PORT_TRACE_CMD_FLTMODE	V_FW_PORT_TRACE_CMD_FLTMODE(1U)
7582
7583#define S_FW_PORT_TRACE_CMD_DUPLEN	13
7584#define M_FW_PORT_TRACE_CMD_DUPLEN	0x1
7585#define V_FW_PORT_TRACE_CMD_DUPLEN(x)	((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
7586#define G_FW_PORT_TRACE_CMD_DUPLEN(x)	\
7587    (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
7588#define F_FW_PORT_TRACE_CMD_DUPLEN	V_FW_PORT_TRACE_CMD_DUPLEN(1U)
7589
7590#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE	8
7591#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE	0x1f
7592#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7593    ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7594#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7595    (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
7596     M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7597
7598#define S_FW_PORT_TRACE_CMD_PCIECH	6
7599#define M_FW_PORT_TRACE_CMD_PCIECH	0x3
7600#define V_FW_PORT_TRACE_CMD_PCIECH(x)	((x) << S_FW_PORT_TRACE_CMD_PCIECH)
7601#define G_FW_PORT_TRACE_CMD_PCIECH(x)	\
7602    (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
7603
7604struct fw_port_trace_mmap_cmd {
7605	__be32 op_to_portid;
7606	__be32 retval_len16;
7607	__be32 fid_to_skipoffset;
7608	__be32 minpktsize_capturemax;
7609	__u8   map[224];
7610};
7611
7612#define S_FW_PORT_TRACE_MMAP_CMD_PORTID	0
7613#define M_FW_PORT_TRACE_MMAP_CMD_PORTID	0xf
7614#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7615    ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
7616#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7617    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
7618     M_FW_PORT_TRACE_MMAP_CMD_PORTID)
7619
7620#define S_FW_PORT_TRACE_MMAP_CMD_FID	30
7621#define M_FW_PORT_TRACE_MMAP_CMD_FID	0x3
7622#define V_FW_PORT_TRACE_MMAP_CMD_FID(x)	((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
7623#define G_FW_PORT_TRACE_MMAP_CMD_FID(x)	\
7624    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
7625
7626#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN	29
7627#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN	0x1
7628#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7629    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7630#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7631    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
7632     M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7633#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
7634
7635#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
7636#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
7637#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7638    ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7639#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7640    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
7641     M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7642#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
7643
7644#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
7645#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
7646#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7647    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7648#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7649    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
7650     M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7651
7652#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
7653#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
7654#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7655    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7656#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7657    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
7658     M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7659
7660#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
7661#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
7662#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7663    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7664#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7665    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
7666     M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7667
7668#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
7669#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
7670#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7671    ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7672#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7673    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
7674     M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7675
7676enum fw_ptp_subop {
7677
7678	/* none */
7679	FW_PTP_SC_INIT_TIMER		= 0x00,
7680	FW_PTP_SC_TX_TYPE		= 0x01,
7681
7682	/* init */
7683	FW_PTP_SC_RXTIME_STAMP		= 0x08,
7684	FW_PTP_SC_RDRX_TYPE		= 0x09,
7685
7686	/* ts */
7687	FW_PTP_SC_ADJ_FREQ		= 0x10,
7688	FW_PTP_SC_ADJ_TIME		= 0x11,
7689	FW_PTP_SC_ADJ_FTIME		= 0x12,
7690	FW_PTP_SC_WALL_CLOCK		= 0x13,
7691	FW_PTP_SC_GET_TIME		= 0x14,
7692	FW_PTP_SC_SET_TIME		= 0x15,
7693};
7694
7695struct fw_ptp_cmd {
7696	__be32 op_to_portid;
7697	__be32 retval_len16;
7698	union fw_ptp {
7699		struct fw_ptp_sc {
7700			__u8   sc;
7701			__u8   r3[7];
7702		} scmd;
7703		struct fw_ptp_init {
7704			__u8   sc;
7705			__u8   txchan;
7706			__be16 absid;
7707			__be16 mode;
7708			__be16 r3;
7709		} init;
7710		struct fw_ptp_ts {
7711			__u8   sc;
7712			__u8   sign;
7713			__be16 r3;
7714			__be32 ppb;
7715			__be64 tm;
7716		} ts;
7717	} u;
7718	__be64 r3;
7719};
7720
7721#define S_FW_PTP_CMD_PORTID		0
7722#define M_FW_PTP_CMD_PORTID		0xf
7723#define V_FW_PTP_CMD_PORTID(x)		((x) << S_FW_PTP_CMD_PORTID)
7724#define G_FW_PTP_CMD_PORTID(x)		\
7725    (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
7726
7727struct fw_rss_ind_tbl_cmd {
7728	__be32 op_to_viid;
7729	__be32 retval_len16;
7730	__be16 niqid;
7731	__be16 startidx;
7732	__be32 r3;
7733	__be32 iq0_to_iq2;
7734	__be32 iq3_to_iq5;
7735	__be32 iq6_to_iq8;
7736	__be32 iq9_to_iq11;
7737	__be32 iq12_to_iq14;
7738	__be32 iq15_to_iq17;
7739	__be32 iq18_to_iq20;
7740	__be32 iq21_to_iq23;
7741	__be32 iq24_to_iq26;
7742	__be32 iq27_to_iq29;
7743	__be32 iq30_iq31;
7744	__be32 r15_lo;
7745};
7746
7747#define S_FW_RSS_IND_TBL_CMD_VIID	0
7748#define M_FW_RSS_IND_TBL_CMD_VIID	0xfff
7749#define V_FW_RSS_IND_TBL_CMD_VIID(x)	((x) << S_FW_RSS_IND_TBL_CMD_VIID)
7750#define G_FW_RSS_IND_TBL_CMD_VIID(x)	\
7751    (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
7752
7753#define S_FW_RSS_IND_TBL_CMD_IQ0	20
7754#define M_FW_RSS_IND_TBL_CMD_IQ0	0x3ff
7755#define V_FW_RSS_IND_TBL_CMD_IQ0(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
7756#define G_FW_RSS_IND_TBL_CMD_IQ0(x)	\
7757    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
7758
7759#define S_FW_RSS_IND_TBL_CMD_IQ1	10
7760#define M_FW_RSS_IND_TBL_CMD_IQ1	0x3ff
7761#define V_FW_RSS_IND_TBL_CMD_IQ1(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
7762#define G_FW_RSS_IND_TBL_CMD_IQ1(x)	\
7763    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
7764
7765#define S_FW_RSS_IND_TBL_CMD_IQ2	0
7766#define M_FW_RSS_IND_TBL_CMD_IQ2	0x3ff
7767#define V_FW_RSS_IND_TBL_CMD_IQ2(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
7768#define G_FW_RSS_IND_TBL_CMD_IQ2(x)	\
7769    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
7770
7771#define S_FW_RSS_IND_TBL_CMD_IQ3	20
7772#define M_FW_RSS_IND_TBL_CMD_IQ3	0x3ff
7773#define V_FW_RSS_IND_TBL_CMD_IQ3(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
7774#define G_FW_RSS_IND_TBL_CMD_IQ3(x)	\
7775    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
7776
7777#define S_FW_RSS_IND_TBL_CMD_IQ4	10
7778#define M_FW_RSS_IND_TBL_CMD_IQ4	0x3ff
7779#define V_FW_RSS_IND_TBL_CMD_IQ4(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
7780#define G_FW_RSS_IND_TBL_CMD_IQ4(x)	\
7781    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
7782
7783#define S_FW_RSS_IND_TBL_CMD_IQ5	0
7784#define M_FW_RSS_IND_TBL_CMD_IQ5	0x3ff
7785#define V_FW_RSS_IND_TBL_CMD_IQ5(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
7786#define G_FW_RSS_IND_TBL_CMD_IQ5(x)	\
7787    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
7788
7789#define S_FW_RSS_IND_TBL_CMD_IQ6	20
7790#define M_FW_RSS_IND_TBL_CMD_IQ6	0x3ff
7791#define V_FW_RSS_IND_TBL_CMD_IQ6(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
7792#define G_FW_RSS_IND_TBL_CMD_IQ6(x)	\
7793    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
7794
7795#define S_FW_RSS_IND_TBL_CMD_IQ7	10
7796#define M_FW_RSS_IND_TBL_CMD_IQ7	0x3ff
7797#define V_FW_RSS_IND_TBL_CMD_IQ7(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
7798#define G_FW_RSS_IND_TBL_CMD_IQ7(x)	\
7799    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
7800
7801#define S_FW_RSS_IND_TBL_CMD_IQ8	0
7802#define M_FW_RSS_IND_TBL_CMD_IQ8	0x3ff
7803#define V_FW_RSS_IND_TBL_CMD_IQ8(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
7804#define G_FW_RSS_IND_TBL_CMD_IQ8(x)	\
7805    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
7806
7807#define S_FW_RSS_IND_TBL_CMD_IQ9	20
7808#define M_FW_RSS_IND_TBL_CMD_IQ9	0x3ff
7809#define V_FW_RSS_IND_TBL_CMD_IQ9(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
7810#define G_FW_RSS_IND_TBL_CMD_IQ9(x)	\
7811    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
7812
7813#define S_FW_RSS_IND_TBL_CMD_IQ10	10
7814#define M_FW_RSS_IND_TBL_CMD_IQ10	0x3ff
7815#define V_FW_RSS_IND_TBL_CMD_IQ10(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
7816#define G_FW_RSS_IND_TBL_CMD_IQ10(x)	\
7817    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
7818
7819#define S_FW_RSS_IND_TBL_CMD_IQ11	0
7820#define M_FW_RSS_IND_TBL_CMD_IQ11	0x3ff
7821#define V_FW_RSS_IND_TBL_CMD_IQ11(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
7822#define G_FW_RSS_IND_TBL_CMD_IQ11(x)	\
7823    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
7824
7825#define S_FW_RSS_IND_TBL_CMD_IQ12	20
7826#define M_FW_RSS_IND_TBL_CMD_IQ12	0x3ff
7827#define V_FW_RSS_IND_TBL_CMD_IQ12(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
7828#define G_FW_RSS_IND_TBL_CMD_IQ12(x)	\
7829    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
7830
7831#define S_FW_RSS_IND_TBL_CMD_IQ13	10
7832#define M_FW_RSS_IND_TBL_CMD_IQ13	0x3ff
7833#define V_FW_RSS_IND_TBL_CMD_IQ13(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
7834#define G_FW_RSS_IND_TBL_CMD_IQ13(x)	\
7835    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
7836
7837#define S_FW_RSS_IND_TBL_CMD_IQ14	0
7838#define M_FW_RSS_IND_TBL_CMD_IQ14	0x3ff
7839#define V_FW_RSS_IND_TBL_CMD_IQ14(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
7840#define G_FW_RSS_IND_TBL_CMD_IQ14(x)	\
7841    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
7842
7843#define S_FW_RSS_IND_TBL_CMD_IQ15	20
7844#define M_FW_RSS_IND_TBL_CMD_IQ15	0x3ff
7845#define V_FW_RSS_IND_TBL_CMD_IQ15(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
7846#define G_FW_RSS_IND_TBL_CMD_IQ15(x)	\
7847    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
7848
7849#define S_FW_RSS_IND_TBL_CMD_IQ16	10
7850#define M_FW_RSS_IND_TBL_CMD_IQ16	0x3ff
7851#define V_FW_RSS_IND_TBL_CMD_IQ16(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
7852#define G_FW_RSS_IND_TBL_CMD_IQ16(x)	\
7853    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
7854
7855#define S_FW_RSS_IND_TBL_CMD_IQ17	0
7856#define M_FW_RSS_IND_TBL_CMD_IQ17	0x3ff
7857#define V_FW_RSS_IND_TBL_CMD_IQ17(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
7858#define G_FW_RSS_IND_TBL_CMD_IQ17(x)	\
7859    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
7860
7861#define S_FW_RSS_IND_TBL_CMD_IQ18	20
7862#define M_FW_RSS_IND_TBL_CMD_IQ18	0x3ff
7863#define V_FW_RSS_IND_TBL_CMD_IQ18(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
7864#define G_FW_RSS_IND_TBL_CMD_IQ18(x)	\
7865    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
7866
7867#define S_FW_RSS_IND_TBL_CMD_IQ19	10
7868#define M_FW_RSS_IND_TBL_CMD_IQ19	0x3ff
7869#define V_FW_RSS_IND_TBL_CMD_IQ19(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
7870#define G_FW_RSS_IND_TBL_CMD_IQ19(x)	\
7871    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
7872
7873#define S_FW_RSS_IND_TBL_CMD_IQ20	0
7874#define M_FW_RSS_IND_TBL_CMD_IQ20	0x3ff
7875#define V_FW_RSS_IND_TBL_CMD_IQ20(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
7876#define G_FW_RSS_IND_TBL_CMD_IQ20(x)	\
7877    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
7878
7879#define S_FW_RSS_IND_TBL_CMD_IQ21	20
7880#define M_FW_RSS_IND_TBL_CMD_IQ21	0x3ff
7881#define V_FW_RSS_IND_TBL_CMD_IQ21(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
7882#define G_FW_RSS_IND_TBL_CMD_IQ21(x)	\
7883    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
7884
7885#define S_FW_RSS_IND_TBL_CMD_IQ22	10
7886#define M_FW_RSS_IND_TBL_CMD_IQ22	0x3ff
7887#define V_FW_RSS_IND_TBL_CMD_IQ22(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
7888#define G_FW_RSS_IND_TBL_CMD_IQ22(x)	\
7889    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
7890
7891#define S_FW_RSS_IND_TBL_CMD_IQ23	0
7892#define M_FW_RSS_IND_TBL_CMD_IQ23	0x3ff
7893#define V_FW_RSS_IND_TBL_CMD_IQ23(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
7894#define G_FW_RSS_IND_TBL_CMD_IQ23(x)	\
7895    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
7896
7897#define S_FW_RSS_IND_TBL_CMD_IQ24	20
7898#define M_FW_RSS_IND_TBL_CMD_IQ24	0x3ff
7899#define V_FW_RSS_IND_TBL_CMD_IQ24(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
7900#define G_FW_RSS_IND_TBL_CMD_IQ24(x)	\
7901    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
7902
7903#define S_FW_RSS_IND_TBL_CMD_IQ25	10
7904#define M_FW_RSS_IND_TBL_CMD_IQ25	0x3ff
7905#define V_FW_RSS_IND_TBL_CMD_IQ25(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
7906#define G_FW_RSS_IND_TBL_CMD_IQ25(x)	\
7907    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
7908
7909#define S_FW_RSS_IND_TBL_CMD_IQ26	0
7910#define M_FW_RSS_IND_TBL_CMD_IQ26	0x3ff
7911#define V_FW_RSS_IND_TBL_CMD_IQ26(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
7912#define G_FW_RSS_IND_TBL_CMD_IQ26(x)	\
7913    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
7914
7915#define S_FW_RSS_IND_TBL_CMD_IQ27	20
7916#define M_FW_RSS_IND_TBL_CMD_IQ27	0x3ff
7917#define V_FW_RSS_IND_TBL_CMD_IQ27(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
7918#define G_FW_RSS_IND_TBL_CMD_IQ27(x)	\
7919    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
7920
7921#define S_FW_RSS_IND_TBL_CMD_IQ28	10
7922#define M_FW_RSS_IND_TBL_CMD_IQ28	0x3ff
7923#define V_FW_RSS_IND_TBL_CMD_IQ28(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
7924#define G_FW_RSS_IND_TBL_CMD_IQ28(x)	\
7925    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
7926
7927#define S_FW_RSS_IND_TBL_CMD_IQ29	0
7928#define M_FW_RSS_IND_TBL_CMD_IQ29	0x3ff
7929#define V_FW_RSS_IND_TBL_CMD_IQ29(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
7930#define G_FW_RSS_IND_TBL_CMD_IQ29(x)	\
7931    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
7932
7933#define S_FW_RSS_IND_TBL_CMD_IQ30	20
7934#define M_FW_RSS_IND_TBL_CMD_IQ30	0x3ff
7935#define V_FW_RSS_IND_TBL_CMD_IQ30(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
7936#define G_FW_RSS_IND_TBL_CMD_IQ30(x)	\
7937    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
7938
7939#define S_FW_RSS_IND_TBL_CMD_IQ31	10
7940#define M_FW_RSS_IND_TBL_CMD_IQ31	0x3ff
7941#define V_FW_RSS_IND_TBL_CMD_IQ31(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
7942#define G_FW_RSS_IND_TBL_CMD_IQ31(x)	\
7943    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
7944
7945struct fw_rss_glb_config_cmd {
7946	__be32 op_to_write;
7947	__be32 retval_len16;
7948	union fw_rss_glb_config {
7949		struct fw_rss_glb_config_manual {
7950			__be32 mode_pkd;
7951			__be32 r3;
7952			__be64 r4;
7953			__be64 r5;
7954		} manual;
7955		struct fw_rss_glb_config_basicvirtual {
7956			__be32 mode_keymode;
7957			__be32 synmapen_to_hashtoeplitz;
7958			__be64 r8;
7959			__be64 r9;
7960		} basicvirtual;
7961	} u;
7962};
7963
7964#define S_FW_RSS_GLB_CONFIG_CMD_MODE	28
7965#define M_FW_RSS_GLB_CONFIG_CMD_MODE	0xf
7966#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
7967#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x)	\
7968    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
7969
7970#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
7971#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
7972#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
7973
7974#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE	26
7975#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE	0x3
7976#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
7977    ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
7978#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
7979    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
7980     M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
7981
7982#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY	0
7983#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY	1
7984#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY	2
7985#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY	3
7986
7987#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
7988#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
7989#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
7990    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
7991#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
7992    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
7993     M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
7994#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
7995
7996#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
7997#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
7998#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
7999    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8000#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8001    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8002     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8003#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8004    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8005
8006#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8007#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8008#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8009    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8010#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8011    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8012     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8013#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8014    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8015
8016#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8017#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8018#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8019    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8020#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8021    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8022     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8023#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8024    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8025
8026#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8027#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8028#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8029    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8030#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8031    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8032     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8033#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8034    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8035
8036#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8037#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8038#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8039    ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8040#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8041    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8042     M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8043#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8044
8045#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8046#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8047#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8048    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8049#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8050    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8051     M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8052#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8053
8054#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8055#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8056#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8057    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8058#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8059    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8060     M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8061#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8062    V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8063
8064#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8065#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8066#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8067    ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8068#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8069    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8070     M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8071#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8072    V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8073
8074struct fw_rss_vi_config_cmd {
8075	__be32 op_to_viid;
8076	__be32 retval_len16;
8077	union fw_rss_vi_config {
8078		struct fw_rss_vi_config_manual {
8079			__be64 r3;
8080			__be64 r4;
8081			__be64 r5;
8082		} manual;
8083		struct fw_rss_vi_config_basicvirtual {
8084			__be32 r6;
8085			__be32 defaultq_to_udpen;
8086			__be32 secretkeyidx_pkd;
8087			__be32 secretkeyxor;
8088			__be64 r10;
8089		} basicvirtual;
8090	} u;
8091};
8092
8093#define S_FW_RSS_VI_CONFIG_CMD_VIID	0
8094#define M_FW_RSS_VI_CONFIG_CMD_VIID	0xfff
8095#define V_FW_RSS_VI_CONFIG_CMD_VIID(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8096#define G_FW_RSS_VI_CONFIG_CMD_VIID(x)	\
8097    (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8098
8099#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ	16
8100#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ	0x3ff
8101#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8102    ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8103#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8104    (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8105     M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8106
8107#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8108#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8109#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8110    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8111#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8112    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8113     M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8114#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8115    V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8116
8117#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8118#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8119#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8120    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8121#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8122    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8123     M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8124#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8125    V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8126
8127#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8128#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8129#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8130    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8131#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8132    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8133     M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8134#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8135    V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8136
8137#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8138#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8139#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8140    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8141#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8142    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8143     M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8144#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8145    V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8146
8147#define S_FW_RSS_VI_CONFIG_CMD_UDPEN	0
8148#define M_FW_RSS_VI_CONFIG_CMD_UDPEN	0x1
8149#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8150#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
8151    (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8152#define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8153
8154#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8155#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8156#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8157    ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8158#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8159    (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8160     M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8161
8162enum fw_sched_sc {
8163	FW_SCHED_SC_CONFIG		= 0,
8164	FW_SCHED_SC_PARAMS		= 1,
8165};
8166
8167enum fw_sched_type {
8168	FW_SCHED_TYPE_PKTSCHED	        = 0,
8169	FW_SCHED_TYPE_STREAMSCHED       = 1,
8170};
8171
8172enum fw_sched_params_level {
8173	FW_SCHED_PARAMS_LEVEL_CL_RL	= 0,
8174	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
8175	FW_SCHED_PARAMS_LEVEL_CH_RL	= 2,
8176};
8177
8178enum fw_sched_params_mode {
8179	FW_SCHED_PARAMS_MODE_CLASS	= 0,
8180	FW_SCHED_PARAMS_MODE_FLOW	= 1,
8181};
8182
8183enum fw_sched_params_unit {
8184	FW_SCHED_PARAMS_UNIT_BITRATE	= 0,
8185	FW_SCHED_PARAMS_UNIT_PKTRATE	= 1,
8186};
8187
8188enum fw_sched_params_rate {
8189	FW_SCHED_PARAMS_RATE_REL	= 0,
8190	FW_SCHED_PARAMS_RATE_ABS	= 1,
8191};
8192
8193struct fw_sched_cmd {
8194	__be32 op_to_write;
8195	__be32 retval_len16;
8196	union fw_sched {
8197		struct fw_sched_config {
8198			__u8   sc;
8199			__u8   type;
8200			__u8   minmaxen;
8201			__u8   r3[5];
8202			__u8   nclasses[4];
8203			__be32 r4;
8204		} config;
8205		struct fw_sched_params {
8206			__u8   sc;
8207			__u8   type;
8208			__u8   level;
8209			__u8   mode;
8210			__u8   unit;
8211			__u8   rate;
8212			__u8   ch;
8213			__u8   cl;
8214			__be32 min;
8215			__be32 max;
8216			__be16 weight;
8217			__be16 pktsize;
8218			__be16 burstsize;
8219			__be16 r4;
8220		} params;
8221	} u;
8222};
8223
8224/*
8225 *	length of the formatting string
8226 */
8227#define FW_DEVLOG_FMT_LEN	192
8228
8229/*
8230 *	maximum number of the formatting string parameters
8231 */
8232#define FW_DEVLOG_FMT_PARAMS_NUM 8
8233
8234/*
8235 *	priority levels
8236 */
8237enum fw_devlog_level {
8238	FW_DEVLOG_LEVEL_EMERG	= 0x0,
8239	FW_DEVLOG_LEVEL_CRIT	= 0x1,
8240	FW_DEVLOG_LEVEL_ERR	= 0x2,
8241	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
8242	FW_DEVLOG_LEVEL_INFO	= 0x4,
8243	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
8244	FW_DEVLOG_LEVEL_MAX	= 0x5,
8245};
8246
8247/*
8248 *	facilities that may send a log message
8249 */
8250enum fw_devlog_facility {
8251	FW_DEVLOG_FACILITY_CORE		= 0x00,
8252	FW_DEVLOG_FACILITY_CF		= 0x01,
8253	FW_DEVLOG_FACILITY_SCHED	= 0x02,
8254	FW_DEVLOG_FACILITY_TIMER	= 0x04,
8255	FW_DEVLOG_FACILITY_RES		= 0x06,
8256	FW_DEVLOG_FACILITY_HW		= 0x08,
8257	FW_DEVLOG_FACILITY_FLR		= 0x10,
8258	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
8259	FW_DEVLOG_FACILITY_PHY		= 0x14,
8260	FW_DEVLOG_FACILITY_MAC		= 0x16,
8261	FW_DEVLOG_FACILITY_PORT		= 0x18,
8262	FW_DEVLOG_FACILITY_VI		= 0x1A,
8263	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
8264	FW_DEVLOG_FACILITY_ACL		= 0x1E,
8265	FW_DEVLOG_FACILITY_TM		= 0x20,
8266	FW_DEVLOG_FACILITY_QFC		= 0x22,
8267	FW_DEVLOG_FACILITY_DCB		= 0x24,
8268	FW_DEVLOG_FACILITY_ETH		= 0x26,
8269	FW_DEVLOG_FACILITY_OFLD		= 0x28,
8270	FW_DEVLOG_FACILITY_RI		= 0x2A,
8271	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
8272	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
8273	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
8274	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
8275	FW_DEVLOG_FACILITY_CHNET	= 0x34,
8276	FW_DEVLOG_FACILITY_COiSCSI	= 0x36,
8277	FW_DEVLOG_FACILITY_MAX		= 0x38,
8278};
8279
8280/*
8281 *	log message format
8282 */
8283struct fw_devlog_e {
8284	__be64	timestamp;
8285	__be32	seqno;
8286	__be16	reserved1;
8287	__u8	level;
8288	__u8	facility;
8289	__u8	fmt[FW_DEVLOG_FMT_LEN];
8290	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
8291	__be32	reserved3[4];
8292};
8293
8294struct fw_devlog_cmd {
8295	__be32 op_to_write;
8296	__be32 retval_len16;
8297	__u8   level;
8298	__u8   r2[7];
8299	__be32 memtype_devlog_memaddr16_devlog;
8300	__be32 memsize_devlog;
8301	__be32 r3[2];
8302};
8303
8304#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG	28
8305#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG	0xf
8306#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8307    ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8308#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8309    (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8310
8311#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8312#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8313#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8314    ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8315#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8316    (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8317     M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8318
8319enum fw_watchdog_actions {
8320	FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8321	FW_WATCHDOG_ACTION_FLR = 1,
8322	FW_WATCHDOG_ACTION_BYPASS = 2,
8323	FW_WATCHDOG_ACTION_TMPCHK = 3,
8324	FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8325
8326	FW_WATCHDOG_ACTION_MAX = 5,
8327};
8328
8329#define FW_WATCHDOG_MAX_TIMEOUT_SECS	60
8330
8331struct fw_watchdog_cmd {
8332	__be32 op_to_vfn;
8333	__be32 retval_len16;
8334	__be32 timeout;
8335	__be32 action;
8336};
8337
8338#define S_FW_WATCHDOG_CMD_PFN		8
8339#define M_FW_WATCHDOG_CMD_PFN		0x7
8340#define V_FW_WATCHDOG_CMD_PFN(x)	((x) << S_FW_WATCHDOG_CMD_PFN)
8341#define G_FW_WATCHDOG_CMD_PFN(x)	\
8342    (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8343
8344#define S_FW_WATCHDOG_CMD_VFN		0
8345#define M_FW_WATCHDOG_CMD_VFN		0xff
8346#define V_FW_WATCHDOG_CMD_VFN(x)	((x) << S_FW_WATCHDOG_CMD_VFN)
8347#define G_FW_WATCHDOG_CMD_VFN(x)	\
8348    (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8349
8350struct fw_clip_cmd {
8351	__be32 op_to_write;
8352	__be32 alloc_to_len16;
8353	__be64 ip_hi;
8354	__be64 ip_lo;
8355	__be32 r4[2];
8356};
8357
8358#define S_FW_CLIP_CMD_ALLOC		31
8359#define M_FW_CLIP_CMD_ALLOC		0x1
8360#define V_FW_CLIP_CMD_ALLOC(x)		((x) << S_FW_CLIP_CMD_ALLOC)
8361#define G_FW_CLIP_CMD_ALLOC(x)		\
8362    (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8363#define F_FW_CLIP_CMD_ALLOC		V_FW_CLIP_CMD_ALLOC(1U)
8364
8365#define S_FW_CLIP_CMD_FREE		30
8366#define M_FW_CLIP_CMD_FREE		0x1
8367#define V_FW_CLIP_CMD_FREE(x)		((x) << S_FW_CLIP_CMD_FREE)
8368#define G_FW_CLIP_CMD_FREE(x)		\
8369    (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8370#define F_FW_CLIP_CMD_FREE		V_FW_CLIP_CMD_FREE(1U)
8371
8372/******************************************************************************
8373 *   F O i S C S I   C O M M A N D s
8374 **************************************/
8375
8376#define	FW_CHNET_IFACE_ADDR_MAX	3
8377
8378enum fw_chnet_iface_cmd_subop {
8379	FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8380
8381	FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8382	FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8383
8384	FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8385	FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8386
8387	FW_CHNET_IFACE_CMD_SUBOP_MAX,
8388};
8389
8390struct fw_chnet_iface_cmd {
8391	__be32 op_to_portid;
8392	__be32 retval_len16;
8393	__u8   subop;
8394	__u8   r2[3];
8395	__be32 ifid_ifstate;
8396	__be16 mtu;
8397	__be16 vlanid;
8398	__be32 r3;
8399	__be16 r4;
8400	__u8   mac[6];
8401};
8402
8403#define S_FW_CHNET_IFACE_CMD_PORTID	0
8404#define M_FW_CHNET_IFACE_CMD_PORTID	0xf
8405#define V_FW_CHNET_IFACE_CMD_PORTID(x)	((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8406#define G_FW_CHNET_IFACE_CMD_PORTID(x)	\
8407    (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8408
8409#define S_FW_CHNET_IFACE_CMD_IFID	8
8410#define M_FW_CHNET_IFACE_CMD_IFID	0xffffff
8411#define V_FW_CHNET_IFACE_CMD_IFID(x)	((x) << S_FW_CHNET_IFACE_CMD_IFID)
8412#define G_FW_CHNET_IFACE_CMD_IFID(x)	\
8413    (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
8414
8415#define S_FW_CHNET_IFACE_CMD_IFSTATE	0
8416#define M_FW_CHNET_IFACE_CMD_IFSTATE	0xff
8417#define V_FW_CHNET_IFACE_CMD_IFSTATE(x)	((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
8418#define G_FW_CHNET_IFACE_CMD_IFSTATE(x)	\
8419    (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
8420
8421struct fw_fcoe_res_info_cmd {
8422	__be32 op_to_read;
8423	__be32 retval_len16;
8424	__be16 e_d_tov;
8425	__be16 r_a_tov_seq;
8426	__be16 r_a_tov_els;
8427	__be16 r_r_tov;
8428	__be32 max_xchgs;
8429	__be32 max_ssns;
8430	__be32 used_xchgs;
8431	__be32 used_ssns;
8432	__be32 max_fcfs;
8433	__be32 max_vnps;
8434	__be32 used_fcfs;
8435	__be32 used_vnps;
8436};
8437
8438struct fw_fcoe_link_cmd {
8439	__be32 op_to_portid;
8440	__be32 retval_len16;
8441	__be32 sub_opcode_fcfi;
8442	__u8   r3;
8443	__u8   lstatus;
8444	__be16 flags;
8445	__u8   r4;
8446	__u8   set_vlan;
8447	__be16 vlan_id;
8448	__be32 vnpi_pkd;
8449	__be16 r6;
8450	__u8   phy_mac[6];
8451	__u8   vnport_wwnn[8];
8452	__u8   vnport_wwpn[8];
8453};
8454
8455#define S_FW_FCOE_LINK_CMD_PORTID	0
8456#define M_FW_FCOE_LINK_CMD_PORTID	0xf
8457#define V_FW_FCOE_LINK_CMD_PORTID(x)	((x) << S_FW_FCOE_LINK_CMD_PORTID)
8458#define G_FW_FCOE_LINK_CMD_PORTID(x)	\
8459    (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
8460
8461#define S_FW_FCOE_LINK_CMD_SUB_OPCODE	24
8462#define M_FW_FCOE_LINK_CMD_SUB_OPCODE	0xff
8463#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8464    ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
8465#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8466    (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
8467
8468#define S_FW_FCOE_LINK_CMD_FCFI		0
8469#define M_FW_FCOE_LINK_CMD_FCFI		0xffffff
8470#define V_FW_FCOE_LINK_CMD_FCFI(x)	((x) << S_FW_FCOE_LINK_CMD_FCFI)
8471#define G_FW_FCOE_LINK_CMD_FCFI(x)	\
8472    (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
8473
8474#define S_FW_FCOE_LINK_CMD_VNPI		0
8475#define M_FW_FCOE_LINK_CMD_VNPI		0xfffff
8476#define V_FW_FCOE_LINK_CMD_VNPI(x)	((x) << S_FW_FCOE_LINK_CMD_VNPI)
8477#define G_FW_FCOE_LINK_CMD_VNPI(x)	\
8478    (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
8479
8480struct fw_fcoe_vnp_cmd {
8481	__be32 op_to_fcfi;
8482	__be32 alloc_to_len16;
8483	__be32 gen_wwn_to_vnpi;
8484	__be32 vf_id;
8485	__be16 iqid;
8486	__u8   vnport_mac[6];
8487	__u8   vnport_wwnn[8];
8488	__u8   vnport_wwpn[8];
8489	__u8   cmn_srv_parms[16];
8490	__u8   clsp_word_0_1[8];
8491};
8492
8493#define S_FW_FCOE_VNP_CMD_FCFI		0
8494#define M_FW_FCOE_VNP_CMD_FCFI		0xfffff
8495#define V_FW_FCOE_VNP_CMD_FCFI(x)	((x) << S_FW_FCOE_VNP_CMD_FCFI)
8496#define G_FW_FCOE_VNP_CMD_FCFI(x)	\
8497    (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
8498
8499#define S_FW_FCOE_VNP_CMD_ALLOC		31
8500#define M_FW_FCOE_VNP_CMD_ALLOC		0x1
8501#define V_FW_FCOE_VNP_CMD_ALLOC(x)	((x) << S_FW_FCOE_VNP_CMD_ALLOC)
8502#define G_FW_FCOE_VNP_CMD_ALLOC(x)	\
8503    (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
8504#define F_FW_FCOE_VNP_CMD_ALLOC		V_FW_FCOE_VNP_CMD_ALLOC(1U)
8505
8506#define S_FW_FCOE_VNP_CMD_FREE		30
8507#define M_FW_FCOE_VNP_CMD_FREE		0x1
8508#define V_FW_FCOE_VNP_CMD_FREE(x)	((x) << S_FW_FCOE_VNP_CMD_FREE)
8509#define G_FW_FCOE_VNP_CMD_FREE(x)	\
8510    (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
8511#define F_FW_FCOE_VNP_CMD_FREE		V_FW_FCOE_VNP_CMD_FREE(1U)
8512
8513#define S_FW_FCOE_VNP_CMD_MODIFY	29
8514#define M_FW_FCOE_VNP_CMD_MODIFY	0x1
8515#define V_FW_FCOE_VNP_CMD_MODIFY(x)	((x) << S_FW_FCOE_VNP_CMD_MODIFY)
8516#define G_FW_FCOE_VNP_CMD_MODIFY(x)	\
8517    (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
8518#define F_FW_FCOE_VNP_CMD_MODIFY	V_FW_FCOE_VNP_CMD_MODIFY(1U)
8519
8520#define S_FW_FCOE_VNP_CMD_GEN_WWN	22
8521#define M_FW_FCOE_VNP_CMD_GEN_WWN	0x1
8522#define V_FW_FCOE_VNP_CMD_GEN_WWN(x)	((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
8523#define G_FW_FCOE_VNP_CMD_GEN_WWN(x)	\
8524    (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
8525#define F_FW_FCOE_VNP_CMD_GEN_WWN	V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
8526
8527#define S_FW_FCOE_VNP_CMD_PERSIST	21
8528#define M_FW_FCOE_VNP_CMD_PERSIST	0x1
8529#define V_FW_FCOE_VNP_CMD_PERSIST(x)	((x) << S_FW_FCOE_VNP_CMD_PERSIST)
8530#define G_FW_FCOE_VNP_CMD_PERSIST(x)	\
8531    (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
8532#define F_FW_FCOE_VNP_CMD_PERSIST	V_FW_FCOE_VNP_CMD_PERSIST(1U)
8533
8534#define S_FW_FCOE_VNP_CMD_VFID_EN	20
8535#define M_FW_FCOE_VNP_CMD_VFID_EN	0x1
8536#define V_FW_FCOE_VNP_CMD_VFID_EN(x)	((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
8537#define G_FW_FCOE_VNP_CMD_VFID_EN(x)	\
8538    (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
8539#define F_FW_FCOE_VNP_CMD_VFID_EN	V_FW_FCOE_VNP_CMD_VFID_EN(1U)
8540
8541#define S_FW_FCOE_VNP_CMD_VNPI		0
8542#define M_FW_FCOE_VNP_CMD_VNPI		0xfffff
8543#define V_FW_FCOE_VNP_CMD_VNPI(x)	((x) << S_FW_FCOE_VNP_CMD_VNPI)
8544#define G_FW_FCOE_VNP_CMD_VNPI(x)	\
8545    (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
8546
8547struct fw_fcoe_sparams_cmd {
8548	__be32 op_to_portid;
8549	__be32 retval_len16;
8550	__u8   r3[7];
8551	__u8   cos;
8552	__u8   lport_wwnn[8];
8553	__u8   lport_wwpn[8];
8554	__u8   cmn_srv_parms[16];
8555	__u8   cls_srv_parms[16];
8556};
8557
8558#define S_FW_FCOE_SPARAMS_CMD_PORTID	0
8559#define M_FW_FCOE_SPARAMS_CMD_PORTID	0xf
8560#define V_FW_FCOE_SPARAMS_CMD_PORTID(x)	((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
8561#define G_FW_FCOE_SPARAMS_CMD_PORTID(x)	\
8562    (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
8563
8564struct fw_fcoe_stats_cmd {
8565	__be32 op_to_flowid;
8566	__be32 free_to_len16;
8567	union fw_fcoe_stats {
8568		struct fw_fcoe_stats_ctl {
8569			__u8   nstats_port;
8570			__u8   port_valid_ix;
8571			__be16 r6;
8572			__be32 r7;
8573			__be64 stat0;
8574			__be64 stat1;
8575			__be64 stat2;
8576			__be64 stat3;
8577			__be64 stat4;
8578			__be64 stat5;
8579		} ctl;
8580		struct fw_fcoe_port_stats {
8581			__be64 tx_bcast_bytes;
8582			__be64 tx_bcast_frames;
8583			__be64 tx_mcast_bytes;
8584			__be64 tx_mcast_frames;
8585			__be64 tx_ucast_bytes;
8586			__be64 tx_ucast_frames;
8587			__be64 tx_drop_frames;
8588			__be64 tx_offload_bytes;
8589			__be64 tx_offload_frames;
8590			__be64 rx_bcast_bytes;
8591			__be64 rx_bcast_frames;
8592			__be64 rx_mcast_bytes;
8593			__be64 rx_mcast_frames;
8594			__be64 rx_ucast_bytes;
8595			__be64 rx_ucast_frames;
8596			__be64 rx_err_frames;
8597		} port_stats;
8598		struct fw_fcoe_fcf_stats {
8599			__be32 fip_tx_bytes;
8600			__be32 fip_tx_fr;
8601			__be64 fcf_ka;
8602			__be64 mcast_adv_rcvd;
8603			__be16 ucast_adv_rcvd;
8604			__be16 sol_sent;
8605			__be16 vlan_req;
8606			__be16 vlan_rpl;
8607			__be16 clr_vlink;
8608			__be16 link_down;
8609			__be16 link_up;
8610			__be16 logo;
8611			__be16 flogi_req;
8612			__be16 flogi_rpl;
8613			__be16 fdisc_req;
8614			__be16 fdisc_rpl;
8615			__be16 fka_prd_chg;
8616			__be16 fc_map_chg;
8617			__be16 vfid_chg;
8618			__u8   no_fka_req;
8619			__u8   no_vnp;
8620		} fcf_stats;
8621		struct fw_fcoe_pcb_stats {
8622			__be64 tx_bytes;
8623			__be64 tx_frames;
8624			__be64 rx_bytes;
8625			__be64 rx_frames;
8626			__be32 vnp_ka;
8627			__be32 unsol_els_rcvd;
8628			__be64 unsol_cmd_rcvd;
8629			__be16 implicit_logo;
8630			__be16 flogi_inv_sparm;
8631			__be16 fdisc_inv_sparm;
8632			__be16 flogi_rjt;
8633			__be16 fdisc_rjt;
8634			__be16 no_ssn;
8635			__be16 mac_flt_fail;
8636			__be16 inv_fr_rcvd;
8637		} pcb_stats;
8638		struct fw_fcoe_scb_stats {
8639			__be64 tx_bytes;
8640			__be64 tx_frames;
8641			__be64 rx_bytes;
8642			__be64 rx_frames;
8643			__be32 host_abrt_req;
8644			__be32 adap_auto_abrt;
8645			__be32 adap_abrt_rsp;
8646			__be32 host_ios_req;
8647			__be16 ssn_offl_ios;
8648			__be16 ssn_not_rdy_ios;
8649			__u8   rx_data_ddp_err;
8650			__u8   ddp_flt_set_err;
8651			__be16 rx_data_fr_err;
8652			__u8   bad_st_abrt_req;
8653			__u8   no_io_abrt_req;
8654			__u8   abort_tmo;
8655			__u8   abort_tmo_2;
8656			__be32 abort_req;
8657			__u8   no_ppod_res_tmo;
8658			__u8   bp_tmo;
8659			__u8   adap_auto_cls;
8660			__u8   no_io_cls_req;
8661			__be32 host_cls_req;
8662			__be64 unsol_cmd_rcvd;
8663			__be32 plogi_req_rcvd;
8664			__be32 prli_req_rcvd;
8665			__be16 logo_req_rcvd;
8666			__be16 prlo_req_rcvd;
8667			__be16 plogi_rjt_rcvd;
8668			__be16 prli_rjt_rcvd;
8669			__be32 adisc_req_rcvd;
8670			__be32 rscn_rcvd;
8671			__be32 rrq_req_rcvd;
8672			__be32 unsol_els_rcvd;
8673			__u8   adisc_rjt_rcvd;
8674			__u8   scr_rjt;
8675			__u8   ct_rjt;
8676			__u8   inval_bls_rcvd;
8677			__be32 ba_rjt_rcvd;
8678		} scb_stats;
8679	} u;
8680};
8681
8682#define S_FW_FCOE_STATS_CMD_FLOWID	0
8683#define M_FW_FCOE_STATS_CMD_FLOWID	0xfffff
8684#define V_FW_FCOE_STATS_CMD_FLOWID(x)	((x) << S_FW_FCOE_STATS_CMD_FLOWID)
8685#define G_FW_FCOE_STATS_CMD_FLOWID(x)	\
8686    (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
8687
8688#define S_FW_FCOE_STATS_CMD_FREE	30
8689#define M_FW_FCOE_STATS_CMD_FREE	0x1
8690#define V_FW_FCOE_STATS_CMD_FREE(x)	((x) << S_FW_FCOE_STATS_CMD_FREE)
8691#define G_FW_FCOE_STATS_CMD_FREE(x)	\
8692    (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
8693#define F_FW_FCOE_STATS_CMD_FREE	V_FW_FCOE_STATS_CMD_FREE(1U)
8694
8695#define S_FW_FCOE_STATS_CMD_NSTATS	4
8696#define M_FW_FCOE_STATS_CMD_NSTATS	0x7
8697#define V_FW_FCOE_STATS_CMD_NSTATS(x)	((x) << S_FW_FCOE_STATS_CMD_NSTATS)
8698#define G_FW_FCOE_STATS_CMD_NSTATS(x)	\
8699    (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
8700
8701#define S_FW_FCOE_STATS_CMD_PORT	0
8702#define M_FW_FCOE_STATS_CMD_PORT	0x3
8703#define V_FW_FCOE_STATS_CMD_PORT(x)	((x) << S_FW_FCOE_STATS_CMD_PORT)
8704#define G_FW_FCOE_STATS_CMD_PORT(x)	\
8705    (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
8706
8707#define S_FW_FCOE_STATS_CMD_PORT_VALID	7
8708#define M_FW_FCOE_STATS_CMD_PORT_VALID	0x1
8709#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8710    ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
8711#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8712    (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
8713#define F_FW_FCOE_STATS_CMD_PORT_VALID	V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
8714
8715#define S_FW_FCOE_STATS_CMD_IX		0
8716#define M_FW_FCOE_STATS_CMD_IX		0x3f
8717#define V_FW_FCOE_STATS_CMD_IX(x)	((x) << S_FW_FCOE_STATS_CMD_IX)
8718#define G_FW_FCOE_STATS_CMD_IX(x)	\
8719    (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
8720
8721struct fw_fcoe_fcf_cmd {
8722	__be32 op_to_fcfi;
8723	__be32 retval_len16;
8724	__be16 priority_pkd;
8725	__u8   mac[6];
8726	__u8   name_id[8];
8727	__u8   fabric[8];
8728	__be16 vf_id;
8729	__be16 max_fcoe_size;
8730	__u8   vlan_id;
8731	__u8   fc_map[3];
8732	__be32 fka_adv;
8733	__be32 r6;
8734	__u8   r7_hi;
8735	__u8   fpma_to_portid;
8736	__u8   spma_mac[6];
8737	__be64 r8;
8738};
8739
8740#define S_FW_FCOE_FCF_CMD_FCFI		0
8741#define M_FW_FCOE_FCF_CMD_FCFI		0xfffff
8742#define V_FW_FCOE_FCF_CMD_FCFI(x)	((x) << S_FW_FCOE_FCF_CMD_FCFI)
8743#define G_FW_FCOE_FCF_CMD_FCFI(x)	\
8744    (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
8745
8746#define S_FW_FCOE_FCF_CMD_PRIORITY	0
8747#define M_FW_FCOE_FCF_CMD_PRIORITY	0xff
8748#define V_FW_FCOE_FCF_CMD_PRIORITY(x)	((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
8749#define G_FW_FCOE_FCF_CMD_PRIORITY(x)	\
8750    (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
8751
8752#define S_FW_FCOE_FCF_CMD_FPMA		6
8753#define M_FW_FCOE_FCF_CMD_FPMA		0x1
8754#define V_FW_FCOE_FCF_CMD_FPMA(x)	((x) << S_FW_FCOE_FCF_CMD_FPMA)
8755#define G_FW_FCOE_FCF_CMD_FPMA(x)	\
8756    (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
8757#define F_FW_FCOE_FCF_CMD_FPMA		V_FW_FCOE_FCF_CMD_FPMA(1U)
8758
8759#define S_FW_FCOE_FCF_CMD_SPMA		5
8760#define M_FW_FCOE_FCF_CMD_SPMA		0x1
8761#define V_FW_FCOE_FCF_CMD_SPMA(x)	((x) << S_FW_FCOE_FCF_CMD_SPMA)
8762#define G_FW_FCOE_FCF_CMD_SPMA(x)	\
8763    (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
8764#define F_FW_FCOE_FCF_CMD_SPMA		V_FW_FCOE_FCF_CMD_SPMA(1U)
8765
8766#define S_FW_FCOE_FCF_CMD_LOGIN		4
8767#define M_FW_FCOE_FCF_CMD_LOGIN		0x1
8768#define V_FW_FCOE_FCF_CMD_LOGIN(x)	((x) << S_FW_FCOE_FCF_CMD_LOGIN)
8769#define G_FW_FCOE_FCF_CMD_LOGIN(x)	\
8770    (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
8771#define F_FW_FCOE_FCF_CMD_LOGIN		V_FW_FCOE_FCF_CMD_LOGIN(1U)
8772
8773#define S_FW_FCOE_FCF_CMD_PORTID	0
8774#define M_FW_FCOE_FCF_CMD_PORTID	0xf
8775#define V_FW_FCOE_FCF_CMD_PORTID(x)	((x) << S_FW_FCOE_FCF_CMD_PORTID)
8776#define G_FW_FCOE_FCF_CMD_PORTID(x)	\
8777    (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
8778
8779/******************************************************************************
8780 *   E R R O R   a n d   D E B U G   C O M M A N D s
8781 ******************************************************/
8782
8783enum fw_error_type {
8784	FW_ERROR_TYPE_EXCEPTION		= 0x0,
8785	FW_ERROR_TYPE_HWMODULE		= 0x1,
8786	FW_ERROR_TYPE_WR		= 0x2,
8787	FW_ERROR_TYPE_ACL		= 0x3,
8788};
8789
8790enum fw_dcb_ieee_locations {
8791	FW_IEEE_LOC_LOCAL,
8792	FW_IEEE_LOC_PEER,
8793	FW_IEEE_LOC_OPERATIONAL,
8794};
8795
8796struct fw_dcb_ieee_cmd {
8797	__be32 op_to_location;
8798	__be32 changed_to_len16;
8799	union fw_dcbx_stats {
8800		struct fw_dcbx_pfc_stats_ieee {
8801			__be32 pfc_mbc_pkd;
8802			__be32 pfc_willing_to_pfc_en;
8803		} dcbx_pfc_stats;
8804		struct fw_dcbx_ets_stats_ieee {
8805			__be32 cbs_to_ets_max_tc;
8806			__be32 pg_table;
8807			__u8   pg_percent[8];
8808			__u8   tsa[8];
8809		} dcbx_ets_stats;
8810		struct fw_dcbx_app_stats_ieee {
8811			__be32 num_apps_pkd;
8812			__be32 r6;
8813			__be32 app[4];
8814		} dcbx_app_stats;
8815		struct fw_dcbx_control {
8816			__be32 multi_peer_invalidated;
8817			__be32 r5_lo;
8818		} dcbx_control;
8819	} u;
8820};
8821
8822#define S_FW_DCB_IEEE_CMD_PORT		8
8823#define M_FW_DCB_IEEE_CMD_PORT		0x7
8824#define V_FW_DCB_IEEE_CMD_PORT(x)	((x) << S_FW_DCB_IEEE_CMD_PORT)
8825#define G_FW_DCB_IEEE_CMD_PORT(x)	\
8826    (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
8827
8828#define S_FW_DCB_IEEE_CMD_FEATURE	2
8829#define M_FW_DCB_IEEE_CMD_FEATURE	0x7
8830#define V_FW_DCB_IEEE_CMD_FEATURE(x)	((x) << S_FW_DCB_IEEE_CMD_FEATURE)
8831#define G_FW_DCB_IEEE_CMD_FEATURE(x)	\
8832    (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
8833
8834#define S_FW_DCB_IEEE_CMD_LOCATION	0
8835#define M_FW_DCB_IEEE_CMD_LOCATION	0x3
8836#define V_FW_DCB_IEEE_CMD_LOCATION(x)	((x) << S_FW_DCB_IEEE_CMD_LOCATION)
8837#define G_FW_DCB_IEEE_CMD_LOCATION(x)	\
8838    (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
8839
8840#define S_FW_DCB_IEEE_CMD_CHANGED	20
8841#define M_FW_DCB_IEEE_CMD_CHANGED	0x1
8842#define V_FW_DCB_IEEE_CMD_CHANGED(x)	((x) << S_FW_DCB_IEEE_CMD_CHANGED)
8843#define G_FW_DCB_IEEE_CMD_CHANGED(x)	\
8844    (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
8845#define F_FW_DCB_IEEE_CMD_CHANGED	V_FW_DCB_IEEE_CMD_CHANGED(1U)
8846
8847#define S_FW_DCB_IEEE_CMD_RECEIVED	19
8848#define M_FW_DCB_IEEE_CMD_RECEIVED	0x1
8849#define V_FW_DCB_IEEE_CMD_RECEIVED(x)	((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
8850#define G_FW_DCB_IEEE_CMD_RECEIVED(x)	\
8851    (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
8852#define F_FW_DCB_IEEE_CMD_RECEIVED	V_FW_DCB_IEEE_CMD_RECEIVED(1U)
8853
8854#define S_FW_DCB_IEEE_CMD_APPLY		18
8855#define M_FW_DCB_IEEE_CMD_APPLY		0x1
8856#define V_FW_DCB_IEEE_CMD_APPLY(x)	((x) << S_FW_DCB_IEEE_CMD_APPLY)
8857#define G_FW_DCB_IEEE_CMD_APPLY(x)	\
8858    (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
8859#define F_FW_DCB_IEEE_CMD_APPLY	V_FW_DCB_IEEE_CMD_APPLY(1U)
8860
8861#define S_FW_DCB_IEEE_CMD_DISABLED	17
8862#define M_FW_DCB_IEEE_CMD_DISABLED	0x1
8863#define V_FW_DCB_IEEE_CMD_DISABLED(x)	((x) << S_FW_DCB_IEEE_CMD_DISABLED)
8864#define G_FW_DCB_IEEE_CMD_DISABLED(x)	\
8865    (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
8866#define F_FW_DCB_IEEE_CMD_DISABLED	V_FW_DCB_IEEE_CMD_DISABLED(1U)
8867
8868#define S_FW_DCB_IEEE_CMD_MORE		16
8869#define M_FW_DCB_IEEE_CMD_MORE		0x1
8870#define V_FW_DCB_IEEE_CMD_MORE(x)	((x) << S_FW_DCB_IEEE_CMD_MORE)
8871#define G_FW_DCB_IEEE_CMD_MORE(x)	\
8872    (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
8873#define F_FW_DCB_IEEE_CMD_MORE	V_FW_DCB_IEEE_CMD_MORE(1U)
8874
8875#define S_FW_DCB_IEEE_CMD_PFC_MBC	0
8876#define M_FW_DCB_IEEE_CMD_PFC_MBC	0x1
8877#define V_FW_DCB_IEEE_CMD_PFC_MBC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
8878#define G_FW_DCB_IEEE_CMD_PFC_MBC(x)	\
8879    (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
8880#define F_FW_DCB_IEEE_CMD_PFC_MBC	V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
8881
8882#define S_FW_DCB_IEEE_CMD_PFC_WILLING		16
8883#define M_FW_DCB_IEEE_CMD_PFC_WILLING		0x1
8884#define V_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
8885    ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
8886#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
8887    (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
8888#define F_FW_DCB_IEEE_CMD_PFC_WILLING	V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
8889
8890#define S_FW_DCB_IEEE_CMD_PFC_MAX_TC	8
8891#define M_FW_DCB_IEEE_CMD_PFC_MAX_TC	0xff
8892#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8893#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	\
8894    (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8895
8896#define S_FW_DCB_IEEE_CMD_PFC_EN	0
8897#define M_FW_DCB_IEEE_CMD_PFC_EN	0xff
8898#define V_FW_DCB_IEEE_CMD_PFC_EN(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
8899#define G_FW_DCB_IEEE_CMD_PFC_EN(x)	\
8900    (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
8901
8902#define S_FW_DCB_IEEE_CMD_CBS		16
8903#define M_FW_DCB_IEEE_CMD_CBS		0x1
8904#define V_FW_DCB_IEEE_CMD_CBS(x)	((x) << S_FW_DCB_IEEE_CMD_CBS)
8905#define G_FW_DCB_IEEE_CMD_CBS(x)	\
8906    (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
8907#define F_FW_DCB_IEEE_CMD_CBS	V_FW_DCB_IEEE_CMD_CBS(1U)
8908
8909#define S_FW_DCB_IEEE_CMD_ETS_WILLING		8
8910#define M_FW_DCB_IEEE_CMD_ETS_WILLING		0x1
8911#define V_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
8912    ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
8913#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
8914    (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
8915#define F_FW_DCB_IEEE_CMD_ETS_WILLING	V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
8916
8917#define S_FW_DCB_IEEE_CMD_ETS_MAX_TC	0
8918#define M_FW_DCB_IEEE_CMD_ETS_MAX_TC	0xff
8919#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
8920#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	\
8921    (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
8922
8923#define S_FW_DCB_IEEE_CMD_NUM_APPS	0
8924#define M_FW_DCB_IEEE_CMD_NUM_APPS	0x7
8925#define V_FW_DCB_IEEE_CMD_NUM_APPS(x)	((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
8926#define G_FW_DCB_IEEE_CMD_NUM_APPS(x)	\
8927    (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
8928
8929#define S_FW_DCB_IEEE_CMD_MULTI_PEER	31
8930#define M_FW_DCB_IEEE_CMD_MULTI_PEER	0x1
8931#define V_FW_DCB_IEEE_CMD_MULTI_PEER(x)	((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
8932#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x)	\
8933    (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
8934#define F_FW_DCB_IEEE_CMD_MULTI_PEER	V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
8935
8936#define S_FW_DCB_IEEE_CMD_INVALIDATED		30
8937#define M_FW_DCB_IEEE_CMD_INVALIDATED		0x1
8938#define V_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
8939    ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
8940#define G_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
8941    (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
8942#define F_FW_DCB_IEEE_CMD_INVALIDATED	V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
8943
8944/* Hand-written */
8945#define S_FW_DCB_IEEE_CMD_APP_PROTOCOL	16
8946#define M_FW_DCB_IEEE_CMD_APP_PROTOCOL	0xffff
8947#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
8948#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	\
8949    (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
8950
8951#define S_FW_DCB_IEEE_CMD_APP_SELECT	3
8952#define M_FW_DCB_IEEE_CMD_APP_SELECT	0x7
8953#define V_FW_DCB_IEEE_CMD_APP_SELECT(x)	((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
8954#define G_FW_DCB_IEEE_CMD_APP_SELECT(x)	\
8955    (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
8956
8957#define S_FW_DCB_IEEE_CMD_APP_PRIORITY	0
8958#define M_FW_DCB_IEEE_CMD_APP_PRIORITY	0x7
8959#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
8960#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	\
8961    (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
8962
8963
8964struct fw_error_cmd {
8965	__be32 op_to_type;
8966	__be32 len16_pkd;
8967	union fw_error {
8968		struct fw_error_exception {
8969			__be32 info[6];
8970		} exception;
8971		struct fw_error_hwmodule {
8972			__be32 regaddr;
8973			__be32 regval;
8974		} hwmodule;
8975		struct fw_error_wr {
8976			__be16 cidx;
8977			__be16 pfn_vfn;
8978			__be32 eqid;
8979			__u8   wrhdr[16];
8980		} wr;
8981		struct fw_error_acl {
8982			__be16 cidx;
8983			__be16 pfn_vfn;
8984			__be32 eqid;
8985			__be16 mv_pkd;
8986			__u8   val[6];
8987			__be64 r4;
8988		} acl;
8989	} u;
8990};
8991
8992#define S_FW_ERROR_CMD_FATAL		4
8993#define M_FW_ERROR_CMD_FATAL		0x1
8994#define V_FW_ERROR_CMD_FATAL(x)		((x) << S_FW_ERROR_CMD_FATAL)
8995#define G_FW_ERROR_CMD_FATAL(x)		\
8996    (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
8997#define F_FW_ERROR_CMD_FATAL		V_FW_ERROR_CMD_FATAL(1U)
8998
8999#define S_FW_ERROR_CMD_TYPE		0
9000#define M_FW_ERROR_CMD_TYPE		0xf
9001#define V_FW_ERROR_CMD_TYPE(x)		((x) << S_FW_ERROR_CMD_TYPE)
9002#define G_FW_ERROR_CMD_TYPE(x)		\
9003    (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9004
9005#define S_FW_ERROR_CMD_PFN		8
9006#define M_FW_ERROR_CMD_PFN		0x7
9007#define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
9008#define G_FW_ERROR_CMD_PFN(x)		\
9009    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9010
9011#define S_FW_ERROR_CMD_VFN		0
9012#define M_FW_ERROR_CMD_VFN		0xff
9013#define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
9014#define G_FW_ERROR_CMD_VFN(x)		\
9015    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9016
9017#define S_FW_ERROR_CMD_PFN		8
9018#define M_FW_ERROR_CMD_PFN		0x7
9019#define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
9020#define G_FW_ERROR_CMD_PFN(x)		\
9021    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9022
9023#define S_FW_ERROR_CMD_VFN		0
9024#define M_FW_ERROR_CMD_VFN		0xff
9025#define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
9026#define G_FW_ERROR_CMD_VFN(x)		\
9027    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9028
9029#define S_FW_ERROR_CMD_MV		15
9030#define M_FW_ERROR_CMD_MV		0x1
9031#define V_FW_ERROR_CMD_MV(x)		((x) << S_FW_ERROR_CMD_MV)
9032#define G_FW_ERROR_CMD_MV(x)		\
9033    (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9034#define F_FW_ERROR_CMD_MV		V_FW_ERROR_CMD_MV(1U)
9035
9036struct fw_debug_cmd {
9037	__be32 op_type;
9038	__be32 len16_pkd;
9039	union fw_debug {
9040		struct fw_debug_assert {
9041			__be32 fcid;
9042			__be32 line;
9043			__be32 x;
9044			__be32 y;
9045			__u8   filename_0_7[8];
9046			__u8   filename_8_15[8];
9047			__be64 r3;
9048		} assert;
9049		struct fw_debug_prt {
9050			__be16 dprtstridx;
9051			__be16 r3[3];
9052			__be32 dprtstrparam0;
9053			__be32 dprtstrparam1;
9054			__be32 dprtstrparam2;
9055			__be32 dprtstrparam3;
9056		} prt;
9057	} u;
9058};
9059
9060#define S_FW_DEBUG_CMD_TYPE		0
9061#define M_FW_DEBUG_CMD_TYPE		0xff
9062#define V_FW_DEBUG_CMD_TYPE(x)		((x) << S_FW_DEBUG_CMD_TYPE)
9063#define G_FW_DEBUG_CMD_TYPE(x)		\
9064    (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9065
9066enum fw_diag_cmd_type {
9067	FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9068};
9069
9070enum fw_diag_cmd_ofldiag_op {
9071	FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9072	FW_DIAG_CMD_OFLDIAG_TEST_START,
9073	FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9074	FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9075};
9076
9077enum fw_diag_cmd_ofldiag_status {
9078	FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9079	FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9080	FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9081	FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9082};
9083
9084struct fw_diag_cmd {
9085	__be32 op_type;
9086	__be32 len16_pkd;
9087	union fw_diag_test {
9088		struct fw_diag_test_ofldiag {
9089			__u8   test_op;
9090			__u8   r3;
9091			__be16 test_status;
9092			__be32 duration;
9093		} ofldiag;
9094	} u;
9095};
9096
9097#define S_FW_DIAG_CMD_TYPE		0
9098#define M_FW_DIAG_CMD_TYPE		0xff
9099#define V_FW_DIAG_CMD_TYPE(x)		((x) << S_FW_DIAG_CMD_TYPE)
9100#define G_FW_DIAG_CMD_TYPE(x)		\
9101    (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9102
9103/******************************************************************************
9104 *   P C I E   F W   R E G I S T E R
9105 **************************************/
9106
9107enum pcie_fw_eval {
9108	PCIE_FW_EVAL_CRASH		= 0,
9109	PCIE_FW_EVAL_PREP		= 1,
9110	PCIE_FW_EVAL_CONF		= 2,
9111	PCIE_FW_EVAL_INIT		= 3,
9112	PCIE_FW_EVAL_UNEXPECTEDEVENT	= 4,
9113	PCIE_FW_EVAL_OVERHEAT		= 5,
9114	PCIE_FW_EVAL_DEVICESHUTDOWN	= 6,
9115};
9116
9117/**
9118 *	Register definitions for the PCIE_FW register which the firmware uses
9119 *	to retain status across RESETs.  This register should be considered
9120 *	as a READ-ONLY register for Host Software and only to be used to
9121 *	track firmware initialization/error state, etc.
9122 */
9123#define S_PCIE_FW_ERR		31
9124#define M_PCIE_FW_ERR		0x1
9125#define V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
9126#define G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9127#define F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
9128
9129#define S_PCIE_FW_INIT		30
9130#define M_PCIE_FW_INIT		0x1
9131#define V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
9132#define G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9133#define F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
9134
9135#define S_PCIE_FW_HALT          29
9136#define M_PCIE_FW_HALT          0x1
9137#define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)
9138#define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9139#define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
9140
9141#define S_PCIE_FW_EVAL		24
9142#define M_PCIE_FW_EVAL		0x7
9143#define V_PCIE_FW_EVAL(x)	((x) << S_PCIE_FW_EVAL)
9144#define G_PCIE_FW_EVAL(x)	(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9145
9146#define S_PCIE_FW_STAGE		21
9147#define M_PCIE_FW_STAGE		0x7
9148#define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
9149#define G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9150
9151#define S_PCIE_FW_ASYNCNOT_VLD	20
9152#define M_PCIE_FW_ASYNCNOT_VLD	0x1
9153#define V_PCIE_FW_ASYNCNOT_VLD(x) \
9154    ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9155#define G_PCIE_FW_ASYNCNOT_VLD(x) \
9156    (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9157#define F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
9158
9159#define S_PCIE_FW_ASYNCNOTINT	19
9160#define M_PCIE_FW_ASYNCNOTINT	0x1
9161#define V_PCIE_FW_ASYNCNOTINT(x) \
9162    ((x) << S_PCIE_FW_ASYNCNOTINT)
9163#define G_PCIE_FW_ASYNCNOTINT(x) \
9164    (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9165#define F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
9166
9167#define S_PCIE_FW_ASYNCNOT	16
9168#define M_PCIE_FW_ASYNCNOT	0x7
9169#define V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
9170#define G_PCIE_FW_ASYNCNOT(x)	\
9171    (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9172
9173#define S_PCIE_FW_MASTER_VLD	15
9174#define M_PCIE_FW_MASTER_VLD	0x1
9175#define V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
9176#define G_PCIE_FW_MASTER_VLD(x)	\
9177    (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9178#define F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
9179
9180#define S_PCIE_FW_MASTER	12
9181#define M_PCIE_FW_MASTER	0x7
9182#define V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
9183#define G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9184
9185#define S_PCIE_FW_RESET_VLD		11
9186#define M_PCIE_FW_RESET_VLD		0x1
9187#define V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
9188#define G_PCIE_FW_RESET_VLD(x)	\
9189    (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9190#define F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
9191
9192#define S_PCIE_FW_RESET		8
9193#define M_PCIE_FW_RESET		0x7
9194#define V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
9195#define G_PCIE_FW_RESET(x)	\
9196    (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9197
9198#define S_PCIE_FW_REGISTERED	0
9199#define M_PCIE_FW_REGISTERED	0xff
9200#define V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
9201#define G_PCIE_FW_REGISTERED(x)	\
9202    (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9203
9204
9205/******************************************************************************
9206 *   P C I E   F W   P F 0   R E G I S T E R
9207 **********************************************/
9208
9209/*
9210 *	this register is available as 32-bit of persistent storage (accross
9211 *	PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9212 *	will not write it)
9213 */
9214
9215
9216/******************************************************************************
9217 *   P C I E   F W   P F 7   R E G I S T E R
9218 **********************************************/
9219
9220/*
9221 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9222 * access the "devlog" which needing to contact firmware.  The encoding is
9223 * mostly the same as that returned by the DEVLOG command except for the size
9224 * which is encoded as the number of entries in multiples-1 of 128 here rather
9225 * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
9226 * and 15 means 2048.  This of course in turn constrains the allowed values
9227 * for the devlog size ...
9228 */
9229#define PCIE_FW_PF_DEVLOG		7
9230
9231#define S_PCIE_FW_PF_DEVLOG_NENTRIES128	28
9232#define M_PCIE_FW_PF_DEVLOG_NENTRIES128	0xf
9233#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9234	((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9235#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9236	(((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9237	 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9238
9239#define S_PCIE_FW_PF_DEVLOG_ADDR16	4
9240#define M_PCIE_FW_PF_DEVLOG_ADDR16	0xffffff
9241#define V_PCIE_FW_PF_DEVLOG_ADDR16(x)	((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9242#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9243	(((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9244
9245#define S_PCIE_FW_PF_DEVLOG_MEMTYPE	0
9246#define M_PCIE_FW_PF_DEVLOG_MEMTYPE	0xf
9247#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x)	((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9248#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9249	(((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9250
9251
9252/******************************************************************************
9253 *   B I N A R Y   H E A D E R   F O R M A T
9254 **********************************************/
9255
9256/*
9257 *	firmware binary header format
9258 */
9259struct fw_hdr {
9260	__u8	ver;
9261	__u8	chip;			/* terminator chip family */
9262	__be16	len512;			/* bin length in units of 512-bytes */
9263	__be32	fw_ver;			/* firmware version */
9264	__be32	tp_microcode_ver;	/* tcp processor microcode version */
9265	__u8	intfver_nic;
9266	__u8	intfver_vnic;
9267	__u8	intfver_ofld;
9268	__u8	intfver_ri;
9269	__u8	intfver_iscsipdu;
9270	__u8	intfver_iscsi;
9271	__u8	intfver_fcoepdu;
9272	__u8	intfver_fcoe;
9273	__u32	reserved2;
9274	__u32	reserved3;
9275	__be32	magic;			/* runtime or bootstrap fw */
9276	__be32	flags;
9277	__be32	reserved6[23];
9278};
9279
9280enum fw_hdr_chip {
9281	FW_HDR_CHIP_T4,
9282	FW_HDR_CHIP_T5,
9283	FW_HDR_CHIP_T6
9284};
9285
9286#define S_FW_HDR_FW_VER_MAJOR	24
9287#define M_FW_HDR_FW_VER_MAJOR	0xff
9288#define V_FW_HDR_FW_VER_MAJOR(x) \
9289    ((x) << S_FW_HDR_FW_VER_MAJOR)
9290#define G_FW_HDR_FW_VER_MAJOR(x) \
9291    (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9292
9293#define S_FW_HDR_FW_VER_MINOR	16
9294#define M_FW_HDR_FW_VER_MINOR	0xff
9295#define V_FW_HDR_FW_VER_MINOR(x) \
9296    ((x) << S_FW_HDR_FW_VER_MINOR)
9297#define G_FW_HDR_FW_VER_MINOR(x) \
9298    (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9299
9300#define S_FW_HDR_FW_VER_MICRO	8
9301#define M_FW_HDR_FW_VER_MICRO	0xff
9302#define V_FW_HDR_FW_VER_MICRO(x) \
9303    ((x) << S_FW_HDR_FW_VER_MICRO)
9304#define G_FW_HDR_FW_VER_MICRO(x) \
9305    (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9306
9307#define S_FW_HDR_FW_VER_BUILD	0
9308#define M_FW_HDR_FW_VER_BUILD	0xff
9309#define V_FW_HDR_FW_VER_BUILD(x) \
9310    ((x) << S_FW_HDR_FW_VER_BUILD)
9311#define G_FW_HDR_FW_VER_BUILD(x) \
9312    (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
9313
9314enum {
9315	T4FW_VERSION_MAJOR	= 0x01,
9316	T4FW_VERSION_MINOR	= 0x10,
9317	T4FW_VERSION_MICRO	= 0x1a,
9318	T4FW_VERSION_BUILD	= 0x00,
9319
9320	T5FW_VERSION_MAJOR	= 0x01,
9321	T5FW_VERSION_MINOR	= 0x10,
9322	T5FW_VERSION_MICRO	= 0x1a,
9323	T5FW_VERSION_BUILD	= 0x00,
9324
9325	T6FW_VERSION_MAJOR	= 0x01,
9326	T6FW_VERSION_MINOR	= 0x10,
9327	T6FW_VERSION_MICRO	= 0x1a,
9328	T6FW_VERSION_BUILD	= 0x00,
9329};
9330
9331enum {
9332	/* T4
9333	 */
9334	T4FW_HDR_INTFVER_NIC	= 0x00,
9335	T4FW_HDR_INTFVER_VNIC	= 0x00,
9336	T4FW_HDR_INTFVER_OFLD	= 0x00,
9337	T4FW_HDR_INTFVER_RI	= 0x00,
9338	T4FW_HDR_INTFVER_ISCSIPDU= 0x00,
9339	T4FW_HDR_INTFVER_ISCSI	= 0x00,
9340	T4FW_HDR_INTFVER_FCOEPDU  = 0x00,
9341	T4FW_HDR_INTFVER_FCOE	= 0x00,
9342
9343	/* T5
9344	 */
9345	T5FW_HDR_INTFVER_NIC	= 0x00,
9346	T5FW_HDR_INTFVER_VNIC	= 0x00,
9347	T5FW_HDR_INTFVER_OFLD	= 0x00,
9348	T5FW_HDR_INTFVER_RI	= 0x00,
9349	T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
9350	T5FW_HDR_INTFVER_ISCSI	= 0x00,
9351	T5FW_HDR_INTFVER_FCOEPDU= 0x00,
9352	T5FW_HDR_INTFVER_FCOE	= 0x00,
9353
9354	/* T6
9355	 */
9356	T6FW_HDR_INTFVER_NIC	= 0x00,
9357	T6FW_HDR_INTFVER_VNIC	= 0x00,
9358	T6FW_HDR_INTFVER_OFLD	= 0x00,
9359	T6FW_HDR_INTFVER_RI	= 0x00,
9360	T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
9361	T6FW_HDR_INTFVER_ISCSI	= 0x00,
9362	T6FW_HDR_INTFVER_FCOEPDU= 0x00,
9363	T6FW_HDR_INTFVER_FCOE	= 0x00,
9364};
9365
9366enum {
9367	FW_HDR_MAGIC_RUNTIME	= 0x00000000,
9368	FW_HDR_MAGIC_BOOTSTRAP	= 0x626f6f74,
9369};
9370
9371enum fw_hdr_flags {
9372	FW_HDR_FLAGS_RESET_HALT	= 0x00000001,
9373};
9374
9375/*
9376 *	External PHY firmware binary header format
9377 */
9378struct fw_ephy_hdr {
9379	__u8	ver;
9380	__u8	reserved;
9381	__be16	len512;			/* bin length in units of 512-bytes */
9382	__be32	magic;
9383
9384	__be16	vendor_id;
9385	__be16	device_id;
9386	__be32	version;
9387
9388	__be32	reserved1[4];
9389};
9390
9391enum {
9392	FW_EPHY_HDR_MAGIC	= 0x65706879,
9393};
9394
9395#endif /* _T4FW_INTERFACE_H_ */
9396