t4fw_interface.h revision 286895
1/*- 2 * Copyright (c) 2012-2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 286895 2015-08-18 18:54:45Z np $ 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76}; 77 78/****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89}; 90 91/****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, 110 FW_RI_RES_WR = 0x0c, 111 FW_RI_RDMA_WRITE_WR = 0x14, 112 FW_RI_SEND_WR = 0x15, 113 FW_RI_RDMA_READ_WR = 0x16, 114 FW_RI_RECV_WR = 0x17, 115 FW_RI_BIND_MW_WR = 0x18, 116 FW_RI_FR_NSMR_WR = 0x19, 117 FW_RI_INV_LSTAG_WR = 0x1a, 118 FW_RI_SEND_IMMEDIATE_WR = 0x15, 119 FW_RI_ATOMIC_WR = 0x16, 120 FW_RI_WR = 0x0d, 121 FW_CHNET_IFCONF_WR = 0x6b, 122 FW_RDEV_WR = 0x38, 123 FW_FOISCSI_NODE_WR = 0x60, 124 FW_FOISCSI_CTRL_WR = 0x6a, 125 FW_FOISCSI_CHAP_WR = 0x6c, 126 FW_FCOE_ELS_CT_WR = 0x30, 127 FW_SCSI_WRITE_WR = 0x31, 128 FW_SCSI_READ_WR = 0x32, 129 FW_SCSI_CMD_WR = 0x33, 130 FW_SCSI_ABRT_CLS_WR = 0x34, 131 FW_SCSI_TGT_ACC_WR = 0x35, 132 FW_SCSI_TGT_XMIT_WR = 0x36, 133 FW_SCSI_TGT_RSP_WR = 0x37, 134 FW_POFCOE_TCB_WR = 0x42, 135 FW_POFCOE_ULPTX_WR = 0x43, 136 FW_ISCSI_TX_DATA_WR = 0x45, 137 FW_PTP_TX_PKT_WR = 0x46, 138 FW_LASTC2E_WR = 0x70 139}; 140 141/* 142 * Generic work request header flit0 143 */ 144struct fw_wr_hdr { 145 __be32 hi; 146 __be32 lo; 147}; 148 149/* work request opcode (hi) 150 */ 151#define S_FW_WR_OP 24 152#define M_FW_WR_OP 0xff 153#define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 154#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 155 156/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 157 */ 158#define S_FW_WR_ATOMIC 23 159#define M_FW_WR_ATOMIC 0x1 160#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 161#define G_FW_WR_ATOMIC(x) \ 162 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 163#define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 164 165/* flush flag (hi) - firmware flushes flushable work request buffered 166 * in the flow context. 167 */ 168#define S_FW_WR_FLUSH 22 169#define M_FW_WR_FLUSH 0x1 170#define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 171#define G_FW_WR_FLUSH(x) \ 172 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 173#define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 174 175/* completion flag (hi) - firmware generates a cpl_fw6_ack 176 */ 177#define S_FW_WR_COMPL 21 178#define M_FW_WR_COMPL 0x1 179#define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 180#define G_FW_WR_COMPL(x) \ 181 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 182#define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 183 184 185/* work request immediate data lengh (hi) 186 */ 187#define S_FW_WR_IMMDLEN 0 188#define M_FW_WR_IMMDLEN 0xff 189#define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 190#define G_FW_WR_IMMDLEN(x) \ 191 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 192 193/* egress queue status update to associated ingress queue entry (lo) 194 */ 195#define S_FW_WR_EQUIQ 31 196#define M_FW_WR_EQUIQ 0x1 197#define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 198#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 199#define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 200 201/* egress queue status update to egress queue status entry (lo) 202 */ 203#define S_FW_WR_EQUEQ 30 204#define M_FW_WR_EQUEQ 0x1 205#define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 206#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 207#define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 208 209/* flow context identifier (lo) 210 */ 211#define S_FW_WR_FLOWID 8 212#define M_FW_WR_FLOWID 0xfffff 213#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 214#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 215 216/* length in units of 16-bytes (lo) 217 */ 218#define S_FW_WR_LEN16 0 219#define M_FW_WR_LEN16 0xff 220#define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 221#define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 222 223struct fw_frag_wr { 224 __be32 op_to_fragoff16; 225 __be32 flowid_len16; 226 __be64 r4; 227}; 228 229#define S_FW_FRAG_WR_EOF 15 230#define M_FW_FRAG_WR_EOF 0x1 231#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 232#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 233#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 234 235#define S_FW_FRAG_WR_FRAGOFF16 8 236#define M_FW_FRAG_WR_FRAGOFF16 0x7f 237#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 238#define G_FW_FRAG_WR_FRAGOFF16(x) \ 239 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 240 241/* valid filter configurations for compressed tuple 242 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 243 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 244 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 245 * OV - Outer VLAN/VNIC_ID, 246*/ 247#define HW_TPL_FR_MT_M_E_P_FC 0x3C3 248#define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 249#define HW_TPL_FR_MT_M_IV_P_FC 0x38B 250#define HW_TPL_FR_MT_M_OV_P_FC 0x387 251#define HW_TPL_FR_MT_E_PR_T 0x370 252#define HW_TPL_FR_MT_E_PR_P_FC 0X363 253#define HW_TPL_FR_MT_E_T_P_FC 0X353 254#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 255#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 256#define HW_TPL_FR_MT_T_IV_P_FC 0X31B 257#define HW_TPL_FR_MT_T_OV_P_FC 0X317 258#define HW_TPL_FR_M_E_PR_FC 0X2E1 259#define HW_TPL_FR_M_E_T_FC 0X2D1 260#define HW_TPL_FR_M_PR_IV_FC 0X2A9 261#define HW_TPL_FR_M_PR_OV_FC 0X2A5 262#define HW_TPL_FR_M_T_IV_FC 0X299 263#define HW_TPL_FR_M_T_OV_FC 0X295 264#define HW_TPL_FR_E_PR_T_P 0X272 265#define HW_TPL_FR_E_PR_T_FC 0X271 266#define HW_TPL_FR_E_IV_FC 0X249 267#define HW_TPL_FR_E_OV_FC 0X245 268#define HW_TPL_FR_PR_T_IV_FC 0X239 269#define HW_TPL_FR_PR_T_OV_FC 0X235 270#define HW_TPL_FR_IV_OV_FC 0X20D 271#define HW_TPL_MT_M_E_PR 0X1E0 272#define HW_TPL_MT_M_E_T 0X1D0 273#define HW_TPL_MT_E_PR_T_FC 0X171 274#define HW_TPL_MT_E_IV 0X148 275#define HW_TPL_MT_E_OV 0X144 276#define HW_TPL_MT_PR_T_IV 0X138 277#define HW_TPL_MT_PR_T_OV 0X134 278#define HW_TPL_M_E_PR_P 0X0E2 279#define HW_TPL_M_E_T_P 0X0D2 280#define HW_TPL_E_PR_T_P_FC 0X073 281#define HW_TPL_E_IV_P 0X04A 282#define HW_TPL_E_OV_P 0X046 283#define HW_TPL_PR_T_IV_P 0X03A 284#define HW_TPL_PR_T_OV_P 0X036 285 286/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 287enum fw_filter_wr_cookie { 288 FW_FILTER_WR_SUCCESS, 289 FW_FILTER_WR_FLT_ADDED, 290 FW_FILTER_WR_FLT_DELETED, 291 FW_FILTER_WR_SMT_TBL_FULL, 292 FW_FILTER_WR_EINVAL, 293}; 294 295struct fw_filter_wr { 296 __be32 op_pkd; 297 __be32 len16_pkd; 298 __be64 r3; 299 __be32 tid_to_iq; 300 __be32 del_filter_to_l2tix; 301 __be16 ethtype; 302 __be16 ethtypem; 303 __u8 frag_to_ovlan_vldm; 304 __u8 smac_sel; 305 __be16 rx_chan_rx_rpl_iq; 306 __be32 maci_to_matchtypem; 307 __u8 ptcl; 308 __u8 ptclm; 309 __u8 ttyp; 310 __u8 ttypm; 311 __be16 ivlan; 312 __be16 ivlanm; 313 __be16 ovlan; 314 __be16 ovlanm; 315 __u8 lip[16]; 316 __u8 lipm[16]; 317 __u8 fip[16]; 318 __u8 fipm[16]; 319 __be16 lp; 320 __be16 lpm; 321 __be16 fp; 322 __be16 fpm; 323 __be16 r7; 324 __u8 sma[6]; 325}; 326 327#define S_FW_FILTER_WR_TID 12 328#define M_FW_FILTER_WR_TID 0xfffff 329#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 330#define G_FW_FILTER_WR_TID(x) \ 331 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 332 333#define S_FW_FILTER_WR_RQTYPE 11 334#define M_FW_FILTER_WR_RQTYPE 0x1 335#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 336#define G_FW_FILTER_WR_RQTYPE(x) \ 337 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 338#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 339 340#define S_FW_FILTER_WR_NOREPLY 10 341#define M_FW_FILTER_WR_NOREPLY 0x1 342#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 343#define G_FW_FILTER_WR_NOREPLY(x) \ 344 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 345#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 346 347#define S_FW_FILTER_WR_IQ 0 348#define M_FW_FILTER_WR_IQ 0x3ff 349#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 350#define G_FW_FILTER_WR_IQ(x) \ 351 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 352 353#define S_FW_FILTER_WR_DEL_FILTER 31 354#define M_FW_FILTER_WR_DEL_FILTER 0x1 355#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 356#define G_FW_FILTER_WR_DEL_FILTER(x) \ 357 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 358#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 359 360#define S_FW_FILTER_WR_RPTTID 25 361#define M_FW_FILTER_WR_RPTTID 0x1 362#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 363#define G_FW_FILTER_WR_RPTTID(x) \ 364 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 365#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 366 367#define S_FW_FILTER_WR_DROP 24 368#define M_FW_FILTER_WR_DROP 0x1 369#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 370#define G_FW_FILTER_WR_DROP(x) \ 371 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 372#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 373 374#define S_FW_FILTER_WR_DIRSTEER 23 375#define M_FW_FILTER_WR_DIRSTEER 0x1 376#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 377#define G_FW_FILTER_WR_DIRSTEER(x) \ 378 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 379#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 380 381#define S_FW_FILTER_WR_MASKHASH 22 382#define M_FW_FILTER_WR_MASKHASH 0x1 383#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 384#define G_FW_FILTER_WR_MASKHASH(x) \ 385 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 386#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 387 388#define S_FW_FILTER_WR_DIRSTEERHASH 21 389#define M_FW_FILTER_WR_DIRSTEERHASH 0x1 390#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 391#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 392 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 393#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 394 395#define S_FW_FILTER_WR_LPBK 20 396#define M_FW_FILTER_WR_LPBK 0x1 397#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 398#define G_FW_FILTER_WR_LPBK(x) \ 399 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 400#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 401 402#define S_FW_FILTER_WR_DMAC 19 403#define M_FW_FILTER_WR_DMAC 0x1 404#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 405#define G_FW_FILTER_WR_DMAC(x) \ 406 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 407#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 408 409#define S_FW_FILTER_WR_SMAC 18 410#define M_FW_FILTER_WR_SMAC 0x1 411#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 412#define G_FW_FILTER_WR_SMAC(x) \ 413 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 414#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 415 416#define S_FW_FILTER_WR_INSVLAN 17 417#define M_FW_FILTER_WR_INSVLAN 0x1 418#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 419#define G_FW_FILTER_WR_INSVLAN(x) \ 420 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 421#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 422 423#define S_FW_FILTER_WR_RMVLAN 16 424#define M_FW_FILTER_WR_RMVLAN 0x1 425#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 426#define G_FW_FILTER_WR_RMVLAN(x) \ 427 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 428#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 429 430#define S_FW_FILTER_WR_HITCNTS 15 431#define M_FW_FILTER_WR_HITCNTS 0x1 432#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 433#define G_FW_FILTER_WR_HITCNTS(x) \ 434 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 435#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 436 437#define S_FW_FILTER_WR_TXCHAN 13 438#define M_FW_FILTER_WR_TXCHAN 0x3 439#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 440#define G_FW_FILTER_WR_TXCHAN(x) \ 441 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 442 443#define S_FW_FILTER_WR_PRIO 12 444#define M_FW_FILTER_WR_PRIO 0x1 445#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 446#define G_FW_FILTER_WR_PRIO(x) \ 447 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 448#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 449 450#define S_FW_FILTER_WR_L2TIX 0 451#define M_FW_FILTER_WR_L2TIX 0xfff 452#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 453#define G_FW_FILTER_WR_L2TIX(x) \ 454 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 455 456#define S_FW_FILTER_WR_FRAG 7 457#define M_FW_FILTER_WR_FRAG 0x1 458#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 459#define G_FW_FILTER_WR_FRAG(x) \ 460 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 461#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 462 463#define S_FW_FILTER_WR_FRAGM 6 464#define M_FW_FILTER_WR_FRAGM 0x1 465#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 466#define G_FW_FILTER_WR_FRAGM(x) \ 467 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 468#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 469 470#define S_FW_FILTER_WR_IVLAN_VLD 5 471#define M_FW_FILTER_WR_IVLAN_VLD 0x1 472#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 473#define G_FW_FILTER_WR_IVLAN_VLD(x) \ 474 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 475#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 476 477#define S_FW_FILTER_WR_OVLAN_VLD 4 478#define M_FW_FILTER_WR_OVLAN_VLD 0x1 479#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 480#define G_FW_FILTER_WR_OVLAN_VLD(x) \ 481 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 482#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 483 484#define S_FW_FILTER_WR_IVLAN_VLDM 3 485#define M_FW_FILTER_WR_IVLAN_VLDM 0x1 486#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 487#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 488 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 489#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 490 491#define S_FW_FILTER_WR_OVLAN_VLDM 2 492#define M_FW_FILTER_WR_OVLAN_VLDM 0x1 493#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 494#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 495 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 496#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 497 498#define S_FW_FILTER_WR_RX_CHAN 15 499#define M_FW_FILTER_WR_RX_CHAN 0x1 500#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 501#define G_FW_FILTER_WR_RX_CHAN(x) \ 502 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 503#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 504 505#define S_FW_FILTER_WR_RX_RPL_IQ 0 506#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 507#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 508#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 509 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 510 511#define S_FW_FILTER_WR_MACI 23 512#define M_FW_FILTER_WR_MACI 0x1ff 513#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 514#define G_FW_FILTER_WR_MACI(x) \ 515 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 516 517#define S_FW_FILTER_WR_MACIM 14 518#define M_FW_FILTER_WR_MACIM 0x1ff 519#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 520#define G_FW_FILTER_WR_MACIM(x) \ 521 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 522 523#define S_FW_FILTER_WR_FCOE 13 524#define M_FW_FILTER_WR_FCOE 0x1 525#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 526#define G_FW_FILTER_WR_FCOE(x) \ 527 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 528#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 529 530#define S_FW_FILTER_WR_FCOEM 12 531#define M_FW_FILTER_WR_FCOEM 0x1 532#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 533#define G_FW_FILTER_WR_FCOEM(x) \ 534 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 535#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 536 537#define S_FW_FILTER_WR_PORT 9 538#define M_FW_FILTER_WR_PORT 0x7 539#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 540#define G_FW_FILTER_WR_PORT(x) \ 541 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 542 543#define S_FW_FILTER_WR_PORTM 6 544#define M_FW_FILTER_WR_PORTM 0x7 545#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 546#define G_FW_FILTER_WR_PORTM(x) \ 547 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 548 549#define S_FW_FILTER_WR_MATCHTYPE 3 550#define M_FW_FILTER_WR_MATCHTYPE 0x7 551#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 552#define G_FW_FILTER_WR_MATCHTYPE(x) \ 553 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 554 555#define S_FW_FILTER_WR_MATCHTYPEM 0 556#define M_FW_FILTER_WR_MATCHTYPEM 0x7 557#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 558#define G_FW_FILTER_WR_MATCHTYPEM(x) \ 559 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 560 561struct fw_ulptx_wr { 562 __be32 op_to_compl; 563 __be32 flowid_len16; 564 __u64 cookie; 565}; 566 567struct fw_tp_wr { 568 __be32 op_to_immdlen; 569 __be32 flowid_len16; 570 __u64 cookie; 571}; 572 573struct fw_eth_tx_pkt_wr { 574 __be32 op_immdlen; 575 __be32 equiq_to_len16; 576 __be64 r3; 577}; 578 579#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 580#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 581#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 582#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 583 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 584 585struct fw_eth_tx_pkt2_wr { 586 __be32 op_immdlen; 587 __be32 equiq_to_len16; 588 __be32 r3; 589 __be32 L4ChkDisable_to_IpHdrLen; 590}; 591 592#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 593#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 594#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 595#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 596 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 597 598#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 599#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 600#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 601 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 602#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 603 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 604 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 605#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 606 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 607 608#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 609#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 610#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 611 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 612#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 613 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 614 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 615#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 616 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 617 618#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 619#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 620#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 621#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 622 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 623#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 624 625#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 626#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 627#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 628#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 629 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 630 631#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 632#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 633#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 634#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 635 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 636 637#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 638#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 639#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 640#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 641 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 642 643struct fw_eth_tx_pkts_wr { 644 __be32 op_pkd; 645 __be32 equiq_to_len16; 646 __be32 r3; 647 __be16 plen; 648 __u8 npkt; 649 __u8 type; 650}; 651 652#define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 653#define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 654#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 655#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 656 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 657 658struct fw_eth_tx_pkt_ptp_wr { 659 __be32 op_immdlen; 660 __be32 equiq_to_len16; 661 __be64 r3; 662}; 663 664enum fw_eth_tx_eo_type { 665 FW_ETH_TX_EO_TYPE_UDPSEG, 666 FW_ETH_TX_EO_TYPE_TCPSEG, 667 FW_ETH_TX_EO_TYPE_NVGRESEG, 668 FW_ETH_TX_EO_TYPE_VXLANSEG, 669 FW_ETH_TX_EO_TYPE_GENEVESEG, 670}; 671 672struct fw_eth_tx_eo_wr { 673 __be32 op_immdlen; 674 __be32 equiq_to_len16; 675 __be64 r3; 676 union fw_eth_tx_eo { 677 struct fw_eth_tx_eo_udpseg { 678 __u8 type; 679 __u8 ethlen; 680 __be16 iplen; 681 __u8 udplen; 682 __u8 rtplen; 683 __be16 r4; 684 __be16 mss; 685 __be16 schedpktsize; 686 __be32 plen; 687 } udpseg; 688 struct fw_eth_tx_eo_tcpseg { 689 __u8 type; 690 __u8 ethlen; 691 __be16 iplen; 692 __u8 tcplen; 693 __u8 tsclk_tsoff; 694 __be16 r4; 695 __be16 mss; 696 __be16 r5; 697 __be32 plen; 698 } tcpseg; 699 struct fw_eth_tx_eo_nvgreseg { 700 __u8 type; 701 __u8 iphdroffout; 702 __be16 grehdroff; 703 __be16 iphdroffin; 704 __be16 tcphdroffin; 705 __be16 mss; 706 __be16 r4; 707 __be32 plen; 708 } nvgreseg; 709 struct fw_eth_tx_eo_vxlanseg { 710 __u8 type; 711 __u8 iphdroffout; 712 __be16 vxlanhdroff; 713 __be16 iphdroffin; 714 __be16 tcphdroffin; 715 __be16 mss; 716 __be16 r4; 717 __be32 plen; 718 719 } vxlanseg; 720 struct fw_eth_tx_eo_geneveseg { 721 __u8 type; 722 __u8 iphdroffout; 723 __be16 genevehdroff; 724 __be16 iphdroffin; 725 __be16 tcphdroffin; 726 __be16 mss; 727 __be16 r4; 728 __be32 plen; 729 } geneveseg; 730 } u; 731}; 732 733#define S_FW_ETH_TX_EO_WR_IMMDLEN 0 734#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 735#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 736#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 737 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 738 739#define S_FW_ETH_TX_EO_WR_TSCLK 6 740#define M_FW_ETH_TX_EO_WR_TSCLK 0x3 741#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 742#define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 743 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 744 745#define S_FW_ETH_TX_EO_WR_TSOFF 0 746#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 747#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 748#define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 749 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 750 751struct fw_eq_flush_wr { 752 __u8 opcode; 753 __u8 r1[3]; 754 __be32 equiq_to_len16; 755 __be64 r3; 756}; 757 758struct fw_ofld_connection_wr { 759 __be32 op_compl; 760 __be32 len16_pkd; 761 __u64 cookie; 762 __be64 r2; 763 __be64 r3; 764 struct fw_ofld_connection_le { 765 __be32 version_cpl; 766 __be32 filter; 767 __be32 r1; 768 __be16 lport; 769 __be16 pport; 770 union fw_ofld_connection_leip { 771 struct fw_ofld_connection_le_ipv4 { 772 __be32 pip; 773 __be32 lip; 774 __be64 r0; 775 __be64 r1; 776 __be64 r2; 777 } ipv4; 778 struct fw_ofld_connection_le_ipv6 { 779 __be64 pip_hi; 780 __be64 pip_lo; 781 __be64 lip_hi; 782 __be64 lip_lo; 783 } ipv6; 784 } u; 785 } le; 786 struct fw_ofld_connection_tcb { 787 __be32 t_state_to_astid; 788 __be16 cplrxdataack_cplpassacceptrpl; 789 __be16 rcv_adv; 790 __be32 rcv_nxt; 791 __be32 tx_max; 792 __be64 opt0; 793 __be32 opt2; 794 __be32 r1; 795 __be64 r2; 796 __be64 r3; 797 } tcb; 798}; 799 800#define S_FW_OFLD_CONNECTION_WR_VERSION 31 801#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 802#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 803 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 804#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 805 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 806 M_FW_OFLD_CONNECTION_WR_VERSION) 807#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 808 809#define S_FW_OFLD_CONNECTION_WR_CPL 30 810#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 811#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 812#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 813 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 814#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 815 816#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 817#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 818#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 819 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 820#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 821 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 822 M_FW_OFLD_CONNECTION_WR_T_STATE) 823 824#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 825#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 826#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 827 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 828#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 829 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 830 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 831 832#define S_FW_OFLD_CONNECTION_WR_ASTID 0 833#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 834#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 835 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 836#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 837 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 838 839#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 840#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 841#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 842 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 843#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 844 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 845 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 846#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 847 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 848 849#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 850#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 851#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 852 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 853#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 854 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 855 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 856#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 857 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 858 859enum fw_flowc_mnem_tcpstate { 860 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 861 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 862 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 863 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 864 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 865 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 866 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 867 * will resend FIN - equiv ESTAB 868 */ 869 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 870 * will resend FIN but have 871 * received FIN 872 */ 873 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 874 * will resend FIN but have 875 * received FIN 876 */ 877 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 878 * waiting for FIN 879 */ 880 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 881}; 882 883enum fw_flowc_mnem_eostate { 884 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 885 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 886 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 887 * outstanding payload 888 */ 889 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 890 * discarding outstanding payload 891 */ 892}; 893 894enum fw_flowc_mnem { 895 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 896 FW_FLOWC_MNEM_CH = 1, 897 FW_FLOWC_MNEM_PORT = 2, 898 FW_FLOWC_MNEM_IQID = 3, 899 FW_FLOWC_MNEM_SNDNXT = 4, 900 FW_FLOWC_MNEM_RCVNXT = 5, 901 FW_FLOWC_MNEM_SNDBUF = 6, 902 FW_FLOWC_MNEM_MSS = 7, 903 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 904 FW_FLOWC_MNEM_TCPSTATE = 9, 905 FW_FLOWC_MNEM_EOSTATE = 10, 906 FW_FLOWC_MNEM_SCHEDCLASS = 11, 907 FW_FLOWC_MNEM_DCBPRIO = 12, 908 FW_FLOWC_MNEM_SND_SCALE = 13, 909 FW_FLOWC_MNEM_RCV_SCALE = 14, 910}; 911 912struct fw_flowc_mnemval { 913 __u8 mnemonic; 914 __u8 r4[3]; 915 __be32 val; 916}; 917 918struct fw_flowc_wr { 919 __be32 op_to_nparams; 920 __be32 flowid_len16; 921#ifndef C99_NOT_SUPPORTED 922 struct fw_flowc_mnemval mnemval[0]; 923#endif 924}; 925 926#define S_FW_FLOWC_WR_NPARAMS 0 927#define M_FW_FLOWC_WR_NPARAMS 0xff 928#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 929#define G_FW_FLOWC_WR_NPARAMS(x) \ 930 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 931 932struct fw_ofld_tx_data_wr { 933 __be32 op_to_immdlen; 934 __be32 flowid_len16; 935 __be32 plen; 936 __be32 lsodisable_to_flags; 937}; 938 939#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 940#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 941#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 942 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 943#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 944 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 945 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 946#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 947 948#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 949#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 950#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 951 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 952#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 953 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 954#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 955 956#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 957#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 958#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 959 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 960#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 961 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 962 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 963#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 964 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 965 966#define S_FW_OFLD_TX_DATA_WR_FLAGS 0 967#define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 968#define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 969#define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 970 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 971 972 973/* Use fw_ofld_tx_data_wr structure */ 974#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 975#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 976#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 977 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 978#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 979 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 980 981#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 982#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 983#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 984 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 985#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 986 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 987 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 988#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 989 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 990 991#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 992#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 993#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 994 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 995#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 996 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 997 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 998#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 999 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1000 1001#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1002#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1003#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1004 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1005#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1006 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1007 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1008#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1009 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1010 1011#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1012#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1013#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1014 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1015#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1016 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1017 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1018#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1019 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1020 1021#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1022#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1023#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1024 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1025#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1026 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1027 1028struct fw_cmd_wr { 1029 __be32 op_dma; 1030 __be32 len16_pkd; 1031 __be64 cookie_daddr; 1032}; 1033 1034#define S_FW_CMD_WR_DMA 17 1035#define M_FW_CMD_WR_DMA 0x1 1036#define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1037#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1038#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1039 1040struct fw_eth_tx_pkt_vm_wr { 1041 __be32 op_immdlen; 1042 __be32 equiq_to_len16; 1043 __be32 r3[2]; 1044 __u8 ethmacdst[6]; 1045 __u8 ethmacsrc[6]; 1046 __be16 ethtype; 1047 __be16 vlantci; 1048}; 1049 1050/****************************************************************************** 1051 * R I W O R K R E Q U E S T s 1052 **************************************/ 1053 1054enum fw_ri_wr_opcode { 1055 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1056 FW_RI_READ_REQ = 0x1, 1057 FW_RI_READ_RESP = 0x2, 1058 FW_RI_SEND = 0x3, 1059 FW_RI_SEND_WITH_INV = 0x4, 1060 FW_RI_SEND_WITH_SE = 0x5, 1061 FW_RI_SEND_WITH_SE_INV = 0x6, 1062 FW_RI_TERMINATE = 0x7, 1063 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1064 FW_RI_BIND_MW = 0x9, 1065 FW_RI_FAST_REGISTER = 0xa, 1066 FW_RI_LOCAL_INV = 0xb, 1067 FW_RI_QP_MODIFY = 0xc, 1068 FW_RI_BYPASS = 0xd, 1069 FW_RI_RECEIVE = 0xe, 1070#if 0 1071 FW_RI_SEND_IMMEDIATE = 0x8, 1072 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1073 FW_RI_ATOMIC_REQUEST = 0xa, 1074 FW_RI_ATOMIC_RESPONSE = 0xb, 1075 1076 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1077 FW_RI_FAST_REGISTER = 0xd, 1078 FW_RI_LOCAL_INV = 0xe, 1079#endif 1080 FW_RI_SGE_EC_CR_RETURN = 0xf 1081}; 1082 1083enum fw_ri_wr_flags { 1084 FW_RI_COMPLETION_FLAG = 0x01, 1085 FW_RI_NOTIFICATION_FLAG = 0x02, 1086 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1087 FW_RI_READ_FENCE_FLAG = 0x08, 1088 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1089 FW_RI_RDMA_READ_INVALIDATE = 0x20 1090}; 1091 1092enum fw_ri_mpa_attrs { 1093 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1094 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1095 FW_RI_MPA_CRC_ENABLE = 0x04, 1096 FW_RI_MPA_IETF_ENABLE = 0x08 1097}; 1098 1099enum fw_ri_qp_caps { 1100 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1101 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1102 FW_RI_QP_BIND_ENABLE = 0x04, 1103 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1104 FW_RI_QP_STAG0_ENABLE = 0x10, 1105 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1106}; 1107 1108enum fw_ri_addr_type { 1109 FW_RI_ZERO_BASED_TO = 0x00, 1110 FW_RI_VA_BASED_TO = 0x01 1111}; 1112 1113enum fw_ri_mem_perms { 1114 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1115 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1116 FW_RI_MEM_ACCESS_REM = 0x03, 1117 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1118 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1119 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1120}; 1121 1122enum fw_ri_stag_type { 1123 FW_RI_STAG_NSMR = 0x00, 1124 FW_RI_STAG_SMR = 0x01, 1125 FW_RI_STAG_MW = 0x02, 1126 FW_RI_STAG_MW_RELAXED = 0x03 1127}; 1128 1129enum fw_ri_data_op { 1130 FW_RI_DATA_IMMD = 0x81, 1131 FW_RI_DATA_DSGL = 0x82, 1132 FW_RI_DATA_ISGL = 0x83 1133}; 1134 1135enum fw_ri_sgl_depth { 1136 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1137 FW_RI_SGL_DEPTH_MAX_RQ = 4 1138}; 1139 1140enum fw_ri_cqe_err { 1141 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1142 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1143 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1144 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1145 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1146 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1147 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1148 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1149 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1150 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1151 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1152 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1153 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1154 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1155 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1156 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1157 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1158 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1159 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1160 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1161 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1162 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1163 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1164 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1165 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1166 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1167 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1168 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1169 1170}; 1171 1172struct fw_ri_dsge_pair { 1173 __be32 len[2]; 1174 __be64 addr[2]; 1175}; 1176 1177struct fw_ri_dsgl { 1178 __u8 op; 1179 __u8 r1; 1180 __be16 nsge; 1181 __be32 len0; 1182 __be64 addr0; 1183#ifndef C99_NOT_SUPPORTED 1184 struct fw_ri_dsge_pair sge[0]; 1185#endif 1186}; 1187 1188struct fw_ri_sge { 1189 __be32 stag; 1190 __be32 len; 1191 __be64 to; 1192}; 1193 1194struct fw_ri_isgl { 1195 __u8 op; 1196 __u8 r1; 1197 __be16 nsge; 1198 __be32 r2; 1199#ifndef C99_NOT_SUPPORTED 1200 struct fw_ri_sge sge[0]; 1201#endif 1202}; 1203 1204struct fw_ri_immd { 1205 __u8 op; 1206 __u8 r1; 1207 __be16 r2; 1208 __be32 immdlen; 1209#ifndef C99_NOT_SUPPORTED 1210 __u8 data[0]; 1211#endif 1212}; 1213 1214struct fw_ri_tpte { 1215 __be32 valid_to_pdid; 1216 __be32 locread_to_qpid; 1217 __be32 nosnoop_pbladdr; 1218 __be32 len_lo; 1219 __be32 va_hi; 1220 __be32 va_lo_fbo; 1221 __be32 dca_mwbcnt_pstag; 1222 __be32 len_hi; 1223}; 1224 1225#define S_FW_RI_TPTE_VALID 31 1226#define M_FW_RI_TPTE_VALID 0x1 1227#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1228#define G_FW_RI_TPTE_VALID(x) \ 1229 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1230#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1231 1232#define S_FW_RI_TPTE_STAGKEY 23 1233#define M_FW_RI_TPTE_STAGKEY 0xff 1234#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1235#define G_FW_RI_TPTE_STAGKEY(x) \ 1236 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1237 1238#define S_FW_RI_TPTE_STAGSTATE 22 1239#define M_FW_RI_TPTE_STAGSTATE 0x1 1240#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1241#define G_FW_RI_TPTE_STAGSTATE(x) \ 1242 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1243#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1244 1245#define S_FW_RI_TPTE_STAGTYPE 20 1246#define M_FW_RI_TPTE_STAGTYPE 0x3 1247#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1248#define G_FW_RI_TPTE_STAGTYPE(x) \ 1249 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1250 1251#define S_FW_RI_TPTE_PDID 0 1252#define M_FW_RI_TPTE_PDID 0xfffff 1253#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1254#define G_FW_RI_TPTE_PDID(x) \ 1255 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1256 1257#define S_FW_RI_TPTE_PERM 28 1258#define M_FW_RI_TPTE_PERM 0xf 1259#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1260#define G_FW_RI_TPTE_PERM(x) \ 1261 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1262 1263#define S_FW_RI_TPTE_REMINVDIS 27 1264#define M_FW_RI_TPTE_REMINVDIS 0x1 1265#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1266#define G_FW_RI_TPTE_REMINVDIS(x) \ 1267 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1268#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1269 1270#define S_FW_RI_TPTE_ADDRTYPE 26 1271#define M_FW_RI_TPTE_ADDRTYPE 1 1272#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1273#define G_FW_RI_TPTE_ADDRTYPE(x) \ 1274 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1275#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1276 1277#define S_FW_RI_TPTE_MWBINDEN 25 1278#define M_FW_RI_TPTE_MWBINDEN 0x1 1279#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1280#define G_FW_RI_TPTE_MWBINDEN(x) \ 1281 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1282#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1283 1284#define S_FW_RI_TPTE_PS 20 1285#define M_FW_RI_TPTE_PS 0x1f 1286#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1287#define G_FW_RI_TPTE_PS(x) \ 1288 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1289 1290#define S_FW_RI_TPTE_QPID 0 1291#define M_FW_RI_TPTE_QPID 0xfffff 1292#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1293#define G_FW_RI_TPTE_QPID(x) \ 1294 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1295 1296#define S_FW_RI_TPTE_NOSNOOP 31 1297#define M_FW_RI_TPTE_NOSNOOP 0x1 1298#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1299#define G_FW_RI_TPTE_NOSNOOP(x) \ 1300 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1301#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1302 1303#define S_FW_RI_TPTE_PBLADDR 0 1304#define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1305#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1306#define G_FW_RI_TPTE_PBLADDR(x) \ 1307 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1308 1309#define S_FW_RI_TPTE_DCA 24 1310#define M_FW_RI_TPTE_DCA 0x1f 1311#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1312#define G_FW_RI_TPTE_DCA(x) \ 1313 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1314 1315#define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1316#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1317#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1318 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1319#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1320 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1321 1322enum fw_ri_cqe_rxtx { 1323 FW_RI_CQE_RXTX_RX = 0x0, 1324 FW_RI_CQE_RXTX_TX = 0x1, 1325}; 1326 1327struct fw_ri_cqe { 1328 union fw_ri_rxtx { 1329 struct fw_ri_scqe { 1330 __be32 qpid_n_stat_rxtx_type; 1331 __be32 plen; 1332 __be32 reserved; 1333 __be32 wrid; 1334 } scqe; 1335 struct fw_ri_rcqe { 1336 __be32 qpid_n_stat_rxtx_type; 1337 __be32 plen; 1338 __be32 stag; 1339 __be32 msn; 1340 } rcqe; 1341 } u; 1342}; 1343 1344#define S_FW_RI_CQE_QPID 12 1345#define M_FW_RI_CQE_QPID 0xfffff 1346#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1347#define G_FW_RI_CQE_QPID(x) \ 1348 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1349 1350#define S_FW_RI_CQE_NOTIFY 10 1351#define M_FW_RI_CQE_NOTIFY 0x1 1352#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1353#define G_FW_RI_CQE_NOTIFY(x) \ 1354 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1355 1356#define S_FW_RI_CQE_STATUS 5 1357#define M_FW_RI_CQE_STATUS 0x1f 1358#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1359#define G_FW_RI_CQE_STATUS(x) \ 1360 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1361 1362 1363#define S_FW_RI_CQE_RXTX 4 1364#define M_FW_RI_CQE_RXTX 0x1 1365#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1366#define G_FW_RI_CQE_RXTX(x) \ 1367 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1368 1369#define S_FW_RI_CQE_TYPE 0 1370#define M_FW_RI_CQE_TYPE 0xf 1371#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1372#define G_FW_RI_CQE_TYPE(x) \ 1373 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1374 1375enum fw_ri_res_type { 1376 FW_RI_RES_TYPE_SQ, 1377 FW_RI_RES_TYPE_RQ, 1378 FW_RI_RES_TYPE_CQ, 1379}; 1380 1381enum fw_ri_res_op { 1382 FW_RI_RES_OP_WRITE, 1383 FW_RI_RES_OP_RESET, 1384}; 1385 1386struct fw_ri_res { 1387 union fw_ri_restype { 1388 struct fw_ri_res_sqrq { 1389 __u8 restype; 1390 __u8 op; 1391 __be16 r3; 1392 __be32 eqid; 1393 __be32 r4[2]; 1394 __be32 fetchszm_to_iqid; 1395 __be32 dcaen_to_eqsize; 1396 __be64 eqaddr; 1397 } sqrq; 1398 struct fw_ri_res_cq { 1399 __u8 restype; 1400 __u8 op; 1401 __be16 r3; 1402 __be32 iqid; 1403 __be32 r4[2]; 1404 __be32 iqandst_to_iqandstindex; 1405 __be16 iqdroprss_to_iqesize; 1406 __be16 iqsize; 1407 __be64 iqaddr; 1408 __be32 iqns_iqro; 1409 __be32 r6_lo; 1410 __be64 r7; 1411 } cq; 1412 } u; 1413}; 1414 1415struct fw_ri_res_wr { 1416 __be32 op_nres; 1417 __be32 len16_pkd; 1418 __u64 cookie; 1419#ifndef C99_NOT_SUPPORTED 1420 struct fw_ri_res res[0]; 1421#endif 1422}; 1423 1424#define S_FW_RI_RES_WR_NRES 0 1425#define M_FW_RI_RES_WR_NRES 0xff 1426#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1427#define G_FW_RI_RES_WR_NRES(x) \ 1428 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1429 1430#define S_FW_RI_RES_WR_FETCHSZM 26 1431#define M_FW_RI_RES_WR_FETCHSZM 0x1 1432#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1433#define G_FW_RI_RES_WR_FETCHSZM(x) \ 1434 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1435#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1436 1437#define S_FW_RI_RES_WR_STATUSPGNS 25 1438#define M_FW_RI_RES_WR_STATUSPGNS 0x1 1439#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1440#define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1441 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1442#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1443 1444#define S_FW_RI_RES_WR_STATUSPGRO 24 1445#define M_FW_RI_RES_WR_STATUSPGRO 0x1 1446#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1447#define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1448 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1449#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1450 1451#define S_FW_RI_RES_WR_FETCHNS 23 1452#define M_FW_RI_RES_WR_FETCHNS 0x1 1453#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1454#define G_FW_RI_RES_WR_FETCHNS(x) \ 1455 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1456#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1457 1458#define S_FW_RI_RES_WR_FETCHRO 22 1459#define M_FW_RI_RES_WR_FETCHRO 0x1 1460#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1461#define G_FW_RI_RES_WR_FETCHRO(x) \ 1462 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1463#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1464 1465#define S_FW_RI_RES_WR_HOSTFCMODE 20 1466#define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1467#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1468#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1469 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1470 1471#define S_FW_RI_RES_WR_CPRIO 19 1472#define M_FW_RI_RES_WR_CPRIO 0x1 1473#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1474#define G_FW_RI_RES_WR_CPRIO(x) \ 1475 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1476#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1477 1478#define S_FW_RI_RES_WR_ONCHIP 18 1479#define M_FW_RI_RES_WR_ONCHIP 0x1 1480#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1481#define G_FW_RI_RES_WR_ONCHIP(x) \ 1482 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1483#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1484 1485#define S_FW_RI_RES_WR_PCIECHN 16 1486#define M_FW_RI_RES_WR_PCIECHN 0x3 1487#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1488#define G_FW_RI_RES_WR_PCIECHN(x) \ 1489 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1490 1491#define S_FW_RI_RES_WR_IQID 0 1492#define M_FW_RI_RES_WR_IQID 0xffff 1493#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1494#define G_FW_RI_RES_WR_IQID(x) \ 1495 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1496 1497#define S_FW_RI_RES_WR_DCAEN 31 1498#define M_FW_RI_RES_WR_DCAEN 0x1 1499#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1500#define G_FW_RI_RES_WR_DCAEN(x) \ 1501 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1502#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1503 1504#define S_FW_RI_RES_WR_DCACPU 26 1505#define M_FW_RI_RES_WR_DCACPU 0x1f 1506#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1507#define G_FW_RI_RES_WR_DCACPU(x) \ 1508 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1509 1510#define S_FW_RI_RES_WR_FBMIN 23 1511#define M_FW_RI_RES_WR_FBMIN 0x7 1512#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1513#define G_FW_RI_RES_WR_FBMIN(x) \ 1514 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1515 1516#define S_FW_RI_RES_WR_FBMAX 20 1517#define M_FW_RI_RES_WR_FBMAX 0x7 1518#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1519#define G_FW_RI_RES_WR_FBMAX(x) \ 1520 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1521 1522#define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1523#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1524#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1525#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1526 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1527#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1528 1529#define S_FW_RI_RES_WR_CIDXFTHRESH 16 1530#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1531#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1532#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1533 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1534 1535#define S_FW_RI_RES_WR_EQSIZE 0 1536#define M_FW_RI_RES_WR_EQSIZE 0xffff 1537#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1538#define G_FW_RI_RES_WR_EQSIZE(x) \ 1539 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1540 1541#define S_FW_RI_RES_WR_IQANDST 15 1542#define M_FW_RI_RES_WR_IQANDST 0x1 1543#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1544#define G_FW_RI_RES_WR_IQANDST(x) \ 1545 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1546#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1547 1548#define S_FW_RI_RES_WR_IQANUS 14 1549#define M_FW_RI_RES_WR_IQANUS 0x1 1550#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1551#define G_FW_RI_RES_WR_IQANUS(x) \ 1552 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1553#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1554 1555#define S_FW_RI_RES_WR_IQANUD 12 1556#define M_FW_RI_RES_WR_IQANUD 0x3 1557#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1558#define G_FW_RI_RES_WR_IQANUD(x) \ 1559 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1560 1561#define S_FW_RI_RES_WR_IQANDSTINDEX 0 1562#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1563#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1564#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1565 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1566 1567#define S_FW_RI_RES_WR_IQDROPRSS 15 1568#define M_FW_RI_RES_WR_IQDROPRSS 0x1 1569#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1570#define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1571 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1572#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1573 1574#define S_FW_RI_RES_WR_IQGTSMODE 14 1575#define M_FW_RI_RES_WR_IQGTSMODE 0x1 1576#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1577#define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1578 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1579#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1580 1581#define S_FW_RI_RES_WR_IQPCIECH 12 1582#define M_FW_RI_RES_WR_IQPCIECH 0x3 1583#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1584#define G_FW_RI_RES_WR_IQPCIECH(x) \ 1585 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1586 1587#define S_FW_RI_RES_WR_IQDCAEN 11 1588#define M_FW_RI_RES_WR_IQDCAEN 0x1 1589#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1590#define G_FW_RI_RES_WR_IQDCAEN(x) \ 1591 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1592#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1593 1594#define S_FW_RI_RES_WR_IQDCACPU 6 1595#define M_FW_RI_RES_WR_IQDCACPU 0x1f 1596#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1597#define G_FW_RI_RES_WR_IQDCACPU(x) \ 1598 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1599 1600#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1601#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1602#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1603 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1604#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1605 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1606 1607#define S_FW_RI_RES_WR_IQO 3 1608#define M_FW_RI_RES_WR_IQO 0x1 1609#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1610#define G_FW_RI_RES_WR_IQO(x) \ 1611 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1612#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1613 1614#define S_FW_RI_RES_WR_IQCPRIO 2 1615#define M_FW_RI_RES_WR_IQCPRIO 0x1 1616#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1617#define G_FW_RI_RES_WR_IQCPRIO(x) \ 1618 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1619#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1620 1621#define S_FW_RI_RES_WR_IQESIZE 0 1622#define M_FW_RI_RES_WR_IQESIZE 0x3 1623#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1624#define G_FW_RI_RES_WR_IQESIZE(x) \ 1625 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1626 1627#define S_FW_RI_RES_WR_IQNS 31 1628#define M_FW_RI_RES_WR_IQNS 0x1 1629#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1630#define G_FW_RI_RES_WR_IQNS(x) \ 1631 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1632#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1633 1634#define S_FW_RI_RES_WR_IQRO 30 1635#define M_FW_RI_RES_WR_IQRO 0x1 1636#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1637#define G_FW_RI_RES_WR_IQRO(x) \ 1638 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1639#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1640 1641struct fw_ri_rdma_write_wr { 1642 __u8 opcode; 1643 __u8 flags; 1644 __u16 wrid; 1645 __u8 r1[3]; 1646 __u8 len16; 1647 __be64 r2; 1648 __be32 plen; 1649 __be32 stag_sink; 1650 __be64 to_sink; 1651#ifndef C99_NOT_SUPPORTED 1652 union { 1653 struct fw_ri_immd immd_src[0]; 1654 struct fw_ri_isgl isgl_src[0]; 1655 } u; 1656#endif 1657}; 1658 1659struct fw_ri_send_wr { 1660 __u8 opcode; 1661 __u8 flags; 1662 __u16 wrid; 1663 __u8 r1[3]; 1664 __u8 len16; 1665 __be32 sendop_pkd; 1666 __be32 stag_inv; 1667 __be32 plen; 1668 __be32 r3; 1669 __be64 r4; 1670#ifndef C99_NOT_SUPPORTED 1671 union { 1672 struct fw_ri_immd immd_src[0]; 1673 struct fw_ri_isgl isgl_src[0]; 1674 } u; 1675#endif 1676}; 1677 1678#define S_FW_RI_SEND_WR_SENDOP 0 1679#define M_FW_RI_SEND_WR_SENDOP 0xf 1680#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1681#define G_FW_RI_SEND_WR_SENDOP(x) \ 1682 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1683 1684struct fw_ri_rdma_read_wr { 1685 __u8 opcode; 1686 __u8 flags; 1687 __u16 wrid; 1688 __u8 r1[3]; 1689 __u8 len16; 1690 __be64 r2; 1691 __be32 stag_sink; 1692 __be32 to_sink_hi; 1693 __be32 to_sink_lo; 1694 __be32 plen; 1695 __be32 stag_src; 1696 __be32 to_src_hi; 1697 __be32 to_src_lo; 1698 __be32 r5; 1699}; 1700 1701struct fw_ri_recv_wr { 1702 __u8 opcode; 1703 __u8 r1; 1704 __u16 wrid; 1705 __u8 r2[3]; 1706 __u8 len16; 1707 struct fw_ri_isgl isgl; 1708}; 1709 1710struct fw_ri_bind_mw_wr { 1711 __u8 opcode; 1712 __u8 flags; 1713 __u16 wrid; 1714 __u8 r1[3]; 1715 __u8 len16; 1716 __u8 qpbinde_to_dcacpu; 1717 __u8 pgsz_shift; 1718 __u8 addr_type; 1719 __u8 mem_perms; 1720 __be32 stag_mr; 1721 __be32 stag_mw; 1722 __be32 r3; 1723 __be64 len_mw; 1724 __be64 va_fbo; 1725 __be64 r4; 1726}; 1727 1728#define S_FW_RI_BIND_MW_WR_QPBINDE 6 1729#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1730#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1731#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1732 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1733#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1734 1735#define S_FW_RI_BIND_MW_WR_NS 5 1736#define M_FW_RI_BIND_MW_WR_NS 0x1 1737#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1738#define G_FW_RI_BIND_MW_WR_NS(x) \ 1739 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1740#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1741 1742#define S_FW_RI_BIND_MW_WR_DCACPU 0 1743#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1744#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1745#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1746 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1747 1748struct fw_ri_fr_nsmr_wr { 1749 __u8 opcode; 1750 __u8 flags; 1751 __u16 wrid; 1752 __u8 r1[3]; 1753 __u8 len16; 1754 __u8 qpbinde_to_dcacpu; 1755 __u8 pgsz_shift; 1756 __u8 addr_type; 1757 __u8 mem_perms; 1758 __be32 stag; 1759 __be32 len_hi; 1760 __be32 len_lo; 1761 __be32 va_hi; 1762 __be32 va_lo_fbo; 1763}; 1764 1765#define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1766#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1767#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1768#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1769 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1770#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1771 1772#define S_FW_RI_FR_NSMR_WR_NS 5 1773#define M_FW_RI_FR_NSMR_WR_NS 0x1 1774#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1775#define G_FW_RI_FR_NSMR_WR_NS(x) \ 1776 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1777#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1778 1779#define S_FW_RI_FR_NSMR_WR_DCACPU 0 1780#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1781#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1782#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1783 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1784 1785struct fw_ri_inv_lstag_wr { 1786 __u8 opcode; 1787 __u8 flags; 1788 __u16 wrid; 1789 __u8 r1[3]; 1790 __u8 len16; 1791 __be32 r2; 1792 __be32 stag_inv; 1793}; 1794 1795struct fw_ri_send_immediate_wr { 1796 __u8 opcode; 1797 __u8 flags; 1798 __u16 wrid; 1799 __u8 r1[3]; 1800 __u8 len16; 1801 __be32 sendimmop_pkd; 1802 __be32 r3; 1803 __be32 plen; 1804 __be32 r4; 1805 __be64 r5; 1806#ifndef C99_NOT_SUPPORTED 1807 struct fw_ri_immd immd_src[0]; 1808#endif 1809}; 1810 1811#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1812#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1813#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1814 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1815#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1816 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1817 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1818 1819enum fw_ri_atomic_op { 1820 FW_RI_ATOMIC_OP_FETCHADD, 1821 FW_RI_ATOMIC_OP_SWAP, 1822 FW_RI_ATOMIC_OP_CMDSWAP, 1823}; 1824 1825struct fw_ri_atomic_wr { 1826 __u8 opcode; 1827 __u8 flags; 1828 __u16 wrid; 1829 __u8 r1[3]; 1830 __u8 len16; 1831 __be32 atomicop_pkd; 1832 __be64 r3; 1833 __be32 aopcode_pkd; 1834 __be32 reqid; 1835 __be32 stag; 1836 __be32 to_hi; 1837 __be32 to_lo; 1838 __be32 addswap_data_hi; 1839 __be32 addswap_data_lo; 1840 __be32 addswap_mask_hi; 1841 __be32 addswap_mask_lo; 1842 __be32 compare_data_hi; 1843 __be32 compare_data_lo; 1844 __be32 compare_mask_hi; 1845 __be32 compare_mask_lo; 1846 __be32 r5; 1847}; 1848 1849#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1850#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1851#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1852#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1853 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1854 1855#define S_FW_RI_ATOMIC_WR_AOPCODE 0 1856#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1857#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1858#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1859 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1860 1861enum fw_ri_type { 1862 FW_RI_TYPE_INIT, 1863 FW_RI_TYPE_FINI, 1864 FW_RI_TYPE_TERMINATE 1865}; 1866 1867enum fw_ri_init_p2ptype { 1868 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1869 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1870 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1871 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1872 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1873 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1874 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1875}; 1876 1877struct fw_ri_wr { 1878 __be32 op_compl; 1879 __be32 flowid_len16; 1880 __u64 cookie; 1881 union fw_ri { 1882 struct fw_ri_init { 1883 __u8 type; 1884 __u8 mpareqbit_p2ptype; 1885 __u8 r4[2]; 1886 __u8 mpa_attrs; 1887 __u8 qp_caps; 1888 __be16 nrqe; 1889 __be32 pdid; 1890 __be32 qpid; 1891 __be32 sq_eqid; 1892 __be32 rq_eqid; 1893 __be32 scqid; 1894 __be32 rcqid; 1895 __be32 ord_max; 1896 __be32 ird_max; 1897 __be32 iss; 1898 __be32 irs; 1899 __be32 hwrqsize; 1900 __be32 hwrqaddr; 1901 __be64 r5; 1902 union fw_ri_init_p2p { 1903 struct fw_ri_rdma_write_wr write; 1904 struct fw_ri_rdma_read_wr read; 1905 struct fw_ri_send_wr send; 1906 } u; 1907 } init; 1908 struct fw_ri_fini { 1909 __u8 type; 1910 __u8 r3[7]; 1911 __be64 r4; 1912 } fini; 1913 struct fw_ri_terminate { 1914 __u8 type; 1915 __u8 r3[3]; 1916 __be32 immdlen; 1917 __u8 termmsg[40]; 1918 } terminate; 1919 } u; 1920}; 1921 1922#define S_FW_RI_WR_MPAREQBIT 7 1923#define M_FW_RI_WR_MPAREQBIT 0x1 1924#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1925#define G_FW_RI_WR_MPAREQBIT(x) \ 1926 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1927#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1928 1929#define S_FW_RI_WR_0BRRBIT 6 1930#define M_FW_RI_WR_0BRRBIT 0x1 1931#define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1932#define G_FW_RI_WR_0BRRBIT(x) \ 1933 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1934#define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1935 1936#define S_FW_RI_WR_P2PTYPE 0 1937#define M_FW_RI_WR_P2PTYPE 0xf 1938#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1939#define G_FW_RI_WR_P2PTYPE(x) \ 1940 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1941 1942/****************************************************************************** 1943 * F O i S C S I W O R K R E Q U E S T s 1944 *********************************************/ 1945 1946#define FW_FOISCSI_NAME_MAX_LEN 224 1947#define FW_FOISCSI_ALIAS_MAX_LEN 224 1948#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1949#define FW_FOISCSI_INIT_NODE_MAX 8 1950 1951enum fw_chnet_ifconf_wr_subop { 1952 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1953 1954 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1955 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1956 1957 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1958 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1959 1960 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1961 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1962 1963 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1964 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1965 1966 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1967 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1968 1969 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1970 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1971 1972 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 1973 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 1974 1975 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 1976 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 1977 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 1978 1979 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1980}; 1981 1982struct fw_chnet_ifconf_wr { 1983 __be32 op_compl; 1984 __be32 flowid_len16; 1985 __be64 cookie; 1986 __be32 if_flowid; 1987 __u8 idx; 1988 __u8 subop; 1989 __u8 retval; 1990 __u8 r2; 1991 __be64 r3; 1992 struct fw_chnet_ifconf_params { 1993 __be32 r0; 1994 __be16 vlanid; 1995 __be16 mtu; 1996 union fw_chnet_ifconf_addr_type { 1997 struct fw_chnet_ifconf_ipv4 { 1998 __be32 addr; 1999 __be32 mask; 2000 __be32 router; 2001 __be32 r0; 2002 __be64 r1; 2003 } ipv4; 2004 struct fw_chnet_ifconf_ipv6 { 2005 __u8 prefix_len; 2006 __u8 r0; 2007 __be16 r1; 2008 __be32 r2; 2009 __be64 addr_hi; 2010 __be64 addr_lo; 2011 __be64 router_hi; 2012 __be64 router_lo; 2013 } ipv6; 2014 } in_attr; 2015 } param; 2016}; 2017 2018enum fw_foiscsi_node_type { 2019 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2020 FW_FOISCSI_NODE_TYPE_TARGET, 2021}; 2022 2023enum fw_foiscsi_session_type { 2024 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2025 FW_FOISCSI_SESSION_TYPE_NORMAL, 2026}; 2027 2028enum fw_foiscsi_auth_policy { 2029 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2030 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2031}; 2032 2033enum fw_foiscsi_auth_method { 2034 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2035 FW_FOISCSI_AUTH_METHOD_CHAP, 2036 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2037 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2038}; 2039 2040enum fw_foiscsi_digest_type { 2041 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2042 FW_FOISCSI_DIGEST_TYPE_CRC32, 2043 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2044 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2045}; 2046 2047enum fw_foiscsi_wr_subop { 2048 FW_FOISCSI_WR_SUBOP_ADD = 1, 2049 FW_FOISCSI_WR_SUBOP_DEL = 2, 2050 FW_FOISCSI_WR_SUBOP_MOD = 4, 2051}; 2052 2053enum fw_foiscsi_ctrl_state { 2054 FW_FOISCSI_CTRL_STATE_FREE = 0, 2055 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2056 FW_FOISCSI_CTRL_STATE_FAILED, 2057 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2058 FW_FOISCSI_CTRL_STATE_REDIRECT, 2059}; 2060 2061struct fw_rdev_wr { 2062 __be32 op_to_immdlen; 2063 __be32 alloc_to_len16; 2064 __be64 cookie; 2065 __u8 protocol; 2066 __u8 event_cause; 2067 __u8 cur_state; 2068 __u8 prev_state; 2069 __be32 flags_to_assoc_flowid; 2070 union rdev_entry { 2071 struct fcoe_rdev_entry { 2072 __be32 flowid; 2073 __u8 protocol; 2074 __u8 event_cause; 2075 __u8 flags; 2076 __u8 rjt_reason; 2077 __u8 cur_login_st; 2078 __u8 prev_login_st; 2079 __be16 rcv_fr_sz; 2080 __u8 rd_xfer_rdy_to_rport_type; 2081 __u8 vft_to_qos; 2082 __u8 org_proc_assoc_to_acc_rsp_code; 2083 __u8 enh_disc_to_tgt; 2084 __u8 wwnn[8]; 2085 __u8 wwpn[8]; 2086 __be16 iqid; 2087 __u8 fc_oui[3]; 2088 __u8 r_id[3]; 2089 } fcoe_rdev; 2090 struct iscsi_rdev_entry { 2091 __be32 flowid; 2092 __u8 protocol; 2093 __u8 event_cause; 2094 __u8 flags; 2095 __u8 r3; 2096 __be16 iscsi_opts; 2097 __be16 tcp_opts; 2098 __be16 ip_opts; 2099 __be16 max_rcv_len; 2100 __be16 max_snd_len; 2101 __be16 first_brst_len; 2102 __be16 max_brst_len; 2103 __be16 r4; 2104 __be16 def_time2wait; 2105 __be16 def_time2ret; 2106 __be16 nop_out_intrvl; 2107 __be16 non_scsi_to; 2108 __be16 isid; 2109 __be16 tsid; 2110 __be16 port; 2111 __be16 tpgt; 2112 __u8 r5[6]; 2113 __be16 iqid; 2114 } iscsi_rdev; 2115 } u; 2116}; 2117 2118#define S_FW_RDEV_WR_IMMDLEN 0 2119#define M_FW_RDEV_WR_IMMDLEN 0xff 2120#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2121#define G_FW_RDEV_WR_IMMDLEN(x) \ 2122 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2123 2124#define S_FW_RDEV_WR_ALLOC 31 2125#define M_FW_RDEV_WR_ALLOC 0x1 2126#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2127#define G_FW_RDEV_WR_ALLOC(x) \ 2128 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2129#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2130 2131#define S_FW_RDEV_WR_FREE 30 2132#define M_FW_RDEV_WR_FREE 0x1 2133#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2134#define G_FW_RDEV_WR_FREE(x) \ 2135 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2136#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2137 2138#define S_FW_RDEV_WR_MODIFY 29 2139#define M_FW_RDEV_WR_MODIFY 0x1 2140#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2141#define G_FW_RDEV_WR_MODIFY(x) \ 2142 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2143#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2144 2145#define S_FW_RDEV_WR_FLOWID 8 2146#define M_FW_RDEV_WR_FLOWID 0xfffff 2147#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2148#define G_FW_RDEV_WR_FLOWID(x) \ 2149 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2150 2151#define S_FW_RDEV_WR_LEN16 0 2152#define M_FW_RDEV_WR_LEN16 0xff 2153#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2154#define G_FW_RDEV_WR_LEN16(x) \ 2155 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2156 2157#define S_FW_RDEV_WR_FLAGS 24 2158#define M_FW_RDEV_WR_FLAGS 0xff 2159#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2160#define G_FW_RDEV_WR_FLAGS(x) \ 2161 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2162 2163#define S_FW_RDEV_WR_GET_NEXT 20 2164#define M_FW_RDEV_WR_GET_NEXT 0xf 2165#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2166#define G_FW_RDEV_WR_GET_NEXT(x) \ 2167 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2168 2169#define S_FW_RDEV_WR_ASSOC_FLOWID 0 2170#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2171#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2172#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2173 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2174 2175#define S_FW_RDEV_WR_RJT 7 2176#define M_FW_RDEV_WR_RJT 0x1 2177#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2178#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2179#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2180 2181#define S_FW_RDEV_WR_REASON 0 2182#define M_FW_RDEV_WR_REASON 0x7f 2183#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2184#define G_FW_RDEV_WR_REASON(x) \ 2185 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2186 2187#define S_FW_RDEV_WR_RD_XFER_RDY 7 2188#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2189#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2190#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2191 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2192#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2193 2194#define S_FW_RDEV_WR_WR_XFER_RDY 6 2195#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2196#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2197#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2198 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2199#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2200 2201#define S_FW_RDEV_WR_FC_SP 5 2202#define M_FW_RDEV_WR_FC_SP 0x1 2203#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2204#define G_FW_RDEV_WR_FC_SP(x) \ 2205 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2206#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2207 2208#define S_FW_RDEV_WR_RPORT_TYPE 0 2209#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2210#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2211#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2212 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2213 2214#define S_FW_RDEV_WR_VFT 7 2215#define M_FW_RDEV_WR_VFT 0x1 2216#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2217#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2218#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2219 2220#define S_FW_RDEV_WR_NPIV 6 2221#define M_FW_RDEV_WR_NPIV 0x1 2222#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2223#define G_FW_RDEV_WR_NPIV(x) \ 2224 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2225#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2226 2227#define S_FW_RDEV_WR_CLASS 4 2228#define M_FW_RDEV_WR_CLASS 0x3 2229#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2230#define G_FW_RDEV_WR_CLASS(x) \ 2231 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2232 2233#define S_FW_RDEV_WR_SEQ_DEL 3 2234#define M_FW_RDEV_WR_SEQ_DEL 0x1 2235#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2236#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2237 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2238#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2239 2240#define S_FW_RDEV_WR_PRIO_PREEMP 2 2241#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2242#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2243#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2244 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2245#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2246 2247#define S_FW_RDEV_WR_PREF 1 2248#define M_FW_RDEV_WR_PREF 0x1 2249#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2250#define G_FW_RDEV_WR_PREF(x) \ 2251 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2252#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2253 2254#define S_FW_RDEV_WR_QOS 0 2255#define M_FW_RDEV_WR_QOS 0x1 2256#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2257#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2258#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2259 2260#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2261#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2262#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2263#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2264 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2265#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2266 2267#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2268#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2269#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2270#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2271 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2272#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2273 2274#define S_FW_RDEV_WR_IMAGE_PAIR 5 2275#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2276#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2277#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2278 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2279#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2280 2281#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2282#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2283#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2284#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2285 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2286 2287#define S_FW_RDEV_WR_ENH_DISC 7 2288#define M_FW_RDEV_WR_ENH_DISC 0x1 2289#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2290#define G_FW_RDEV_WR_ENH_DISC(x) \ 2291 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2292#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2293 2294#define S_FW_RDEV_WR_REC 6 2295#define M_FW_RDEV_WR_REC 0x1 2296#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2297#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2298#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2299 2300#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2301#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2302#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2303#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2304 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2305#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2306 2307#define S_FW_RDEV_WR_RETRY 4 2308#define M_FW_RDEV_WR_RETRY 0x1 2309#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2310#define G_FW_RDEV_WR_RETRY(x) \ 2311 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2312#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2313 2314#define S_FW_RDEV_WR_CONF_CMPL 3 2315#define M_FW_RDEV_WR_CONF_CMPL 0x1 2316#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2317#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2318 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2319#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2320 2321#define S_FW_RDEV_WR_DATA_OVLY 2 2322#define M_FW_RDEV_WR_DATA_OVLY 0x1 2323#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2324#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2325 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2326#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2327 2328#define S_FW_RDEV_WR_INI 1 2329#define M_FW_RDEV_WR_INI 0x1 2330#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2331#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2332#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2333 2334#define S_FW_RDEV_WR_TGT 0 2335#define M_FW_RDEV_WR_TGT 0x1 2336#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2337#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2338#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2339 2340struct fw_foiscsi_node_wr { 2341 __be32 op_to_immdlen; 2342 __be32 flowid_len16; 2343 __u64 cookie; 2344 __u8 subop; 2345 __u8 status; 2346 __u8 alias_len; 2347 __u8 iqn_len; 2348 __be32 node_flowid; 2349 __be16 nodeid; 2350 __be16 login_retry; 2351 __be16 retry_timeout; 2352 __be16 r3; 2353 __u8 iqn[224]; 2354 __u8 alias[224]; 2355}; 2356 2357#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2358#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2359#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2360#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2361 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2362 2363struct fw_foiscsi_ctrl_wr { 2364 __be32 op_compl; 2365 __be32 flowid_len16; 2366 __u64 cookie; 2367 __u8 subop; 2368 __u8 status; 2369 __u8 ctrl_state; 2370 __u8 io_state; 2371 __be32 node_id; 2372 __be32 ctrl_id; 2373 __be32 io_id; 2374 struct fw_foiscsi_sess_attr { 2375 __be32 sess_type_to_erl; 2376 __be16 max_conn; 2377 __be16 max_r2t; 2378 __be16 time2wait; 2379 __be16 time2retain; 2380 __be32 max_burst; 2381 __be32 first_burst; 2382 __be32 r1; 2383 } sess_attr; 2384 struct fw_foiscsi_conn_attr { 2385 __be32 hdigest_to_ddp_pgsz; 2386 __be32 max_rcv_dsl; 2387 __be32 ping_tmo; 2388 __be16 dst_port; 2389 __be16 src_port; 2390 union fw_foiscsi_conn_attr_addr { 2391 struct fw_foiscsi_conn_attr_ipv6 { 2392 __be64 dst_addr[2]; 2393 __be64 src_addr[2]; 2394 } ipv6_addr; 2395 struct fw_foiscsi_conn_attr_ipv4 { 2396 __be32 dst_addr; 2397 __be32 src_addr; 2398 } ipv4_addr; 2399 } u; 2400 } conn_attr; 2401 __u8 tgt_name_len; 2402 __u8 r3[7]; 2403 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2404}; 2405 2406#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2407#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2408#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2409 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2410#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2411 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2412 2413#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2414#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2415#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2416 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2417#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2418 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2419 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2420#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2421 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2422 2423#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2424#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2425#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2426 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2427#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2428 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2429 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2430#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2431 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2432 2433#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2434#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2435#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2436 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2437#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2438 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2439 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2440#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2441 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2442 2443#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2444#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2445#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2446 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2447#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2448 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2449 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2450#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2451 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2452 2453#define S_FW_FOISCSI_CTRL_WR_ERL 24 2454#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2455#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2456#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2457 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2458 2459#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2460#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2461#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2462#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2463 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2464 2465#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2466#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2467#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2468#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2469 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2470 2471#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2472#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2473#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2474 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2475#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2476 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2477 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2478 2479#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2480#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2481#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2482 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2483#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2484 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2485 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2486 2487#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2488#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2489#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2490 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2491#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2492 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2493 2494#define S_FW_FOISCSI_CTRL_WR_IPV6 20 2495#define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2496#define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2497#define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2498 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2499#define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2500 2501struct fw_foiscsi_chap_wr { 2502 __be32 op_compl; 2503 __be32 flowid_len16; 2504 __u64 cookie; 2505 __u8 status; 2506 __u8 id_len; 2507 __u8 sec_len; 2508 __u8 node_type; 2509 __be16 node_id; 2510 __u8 r3[2]; 2511 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2512 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2513}; 2514 2515/****************************************************************************** 2516 * F O F C O E W O R K R E Q U E S T s 2517 *******************************************/ 2518 2519struct fw_fcoe_els_ct_wr { 2520 __be32 op_immdlen; 2521 __be32 flowid_len16; 2522 __be64 cookie; 2523 __be16 iqid; 2524 __u8 tmo_val; 2525 __u8 els_ct_type; 2526 __u8 ctl_pri; 2527 __u8 cp_en_class; 2528 __be16 xfer_cnt; 2529 __u8 fl_to_sp; 2530 __u8 l_id[3]; 2531 __u8 r5; 2532 __u8 r_id[3]; 2533 __be64 rsp_dmaaddr; 2534 __be32 rsp_dmalen; 2535 __be32 r6; 2536}; 2537 2538#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2539#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2540#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2541#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2542 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2543 2544#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2545#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2546#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2547#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2548 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2549 2550#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2551#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2552#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2553#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2554 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2555 2556#define S_FW_FCOE_ELS_CT_WR_LEN16 0 2557#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2558#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2559#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2560 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2561 2562#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2563#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2564#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2565#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2566 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2567 2568#define S_FW_FCOE_ELS_CT_WR_CLASS 4 2569#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2570#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2571#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2572 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2573 2574#define S_FW_FCOE_ELS_CT_WR_FL 2 2575#define M_FW_FCOE_ELS_CT_WR_FL 0x1 2576#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2577#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2578 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2579#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2580 2581#define S_FW_FCOE_ELS_CT_WR_NPIV 1 2582#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2583#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2584#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2585 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2586#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2587 2588#define S_FW_FCOE_ELS_CT_WR_SP 0 2589#define M_FW_FCOE_ELS_CT_WR_SP 0x1 2590#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2591#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2592 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2593#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2594 2595/****************************************************************************** 2596 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2597 *****************************************************************************/ 2598 2599struct fw_scsi_write_wr { 2600 __be32 op_immdlen; 2601 __be32 flowid_len16; 2602 __be64 cookie; 2603 __be16 iqid; 2604 __u8 tmo_val; 2605 __u8 use_xfer_cnt; 2606 union fw_scsi_write_priv { 2607 struct fcoe_write_priv { 2608 __u8 ctl_pri; 2609 __u8 cp_en_class; 2610 __u8 r3_lo[2]; 2611 } fcoe; 2612 struct iscsi_write_priv { 2613 __u8 r3[4]; 2614 } iscsi; 2615 } u; 2616 __be32 xfer_cnt; 2617 __be32 ini_xfer_cnt; 2618 __be64 rsp_dmaaddr; 2619 __be32 rsp_dmalen; 2620 __be32 r4; 2621}; 2622 2623#define S_FW_SCSI_WRITE_WR_OPCODE 24 2624#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2625#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2626#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2627 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2628 2629#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2630#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2631#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2632#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2633 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2634 2635#define S_FW_SCSI_WRITE_WR_FLOWID 8 2636#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2637#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2638#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2639 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2640 2641#define S_FW_SCSI_WRITE_WR_LEN16 0 2642#define M_FW_SCSI_WRITE_WR_LEN16 0xff 2643#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2644#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2645 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2646 2647#define S_FW_SCSI_WRITE_WR_CP_EN 6 2648#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2649#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2650#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2651 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2652 2653#define S_FW_SCSI_WRITE_WR_CLASS 4 2654#define M_FW_SCSI_WRITE_WR_CLASS 0x3 2655#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2656#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2657 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2658 2659struct fw_scsi_read_wr { 2660 __be32 op_immdlen; 2661 __be32 flowid_len16; 2662 __be64 cookie; 2663 __be16 iqid; 2664 __u8 tmo_val; 2665 __u8 use_xfer_cnt; 2666 union fw_scsi_read_priv { 2667 struct fcoe_read_priv { 2668 __u8 ctl_pri; 2669 __u8 cp_en_class; 2670 __u8 r3_lo[2]; 2671 } fcoe; 2672 struct iscsi_read_priv { 2673 __u8 r3[4]; 2674 } iscsi; 2675 } u; 2676 __be32 xfer_cnt; 2677 __be32 ini_xfer_cnt; 2678 __be64 rsp_dmaaddr; 2679 __be32 rsp_dmalen; 2680 __be32 r4; 2681}; 2682 2683#define S_FW_SCSI_READ_WR_OPCODE 24 2684#define M_FW_SCSI_READ_WR_OPCODE 0xff 2685#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2686#define G_FW_SCSI_READ_WR_OPCODE(x) \ 2687 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2688 2689#define S_FW_SCSI_READ_WR_IMMDLEN 0 2690#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2691#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2692#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2693 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2694 2695#define S_FW_SCSI_READ_WR_FLOWID 8 2696#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2697#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2698#define G_FW_SCSI_READ_WR_FLOWID(x) \ 2699 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2700 2701#define S_FW_SCSI_READ_WR_LEN16 0 2702#define M_FW_SCSI_READ_WR_LEN16 0xff 2703#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2704#define G_FW_SCSI_READ_WR_LEN16(x) \ 2705 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2706 2707#define S_FW_SCSI_READ_WR_CP_EN 6 2708#define M_FW_SCSI_READ_WR_CP_EN 0x3 2709#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2710#define G_FW_SCSI_READ_WR_CP_EN(x) \ 2711 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2712 2713#define S_FW_SCSI_READ_WR_CLASS 4 2714#define M_FW_SCSI_READ_WR_CLASS 0x3 2715#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2716#define G_FW_SCSI_READ_WR_CLASS(x) \ 2717 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2718 2719struct fw_scsi_cmd_wr { 2720 __be32 op_immdlen; 2721 __be32 flowid_len16; 2722 __be64 cookie; 2723 __be16 iqid; 2724 __u8 tmo_val; 2725 __u8 r3; 2726 union fw_scsi_cmd_priv { 2727 struct fcoe_cmd_priv { 2728 __u8 ctl_pri; 2729 __u8 cp_en_class; 2730 __u8 r4_lo[2]; 2731 } fcoe; 2732 struct iscsi_cmd_priv { 2733 __u8 r4[4]; 2734 } iscsi; 2735 } u; 2736 __u8 r5[8]; 2737 __be64 rsp_dmaaddr; 2738 __be32 rsp_dmalen; 2739 __be32 r6; 2740}; 2741 2742#define S_FW_SCSI_CMD_WR_OPCODE 24 2743#define M_FW_SCSI_CMD_WR_OPCODE 0xff 2744#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2745#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2746 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2747 2748#define S_FW_SCSI_CMD_WR_IMMDLEN 0 2749#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2750#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2751#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2752 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2753 2754#define S_FW_SCSI_CMD_WR_FLOWID 8 2755#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2756#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2757#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2758 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2759 2760#define S_FW_SCSI_CMD_WR_LEN16 0 2761#define M_FW_SCSI_CMD_WR_LEN16 0xff 2762#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2763#define G_FW_SCSI_CMD_WR_LEN16(x) \ 2764 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2765 2766#define S_FW_SCSI_CMD_WR_CP_EN 6 2767#define M_FW_SCSI_CMD_WR_CP_EN 0x3 2768#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2769#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2770 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2771 2772#define S_FW_SCSI_CMD_WR_CLASS 4 2773#define M_FW_SCSI_CMD_WR_CLASS 0x3 2774#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2775#define G_FW_SCSI_CMD_WR_CLASS(x) \ 2776 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2777 2778struct fw_scsi_abrt_cls_wr { 2779 __be32 op_immdlen; 2780 __be32 flowid_len16; 2781 __be64 cookie; 2782 __be16 iqid; 2783 __u8 tmo_val; 2784 __u8 sub_opcode_to_chk_all_io; 2785 __u8 r3[4]; 2786 __be64 t_cookie; 2787}; 2788 2789#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2790#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2791#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2792#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2793 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2794 2795#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2796#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2797#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2798 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2799#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2800 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2801 2802#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2803#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2804#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2805#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2806 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2807 2808#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2809#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2810#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2811#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2812 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2813 2814#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2815#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2816#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2817 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2818#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2819 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2820 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2821 2822#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2823#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2824#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2825#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2826 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2827#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2828 2829#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2830#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2831#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2832 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2833#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2834 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2835 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2836#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2837 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2838 2839struct fw_scsi_tgt_acc_wr { 2840 __be32 op_immdlen; 2841 __be32 flowid_len16; 2842 __be64 cookie; 2843 __be16 iqid; 2844 __u8 r3; 2845 __u8 use_burst_len; 2846 union fw_scsi_tgt_acc_priv { 2847 struct fcoe_tgt_acc_priv { 2848 __u8 ctl_pri; 2849 __u8 cp_en_class; 2850 __u8 r4_lo[2]; 2851 } fcoe; 2852 struct iscsi_tgt_acc_priv { 2853 __u8 r4[4]; 2854 } iscsi; 2855 } u; 2856 __be32 burst_len; 2857 __be32 rel_off; 2858 __be64 r5; 2859 __be32 r6; 2860 __be32 tot_xfer_len; 2861}; 2862 2863#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2864#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2865#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2866#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2867 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2868 2869#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2870#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2871#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2872#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2873 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2874 2875#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2876#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2877#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2878#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2879 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2880 2881#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2882#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2883#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2884#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2885 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2886 2887#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2888#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2889#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2890#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2891 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2892 2893#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2894#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2895#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2896#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2897 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2898 2899struct fw_scsi_tgt_xmit_wr { 2900 __be32 op_immdlen; 2901 __be32 flowid_len16; 2902 __be64 cookie; 2903 __be16 iqid; 2904 __u8 auto_rsp; 2905 __u8 use_xfer_cnt; 2906 union fw_scsi_tgt_xmit_priv { 2907 struct fcoe_tgt_xmit_priv { 2908 __u8 ctl_pri; 2909 __u8 cp_en_class; 2910 __u8 r3_lo[2]; 2911 } fcoe; 2912 struct iscsi_tgt_xmit_priv { 2913 __u8 r3[4]; 2914 } iscsi; 2915 } u; 2916 __be32 xfer_cnt; 2917 __be32 r4; 2918 __be64 r5; 2919 __be32 r6; 2920 __be32 tot_xfer_len; 2921}; 2922 2923#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2924#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2925#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2926#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2927 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2928 2929#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2930#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2931#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2932 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2933#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2934 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2935 2936#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2937#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2938#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2939#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2940 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2941 2942#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2943#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2944#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2945#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2946 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2947 2948#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2949#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2950#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2951#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2952 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2953 2954#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2955#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2956#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2957#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2958 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2959 2960struct fw_scsi_tgt_rsp_wr { 2961 __be32 op_immdlen; 2962 __be32 flowid_len16; 2963 __be64 cookie; 2964 __be16 iqid; 2965 __u8 r3[2]; 2966 union fw_scsi_tgt_rsp_priv { 2967 struct fcoe_tgt_rsp_priv { 2968 __u8 ctl_pri; 2969 __u8 cp_en_class; 2970 __u8 r4_lo[2]; 2971 } fcoe; 2972 struct iscsi_tgt_rsp_priv { 2973 __u8 r4[4]; 2974 } iscsi; 2975 } u; 2976 __u8 r5[8]; 2977}; 2978 2979#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2980#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2981#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2982#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2983 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2984 2985#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2986#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2987#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2988#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2989 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2990 2991#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2992#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2993#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2994#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2995 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2996 2997#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2998#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2999#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3000#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3001 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3002 3003#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3004#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3005#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3006#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3007 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3008 3009#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3010#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3011#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3012#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3013 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3014 3015struct fw_pofcoe_tcb_wr { 3016 __be32 op_compl; 3017 __be32 equiq_to_len16; 3018 __be32 r4; 3019 __be32 xfer_len; 3020 __be32 tid_to_port; 3021 __be16 x_id; 3022 __be16 vlan_id; 3023 __be64 cookie; 3024 __be32 s_id; 3025 __be32 d_id; 3026 __be32 tag; 3027 __be16 r6; 3028 __be16 iqid; 3029}; 3030 3031#define S_FW_POFCOE_TCB_WR_TID 12 3032#define M_FW_POFCOE_TCB_WR_TID 0xfffff 3033#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3034#define G_FW_POFCOE_TCB_WR_TID(x) \ 3035 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3036 3037#define S_FW_POFCOE_TCB_WR_ALLOC 4 3038#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3039#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3040#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3041 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3042#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3043 3044#define S_FW_POFCOE_TCB_WR_FREE 3 3045#define M_FW_POFCOE_TCB_WR_FREE 0x1 3046#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3047#define G_FW_POFCOE_TCB_WR_FREE(x) \ 3048 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3049#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3050 3051#define S_FW_POFCOE_TCB_WR_PORT 0 3052#define M_FW_POFCOE_TCB_WR_PORT 0x7 3053#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3054#define G_FW_POFCOE_TCB_WR_PORT(x) \ 3055 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3056 3057struct fw_pofcoe_ulptx_wr { 3058 __be32 op_pkd; 3059 __be32 equiq_to_len16; 3060 __u64 cookie; 3061}; 3062 3063/******************************************************************* 3064 * T10 DIF related definition 3065 *******************************************************************/ 3066struct fw_tx_pi_header { 3067 __be16 op_to_inline; 3068 __u8 pi_interval_tag_type; 3069 __u8 num_pi; 3070 __be32 pi_start4_pi_end4; 3071 __u8 tag_gen_enabled_pkd; 3072 __u8 num_pi_dsg; 3073 __be16 app_tag; 3074 __be32 ref_tag; 3075}; 3076 3077#define S_FW_TX_PI_HEADER_OP 8 3078#define M_FW_TX_PI_HEADER_OP 0xff 3079#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3080#define G_FW_TX_PI_HEADER_OP(x) \ 3081 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3082 3083#define S_FW_TX_PI_HEADER_ULPTXMORE 7 3084#define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3085#define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3086#define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3087 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3088#define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3089 3090#define S_FW_TX_PI_HEADER_PI_CONTROL 4 3091#define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3092#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3093#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3094 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3095 3096#define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3097#define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3098#define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3099#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3100 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3101#define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3102 3103#define S_FW_TX_PI_HEADER_VALIDATE 1 3104#define M_FW_TX_PI_HEADER_VALIDATE 0x1 3105#define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3106#define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3107 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3108#define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3109 3110#define S_FW_TX_PI_HEADER_INLINE 0 3111#define M_FW_TX_PI_HEADER_INLINE 0x1 3112#define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3113#define G_FW_TX_PI_HEADER_INLINE(x) \ 3114 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3115#define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3116 3117#define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3118#define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3119#define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3120 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3121#define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3122 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3123#define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3124 3125#define S_FW_TX_PI_HEADER_TAG_TYPE 5 3126#define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3127#define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3128#define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3129 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3130 3131#define S_FW_TX_PI_HEADER_PI_START4 22 3132#define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3133#define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3134#define G_FW_TX_PI_HEADER_PI_START4(x) \ 3135 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3136 3137#define S_FW_TX_PI_HEADER_PI_END4 0 3138#define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3139#define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3140#define G_FW_TX_PI_HEADER_PI_END4(x) \ 3141 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3142 3143#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3144#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3145#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3146 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3147#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3148 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3149 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3150 3151enum fw_pi_error_type { 3152 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3153}; 3154 3155struct fw_pi_error { 3156 __be32 err_type_pkd; 3157 __be32 flowid_len16; 3158 __be16 r2; 3159 __be16 app_tag; 3160 __be32 ref_tag; 3161 __be32 pisc[4]; 3162}; 3163 3164#define S_FW_PI_ERROR_ERR_TYPE 24 3165#define M_FW_PI_ERROR_ERR_TYPE 0xff 3166#define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3167#define G_FW_PI_ERROR_ERR_TYPE(x) \ 3168 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3169 3170 3171/****************************************************************************** 3172 * C O M M A N D s 3173 *********************/ 3174 3175/* 3176 * The maximum length of time, in miliseconds, that we expect any firmware 3177 * command to take to execute and return a reply to the host. The RESET 3178 * and INITIALIZE commands can take a fair amount of time to execute but 3179 * most execute in far less time than this maximum. This constant is used 3180 * by host software to determine how long to wait for a firmware command 3181 * reply before declaring the firmware as dead/unreachable ... 3182 */ 3183#define FW_CMD_MAX_TIMEOUT 10000 3184 3185/* 3186 * If a host driver does a HELLO and discovers that there's already a MASTER 3187 * selected, we may have to wait for that MASTER to finish issuing RESET, 3188 * configuration and INITIALIZE commands. Also, there's a possibility that 3189 * our own HELLO may get lost if it happens right as the MASTER is issuign a 3190 * RESET command, so we need to be willing to make a few retries of our HELLO. 3191 */ 3192#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 3193#define FW_CMD_HELLO_RETRIES 3 3194 3195enum fw_cmd_opcodes { 3196 FW_LDST_CMD = 0x01, 3197 FW_RESET_CMD = 0x03, 3198 FW_HELLO_CMD = 0x04, 3199 FW_BYE_CMD = 0x05, 3200 FW_INITIALIZE_CMD = 0x06, 3201 FW_CAPS_CONFIG_CMD = 0x07, 3202 FW_PARAMS_CMD = 0x08, 3203 FW_PFVF_CMD = 0x09, 3204 FW_IQ_CMD = 0x10, 3205 FW_EQ_MNGT_CMD = 0x11, 3206 FW_EQ_ETH_CMD = 0x12, 3207 FW_EQ_CTRL_CMD = 0x13, 3208 FW_EQ_OFLD_CMD = 0x21, 3209 FW_VI_CMD = 0x14, 3210 FW_VI_MAC_CMD = 0x15, 3211 FW_VI_RXMODE_CMD = 0x16, 3212 FW_VI_ENABLE_CMD = 0x17, 3213 FW_VI_STATS_CMD = 0x1a, 3214 FW_ACL_MAC_CMD = 0x18, 3215 FW_ACL_VLAN_CMD = 0x19, 3216 FW_PORT_CMD = 0x1b, 3217 FW_PORT_STATS_CMD = 0x1c, 3218 FW_PORT_LB_STATS_CMD = 0x1d, 3219 FW_PORT_TRACE_CMD = 0x1e, 3220 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3221 FW_RSS_IND_TBL_CMD = 0x20, 3222 FW_RSS_GLB_CONFIG_CMD = 0x22, 3223 FW_RSS_VI_CONFIG_CMD = 0x23, 3224 FW_SCHED_CMD = 0x24, 3225 FW_DEVLOG_CMD = 0x25, 3226 FW_WATCHDOG_CMD = 0x27, 3227 FW_CLIP_CMD = 0x28, 3228 FW_CHNET_IFACE_CMD = 0x26, 3229 FW_FCOE_RES_INFO_CMD = 0x31, 3230 FW_FCOE_LINK_CMD = 0x32, 3231 FW_FCOE_VNP_CMD = 0x33, 3232 FW_FCOE_SPARAMS_CMD = 0x35, 3233 FW_FCOE_STATS_CMD = 0x37, 3234 FW_FCOE_FCF_CMD = 0x38, 3235 FW_PTP_CMD = 0x39, 3236 FW_LASTC2E_CMD = 0x40, 3237 FW_ERROR_CMD = 0x80, 3238 FW_DEBUG_CMD = 0x81, 3239}; 3240 3241enum fw_cmd_cap { 3242 FW_CMD_CAP_PF = 0x01, 3243 FW_CMD_CAP_DMAQ = 0x02, 3244 FW_CMD_CAP_PORT = 0x04, 3245 FW_CMD_CAP_PORTPROMISC = 0x08, 3246 FW_CMD_CAP_PORTSTATS = 0x10, 3247 FW_CMD_CAP_VF = 0x80, 3248}; 3249 3250/* 3251 * Generic command header flit0 3252 */ 3253struct fw_cmd_hdr { 3254 __be32 hi; 3255 __be32 lo; 3256}; 3257 3258#define S_FW_CMD_OP 24 3259#define M_FW_CMD_OP 0xff 3260#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 3261#define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 3262 3263#define S_FW_CMD_REQUEST 23 3264#define M_FW_CMD_REQUEST 0x1 3265#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 3266#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 3267#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 3268 3269#define S_FW_CMD_READ 22 3270#define M_FW_CMD_READ 0x1 3271#define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3272#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3273#define F_FW_CMD_READ V_FW_CMD_READ(1U) 3274 3275#define S_FW_CMD_WRITE 21 3276#define M_FW_CMD_WRITE 0x1 3277#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3278#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3279#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3280 3281#define S_FW_CMD_EXEC 20 3282#define M_FW_CMD_EXEC 0x1 3283#define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3284#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3285#define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3286 3287#define S_FW_CMD_RAMASK 20 3288#define M_FW_CMD_RAMASK 0xf 3289#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3290#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3291 3292#define S_FW_CMD_RETVAL 8 3293#define M_FW_CMD_RETVAL 0xff 3294#define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3295#define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3296 3297#define S_FW_CMD_LEN16 0 3298#define M_FW_CMD_LEN16 0xff 3299#define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3300#define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3301 3302#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 3303 3304/* 3305 * address spaces 3306 */ 3307enum fw_ldst_addrspc { 3308 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3309 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3310 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3311 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3312 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3313 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3314 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3315 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3316 FW_LDST_ADDRSPC_MDIO = 0x0018, 3317 FW_LDST_ADDRSPC_MPS = 0x0020, 3318 FW_LDST_ADDRSPC_FUNC = 0x0028, 3319 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3320 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3321 FW_LDST_ADDRSPC_LE = 0x0030, 3322 FW_LDST_ADDRSPC_I2C = 0x0038, 3323 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3324 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3325 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3326 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 3327}; 3328 3329/* 3330 * MDIO VSC8634 register access control field 3331 */ 3332enum fw_ldst_mdio_vsc8634_aid { 3333 FW_LDST_MDIO_VS_STANDARD, 3334 FW_LDST_MDIO_VS_EXTENDED, 3335 FW_LDST_MDIO_VS_GPIO 3336}; 3337 3338enum fw_ldst_mps_fid { 3339 FW_LDST_MPS_ATRB, 3340 FW_LDST_MPS_RPLC 3341}; 3342 3343enum fw_ldst_func_access_ctl { 3344 FW_LDST_FUNC_ACC_CTL_VIID, 3345 FW_LDST_FUNC_ACC_CTL_FID 3346}; 3347 3348enum fw_ldst_func_mod_index { 3349 FW_LDST_FUNC_MPS 3350}; 3351 3352struct fw_ldst_cmd { 3353 __be32 op_to_addrspace; 3354 __be32 cycles_to_len16; 3355 union fw_ldst { 3356 struct fw_ldst_addrval { 3357 __be32 addr; 3358 __be32 val; 3359 } addrval; 3360 struct fw_ldst_idctxt { 3361 __be32 physid; 3362 __be32 msg_ctxtflush; 3363 __be32 ctxt_data7; 3364 __be32 ctxt_data6; 3365 __be32 ctxt_data5; 3366 __be32 ctxt_data4; 3367 __be32 ctxt_data3; 3368 __be32 ctxt_data2; 3369 __be32 ctxt_data1; 3370 __be32 ctxt_data0; 3371 } idctxt; 3372 struct fw_ldst_mdio { 3373 __be16 paddr_mmd; 3374 __be16 raddr; 3375 __be16 vctl; 3376 __be16 rval; 3377 } mdio; 3378 struct fw_ldst_cim_rq { 3379 __u8 req_first64[8]; 3380 __u8 req_second64[8]; 3381 __u8 resp_first64[8]; 3382 __u8 resp_second64[8]; 3383 __be32 r3[2]; 3384 } cim_rq; 3385 union fw_ldst_mps { 3386 struct fw_ldst_mps_rplc { 3387 __be16 fid_idx; 3388 __be16 rplcpf_pkd; 3389 __be32 rplc255_224; 3390 __be32 rplc223_192; 3391 __be32 rplc191_160; 3392 __be32 rplc159_128; 3393 __be32 rplc127_96; 3394 __be32 rplc95_64; 3395 __be32 rplc63_32; 3396 __be32 rplc31_0; 3397 } rplc; 3398 struct fw_ldst_mps_atrb { 3399 __be16 fid_mpsid; 3400 __be16 r2[3]; 3401 __be32 r3[2]; 3402 __be32 r4; 3403 __be32 atrb; 3404 __be16 vlan[16]; 3405 } atrb; 3406 } mps; 3407 struct fw_ldst_func { 3408 __u8 access_ctl; 3409 __u8 mod_index; 3410 __be16 ctl_id; 3411 __be32 offset; 3412 __be64 data0; 3413 __be64 data1; 3414 } func; 3415 struct fw_ldst_pcie { 3416 __u8 ctrl_to_fn; 3417 __u8 bnum; 3418 __u8 r; 3419 __u8 ext_r; 3420 __u8 select_naccess; 3421 __u8 pcie_fn; 3422 __be16 nset_pkd; 3423 __be32 data[12]; 3424 } pcie; 3425 struct fw_ldst_i2c_deprecated { 3426 __u8 pid_pkd; 3427 __u8 base; 3428 __u8 boffset; 3429 __u8 data; 3430 __be32 r9; 3431 } i2c_deprecated; 3432 struct fw_ldst_i2c { 3433 __u8 pid; 3434 __u8 did; 3435 __u8 boffset; 3436 __u8 blen; 3437 __be32 r9; 3438 __u8 data[48]; 3439 } i2c; 3440 struct fw_ldst_le { 3441 __be32 index; 3442 __be32 r9; 3443 __u8 val[33]; 3444 __u8 r11[7]; 3445 } le; 3446 } u; 3447}; 3448 3449#define S_FW_LDST_CMD_ADDRSPACE 0 3450#define M_FW_LDST_CMD_ADDRSPACE 0xff 3451#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3452#define G_FW_LDST_CMD_ADDRSPACE(x) \ 3453 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3454 3455#define S_FW_LDST_CMD_CYCLES 16 3456#define M_FW_LDST_CMD_CYCLES 0xffff 3457#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3458#define G_FW_LDST_CMD_CYCLES(x) \ 3459 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3460 3461#define S_FW_LDST_CMD_MSG 31 3462#define M_FW_LDST_CMD_MSG 0x1 3463#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3464#define G_FW_LDST_CMD_MSG(x) \ 3465 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3466#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3467 3468#define S_FW_LDST_CMD_CTXTFLUSH 30 3469#define M_FW_LDST_CMD_CTXTFLUSH 0x1 3470#define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3471#define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3472 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3473#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3474 3475#define S_FW_LDST_CMD_PADDR 8 3476#define M_FW_LDST_CMD_PADDR 0x1f 3477#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3478#define G_FW_LDST_CMD_PADDR(x) \ 3479 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3480 3481#define S_FW_LDST_CMD_MMD 0 3482#define M_FW_LDST_CMD_MMD 0x1f 3483#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3484#define G_FW_LDST_CMD_MMD(x) \ 3485 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3486 3487#define S_FW_LDST_CMD_FID 15 3488#define M_FW_LDST_CMD_FID 0x1 3489#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3490#define G_FW_LDST_CMD_FID(x) \ 3491 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3492#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3493 3494#define S_FW_LDST_CMD_IDX 0 3495#define M_FW_LDST_CMD_IDX 0x7fff 3496#define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 3497#define G_FW_LDST_CMD_IDX(x) \ 3498 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 3499 3500#define S_FW_LDST_CMD_RPLCPF 0 3501#define M_FW_LDST_CMD_RPLCPF 0xff 3502#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3503#define G_FW_LDST_CMD_RPLCPF(x) \ 3504 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3505 3506#define S_FW_LDST_CMD_MPSID 0 3507#define M_FW_LDST_CMD_MPSID 0x7fff 3508#define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 3509#define G_FW_LDST_CMD_MPSID(x) \ 3510 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 3511 3512#define S_FW_LDST_CMD_CTRL 7 3513#define M_FW_LDST_CMD_CTRL 0x1 3514#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3515#define G_FW_LDST_CMD_CTRL(x) \ 3516 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3517#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3518 3519#define S_FW_LDST_CMD_LC 4 3520#define M_FW_LDST_CMD_LC 0x1 3521#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3522#define G_FW_LDST_CMD_LC(x) \ 3523 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3524#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3525 3526#define S_FW_LDST_CMD_AI 3 3527#define M_FW_LDST_CMD_AI 0x1 3528#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3529#define G_FW_LDST_CMD_AI(x) \ 3530 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3531#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3532 3533#define S_FW_LDST_CMD_FN 0 3534#define M_FW_LDST_CMD_FN 0x7 3535#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3536#define G_FW_LDST_CMD_FN(x) \ 3537 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3538 3539#define S_FW_LDST_CMD_SELECT 4 3540#define M_FW_LDST_CMD_SELECT 0xf 3541#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3542#define G_FW_LDST_CMD_SELECT(x) \ 3543 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3544 3545#define S_FW_LDST_CMD_NACCESS 0 3546#define M_FW_LDST_CMD_NACCESS 0xf 3547#define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3548#define G_FW_LDST_CMD_NACCESS(x) \ 3549 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3550 3551#define S_FW_LDST_CMD_NSET 14 3552#define M_FW_LDST_CMD_NSET 0x3 3553#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3554#define G_FW_LDST_CMD_NSET(x) \ 3555 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3556 3557#define S_FW_LDST_CMD_PID 6 3558#define M_FW_LDST_CMD_PID 0x3 3559#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3560#define G_FW_LDST_CMD_PID(x) \ 3561 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3562 3563struct fw_reset_cmd { 3564 __be32 op_to_write; 3565 __be32 retval_len16; 3566 __be32 val; 3567 __be32 halt_pkd; 3568}; 3569 3570#define S_FW_RESET_CMD_HALT 31 3571#define M_FW_RESET_CMD_HALT 0x1 3572#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3573#define G_FW_RESET_CMD_HALT(x) \ 3574 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3575#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3576 3577enum { 3578 FW_HELLO_CMD_STAGE_OS = 0, 3579 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3580 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3581 FW_HELLO_CMD_STAGE_POSTOS = 3, 3582}; 3583 3584struct fw_hello_cmd { 3585 __be32 op_to_write; 3586 __be32 retval_len16; 3587 __be32 err_to_clearinit; 3588 __be32 fwrev; 3589}; 3590 3591#define S_FW_HELLO_CMD_ERR 31 3592#define M_FW_HELLO_CMD_ERR 0x1 3593#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3594#define G_FW_HELLO_CMD_ERR(x) \ 3595 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3596#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3597 3598#define S_FW_HELLO_CMD_INIT 30 3599#define M_FW_HELLO_CMD_INIT 0x1 3600#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3601#define G_FW_HELLO_CMD_INIT(x) \ 3602 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3603#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3604 3605#define S_FW_HELLO_CMD_MASTERDIS 29 3606#define M_FW_HELLO_CMD_MASTERDIS 0x1 3607#define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3608#define G_FW_HELLO_CMD_MASTERDIS(x) \ 3609 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3610#define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3611 3612#define S_FW_HELLO_CMD_MASTERFORCE 28 3613#define M_FW_HELLO_CMD_MASTERFORCE 0x1 3614#define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3615#define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3616 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3617#define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3618 3619#define S_FW_HELLO_CMD_MBMASTER 24 3620#define M_FW_HELLO_CMD_MBMASTER 0xf 3621#define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3622#define G_FW_HELLO_CMD_MBMASTER(x) \ 3623 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3624 3625#define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3626#define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3627#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3628#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3629 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3630#define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3631 3632#define S_FW_HELLO_CMD_MBASYNCNOT 20 3633#define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3634#define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3635#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3636 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3637 3638#define S_FW_HELLO_CMD_STAGE 17 3639#define M_FW_HELLO_CMD_STAGE 0x7 3640#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3641#define G_FW_HELLO_CMD_STAGE(x) \ 3642 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3643 3644#define S_FW_HELLO_CMD_CLEARINIT 16 3645#define M_FW_HELLO_CMD_CLEARINIT 0x1 3646#define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3647#define G_FW_HELLO_CMD_CLEARINIT(x) \ 3648 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3649#define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3650 3651struct fw_bye_cmd { 3652 __be32 op_to_write; 3653 __be32 retval_len16; 3654 __be64 r3; 3655}; 3656 3657struct fw_initialize_cmd { 3658 __be32 op_to_write; 3659 __be32 retval_len16; 3660 __be64 r3; 3661}; 3662 3663enum fw_caps_config_hm { 3664 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3665 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3666 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3667 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3668 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3669 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3670 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3671 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3672 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3673 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3674 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3675 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3676 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3677 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3678 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3679 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3680 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3681 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3682 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3683 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3684 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3685 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3686 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3687 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3688}; 3689 3690/* 3691 * The VF Register Map. 3692 * 3693 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3694 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3695 * the Slice to Module Map Table (see below) in the Physical Function Register 3696 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3697 * and Offset registers in the PF Register Map. The MBDATA base address is 3698 * quite constrained as it determines the Mailbox Data addresses for both PFs 3699 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3700 * overlapping other registers. 3701 */ 3702#define FW_T4VF_SGE_BASE_ADDR 0x0000 3703#define FW_T4VF_MPS_BASE_ADDR 0x0100 3704#define FW_T4VF_PL_BASE_ADDR 0x0200 3705#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3706#define FW_T4VF_CIM_BASE_ADDR 0x0300 3707 3708#define FW_T4VF_REGMAP_START 0x0000 3709#define FW_T4VF_REGMAP_SIZE 0x0400 3710 3711enum fw_caps_config_nbm { 3712 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3713 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3714}; 3715 3716enum fw_caps_config_link { 3717 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3718 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3719 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3720}; 3721 3722enum fw_caps_config_switch { 3723 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3724 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3725}; 3726 3727enum fw_caps_config_nic { 3728 FW_CAPS_CONFIG_NIC = 0x00000001, 3729 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3730 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3731 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3732 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3733 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 3734 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 3735}; 3736 3737enum fw_caps_config_toe { 3738 FW_CAPS_CONFIG_TOE = 0x00000001, 3739}; 3740 3741enum fw_caps_config_rdma { 3742 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3743 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3744}; 3745 3746enum fw_caps_config_iscsi { 3747 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3748 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3749 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3750 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3751 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3752 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3753 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 3754}; 3755 3756enum fw_caps_config_fcoe { 3757 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3758 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3759 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3760 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3761 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3762}; 3763 3764enum fw_memtype_cf { 3765 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 3766 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 3767 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 3768 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 3769 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 3770 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 3771}; 3772 3773struct fw_caps_config_cmd { 3774 __be32 op_to_write; 3775 __be32 cfvalid_to_len16; 3776 __be32 r2; 3777 __be32 hwmbitmap; 3778 __be16 nbmcaps; 3779 __be16 linkcaps; 3780 __be16 switchcaps; 3781 __be16 r3; 3782 __be16 niccaps; 3783 __be16 toecaps; 3784 __be16 rdmacaps; 3785 __be16 r4; 3786 __be16 iscsicaps; 3787 __be16 fcoecaps; 3788 __be32 cfcsum; 3789 __be32 finiver; 3790 __be32 finicsum; 3791}; 3792 3793#define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3794#define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3795#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3796#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3797 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3798#define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3799 3800#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3801#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3802#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3803 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3804#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3805 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3806 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3807 3808#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3809#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3810#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3811 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3812#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3813 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3814 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3815 3816/* 3817 * params command mnemonics 3818 */ 3819enum fw_params_mnem { 3820 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3821 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3822 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3823 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3824 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 3825 FW_PARAMS_MNEM_LAST 3826}; 3827 3828/* 3829 * device parameters 3830 */ 3831enum fw_params_param_dev { 3832 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3833 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3834 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3835 * allocated by the device's 3836 * Lookup Engine 3837 */ 3838 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3839 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3840 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3841 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3842 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3843 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3844 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3845 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3846 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3847 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3848 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3849 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3850 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3851 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3852 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3853 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3854 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3855 */ 3856 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3857 */ 3858 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3859 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3860 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 3861 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 3862 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 3863}; 3864 3865/* 3866 * dev bypass parameters; actions and modes 3867 */ 3868enum fw_params_param_dev_bypass { 3869 3870 /* actions 3871 */ 3872 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3873 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3874 3875 /* modes 3876 */ 3877 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3878 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3879 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3880}; 3881 3882enum fw_params_param_dev_phyfw { 3883 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 3884 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 3885}; 3886 3887enum fw_params_param_dev_diag { 3888 FW_PARAM_DEV_DIAG_TMP = 0x00, 3889 FW_PARAM_DEV_DIAG_VDD = 0x01, 3890}; 3891 3892enum fw_params_param_dev_fwcache { 3893 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 3894 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 3895}; 3896 3897/* 3898 * physical and virtual function parameters 3899 */ 3900enum fw_params_param_pfvf { 3901 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3902 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3903 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3904 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3905 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3906 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3907 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3908 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3909 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3910 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3911 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3912 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3913 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3914 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3915 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3916 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3917 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3918 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3919 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3920 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3921 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3922 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3923 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3924 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3925 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3926 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3927 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3928 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3929 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3930 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3931 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3932 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3933 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3934 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3935 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3936 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3937 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3938 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3939 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3940 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3941}; 3942 3943/* 3944 * dma queue parameters 3945 */ 3946enum fw_params_param_dmaq { 3947 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3948 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3949 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3950 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3951 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3952 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3953 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 3954 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 3955}; 3956 3957/* 3958 * chnet parameters 3959 */ 3960enum fw_params_param_chnet { 3961 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 3962}; 3963 3964enum fw_params_param_chnet_flags { 3965 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 3966 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 3967 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 3968}; 3969 3970#define S_FW_PARAMS_MNEM 24 3971#define M_FW_PARAMS_MNEM 0xff 3972#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3973#define G_FW_PARAMS_MNEM(x) \ 3974 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3975 3976#define S_FW_PARAMS_PARAM_X 16 3977#define M_FW_PARAMS_PARAM_X 0xff 3978#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3979#define G_FW_PARAMS_PARAM_X(x) \ 3980 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3981 3982#define S_FW_PARAMS_PARAM_Y 8 3983#define M_FW_PARAMS_PARAM_Y 0xff 3984#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3985#define G_FW_PARAMS_PARAM_Y(x) \ 3986 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3987 3988#define S_FW_PARAMS_PARAM_Z 0 3989#define M_FW_PARAMS_PARAM_Z 0xff 3990#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3991#define G_FW_PARAMS_PARAM_Z(x) \ 3992 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3993 3994#define S_FW_PARAMS_PARAM_XYZ 0 3995#define M_FW_PARAMS_PARAM_XYZ 0xffffff 3996#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3997#define G_FW_PARAMS_PARAM_XYZ(x) \ 3998 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3999 4000#define S_FW_PARAMS_PARAM_YZ 0 4001#define M_FW_PARAMS_PARAM_YZ 0xffff 4002#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4003#define G_FW_PARAMS_PARAM_YZ(x) \ 4004 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4005 4006struct fw_params_cmd { 4007 __be32 op_to_vfn; 4008 __be32 retval_len16; 4009 struct fw_params_param { 4010 __be32 mnem; 4011 __be32 val; 4012 } param[7]; 4013}; 4014 4015#define S_FW_PARAMS_CMD_PFN 8 4016#define M_FW_PARAMS_CMD_PFN 0x7 4017#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4018#define G_FW_PARAMS_CMD_PFN(x) \ 4019 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4020 4021#define S_FW_PARAMS_CMD_VFN 0 4022#define M_FW_PARAMS_CMD_VFN 0xff 4023#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4024#define G_FW_PARAMS_CMD_VFN(x) \ 4025 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4026 4027struct fw_pfvf_cmd { 4028 __be32 op_to_vfn; 4029 __be32 retval_len16; 4030 __be32 niqflint_niq; 4031 __be32 type_to_neq; 4032 __be32 tc_to_nexactf; 4033 __be32 r_caps_to_nethctrl; 4034 __be16 nricq; 4035 __be16 nriqp; 4036 __be32 r4; 4037}; 4038 4039#define S_FW_PFVF_CMD_PFN 8 4040#define M_FW_PFVF_CMD_PFN 0x7 4041#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4042#define G_FW_PFVF_CMD_PFN(x) \ 4043 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4044 4045#define S_FW_PFVF_CMD_VFN 0 4046#define M_FW_PFVF_CMD_VFN 0xff 4047#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4048#define G_FW_PFVF_CMD_VFN(x) \ 4049 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4050 4051#define S_FW_PFVF_CMD_NIQFLINT 20 4052#define M_FW_PFVF_CMD_NIQFLINT 0xfff 4053#define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4054#define G_FW_PFVF_CMD_NIQFLINT(x) \ 4055 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4056 4057#define S_FW_PFVF_CMD_NIQ 0 4058#define M_FW_PFVF_CMD_NIQ 0xfffff 4059#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 4060#define G_FW_PFVF_CMD_NIQ(x) \ 4061 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 4062 4063#define S_FW_PFVF_CMD_TYPE 31 4064#define M_FW_PFVF_CMD_TYPE 0x1 4065#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 4066#define G_FW_PFVF_CMD_TYPE(x) \ 4067 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 4068#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 4069 4070#define S_FW_PFVF_CMD_CMASK 24 4071#define M_FW_PFVF_CMD_CMASK 0xf 4072#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 4073#define G_FW_PFVF_CMD_CMASK(x) \ 4074 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 4075 4076#define S_FW_PFVF_CMD_PMASK 20 4077#define M_FW_PFVF_CMD_PMASK 0xf 4078#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 4079#define G_FW_PFVF_CMD_PMASK(x) \ 4080 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 4081 4082#define S_FW_PFVF_CMD_NEQ 0 4083#define M_FW_PFVF_CMD_NEQ 0xfffff 4084#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 4085#define G_FW_PFVF_CMD_NEQ(x) \ 4086 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 4087 4088#define S_FW_PFVF_CMD_TC 24 4089#define M_FW_PFVF_CMD_TC 0xff 4090#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 4091#define G_FW_PFVF_CMD_TC(x) \ 4092 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 4093 4094#define S_FW_PFVF_CMD_NVI 16 4095#define M_FW_PFVF_CMD_NVI 0xff 4096#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 4097#define G_FW_PFVF_CMD_NVI(x) \ 4098 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 4099 4100#define S_FW_PFVF_CMD_NEXACTF 0 4101#define M_FW_PFVF_CMD_NEXACTF 0xffff 4102#define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 4103#define G_FW_PFVF_CMD_NEXACTF(x) \ 4104 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 4105 4106#define S_FW_PFVF_CMD_R_CAPS 24 4107#define M_FW_PFVF_CMD_R_CAPS 0xff 4108#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 4109#define G_FW_PFVF_CMD_R_CAPS(x) \ 4110 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 4111 4112#define S_FW_PFVF_CMD_WX_CAPS 16 4113#define M_FW_PFVF_CMD_WX_CAPS 0xff 4114#define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 4115#define G_FW_PFVF_CMD_WX_CAPS(x) \ 4116 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 4117 4118#define S_FW_PFVF_CMD_NETHCTRL 0 4119#define M_FW_PFVF_CMD_NETHCTRL 0xffff 4120#define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 4121#define G_FW_PFVF_CMD_NETHCTRL(x) \ 4122 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 4123 4124/* 4125 * ingress queue type; the first 1K ingress queues can have associated 0, 4126 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 4127 * capabilities 4128 */ 4129enum fw_iq_type { 4130 FW_IQ_TYPE_FL_INT_CAP, 4131 FW_IQ_TYPE_NO_FL_INT_CAP 4132}; 4133 4134struct fw_iq_cmd { 4135 __be32 op_to_vfn; 4136 __be32 alloc_to_len16; 4137 __be16 physiqid; 4138 __be16 iqid; 4139 __be16 fl0id; 4140 __be16 fl1id; 4141 __be32 type_to_iqandstindex; 4142 __be16 iqdroprss_to_iqesize; 4143 __be16 iqsize; 4144 __be64 iqaddr; 4145 __be32 iqns_to_fl0congen; 4146 __be16 fl0dcaen_to_fl0cidxfthresh; 4147 __be16 fl0size; 4148 __be64 fl0addr; 4149 __be32 fl1cngchmap_to_fl1congen; 4150 __be16 fl1dcaen_to_fl1cidxfthresh; 4151 __be16 fl1size; 4152 __be64 fl1addr; 4153}; 4154 4155#define S_FW_IQ_CMD_PFN 8 4156#define M_FW_IQ_CMD_PFN 0x7 4157#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 4158#define G_FW_IQ_CMD_PFN(x) \ 4159 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 4160 4161#define S_FW_IQ_CMD_VFN 0 4162#define M_FW_IQ_CMD_VFN 0xff 4163#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 4164#define G_FW_IQ_CMD_VFN(x) \ 4165 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 4166 4167#define S_FW_IQ_CMD_ALLOC 31 4168#define M_FW_IQ_CMD_ALLOC 0x1 4169#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 4170#define G_FW_IQ_CMD_ALLOC(x) \ 4171 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 4172#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 4173 4174#define S_FW_IQ_CMD_FREE 30 4175#define M_FW_IQ_CMD_FREE 0x1 4176#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 4177#define G_FW_IQ_CMD_FREE(x) \ 4178 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 4179#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 4180 4181#define S_FW_IQ_CMD_MODIFY 29 4182#define M_FW_IQ_CMD_MODIFY 0x1 4183#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 4184#define G_FW_IQ_CMD_MODIFY(x) \ 4185 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 4186#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 4187 4188#define S_FW_IQ_CMD_IQSTART 28 4189#define M_FW_IQ_CMD_IQSTART 0x1 4190#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 4191#define G_FW_IQ_CMD_IQSTART(x) \ 4192 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 4193#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 4194 4195#define S_FW_IQ_CMD_IQSTOP 27 4196#define M_FW_IQ_CMD_IQSTOP 0x1 4197#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 4198#define G_FW_IQ_CMD_IQSTOP(x) \ 4199 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 4200#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 4201 4202#define S_FW_IQ_CMD_TYPE 29 4203#define M_FW_IQ_CMD_TYPE 0x7 4204#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 4205#define G_FW_IQ_CMD_TYPE(x) \ 4206 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 4207 4208#define S_FW_IQ_CMD_IQASYNCH 28 4209#define M_FW_IQ_CMD_IQASYNCH 0x1 4210#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 4211#define G_FW_IQ_CMD_IQASYNCH(x) \ 4212 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 4213#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 4214 4215#define S_FW_IQ_CMD_VIID 16 4216#define M_FW_IQ_CMD_VIID 0xfff 4217#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 4218#define G_FW_IQ_CMD_VIID(x) \ 4219 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 4220 4221#define S_FW_IQ_CMD_IQANDST 15 4222#define M_FW_IQ_CMD_IQANDST 0x1 4223#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 4224#define G_FW_IQ_CMD_IQANDST(x) \ 4225 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 4226#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 4227 4228#define S_FW_IQ_CMD_IQANUS 14 4229#define M_FW_IQ_CMD_IQANUS 0x1 4230#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 4231#define G_FW_IQ_CMD_IQANUS(x) \ 4232 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 4233#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 4234 4235#define S_FW_IQ_CMD_IQANUD 12 4236#define M_FW_IQ_CMD_IQANUD 0x3 4237#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 4238#define G_FW_IQ_CMD_IQANUD(x) \ 4239 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 4240 4241#define S_FW_IQ_CMD_IQANDSTINDEX 0 4242#define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 4243#define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 4244#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 4245 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 4246 4247#define S_FW_IQ_CMD_IQDROPRSS 15 4248#define M_FW_IQ_CMD_IQDROPRSS 0x1 4249#define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 4250#define G_FW_IQ_CMD_IQDROPRSS(x) \ 4251 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 4252#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 4253 4254#define S_FW_IQ_CMD_IQGTSMODE 14 4255#define M_FW_IQ_CMD_IQGTSMODE 0x1 4256#define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 4257#define G_FW_IQ_CMD_IQGTSMODE(x) \ 4258 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 4259#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 4260 4261#define S_FW_IQ_CMD_IQPCIECH 12 4262#define M_FW_IQ_CMD_IQPCIECH 0x3 4263#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 4264#define G_FW_IQ_CMD_IQPCIECH(x) \ 4265 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 4266 4267#define S_FW_IQ_CMD_IQDCAEN 11 4268#define M_FW_IQ_CMD_IQDCAEN 0x1 4269#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 4270#define G_FW_IQ_CMD_IQDCAEN(x) \ 4271 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 4272#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 4273 4274#define S_FW_IQ_CMD_IQDCACPU 6 4275#define M_FW_IQ_CMD_IQDCACPU 0x1f 4276#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 4277#define G_FW_IQ_CMD_IQDCACPU(x) \ 4278 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 4279 4280#define S_FW_IQ_CMD_IQINTCNTTHRESH 4 4281#define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 4282#define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 4283#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 4284 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 4285 4286#define S_FW_IQ_CMD_IQO 3 4287#define M_FW_IQ_CMD_IQO 0x1 4288#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 4289#define G_FW_IQ_CMD_IQO(x) \ 4290 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 4291#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 4292 4293#define S_FW_IQ_CMD_IQCPRIO 2 4294#define M_FW_IQ_CMD_IQCPRIO 0x1 4295#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 4296#define G_FW_IQ_CMD_IQCPRIO(x) \ 4297 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 4298#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 4299 4300#define S_FW_IQ_CMD_IQESIZE 0 4301#define M_FW_IQ_CMD_IQESIZE 0x3 4302#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 4303#define G_FW_IQ_CMD_IQESIZE(x) \ 4304 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 4305 4306#define S_FW_IQ_CMD_IQNS 31 4307#define M_FW_IQ_CMD_IQNS 0x1 4308#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 4309#define G_FW_IQ_CMD_IQNS(x) \ 4310 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 4311#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 4312 4313#define S_FW_IQ_CMD_IQRO 30 4314#define M_FW_IQ_CMD_IQRO 0x1 4315#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 4316#define G_FW_IQ_CMD_IQRO(x) \ 4317 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 4318#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 4319 4320#define S_FW_IQ_CMD_IQFLINTIQHSEN 28 4321#define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 4322#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 4323#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 4324 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 4325 4326#define S_FW_IQ_CMD_IQFLINTCONGEN 27 4327#define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 4328#define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 4329#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 4330 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 4331#define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 4332 4333#define S_FW_IQ_CMD_IQFLINTISCSIC 26 4334#define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4335#define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4336#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4337 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4338#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4339 4340#define S_FW_IQ_CMD_FL0CNGCHMAP 20 4341#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4342#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4343#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4344 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4345 4346#define S_FW_IQ_CMD_FL0CONGDROP 16 4347#define M_FW_IQ_CMD_FL0CONGDROP 0x1 4348#define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 4349#define G_FW_IQ_CMD_FL0CONGDROP(x) \ 4350 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 4351#define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 4352 4353#define S_FW_IQ_CMD_FL0CACHELOCK 15 4354#define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4355#define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4356#define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4357 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4358#define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4359 4360#define S_FW_IQ_CMD_FL0DBP 14 4361#define M_FW_IQ_CMD_FL0DBP 0x1 4362#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4363#define G_FW_IQ_CMD_FL0DBP(x) \ 4364 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4365#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4366 4367#define S_FW_IQ_CMD_FL0DATANS 13 4368#define M_FW_IQ_CMD_FL0DATANS 0x1 4369#define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4370#define G_FW_IQ_CMD_FL0DATANS(x) \ 4371 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4372#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4373 4374#define S_FW_IQ_CMD_FL0DATARO 12 4375#define M_FW_IQ_CMD_FL0DATARO 0x1 4376#define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4377#define G_FW_IQ_CMD_FL0DATARO(x) \ 4378 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4379#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4380 4381#define S_FW_IQ_CMD_FL0CONGCIF 11 4382#define M_FW_IQ_CMD_FL0CONGCIF 0x1 4383#define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4384#define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4385 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4386#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4387 4388#define S_FW_IQ_CMD_FL0ONCHIP 10 4389#define M_FW_IQ_CMD_FL0ONCHIP 0x1 4390#define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4391#define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4392 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4393#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4394 4395#define S_FW_IQ_CMD_FL0STATUSPGNS 9 4396#define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4397#define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4398#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4399 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4400#define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4401 4402#define S_FW_IQ_CMD_FL0STATUSPGRO 8 4403#define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4404#define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4405#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4406 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4407#define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4408 4409#define S_FW_IQ_CMD_FL0FETCHNS 7 4410#define M_FW_IQ_CMD_FL0FETCHNS 0x1 4411#define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4412#define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4413 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4414#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4415 4416#define S_FW_IQ_CMD_FL0FETCHRO 6 4417#define M_FW_IQ_CMD_FL0FETCHRO 0x1 4418#define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4419#define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4420 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4421#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4422 4423#define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4424#define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4425#define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4426#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4427 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4428 4429#define S_FW_IQ_CMD_FL0CPRIO 3 4430#define M_FW_IQ_CMD_FL0CPRIO 0x1 4431#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4432#define G_FW_IQ_CMD_FL0CPRIO(x) \ 4433 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4434#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4435 4436#define S_FW_IQ_CMD_FL0PADEN 2 4437#define M_FW_IQ_CMD_FL0PADEN 0x1 4438#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4439#define G_FW_IQ_CMD_FL0PADEN(x) \ 4440 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4441#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4442 4443#define S_FW_IQ_CMD_FL0PACKEN 1 4444#define M_FW_IQ_CMD_FL0PACKEN 0x1 4445#define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4446#define G_FW_IQ_CMD_FL0PACKEN(x) \ 4447 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4448#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4449 4450#define S_FW_IQ_CMD_FL0CONGEN 0 4451#define M_FW_IQ_CMD_FL0CONGEN 0x1 4452#define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4453#define G_FW_IQ_CMD_FL0CONGEN(x) \ 4454 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4455#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4456 4457#define S_FW_IQ_CMD_FL0DCAEN 15 4458#define M_FW_IQ_CMD_FL0DCAEN 0x1 4459#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4460#define G_FW_IQ_CMD_FL0DCAEN(x) \ 4461 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4462#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4463 4464#define S_FW_IQ_CMD_FL0DCACPU 10 4465#define M_FW_IQ_CMD_FL0DCACPU 0x1f 4466#define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4467#define G_FW_IQ_CMD_FL0DCACPU(x) \ 4468 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4469 4470#define S_FW_IQ_CMD_FL0FBMIN 7 4471#define M_FW_IQ_CMD_FL0FBMIN 0x7 4472#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4473#define G_FW_IQ_CMD_FL0FBMIN(x) \ 4474 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4475 4476#define S_FW_IQ_CMD_FL0FBMAX 4 4477#define M_FW_IQ_CMD_FL0FBMAX 0x7 4478#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4479#define G_FW_IQ_CMD_FL0FBMAX(x) \ 4480 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4481 4482#define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4483#define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4484#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4485#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4486 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4487#define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4488 4489#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4490#define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4491#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4492#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4493 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4494 4495#define S_FW_IQ_CMD_FL1CNGCHMAP 20 4496#define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4497#define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4498#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4499 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4500 4501#define S_FW_IQ_CMD_FL1CONGDROP 16 4502#define M_FW_IQ_CMD_FL1CONGDROP 0x1 4503#define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 4504#define G_FW_IQ_CMD_FL1CONGDROP(x) \ 4505 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 4506#define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 4507 4508#define S_FW_IQ_CMD_FL1CACHELOCK 15 4509#define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4510#define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4511#define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4512 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4513#define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4514 4515#define S_FW_IQ_CMD_FL1DBP 14 4516#define M_FW_IQ_CMD_FL1DBP 0x1 4517#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4518#define G_FW_IQ_CMD_FL1DBP(x) \ 4519 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4520#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4521 4522#define S_FW_IQ_CMD_FL1DATANS 13 4523#define M_FW_IQ_CMD_FL1DATANS 0x1 4524#define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4525#define G_FW_IQ_CMD_FL1DATANS(x) \ 4526 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4527#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4528 4529#define S_FW_IQ_CMD_FL1DATARO 12 4530#define M_FW_IQ_CMD_FL1DATARO 0x1 4531#define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4532#define G_FW_IQ_CMD_FL1DATARO(x) \ 4533 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4534#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4535 4536#define S_FW_IQ_CMD_FL1CONGCIF 11 4537#define M_FW_IQ_CMD_FL1CONGCIF 0x1 4538#define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4539#define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4540 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4541#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4542 4543#define S_FW_IQ_CMD_FL1ONCHIP 10 4544#define M_FW_IQ_CMD_FL1ONCHIP 0x1 4545#define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4546#define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4547 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4548#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4549 4550#define S_FW_IQ_CMD_FL1STATUSPGNS 9 4551#define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4552#define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4553#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4554 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4555#define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4556 4557#define S_FW_IQ_CMD_FL1STATUSPGRO 8 4558#define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4559#define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4560#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4561 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4562#define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4563 4564#define S_FW_IQ_CMD_FL1FETCHNS 7 4565#define M_FW_IQ_CMD_FL1FETCHNS 0x1 4566#define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4567#define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4568 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4569#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4570 4571#define S_FW_IQ_CMD_FL1FETCHRO 6 4572#define M_FW_IQ_CMD_FL1FETCHRO 0x1 4573#define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4574#define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4575 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4576#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4577 4578#define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4579#define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4580#define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4581#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4582 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4583 4584#define S_FW_IQ_CMD_FL1CPRIO 3 4585#define M_FW_IQ_CMD_FL1CPRIO 0x1 4586#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4587#define G_FW_IQ_CMD_FL1CPRIO(x) \ 4588 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4589#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4590 4591#define S_FW_IQ_CMD_FL1PADEN 2 4592#define M_FW_IQ_CMD_FL1PADEN 0x1 4593#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4594#define G_FW_IQ_CMD_FL1PADEN(x) \ 4595 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4596#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4597 4598#define S_FW_IQ_CMD_FL1PACKEN 1 4599#define M_FW_IQ_CMD_FL1PACKEN 0x1 4600#define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4601#define G_FW_IQ_CMD_FL1PACKEN(x) \ 4602 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4603#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4604 4605#define S_FW_IQ_CMD_FL1CONGEN 0 4606#define M_FW_IQ_CMD_FL1CONGEN 0x1 4607#define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4608#define G_FW_IQ_CMD_FL1CONGEN(x) \ 4609 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4610#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4611 4612#define S_FW_IQ_CMD_FL1DCAEN 15 4613#define M_FW_IQ_CMD_FL1DCAEN 0x1 4614#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4615#define G_FW_IQ_CMD_FL1DCAEN(x) \ 4616 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4617#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4618 4619#define S_FW_IQ_CMD_FL1DCACPU 10 4620#define M_FW_IQ_CMD_FL1DCACPU 0x1f 4621#define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4622#define G_FW_IQ_CMD_FL1DCACPU(x) \ 4623 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4624 4625#define S_FW_IQ_CMD_FL1FBMIN 7 4626#define M_FW_IQ_CMD_FL1FBMIN 0x7 4627#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4628#define G_FW_IQ_CMD_FL1FBMIN(x) \ 4629 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4630 4631#define S_FW_IQ_CMD_FL1FBMAX 4 4632#define M_FW_IQ_CMD_FL1FBMAX 0x7 4633#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4634#define G_FW_IQ_CMD_FL1FBMAX(x) \ 4635 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4636 4637#define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4638#define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4639#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4640#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4641 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4642#define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4643 4644#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4645#define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4646#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4647#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4648 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4649 4650struct fw_eq_mngt_cmd { 4651 __be32 op_to_vfn; 4652 __be32 alloc_to_len16; 4653 __be32 cmpliqid_eqid; 4654 __be32 physeqid_pkd; 4655 __be32 fetchszm_to_iqid; 4656 __be32 dcaen_to_eqsize; 4657 __be64 eqaddr; 4658}; 4659 4660#define S_FW_EQ_MNGT_CMD_PFN 8 4661#define M_FW_EQ_MNGT_CMD_PFN 0x7 4662#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4663#define G_FW_EQ_MNGT_CMD_PFN(x) \ 4664 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4665 4666#define S_FW_EQ_MNGT_CMD_VFN 0 4667#define M_FW_EQ_MNGT_CMD_VFN 0xff 4668#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4669#define G_FW_EQ_MNGT_CMD_VFN(x) \ 4670 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4671 4672#define S_FW_EQ_MNGT_CMD_ALLOC 31 4673#define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4674#define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4675#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4676 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4677#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4678 4679#define S_FW_EQ_MNGT_CMD_FREE 30 4680#define M_FW_EQ_MNGT_CMD_FREE 0x1 4681#define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4682#define G_FW_EQ_MNGT_CMD_FREE(x) \ 4683 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4684#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4685 4686#define S_FW_EQ_MNGT_CMD_MODIFY 29 4687#define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4688#define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4689#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4690 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4691#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4692 4693#define S_FW_EQ_MNGT_CMD_EQSTART 28 4694#define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4695#define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4696#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4697 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4698#define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4699 4700#define S_FW_EQ_MNGT_CMD_EQSTOP 27 4701#define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4702#define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4703#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4704 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4705#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4706 4707#define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4708#define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4709#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4710#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4711 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4712 4713#define S_FW_EQ_MNGT_CMD_EQID 0 4714#define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4715#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4716#define G_FW_EQ_MNGT_CMD_EQID(x) \ 4717 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4718 4719#define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4720#define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4721#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4722#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4723 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4724 4725#define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4726#define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4727#define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4728#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4729 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4730#define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4731 4732#define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4733#define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4734#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4735#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4736 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4737#define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4738 4739#define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4740#define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4741#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4742#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4743 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4744#define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4745 4746#define S_FW_EQ_MNGT_CMD_FETCHNS 23 4747#define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4748#define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4749#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4750 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4751#define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4752 4753#define S_FW_EQ_MNGT_CMD_FETCHRO 22 4754#define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4755#define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4756#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4757 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4758#define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4759 4760#define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4761#define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4762#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4763#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4764 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4765 4766#define S_FW_EQ_MNGT_CMD_CPRIO 19 4767#define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4768#define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4769#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4770 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4771#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4772 4773#define S_FW_EQ_MNGT_CMD_ONCHIP 18 4774#define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4775#define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4776#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4777 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4778#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4779 4780#define S_FW_EQ_MNGT_CMD_PCIECHN 16 4781#define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4782#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4783#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4784 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4785 4786#define S_FW_EQ_MNGT_CMD_IQID 0 4787#define M_FW_EQ_MNGT_CMD_IQID 0xffff 4788#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4789#define G_FW_EQ_MNGT_CMD_IQID(x) \ 4790 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4791 4792#define S_FW_EQ_MNGT_CMD_DCAEN 31 4793#define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4794#define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4795#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4796 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4797#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4798 4799#define S_FW_EQ_MNGT_CMD_DCACPU 26 4800#define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4801#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4802#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4803 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4804 4805#define S_FW_EQ_MNGT_CMD_FBMIN 23 4806#define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4807#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4808#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4809 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4810 4811#define S_FW_EQ_MNGT_CMD_FBMAX 20 4812#define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4813#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4814#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4815 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4816 4817#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4818#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4819#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4820 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4821#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4822 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4823#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4824 4825#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4826#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4827#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4828#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4829 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4830 4831#define S_FW_EQ_MNGT_CMD_EQSIZE 0 4832#define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4833#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4834#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4835 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4836 4837struct fw_eq_eth_cmd { 4838 __be32 op_to_vfn; 4839 __be32 alloc_to_len16; 4840 __be32 eqid_pkd; 4841 __be32 physeqid_pkd; 4842 __be32 fetchszm_to_iqid; 4843 __be32 dcaen_to_eqsize; 4844 __be64 eqaddr; 4845 __be32 autoequiqe_to_viid; 4846 __be32 r8_lo; 4847 __be64 r9; 4848}; 4849 4850#define S_FW_EQ_ETH_CMD_PFN 8 4851#define M_FW_EQ_ETH_CMD_PFN 0x7 4852#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4853#define G_FW_EQ_ETH_CMD_PFN(x) \ 4854 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4855 4856#define S_FW_EQ_ETH_CMD_VFN 0 4857#define M_FW_EQ_ETH_CMD_VFN 0xff 4858#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4859#define G_FW_EQ_ETH_CMD_VFN(x) \ 4860 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4861 4862#define S_FW_EQ_ETH_CMD_ALLOC 31 4863#define M_FW_EQ_ETH_CMD_ALLOC 0x1 4864#define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4865#define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4866 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4867#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4868 4869#define S_FW_EQ_ETH_CMD_FREE 30 4870#define M_FW_EQ_ETH_CMD_FREE 0x1 4871#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4872#define G_FW_EQ_ETH_CMD_FREE(x) \ 4873 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4874#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4875 4876#define S_FW_EQ_ETH_CMD_MODIFY 29 4877#define M_FW_EQ_ETH_CMD_MODIFY 0x1 4878#define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4879#define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4880 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4881#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4882 4883#define S_FW_EQ_ETH_CMD_EQSTART 28 4884#define M_FW_EQ_ETH_CMD_EQSTART 0x1 4885#define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4886#define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4887 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4888#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4889 4890#define S_FW_EQ_ETH_CMD_EQSTOP 27 4891#define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4892#define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4893#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4894 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4895#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4896 4897#define S_FW_EQ_ETH_CMD_EQID 0 4898#define M_FW_EQ_ETH_CMD_EQID 0xfffff 4899#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4900#define G_FW_EQ_ETH_CMD_EQID(x) \ 4901 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4902 4903#define S_FW_EQ_ETH_CMD_PHYSEQID 0 4904#define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4905#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4906#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4907 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4908 4909#define S_FW_EQ_ETH_CMD_FETCHSZM 26 4910#define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4911#define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4912#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4913 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4914#define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4915 4916#define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4917#define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4918#define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4919#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4920 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4921#define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4922 4923#define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4924#define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4925#define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4926#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4927 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4928#define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4929 4930#define S_FW_EQ_ETH_CMD_FETCHNS 23 4931#define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4932#define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4933#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4934 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4935#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4936 4937#define S_FW_EQ_ETH_CMD_FETCHRO 22 4938#define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4939#define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4940#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4941 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4942#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4943 4944#define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4945#define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4946#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4947#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4948 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4949 4950#define S_FW_EQ_ETH_CMD_CPRIO 19 4951#define M_FW_EQ_ETH_CMD_CPRIO 0x1 4952#define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4953#define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4954 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4955#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4956 4957#define S_FW_EQ_ETH_CMD_ONCHIP 18 4958#define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4959#define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4960#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4961 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4962#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4963 4964#define S_FW_EQ_ETH_CMD_PCIECHN 16 4965#define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4966#define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4967#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4968 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4969 4970#define S_FW_EQ_ETH_CMD_IQID 0 4971#define M_FW_EQ_ETH_CMD_IQID 0xffff 4972#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4973#define G_FW_EQ_ETH_CMD_IQID(x) \ 4974 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4975 4976#define S_FW_EQ_ETH_CMD_DCAEN 31 4977#define M_FW_EQ_ETH_CMD_DCAEN 0x1 4978#define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4979#define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4980 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4981#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4982 4983#define S_FW_EQ_ETH_CMD_DCACPU 26 4984#define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4985#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4986#define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4987 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4988 4989#define S_FW_EQ_ETH_CMD_FBMIN 23 4990#define M_FW_EQ_ETH_CMD_FBMIN 0x7 4991#define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4992#define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4993 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4994 4995#define S_FW_EQ_ETH_CMD_FBMAX 20 4996#define M_FW_EQ_ETH_CMD_FBMAX 0x7 4997#define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4998#define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4999 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5000 5001#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5002#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5003#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5004#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5005 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5006#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5007 5008#define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5009#define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5010#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5011#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5012 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5013 5014#define S_FW_EQ_ETH_CMD_EQSIZE 0 5015#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5016#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5017#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5018 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5019 5020#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5021#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5022#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5023#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5024 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5025#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5026 5027#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5028#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5029#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5030#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5031 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5032#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5033 5034#define S_FW_EQ_ETH_CMD_VIID 16 5035#define M_FW_EQ_ETH_CMD_VIID 0xfff 5036#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5037#define G_FW_EQ_ETH_CMD_VIID(x) \ 5038 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 5039 5040struct fw_eq_ctrl_cmd { 5041 __be32 op_to_vfn; 5042 __be32 alloc_to_len16; 5043 __be32 cmpliqid_eqid; 5044 __be32 physeqid_pkd; 5045 __be32 fetchszm_to_iqid; 5046 __be32 dcaen_to_eqsize; 5047 __be64 eqaddr; 5048}; 5049 5050#define S_FW_EQ_CTRL_CMD_PFN 8 5051#define M_FW_EQ_CTRL_CMD_PFN 0x7 5052#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5053#define G_FW_EQ_CTRL_CMD_PFN(x) \ 5054 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5055 5056#define S_FW_EQ_CTRL_CMD_VFN 0 5057#define M_FW_EQ_CTRL_CMD_VFN 0xff 5058#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 5059#define G_FW_EQ_CTRL_CMD_VFN(x) \ 5060 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 5061 5062#define S_FW_EQ_CTRL_CMD_ALLOC 31 5063#define M_FW_EQ_CTRL_CMD_ALLOC 0x1 5064#define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 5065#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 5066 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 5067#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 5068 5069#define S_FW_EQ_CTRL_CMD_FREE 30 5070#define M_FW_EQ_CTRL_CMD_FREE 0x1 5071#define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 5072#define G_FW_EQ_CTRL_CMD_FREE(x) \ 5073 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 5074#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 5075 5076#define S_FW_EQ_CTRL_CMD_MODIFY 29 5077#define M_FW_EQ_CTRL_CMD_MODIFY 0x1 5078#define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 5079#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 5080 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 5081#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 5082 5083#define S_FW_EQ_CTRL_CMD_EQSTART 28 5084#define M_FW_EQ_CTRL_CMD_EQSTART 0x1 5085#define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 5086#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 5087 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 5088#define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 5089 5090#define S_FW_EQ_CTRL_CMD_EQSTOP 27 5091#define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 5092#define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 5093#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 5094 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 5095#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 5096 5097#define S_FW_EQ_CTRL_CMD_CMPLIQID 20 5098#define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 5099#define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 5100#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 5101 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 5102 5103#define S_FW_EQ_CTRL_CMD_EQID 0 5104#define M_FW_EQ_CTRL_CMD_EQID 0xfffff 5105#define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 5106#define G_FW_EQ_CTRL_CMD_EQID(x) \ 5107 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 5108 5109#define S_FW_EQ_CTRL_CMD_PHYSEQID 0 5110#define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 5111#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 5112#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 5113 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 5114 5115#define S_FW_EQ_CTRL_CMD_FETCHSZM 26 5116#define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 5117#define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 5118#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 5119 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 5120#define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 5121 5122#define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 5123#define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 5124#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 5125#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 5126 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 5127#define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 5128 5129#define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 5130#define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 5131#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 5132#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 5133 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 5134#define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 5135 5136#define S_FW_EQ_CTRL_CMD_FETCHNS 23 5137#define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 5138#define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 5139#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 5140 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 5141#define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 5142 5143#define S_FW_EQ_CTRL_CMD_FETCHRO 22 5144#define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 5145#define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 5146#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 5147 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 5148#define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 5149 5150#define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 5151#define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 5152#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 5153#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 5154 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 5155 5156#define S_FW_EQ_CTRL_CMD_CPRIO 19 5157#define M_FW_EQ_CTRL_CMD_CPRIO 0x1 5158#define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 5159#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 5160 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 5161#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 5162 5163#define S_FW_EQ_CTRL_CMD_ONCHIP 18 5164#define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 5165#define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 5166#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 5167 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 5168#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 5169 5170#define S_FW_EQ_CTRL_CMD_PCIECHN 16 5171#define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 5172#define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 5173#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 5174 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 5175 5176#define S_FW_EQ_CTRL_CMD_IQID 0 5177#define M_FW_EQ_CTRL_CMD_IQID 0xffff 5178#define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 5179#define G_FW_EQ_CTRL_CMD_IQID(x) \ 5180 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 5181 5182#define S_FW_EQ_CTRL_CMD_DCAEN 31 5183#define M_FW_EQ_CTRL_CMD_DCAEN 0x1 5184#define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 5185#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 5186 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 5187#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 5188 5189#define S_FW_EQ_CTRL_CMD_DCACPU 26 5190#define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 5191#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 5192#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 5193 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 5194 5195#define S_FW_EQ_CTRL_CMD_FBMIN 23 5196#define M_FW_EQ_CTRL_CMD_FBMIN 0x7 5197#define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 5198#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 5199 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 5200 5201#define S_FW_EQ_CTRL_CMD_FBMAX 20 5202#define M_FW_EQ_CTRL_CMD_FBMAX 0x7 5203#define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 5204#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 5205 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 5206 5207#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 5208#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 5209#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5210 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5211#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 5212 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 5213#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 5214 5215#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 5216#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 5217#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5218#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 5219 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 5220 5221#define S_FW_EQ_CTRL_CMD_EQSIZE 0 5222#define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 5223#define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 5224#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 5225 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 5226 5227struct fw_eq_ofld_cmd { 5228 __be32 op_to_vfn; 5229 __be32 alloc_to_len16; 5230 __be32 eqid_pkd; 5231 __be32 physeqid_pkd; 5232 __be32 fetchszm_to_iqid; 5233 __be32 dcaen_to_eqsize; 5234 __be64 eqaddr; 5235}; 5236 5237#define S_FW_EQ_OFLD_CMD_PFN 8 5238#define M_FW_EQ_OFLD_CMD_PFN 0x7 5239#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 5240#define G_FW_EQ_OFLD_CMD_PFN(x) \ 5241 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 5242 5243#define S_FW_EQ_OFLD_CMD_VFN 0 5244#define M_FW_EQ_OFLD_CMD_VFN 0xff 5245#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 5246#define G_FW_EQ_OFLD_CMD_VFN(x) \ 5247 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 5248 5249#define S_FW_EQ_OFLD_CMD_ALLOC 31 5250#define M_FW_EQ_OFLD_CMD_ALLOC 0x1 5251#define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 5252#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 5253 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 5254#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 5255 5256#define S_FW_EQ_OFLD_CMD_FREE 30 5257#define M_FW_EQ_OFLD_CMD_FREE 0x1 5258#define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 5259#define G_FW_EQ_OFLD_CMD_FREE(x) \ 5260 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 5261#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 5262 5263#define S_FW_EQ_OFLD_CMD_MODIFY 29 5264#define M_FW_EQ_OFLD_CMD_MODIFY 0x1 5265#define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 5266#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 5267 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 5268#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 5269 5270#define S_FW_EQ_OFLD_CMD_EQSTART 28 5271#define M_FW_EQ_OFLD_CMD_EQSTART 0x1 5272#define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 5273#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 5274 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 5275#define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 5276 5277#define S_FW_EQ_OFLD_CMD_EQSTOP 27 5278#define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 5279#define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 5280#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 5281 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 5282#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 5283 5284#define S_FW_EQ_OFLD_CMD_EQID 0 5285#define M_FW_EQ_OFLD_CMD_EQID 0xfffff 5286#define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 5287#define G_FW_EQ_OFLD_CMD_EQID(x) \ 5288 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 5289 5290#define S_FW_EQ_OFLD_CMD_PHYSEQID 0 5291#define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 5292#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 5293#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 5294 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 5295 5296#define S_FW_EQ_OFLD_CMD_FETCHSZM 26 5297#define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 5298#define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 5299#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 5300 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 5301#define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 5302 5303#define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 5304#define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 5305#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 5306#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 5307 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 5308#define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 5309 5310#define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 5311#define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 5312#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 5313#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 5314 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 5315#define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 5316 5317#define S_FW_EQ_OFLD_CMD_FETCHNS 23 5318#define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 5319#define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 5320#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 5321 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 5322#define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 5323 5324#define S_FW_EQ_OFLD_CMD_FETCHRO 22 5325#define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 5326#define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 5327#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 5328 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 5329#define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 5330 5331#define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 5332#define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 5333#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 5334#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 5335 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 5336 5337#define S_FW_EQ_OFLD_CMD_CPRIO 19 5338#define M_FW_EQ_OFLD_CMD_CPRIO 0x1 5339#define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 5340#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 5341 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 5342#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 5343 5344#define S_FW_EQ_OFLD_CMD_ONCHIP 18 5345#define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 5346#define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 5347#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 5348 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 5349#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 5350 5351#define S_FW_EQ_OFLD_CMD_PCIECHN 16 5352#define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 5353#define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 5354#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 5355 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 5356 5357#define S_FW_EQ_OFLD_CMD_IQID 0 5358#define M_FW_EQ_OFLD_CMD_IQID 0xffff 5359#define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 5360#define G_FW_EQ_OFLD_CMD_IQID(x) \ 5361 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 5362 5363#define S_FW_EQ_OFLD_CMD_DCAEN 31 5364#define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5365#define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5366#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5367 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5368#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5369 5370#define S_FW_EQ_OFLD_CMD_DCACPU 26 5371#define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5372#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5373#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5374 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5375 5376#define S_FW_EQ_OFLD_CMD_FBMIN 23 5377#define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5378#define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5379#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5380 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5381 5382#define S_FW_EQ_OFLD_CMD_FBMAX 20 5383#define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5384#define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5385#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5386 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5387 5388#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5389#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5390#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5391 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5392#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5393 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5394#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5395 5396#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5397#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5398#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5399#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5400 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5401 5402#define S_FW_EQ_OFLD_CMD_EQSIZE 0 5403#define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5404#define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5405#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5406 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5407 5408/* Macros for VIID parsing: 5409 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5410#define S_FW_VIID_PFN 8 5411#define M_FW_VIID_PFN 0x7 5412#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5413#define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5414 5415#define S_FW_VIID_VIVLD 7 5416#define M_FW_VIID_VIVLD 0x1 5417#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5418#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5419 5420#define S_FW_VIID_VIN 0 5421#define M_FW_VIID_VIN 0x7F 5422#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5423#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5424 5425enum fw_vi_func { 5426 FW_VI_FUNC_ETH, 5427 FW_VI_FUNC_OFLD, 5428 FW_VI_FUNC_IWARP, 5429 FW_VI_FUNC_OPENISCSI, 5430 FW_VI_FUNC_OPENFCOE, 5431 FW_VI_FUNC_FOISCSI, 5432 FW_VI_FUNC_FOFCOE, 5433 FW_VI_FUNC_FW, 5434}; 5435 5436struct fw_vi_cmd { 5437 __be32 op_to_vfn; 5438 __be32 alloc_to_len16; 5439 __be16 type_to_viid; 5440 __u8 mac[6]; 5441 __u8 portid_pkd; 5442 __u8 nmac; 5443 __u8 nmac0[6]; 5444 __be16 norss_rsssize; 5445 __u8 nmac1[6]; 5446 __be16 idsiiq_pkd; 5447 __u8 nmac2[6]; 5448 __be16 idseiq_pkd; 5449 __u8 nmac3[6]; 5450 __be64 r9; 5451 __be64 r10; 5452}; 5453 5454#define S_FW_VI_CMD_PFN 8 5455#define M_FW_VI_CMD_PFN 0x7 5456#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5457#define G_FW_VI_CMD_PFN(x) \ 5458 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5459 5460#define S_FW_VI_CMD_VFN 0 5461#define M_FW_VI_CMD_VFN 0xff 5462#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5463#define G_FW_VI_CMD_VFN(x) \ 5464 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5465 5466#define S_FW_VI_CMD_ALLOC 31 5467#define M_FW_VI_CMD_ALLOC 0x1 5468#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5469#define G_FW_VI_CMD_ALLOC(x) \ 5470 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5471#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5472 5473#define S_FW_VI_CMD_FREE 30 5474#define M_FW_VI_CMD_FREE 0x1 5475#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5476#define G_FW_VI_CMD_FREE(x) \ 5477 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5478#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5479 5480#define S_FW_VI_CMD_TYPE 15 5481#define M_FW_VI_CMD_TYPE 0x1 5482#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5483#define G_FW_VI_CMD_TYPE(x) \ 5484 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5485#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5486 5487#define S_FW_VI_CMD_FUNC 12 5488#define M_FW_VI_CMD_FUNC 0x7 5489#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5490#define G_FW_VI_CMD_FUNC(x) \ 5491 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5492 5493#define S_FW_VI_CMD_VIID 0 5494#define M_FW_VI_CMD_VIID 0xfff 5495#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5496#define G_FW_VI_CMD_VIID(x) \ 5497 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5498 5499#define S_FW_VI_CMD_PORTID 4 5500#define M_FW_VI_CMD_PORTID 0xf 5501#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5502#define G_FW_VI_CMD_PORTID(x) \ 5503 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5504 5505#define S_FW_VI_CMD_NORSS 11 5506#define M_FW_VI_CMD_NORSS 0x1 5507#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5508#define G_FW_VI_CMD_NORSS(x) \ 5509 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5510#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5511 5512#define S_FW_VI_CMD_RSSSIZE 0 5513#define M_FW_VI_CMD_RSSSIZE 0x7ff 5514#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5515#define G_FW_VI_CMD_RSSSIZE(x) \ 5516 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5517 5518#define S_FW_VI_CMD_IDSIIQ 0 5519#define M_FW_VI_CMD_IDSIIQ 0x3ff 5520#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5521#define G_FW_VI_CMD_IDSIIQ(x) \ 5522 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5523 5524#define S_FW_VI_CMD_IDSEIQ 0 5525#define M_FW_VI_CMD_IDSEIQ 0x3ff 5526#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5527#define G_FW_VI_CMD_IDSEIQ(x) \ 5528 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5529 5530/* Special VI_MAC command index ids */ 5531#define FW_VI_MAC_ADD_MAC 0x3FF 5532#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5533#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5534 5535enum fw_vi_mac_smac { 5536 FW_VI_MAC_MPS_TCAM_ENTRY, 5537 FW_VI_MAC_MPS_TCAM_ONLY, 5538 FW_VI_MAC_SMT_ONLY, 5539 FW_VI_MAC_SMT_AND_MPSTCAM 5540}; 5541 5542enum fw_vi_mac_result { 5543 FW_VI_MAC_R_SUCCESS, 5544 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5545 FW_VI_MAC_R_SMAC_FAIL, 5546 FW_VI_MAC_R_F_ACL_CHECK 5547}; 5548 5549struct fw_vi_mac_cmd { 5550 __be32 op_to_viid; 5551 __be32 freemacs_to_len16; 5552 union fw_vi_mac { 5553 struct fw_vi_mac_exact { 5554 __be16 valid_to_idx; 5555 __u8 macaddr[6]; 5556 } exact[7]; 5557 struct fw_vi_mac_hash { 5558 __be64 hashvec; 5559 } hash; 5560 } u; 5561}; 5562 5563#define S_FW_VI_MAC_CMD_VIID 0 5564#define M_FW_VI_MAC_CMD_VIID 0xfff 5565#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5566#define G_FW_VI_MAC_CMD_VIID(x) \ 5567 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5568 5569#define S_FW_VI_MAC_CMD_FREEMACS 31 5570#define M_FW_VI_MAC_CMD_FREEMACS 0x1 5571#define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5572#define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5573 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5574#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5575 5576#define S_FW_VI_MAC_CMD_HASHVECEN 23 5577#define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5578#define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5579#define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5580 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5581#define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5582 5583#define S_FW_VI_MAC_CMD_HASHUNIEN 22 5584#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5585#define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5586#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5587 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5588#define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5589 5590#define S_FW_VI_MAC_CMD_VALID 15 5591#define M_FW_VI_MAC_CMD_VALID 0x1 5592#define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5593#define G_FW_VI_MAC_CMD_VALID(x) \ 5594 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5595#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5596 5597#define S_FW_VI_MAC_CMD_PRIO 12 5598#define M_FW_VI_MAC_CMD_PRIO 0x7 5599#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5600#define G_FW_VI_MAC_CMD_PRIO(x) \ 5601 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5602 5603#define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5604#define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5605#define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5606#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5607 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5608 5609#define S_FW_VI_MAC_CMD_IDX 0 5610#define M_FW_VI_MAC_CMD_IDX 0x3ff 5611#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5612#define G_FW_VI_MAC_CMD_IDX(x) \ 5613 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5614 5615/* T4 max MTU supported */ 5616#define T4_MAX_MTU_SUPPORTED 9600 5617#define FW_RXMODE_MTU_NO_CHG 65535 5618 5619struct fw_vi_rxmode_cmd { 5620 __be32 op_to_viid; 5621 __be32 retval_len16; 5622 __be32 mtu_to_vlanexen; 5623 __be32 r4_lo; 5624}; 5625 5626#define S_FW_VI_RXMODE_CMD_VIID 0 5627#define M_FW_VI_RXMODE_CMD_VIID 0xfff 5628#define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5629#define G_FW_VI_RXMODE_CMD_VIID(x) \ 5630 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5631 5632#define S_FW_VI_RXMODE_CMD_MTU 16 5633#define M_FW_VI_RXMODE_CMD_MTU 0xffff 5634#define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5635#define G_FW_VI_RXMODE_CMD_MTU(x) \ 5636 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5637 5638#define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5639#define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5640#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5641#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5642 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5643 5644#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5645#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5646#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5647 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5648#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5649 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5650 5651#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5652#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5653#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5654 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5655#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5656 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5657 5658#define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5659#define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5660#define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5661#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5662 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5663 5664struct fw_vi_enable_cmd { 5665 __be32 op_to_viid; 5666 __be32 ien_to_len16; 5667 __be16 blinkdur; 5668 __be16 r3; 5669 __be32 r4; 5670}; 5671 5672#define S_FW_VI_ENABLE_CMD_VIID 0 5673#define M_FW_VI_ENABLE_CMD_VIID 0xfff 5674#define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5675#define G_FW_VI_ENABLE_CMD_VIID(x) \ 5676 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5677 5678#define S_FW_VI_ENABLE_CMD_IEN 31 5679#define M_FW_VI_ENABLE_CMD_IEN 0x1 5680#define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5681#define G_FW_VI_ENABLE_CMD_IEN(x) \ 5682 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5683#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5684 5685#define S_FW_VI_ENABLE_CMD_EEN 30 5686#define M_FW_VI_ENABLE_CMD_EEN 0x1 5687#define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5688#define G_FW_VI_ENABLE_CMD_EEN(x) \ 5689 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5690#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5691 5692#define S_FW_VI_ENABLE_CMD_LED 29 5693#define M_FW_VI_ENABLE_CMD_LED 0x1 5694#define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5695#define G_FW_VI_ENABLE_CMD_LED(x) \ 5696 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5697#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5698 5699#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5700#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5701#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5702#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5703 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5704#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5705 5706/* VI VF stats offset definitions */ 5707#define VI_VF_NUM_STATS 16 5708enum fw_vi_stats_vf_index { 5709 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5710 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5711 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5712 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5713 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5714 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5715 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5716 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5717 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5718 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5719 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5720 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5721 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5722 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5723 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5724 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5725}; 5726 5727/* VI PF stats offset definitions */ 5728#define VI_PF_NUM_STATS 17 5729enum fw_vi_stats_pf_index { 5730 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5731 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5732 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5733 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5734 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5735 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5736 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5737 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5738 FW_VI_PF_STAT_RX_BYTES_IX, 5739 FW_VI_PF_STAT_RX_FRAMES_IX, 5740 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5741 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5742 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5743 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5744 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5745 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5746 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5747}; 5748 5749struct fw_vi_stats_cmd { 5750 __be32 op_to_viid; 5751 __be32 retval_len16; 5752 union fw_vi_stats { 5753 struct fw_vi_stats_ctl { 5754 __be16 nstats_ix; 5755 __be16 r6; 5756 __be32 r7; 5757 __be64 stat0; 5758 __be64 stat1; 5759 __be64 stat2; 5760 __be64 stat3; 5761 __be64 stat4; 5762 __be64 stat5; 5763 } ctl; 5764 struct fw_vi_stats_pf { 5765 __be64 tx_bcast_bytes; 5766 __be64 tx_bcast_frames; 5767 __be64 tx_mcast_bytes; 5768 __be64 tx_mcast_frames; 5769 __be64 tx_ucast_bytes; 5770 __be64 tx_ucast_frames; 5771 __be64 tx_offload_bytes; 5772 __be64 tx_offload_frames; 5773 __be64 rx_pf_bytes; 5774 __be64 rx_pf_frames; 5775 __be64 rx_bcast_bytes; 5776 __be64 rx_bcast_frames; 5777 __be64 rx_mcast_bytes; 5778 __be64 rx_mcast_frames; 5779 __be64 rx_ucast_bytes; 5780 __be64 rx_ucast_frames; 5781 __be64 rx_err_frames; 5782 } pf; 5783 struct fw_vi_stats_vf { 5784 __be64 tx_bcast_bytes; 5785 __be64 tx_bcast_frames; 5786 __be64 tx_mcast_bytes; 5787 __be64 tx_mcast_frames; 5788 __be64 tx_ucast_bytes; 5789 __be64 tx_ucast_frames; 5790 __be64 tx_drop_frames; 5791 __be64 tx_offload_bytes; 5792 __be64 tx_offload_frames; 5793 __be64 rx_bcast_bytes; 5794 __be64 rx_bcast_frames; 5795 __be64 rx_mcast_bytes; 5796 __be64 rx_mcast_frames; 5797 __be64 rx_ucast_bytes; 5798 __be64 rx_ucast_frames; 5799 __be64 rx_err_frames; 5800 } vf; 5801 } u; 5802}; 5803 5804#define S_FW_VI_STATS_CMD_VIID 0 5805#define M_FW_VI_STATS_CMD_VIID 0xfff 5806#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5807#define G_FW_VI_STATS_CMD_VIID(x) \ 5808 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5809 5810#define S_FW_VI_STATS_CMD_NSTATS 12 5811#define M_FW_VI_STATS_CMD_NSTATS 0x7 5812#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5813#define G_FW_VI_STATS_CMD_NSTATS(x) \ 5814 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5815 5816#define S_FW_VI_STATS_CMD_IX 0 5817#define M_FW_VI_STATS_CMD_IX 0x1f 5818#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5819#define G_FW_VI_STATS_CMD_IX(x) \ 5820 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5821 5822struct fw_acl_mac_cmd { 5823 __be32 op_to_vfn; 5824 __be32 en_to_len16; 5825 __u8 nmac; 5826 __u8 r3[7]; 5827 __be16 r4; 5828 __u8 macaddr0[6]; 5829 __be16 r5; 5830 __u8 macaddr1[6]; 5831 __be16 r6; 5832 __u8 macaddr2[6]; 5833 __be16 r7; 5834 __u8 macaddr3[6]; 5835}; 5836 5837#define S_FW_ACL_MAC_CMD_PFN 8 5838#define M_FW_ACL_MAC_CMD_PFN 0x7 5839#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5840#define G_FW_ACL_MAC_CMD_PFN(x) \ 5841 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5842 5843#define S_FW_ACL_MAC_CMD_VFN 0 5844#define M_FW_ACL_MAC_CMD_VFN 0xff 5845#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5846#define G_FW_ACL_MAC_CMD_VFN(x) \ 5847 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5848 5849#define S_FW_ACL_MAC_CMD_EN 31 5850#define M_FW_ACL_MAC_CMD_EN 0x1 5851#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5852#define G_FW_ACL_MAC_CMD_EN(x) \ 5853 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5854#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5855 5856struct fw_acl_vlan_cmd { 5857 __be32 op_to_vfn; 5858 __be32 en_to_len16; 5859 __u8 nvlan; 5860 __u8 dropnovlan_fm; 5861 __u8 r3_lo[6]; 5862 __be16 vlanid[16]; 5863}; 5864 5865#define S_FW_ACL_VLAN_CMD_PFN 8 5866#define M_FW_ACL_VLAN_CMD_PFN 0x7 5867#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5868#define G_FW_ACL_VLAN_CMD_PFN(x) \ 5869 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5870 5871#define S_FW_ACL_VLAN_CMD_VFN 0 5872#define M_FW_ACL_VLAN_CMD_VFN 0xff 5873#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5874#define G_FW_ACL_VLAN_CMD_VFN(x) \ 5875 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5876 5877#define S_FW_ACL_VLAN_CMD_EN 31 5878#define M_FW_ACL_VLAN_CMD_EN 0x1 5879#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5880#define G_FW_ACL_VLAN_CMD_EN(x) \ 5881 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5882#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5883 5884#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5885#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5886#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5887#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5888 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5889#define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5890 5891#define S_FW_ACL_VLAN_CMD_FM 6 5892#define M_FW_ACL_VLAN_CMD_FM 0x1 5893#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5894#define G_FW_ACL_VLAN_CMD_FM(x) \ 5895 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5896#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5897 5898/* port capabilities bitmap */ 5899enum fw_port_cap { 5900 FW_PORT_CAP_SPEED_100M = 0x0001, 5901 FW_PORT_CAP_SPEED_1G = 0x0002, 5902 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5903 FW_PORT_CAP_SPEED_10G = 0x0008, 5904 FW_PORT_CAP_SPEED_40G = 0x0010, 5905 FW_PORT_CAP_SPEED_100G = 0x0020, 5906 FW_PORT_CAP_FC_RX = 0x0040, 5907 FW_PORT_CAP_FC_TX = 0x0080, 5908 FW_PORT_CAP_ANEG = 0x0100, 5909 FW_PORT_CAP_MDIX = 0x0200, 5910 FW_PORT_CAP_MDIAUTO = 0x0400, 5911 FW_PORT_CAP_FEC = 0x0800, 5912 FW_PORT_CAP_TECHKR = 0x1000, 5913 FW_PORT_CAP_TECHKX4 = 0x2000, 5914 FW_PORT_CAP_802_3_PAUSE = 0x4000, 5915 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 5916}; 5917 5918#define S_FW_PORT_AUXLINFO_MDI 3 5919#define M_FW_PORT_AUXLINFO_MDI 0x3 5920#define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5921#define G_FW_PORT_AUXLINFO_MDI(x) \ 5922 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5923 5924#define S_FW_PORT_AUXLINFO_KX4 2 5925#define M_FW_PORT_AUXLINFO_KX4 0x1 5926#define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5927#define G_FW_PORT_AUXLINFO_KX4(x) \ 5928 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5929#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5930 5931#define S_FW_PORT_AUXLINFO_KR 1 5932#define M_FW_PORT_AUXLINFO_KR 0x1 5933#define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5934#define G_FW_PORT_AUXLINFO_KR(x) \ 5935 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5936#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5937 5938#define S_FW_PORT_AUXLINFO_FEC 0 5939#define M_FW_PORT_AUXLINFO_FEC 0x1 5940#define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5941#define G_FW_PORT_AUXLINFO_FEC(x) \ 5942 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5943#define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5944 5945#define S_FW_PORT_RCAP_AUX 11 5946#define M_FW_PORT_RCAP_AUX 0x7 5947#define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5948#define G_FW_PORT_RCAP_AUX(x) \ 5949 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5950 5951#define S_FW_PORT_CAP_SPEED 0 5952#define M_FW_PORT_CAP_SPEED 0x3f 5953#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5954#define G_FW_PORT_CAP_SPEED(x) \ 5955 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5956 5957#define S_FW_PORT_CAP_FC 6 5958#define M_FW_PORT_CAP_FC 0x3 5959#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5960#define G_FW_PORT_CAP_FC(x) \ 5961 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5962 5963#define S_FW_PORT_CAP_ANEG 8 5964#define M_FW_PORT_CAP_ANEG 0x1 5965#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5966#define G_FW_PORT_CAP_ANEG(x) \ 5967 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5968 5969#define S_FW_PORT_CAP_802_3 14 5970#define M_FW_PORT_CAP_802_3 0x3 5971#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 5972#define G_FW_PORT_CAP_802_3(x) \ 5973 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 5974 5975enum fw_port_mdi { 5976 FW_PORT_CAP_MDI_UNCHANGED, 5977 FW_PORT_CAP_MDI_AUTO, 5978 FW_PORT_CAP_MDI_F_STRAIGHT, 5979 FW_PORT_CAP_MDI_F_CROSSOVER 5980}; 5981 5982#define S_FW_PORT_CAP_MDI 9 5983#define M_FW_PORT_CAP_MDI 3 5984#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5985#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5986 5987enum fw_port_action { 5988 FW_PORT_ACTION_L1_CFG = 0x0001, 5989 FW_PORT_ACTION_L2_CFG = 0x0002, 5990 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5991 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5992 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5993 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5994 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5995 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5996 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5997 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5998 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5999 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 6000 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 6001 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 6002 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 6003 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 6004 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 6005 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 6006 FW_PORT_ACTION_PHY_RESET = 0x0040, 6007 FW_PORT_ACTION_PMA_RESET = 0x0041, 6008 FW_PORT_ACTION_PCS_RESET = 0x0042, 6009 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 6010 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 6011 FW_PORT_ACTION_AN_RESET = 0x0045, 6012 6013}; 6014 6015enum fw_port_l2cfg_ctlbf { 6016 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 6017 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 6018 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 6019 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 6020 FW_PORT_L2_CTLBF_IVLAN = 0x10, 6021 FW_PORT_L2_CTLBF_TXIPG = 0x20, 6022 FW_PORT_L2_CTLBF_MTU = 0x40 6023}; 6024 6025enum fw_dcb_app_tlv_sf { 6026 FW_DCB_APP_SF_ETHERTYPE, 6027 FW_DCB_APP_SF_SOCKET_TCP, 6028 FW_DCB_APP_SF_SOCKET_UDP, 6029 FW_DCB_APP_SF_SOCKET_ALL, 6030}; 6031 6032enum fw_port_dcb_versions { 6033 FW_PORT_DCB_VER_UNKNOWN, 6034 FW_PORT_DCB_VER_CEE1D0, 6035 FW_PORT_DCB_VER_CEE1D01, 6036 FW_PORT_DCB_VER_IEEE, 6037 FW_PORT_DCB_VER_AUTO=7 6038}; 6039 6040enum fw_port_dcb_cfg { 6041 FW_PORT_DCB_CFG_PG = 0x01, 6042 FW_PORT_DCB_CFG_PFC = 0x02, 6043 FW_PORT_DCB_CFG_APPL = 0x04 6044}; 6045 6046enum fw_port_dcb_cfg_rc { 6047 FW_PORT_DCB_CFG_SUCCESS = 0x0, 6048 FW_PORT_DCB_CFG_ERROR = 0x1 6049}; 6050 6051enum fw_port_dcb_type { 6052 FW_PORT_DCB_TYPE_PGID = 0x00, 6053 FW_PORT_DCB_TYPE_PGRATE = 0x01, 6054 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 6055 FW_PORT_DCB_TYPE_PFC = 0x03, 6056 FW_PORT_DCB_TYPE_APP_ID = 0x04, 6057 FW_PORT_DCB_TYPE_CONTROL = 0x05, 6058}; 6059 6060enum fw_port_dcb_feature_state { 6061 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 6062 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 6063 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 6064 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 6065}; 6066 6067enum fw_port_diag_ops { 6068 FW_PORT_DIAGS_TEMP = 0x00, 6069 FW_PORT_DIAGS_TX_POWER = 0x01, 6070 FW_PORT_DIAGS_RX_POWER = 0x02, 6071 FW_PORT_DIAGS_TX_DIS = 0x03, 6072}; 6073 6074struct fw_port_cmd { 6075 __be32 op_to_portid; 6076 __be32 action_to_len16; 6077 union fw_port { 6078 struct fw_port_l1cfg { 6079 __be32 rcap; 6080 __be32 r; 6081 } l1cfg; 6082 struct fw_port_l2cfg { 6083 __u8 ctlbf; 6084 __u8 ovlan3_to_ivlan0; 6085 __be16 ivlantype; 6086 __be16 txipg_force_pinfo; 6087 __be16 mtu; 6088 __be16 ovlan0mask; 6089 __be16 ovlan0type; 6090 __be16 ovlan1mask; 6091 __be16 ovlan1type; 6092 __be16 ovlan2mask; 6093 __be16 ovlan2type; 6094 __be16 ovlan3mask; 6095 __be16 ovlan3type; 6096 } l2cfg; 6097 struct fw_port_info { 6098 __be32 lstatus_to_modtype; 6099 __be16 pcap; 6100 __be16 acap; 6101 __be16 mtu; 6102 __u8 cbllen; 6103 __u8 auxlinfo; 6104 __u8 dcbxdis_pkd; 6105 __u8 r8_lo; 6106 __be16 lpacap; 6107 __be64 r9; 6108 } info; 6109 struct fw_port_diags { 6110 __u8 diagop; 6111 __u8 r[3]; 6112 __be32 diagval; 6113 } diags; 6114 union fw_port_dcb { 6115 struct fw_port_dcb_pgid { 6116 __u8 type; 6117 __u8 apply_pkd; 6118 __u8 r10_lo[2]; 6119 __be32 pgid; 6120 __be64 r11; 6121 } pgid; 6122 struct fw_port_dcb_pgrate { 6123 __u8 type; 6124 __u8 apply_pkd; 6125 __u8 r10_lo[5]; 6126 __u8 num_tcs_supported; 6127 __u8 pgrate[8]; 6128 __u8 tsa[8]; 6129 } pgrate; 6130 struct fw_port_dcb_priorate { 6131 __u8 type; 6132 __u8 apply_pkd; 6133 __u8 r10_lo[6]; 6134 __u8 strict_priorate[8]; 6135 } priorate; 6136 struct fw_port_dcb_pfc { 6137 __u8 type; 6138 __u8 pfcen; 6139 __u8 r10[5]; 6140 __u8 max_pfc_tcs; 6141 __be64 r11; 6142 } pfc; 6143 struct fw_port_app_priority { 6144 __u8 type; 6145 __u8 r10[2]; 6146 __u8 idx; 6147 __u8 user_prio_map; 6148 __u8 sel_field; 6149 __be16 protocolid; 6150 __be64 r12; 6151 } app_priority; 6152 struct fw_port_dcb_control { 6153 __u8 type; 6154 __u8 all_syncd_pkd; 6155 __be16 dcb_version_to_app_state; 6156 __be32 r11; 6157 __be64 r12; 6158 } control; 6159 } dcb; 6160 } u; 6161}; 6162 6163#define S_FW_PORT_CMD_READ 22 6164#define M_FW_PORT_CMD_READ 0x1 6165#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 6166#define G_FW_PORT_CMD_READ(x) \ 6167 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 6168#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 6169 6170#define S_FW_PORT_CMD_PORTID 0 6171#define M_FW_PORT_CMD_PORTID 0xf 6172#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 6173#define G_FW_PORT_CMD_PORTID(x) \ 6174 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 6175 6176#define S_FW_PORT_CMD_ACTION 16 6177#define M_FW_PORT_CMD_ACTION 0xffff 6178#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 6179#define G_FW_PORT_CMD_ACTION(x) \ 6180 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 6181 6182#define S_FW_PORT_CMD_OVLAN3 7 6183#define M_FW_PORT_CMD_OVLAN3 0x1 6184#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 6185#define G_FW_PORT_CMD_OVLAN3(x) \ 6186 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 6187#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 6188 6189#define S_FW_PORT_CMD_OVLAN2 6 6190#define M_FW_PORT_CMD_OVLAN2 0x1 6191#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 6192#define G_FW_PORT_CMD_OVLAN2(x) \ 6193 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 6194#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 6195 6196#define S_FW_PORT_CMD_OVLAN1 5 6197#define M_FW_PORT_CMD_OVLAN1 0x1 6198#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 6199#define G_FW_PORT_CMD_OVLAN1(x) \ 6200 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 6201#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 6202 6203#define S_FW_PORT_CMD_OVLAN0 4 6204#define M_FW_PORT_CMD_OVLAN0 0x1 6205#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 6206#define G_FW_PORT_CMD_OVLAN0(x) \ 6207 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 6208#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 6209 6210#define S_FW_PORT_CMD_IVLAN0 3 6211#define M_FW_PORT_CMD_IVLAN0 0x1 6212#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 6213#define G_FW_PORT_CMD_IVLAN0(x) \ 6214 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 6215#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 6216 6217#define S_FW_PORT_CMD_TXIPG 3 6218#define M_FW_PORT_CMD_TXIPG 0x1fff 6219#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 6220#define G_FW_PORT_CMD_TXIPG(x) \ 6221 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 6222 6223#define S_FW_PORT_CMD_FORCE_PINFO 0 6224#define M_FW_PORT_CMD_FORCE_PINFO 0x1 6225#define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 6226#define G_FW_PORT_CMD_FORCE_PINFO(x) \ 6227 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 6228#define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 6229 6230#define S_FW_PORT_CMD_LSTATUS 31 6231#define M_FW_PORT_CMD_LSTATUS 0x1 6232#define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 6233#define G_FW_PORT_CMD_LSTATUS(x) \ 6234 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 6235#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 6236 6237#define S_FW_PORT_CMD_LSPEED 24 6238#define M_FW_PORT_CMD_LSPEED 0x3f 6239#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 6240#define G_FW_PORT_CMD_LSPEED(x) \ 6241 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 6242 6243#define S_FW_PORT_CMD_TXPAUSE 23 6244#define M_FW_PORT_CMD_TXPAUSE 0x1 6245#define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 6246#define G_FW_PORT_CMD_TXPAUSE(x) \ 6247 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 6248#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 6249 6250#define S_FW_PORT_CMD_RXPAUSE 22 6251#define M_FW_PORT_CMD_RXPAUSE 0x1 6252#define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 6253#define G_FW_PORT_CMD_RXPAUSE(x) \ 6254 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 6255#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 6256 6257#define S_FW_PORT_CMD_MDIOCAP 21 6258#define M_FW_PORT_CMD_MDIOCAP 0x1 6259#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 6260#define G_FW_PORT_CMD_MDIOCAP(x) \ 6261 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 6262#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 6263 6264#define S_FW_PORT_CMD_MDIOADDR 16 6265#define M_FW_PORT_CMD_MDIOADDR 0x1f 6266#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 6267#define G_FW_PORT_CMD_MDIOADDR(x) \ 6268 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 6269 6270#define S_FW_PORT_CMD_LPTXPAUSE 15 6271#define M_FW_PORT_CMD_LPTXPAUSE 0x1 6272#define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 6273#define G_FW_PORT_CMD_LPTXPAUSE(x) \ 6274 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 6275#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 6276 6277#define S_FW_PORT_CMD_LPRXPAUSE 14 6278#define M_FW_PORT_CMD_LPRXPAUSE 0x1 6279#define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 6280#define G_FW_PORT_CMD_LPRXPAUSE(x) \ 6281 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 6282#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 6283 6284#define S_FW_PORT_CMD_PTYPE 8 6285#define M_FW_PORT_CMD_PTYPE 0x1f 6286#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 6287#define G_FW_PORT_CMD_PTYPE(x) \ 6288 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 6289 6290#define S_FW_PORT_CMD_LINKDNRC 5 6291#define M_FW_PORT_CMD_LINKDNRC 0x7 6292#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 6293#define G_FW_PORT_CMD_LINKDNRC(x) \ 6294 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 6295 6296#define S_FW_PORT_CMD_MODTYPE 0 6297#define M_FW_PORT_CMD_MODTYPE 0x1f 6298#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 6299#define G_FW_PORT_CMD_MODTYPE(x) \ 6300 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 6301 6302#define S_FW_PORT_CMD_DCBXDIS 7 6303#define M_FW_PORT_CMD_DCBXDIS 0x1 6304#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 6305#define G_FW_PORT_CMD_DCBXDIS(x) \ 6306 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 6307#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 6308 6309#define S_FW_PORT_CMD_APPLY 7 6310#define M_FW_PORT_CMD_APPLY 0x1 6311#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 6312#define G_FW_PORT_CMD_APPLY(x) \ 6313 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 6314#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 6315 6316#define S_FW_PORT_CMD_ALL_SYNCD 7 6317#define M_FW_PORT_CMD_ALL_SYNCD 0x1 6318#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 6319#define G_FW_PORT_CMD_ALL_SYNCD(x) \ 6320 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 6321#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 6322 6323#define S_FW_PORT_CMD_DCB_VERSION 12 6324#define M_FW_PORT_CMD_DCB_VERSION 0x7 6325#define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 6326#define G_FW_PORT_CMD_DCB_VERSION(x) \ 6327 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 6328 6329#define S_FW_PORT_CMD_PFC_STATE 8 6330#define M_FW_PORT_CMD_PFC_STATE 0xf 6331#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 6332#define G_FW_PORT_CMD_PFC_STATE(x) \ 6333 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 6334 6335#define S_FW_PORT_CMD_ETS_STATE 4 6336#define M_FW_PORT_CMD_ETS_STATE 0xf 6337#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 6338#define G_FW_PORT_CMD_ETS_STATE(x) \ 6339 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 6340 6341#define S_FW_PORT_CMD_APP_STATE 0 6342#define M_FW_PORT_CMD_APP_STATE 0xf 6343#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 6344#define G_FW_PORT_CMD_APP_STATE(x) \ 6345 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 6346 6347/* 6348 * These are configured into the VPD and hence tools that generate 6349 * VPD may use this enumeration. 6350 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 6351 * 6352 * REMEMBER: 6353 * Update the Common Code t4_hw.c:t4_get_port_type_description() 6354 * with any new Firmware Port Technology Types! 6355 */ 6356enum fw_port_type { 6357 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 6358 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 6359 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 6360 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 6361 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 6362 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 6363 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 6364 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 6365 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 6366 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 6367 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 6368 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 6369 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 6370 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 6371 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 6372 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 6373 6374 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 6375}; 6376 6377/* These are read from module's EEPROM and determined once the 6378 module is inserted. */ 6379enum fw_port_module_type { 6380 FW_PORT_MOD_TYPE_NA = 0x0, 6381 FW_PORT_MOD_TYPE_LR = 0x1, 6382 FW_PORT_MOD_TYPE_SR = 0x2, 6383 FW_PORT_MOD_TYPE_ER = 0x3, 6384 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 6385 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 6386 FW_PORT_MOD_TYPE_LRM = 0x6, 6387 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 6388 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 6389 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 6390 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 6391}; 6392 6393/* used by FW and tools may use this to generate VPD */ 6394enum fw_port_mod_sub_type { 6395 FW_PORT_MOD_SUB_TYPE_NA, 6396 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6397 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6398 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6399 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6400 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 6401 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 6402 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 6403 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6404 6405 /* 6406 * The following will never been in the VPD. They are TWINAX cable 6407 * lengths decoded from SFP+ module i2c PROMs. These should almost 6408 * certainly go somewhere else ... 6409 */ 6410 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 6411 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 6412 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 6413 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 6414}; 6415 6416/* link down reason codes (3b) */ 6417enum fw_port_link_dn_rc { 6418 FW_PORT_LINK_DN_RC_NONE, 6419 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 6420 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 6421 FW_PORT_LINK_DN_RESERVED3, 6422 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 6423 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 6424 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 6425 FW_PORT_LINK_DN_RESERVED7 6426}; 6427enum fw_port_stats_tx_index { 6428 FW_STAT_TX_PORT_BYTES_IX = 0, 6429 FW_STAT_TX_PORT_FRAMES_IX, 6430 FW_STAT_TX_PORT_BCAST_IX, 6431 FW_STAT_TX_PORT_MCAST_IX, 6432 FW_STAT_TX_PORT_UCAST_IX, 6433 FW_STAT_TX_PORT_ERROR_IX, 6434 FW_STAT_TX_PORT_64B_IX, 6435 FW_STAT_TX_PORT_65B_127B_IX, 6436 FW_STAT_TX_PORT_128B_255B_IX, 6437 FW_STAT_TX_PORT_256B_511B_IX, 6438 FW_STAT_TX_PORT_512B_1023B_IX, 6439 FW_STAT_TX_PORT_1024B_1518B_IX, 6440 FW_STAT_TX_PORT_1519B_MAX_IX, 6441 FW_STAT_TX_PORT_DROP_IX, 6442 FW_STAT_TX_PORT_PAUSE_IX, 6443 FW_STAT_TX_PORT_PPP0_IX, 6444 FW_STAT_TX_PORT_PPP1_IX, 6445 FW_STAT_TX_PORT_PPP2_IX, 6446 FW_STAT_TX_PORT_PPP3_IX, 6447 FW_STAT_TX_PORT_PPP4_IX, 6448 FW_STAT_TX_PORT_PPP5_IX, 6449 FW_STAT_TX_PORT_PPP6_IX, 6450 FW_STAT_TX_PORT_PPP7_IX, 6451 FW_NUM_PORT_TX_STATS 6452}; 6453 6454enum fw_port_stat_rx_index { 6455 FW_STAT_RX_PORT_BYTES_IX = 0, 6456 FW_STAT_RX_PORT_FRAMES_IX, 6457 FW_STAT_RX_PORT_BCAST_IX, 6458 FW_STAT_RX_PORT_MCAST_IX, 6459 FW_STAT_RX_PORT_UCAST_IX, 6460 FW_STAT_RX_PORT_MTU_ERROR_IX, 6461 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6462 FW_STAT_RX_PORT_CRC_ERROR_IX, 6463 FW_STAT_RX_PORT_LEN_ERROR_IX, 6464 FW_STAT_RX_PORT_SYM_ERROR_IX, 6465 FW_STAT_RX_PORT_64B_IX, 6466 FW_STAT_RX_PORT_65B_127B_IX, 6467 FW_STAT_RX_PORT_128B_255B_IX, 6468 FW_STAT_RX_PORT_256B_511B_IX, 6469 FW_STAT_RX_PORT_512B_1023B_IX, 6470 FW_STAT_RX_PORT_1024B_1518B_IX, 6471 FW_STAT_RX_PORT_1519B_MAX_IX, 6472 FW_STAT_RX_PORT_PAUSE_IX, 6473 FW_STAT_RX_PORT_PPP0_IX, 6474 FW_STAT_RX_PORT_PPP1_IX, 6475 FW_STAT_RX_PORT_PPP2_IX, 6476 FW_STAT_RX_PORT_PPP3_IX, 6477 FW_STAT_RX_PORT_PPP4_IX, 6478 FW_STAT_RX_PORT_PPP5_IX, 6479 FW_STAT_RX_PORT_PPP6_IX, 6480 FW_STAT_RX_PORT_PPP7_IX, 6481 FW_STAT_RX_PORT_LESS_64B_IX, 6482 FW_STAT_RX_PORT_MAC_ERROR_IX, 6483 FW_NUM_PORT_RX_STATS 6484}; 6485/* port stats */ 6486#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 6487 FW_NUM_PORT_RX_STATS) 6488 6489 6490struct fw_port_stats_cmd { 6491 __be32 op_to_portid; 6492 __be32 retval_len16; 6493 union fw_port_stats { 6494 struct fw_port_stats_ctl { 6495 __u8 nstats_bg_bm; 6496 __u8 tx_ix; 6497 __be16 r6; 6498 __be32 r7; 6499 __be64 stat0; 6500 __be64 stat1; 6501 __be64 stat2; 6502 __be64 stat3; 6503 __be64 stat4; 6504 __be64 stat5; 6505 } ctl; 6506 struct fw_port_stats_all { 6507 __be64 tx_bytes; 6508 __be64 tx_frames; 6509 __be64 tx_bcast; 6510 __be64 tx_mcast; 6511 __be64 tx_ucast; 6512 __be64 tx_error; 6513 __be64 tx_64b; 6514 __be64 tx_65b_127b; 6515 __be64 tx_128b_255b; 6516 __be64 tx_256b_511b; 6517 __be64 tx_512b_1023b; 6518 __be64 tx_1024b_1518b; 6519 __be64 tx_1519b_max; 6520 __be64 tx_drop; 6521 __be64 tx_pause; 6522 __be64 tx_ppp0; 6523 __be64 tx_ppp1; 6524 __be64 tx_ppp2; 6525 __be64 tx_ppp3; 6526 __be64 tx_ppp4; 6527 __be64 tx_ppp5; 6528 __be64 tx_ppp6; 6529 __be64 tx_ppp7; 6530 __be64 rx_bytes; 6531 __be64 rx_frames; 6532 __be64 rx_bcast; 6533 __be64 rx_mcast; 6534 __be64 rx_ucast; 6535 __be64 rx_mtu_error; 6536 __be64 rx_mtu_crc_error; 6537 __be64 rx_crc_error; 6538 __be64 rx_len_error; 6539 __be64 rx_sym_error; 6540 __be64 rx_64b; 6541 __be64 rx_65b_127b; 6542 __be64 rx_128b_255b; 6543 __be64 rx_256b_511b; 6544 __be64 rx_512b_1023b; 6545 __be64 rx_1024b_1518b; 6546 __be64 rx_1519b_max; 6547 __be64 rx_pause; 6548 __be64 rx_ppp0; 6549 __be64 rx_ppp1; 6550 __be64 rx_ppp2; 6551 __be64 rx_ppp3; 6552 __be64 rx_ppp4; 6553 __be64 rx_ppp5; 6554 __be64 rx_ppp6; 6555 __be64 rx_ppp7; 6556 __be64 rx_less_64b; 6557 __be64 rx_bg_drop; 6558 __be64 rx_bg_trunc; 6559 } all; 6560 } u; 6561}; 6562 6563#define S_FW_PORT_STATS_CMD_NSTATS 4 6564#define M_FW_PORT_STATS_CMD_NSTATS 0x7 6565#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6566#define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6567 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6568 6569#define S_FW_PORT_STATS_CMD_BG_BM 0 6570#define M_FW_PORT_STATS_CMD_BG_BM 0x3 6571#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6572#define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6573 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6574 6575#define S_FW_PORT_STATS_CMD_TX 7 6576#define M_FW_PORT_STATS_CMD_TX 0x1 6577#define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6578#define G_FW_PORT_STATS_CMD_TX(x) \ 6579 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6580#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6581 6582#define S_FW_PORT_STATS_CMD_IX 0 6583#define M_FW_PORT_STATS_CMD_IX 0x3f 6584#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6585#define G_FW_PORT_STATS_CMD_IX(x) \ 6586 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6587 6588/* port loopback stats */ 6589#define FW_NUM_LB_STATS 14 6590enum fw_port_lb_stats_index { 6591 FW_STAT_LB_PORT_BYTES_IX, 6592 FW_STAT_LB_PORT_FRAMES_IX, 6593 FW_STAT_LB_PORT_BCAST_IX, 6594 FW_STAT_LB_PORT_MCAST_IX, 6595 FW_STAT_LB_PORT_UCAST_IX, 6596 FW_STAT_LB_PORT_ERROR_IX, 6597 FW_STAT_LB_PORT_64B_IX, 6598 FW_STAT_LB_PORT_65B_127B_IX, 6599 FW_STAT_LB_PORT_128B_255B_IX, 6600 FW_STAT_LB_PORT_256B_511B_IX, 6601 FW_STAT_LB_PORT_512B_1023B_IX, 6602 FW_STAT_LB_PORT_1024B_1518B_IX, 6603 FW_STAT_LB_PORT_1519B_MAX_IX, 6604 FW_STAT_LB_PORT_DROP_FRAMES_IX 6605}; 6606 6607struct fw_port_lb_stats_cmd { 6608 __be32 op_to_lbport; 6609 __be32 retval_len16; 6610 union fw_port_lb_stats { 6611 struct fw_port_lb_stats_ctl { 6612 __u8 nstats_bg_bm; 6613 __u8 ix_pkd; 6614 __be16 r6; 6615 __be32 r7; 6616 __be64 stat0; 6617 __be64 stat1; 6618 __be64 stat2; 6619 __be64 stat3; 6620 __be64 stat4; 6621 __be64 stat5; 6622 } ctl; 6623 struct fw_port_lb_stats_all { 6624 __be64 tx_bytes; 6625 __be64 tx_frames; 6626 __be64 tx_bcast; 6627 __be64 tx_mcast; 6628 __be64 tx_ucast; 6629 __be64 tx_error; 6630 __be64 tx_64b; 6631 __be64 tx_65b_127b; 6632 __be64 tx_128b_255b; 6633 __be64 tx_256b_511b; 6634 __be64 tx_512b_1023b; 6635 __be64 tx_1024b_1518b; 6636 __be64 tx_1519b_max; 6637 __be64 rx_lb_drop; 6638 __be64 rx_lb_trunc; 6639 } all; 6640 } u; 6641}; 6642 6643#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6644#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6645#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6646 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6647#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6648 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6649 6650#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6651#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6652#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6653 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6654#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6655 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6656 6657#define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6658#define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6659#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6660#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6661 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6662 6663#define S_FW_PORT_LB_STATS_CMD_IX 0 6664#define M_FW_PORT_LB_STATS_CMD_IX 0xf 6665#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6666#define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6667 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6668 6669/* Trace related defines */ 6670#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6671#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6672 6673struct fw_port_trace_cmd { 6674 __be32 op_to_portid; 6675 __be32 retval_len16; 6676 __be16 traceen_to_pciech; 6677 __be16 qnum; 6678 __be32 r5; 6679}; 6680 6681#define S_FW_PORT_TRACE_CMD_PORTID 0 6682#define M_FW_PORT_TRACE_CMD_PORTID 0xf 6683#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6684#define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6685 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6686 6687#define S_FW_PORT_TRACE_CMD_TRACEEN 15 6688#define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6689#define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6690#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6691 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6692#define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6693 6694#define S_FW_PORT_TRACE_CMD_FLTMODE 14 6695#define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6696#define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6697#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6698 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6699#define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6700 6701#define S_FW_PORT_TRACE_CMD_DUPLEN 13 6702#define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6703#define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6704#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6705 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6706#define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6707 6708#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6709#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6710#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6711 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6712#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6713 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6714 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6715 6716#define S_FW_PORT_TRACE_CMD_PCIECH 6 6717#define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6718#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6719#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6720 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6721 6722struct fw_port_trace_mmap_cmd { 6723 __be32 op_to_portid; 6724 __be32 retval_len16; 6725 __be32 fid_to_skipoffset; 6726 __be32 minpktsize_capturemax; 6727 __u8 map[224]; 6728}; 6729 6730#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6731#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6732#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6733 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6734#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6735 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6736 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6737 6738#define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6739#define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6740#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6741#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6742 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6743 6744#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6745#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6746#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6747 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6748#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6749 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6750 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6751#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6752 6753#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6754#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6755#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6756 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6757#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6758 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6759 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6760#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6761 6762#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6763#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6764#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6765 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6766#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6767 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6768 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6769 6770#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6771#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6772#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6773 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6774#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6775 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6776 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6777 6778#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6779#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6780#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6781 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6782#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6783 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6784 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6785 6786#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6787#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6788#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6789 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6790#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6791 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6792 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6793 6794enum fw_ptp_subop { 6795 6796 /* none */ 6797 FW_PTP_SC_INIT_TIMER = 0x00, 6798 FW_PTP_SC_TX_TYPE = 0x01, 6799 6800 /* init */ 6801 FW_PTP_SC_RXTIME_STAMP = 0x08, 6802 FW_PTP_SC_RDRX_TYPE = 0x09, 6803 6804 /* ts */ 6805 FW_PTP_SC_ADJ_FREQ = 0x10, 6806 FW_PTP_SC_ADJ_TIME = 0x11, 6807 FW_PTP_SC_ADJ_FTIME = 0x12, 6808 FW_PTP_SC_WALL_CLOCK = 0x13, 6809 FW_PTP_SC_GET_TIME = 0x14, 6810 FW_PTP_SC_SET_TIME = 0x15, 6811}; 6812 6813struct fw_ptp_cmd { 6814 __be32 op_to_portid; 6815 __be32 retval_len16; 6816 union fw_ptp { 6817 struct fw_ptp_sc { 6818 __u8 sc; 6819 __u8 r3[7]; 6820 } scmd; 6821 struct fw_ptp_init { 6822 __u8 sc; 6823 __u8 txchan; 6824 __be16 absid; 6825 __be16 mode; 6826 __be16 r3; 6827 } init; 6828 struct fw_ptp_ts { 6829 __u8 sc; 6830 __u8 r3; 6831 __be16 ppb; 6832 __be32 r4; 6833 __be64 tm; 6834 } ts; 6835 } u; 6836 __be64 r3; 6837}; 6838 6839#define S_FW_PTP_CMD_PORTID 0 6840#define M_FW_PTP_CMD_PORTID 0xf 6841#define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 6842#define G_FW_PTP_CMD_PORTID(x) \ 6843 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 6844 6845struct fw_rss_ind_tbl_cmd { 6846 __be32 op_to_viid; 6847 __be32 retval_len16; 6848 __be16 niqid; 6849 __be16 startidx; 6850 __be32 r3; 6851 __be32 iq0_to_iq2; 6852 __be32 iq3_to_iq5; 6853 __be32 iq6_to_iq8; 6854 __be32 iq9_to_iq11; 6855 __be32 iq12_to_iq14; 6856 __be32 iq15_to_iq17; 6857 __be32 iq18_to_iq20; 6858 __be32 iq21_to_iq23; 6859 __be32 iq24_to_iq26; 6860 __be32 iq27_to_iq29; 6861 __be32 iq30_iq31; 6862 __be32 r15_lo; 6863}; 6864 6865#define S_FW_RSS_IND_TBL_CMD_VIID 0 6866#define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6867#define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6868#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6869 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6870 6871#define S_FW_RSS_IND_TBL_CMD_IQ0 20 6872#define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6873#define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6874#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6875 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6876 6877#define S_FW_RSS_IND_TBL_CMD_IQ1 10 6878#define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6879#define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6880#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6881 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6882 6883#define S_FW_RSS_IND_TBL_CMD_IQ2 0 6884#define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6885#define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6886#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6887 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6888 6889#define S_FW_RSS_IND_TBL_CMD_IQ3 20 6890#define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6891#define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6892#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6893 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6894 6895#define S_FW_RSS_IND_TBL_CMD_IQ4 10 6896#define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6897#define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6898#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6899 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6900 6901#define S_FW_RSS_IND_TBL_CMD_IQ5 0 6902#define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6903#define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6904#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6905 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6906 6907#define S_FW_RSS_IND_TBL_CMD_IQ6 20 6908#define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6909#define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6910#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6911 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6912 6913#define S_FW_RSS_IND_TBL_CMD_IQ7 10 6914#define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6915#define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6916#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6917 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6918 6919#define S_FW_RSS_IND_TBL_CMD_IQ8 0 6920#define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6921#define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6922#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6923 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6924 6925#define S_FW_RSS_IND_TBL_CMD_IQ9 20 6926#define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6927#define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6928#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6929 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6930 6931#define S_FW_RSS_IND_TBL_CMD_IQ10 10 6932#define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6933#define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6934#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6935 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6936 6937#define S_FW_RSS_IND_TBL_CMD_IQ11 0 6938#define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6939#define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6940#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6941 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6942 6943#define S_FW_RSS_IND_TBL_CMD_IQ12 20 6944#define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6945#define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6946#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6947 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6948 6949#define S_FW_RSS_IND_TBL_CMD_IQ13 10 6950#define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6951#define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6952#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6953 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6954 6955#define S_FW_RSS_IND_TBL_CMD_IQ14 0 6956#define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6957#define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6958#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6959 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6960 6961#define S_FW_RSS_IND_TBL_CMD_IQ15 20 6962#define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6963#define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6964#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6965 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6966 6967#define S_FW_RSS_IND_TBL_CMD_IQ16 10 6968#define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6969#define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6970#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6971 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6972 6973#define S_FW_RSS_IND_TBL_CMD_IQ17 0 6974#define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6975#define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6976#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6977 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6978 6979#define S_FW_RSS_IND_TBL_CMD_IQ18 20 6980#define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6981#define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6982#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6983 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6984 6985#define S_FW_RSS_IND_TBL_CMD_IQ19 10 6986#define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6987#define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6988#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6989 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6990 6991#define S_FW_RSS_IND_TBL_CMD_IQ20 0 6992#define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6993#define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6994#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6995 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6996 6997#define S_FW_RSS_IND_TBL_CMD_IQ21 20 6998#define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6999#define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 7000#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 7001 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 7002 7003#define S_FW_RSS_IND_TBL_CMD_IQ22 10 7004#define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 7005#define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 7006#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 7007 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 7008 7009#define S_FW_RSS_IND_TBL_CMD_IQ23 0 7010#define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 7011#define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 7012#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 7013 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 7014 7015#define S_FW_RSS_IND_TBL_CMD_IQ24 20 7016#define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 7017#define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 7018#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 7019 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 7020 7021#define S_FW_RSS_IND_TBL_CMD_IQ25 10 7022#define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 7023#define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 7024#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 7025 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 7026 7027#define S_FW_RSS_IND_TBL_CMD_IQ26 0 7028#define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 7029#define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 7030#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 7031 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 7032 7033#define S_FW_RSS_IND_TBL_CMD_IQ27 20 7034#define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 7035#define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 7036#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 7037 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 7038 7039#define S_FW_RSS_IND_TBL_CMD_IQ28 10 7040#define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 7041#define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 7042#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 7043 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 7044 7045#define S_FW_RSS_IND_TBL_CMD_IQ29 0 7046#define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 7047#define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 7048#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 7049 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 7050 7051#define S_FW_RSS_IND_TBL_CMD_IQ30 20 7052#define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 7053#define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 7054#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 7055 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 7056 7057#define S_FW_RSS_IND_TBL_CMD_IQ31 10 7058#define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 7059#define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 7060#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 7061 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 7062 7063struct fw_rss_glb_config_cmd { 7064 __be32 op_to_write; 7065 __be32 retval_len16; 7066 union fw_rss_glb_config { 7067 struct fw_rss_glb_config_manual { 7068 __be32 mode_pkd; 7069 __be32 r3; 7070 __be64 r4; 7071 __be64 r5; 7072 } manual; 7073 struct fw_rss_glb_config_basicvirtual { 7074 __be32 mode_pkd; 7075 __be32 synmapen_to_hashtoeplitz; 7076 __be64 r8; 7077 __be64 r9; 7078 } basicvirtual; 7079 } u; 7080}; 7081 7082#define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 7083#define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 7084#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 7085#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 7086 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 7087 7088#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 7089#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 7090#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 7091 7092#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 7093#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 7094#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7095 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7096#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7097 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 7098 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7099#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 7100 7101#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 7102#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 7103#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7104 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7105#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7106 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 7107 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7108#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 7109 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 7110 7111#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 7112#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 7113#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7114 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7115#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7116 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 7117 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7118#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 7119 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 7120 7121#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 7122#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 7123#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7124 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7125#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7126 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 7127 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7128#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 7129 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 7130 7131#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 7132#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 7133#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7134 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7135#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7136 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 7137 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7138#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 7139 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 7140 7141#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 7142#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 7143#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7144 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7145#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7146 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 7147 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7148#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 7149 7150#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 7151#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 7152#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7153 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7154#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7155 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 7156 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7157#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 7158 7159#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 7160#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 7161#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7162 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7163#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7164 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 7165 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7166#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 7167 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 7168 7169#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 7170#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 7171#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7172 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7173#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 7174 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 7175 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 7176#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 7177 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 7178 7179struct fw_rss_vi_config_cmd { 7180 __be32 op_to_viid; 7181 __be32 retval_len16; 7182 union fw_rss_vi_config { 7183 struct fw_rss_vi_config_manual { 7184 __be64 r3; 7185 __be64 r4; 7186 __be64 r5; 7187 } manual; 7188 struct fw_rss_vi_config_basicvirtual { 7189 __be32 r6; 7190 __be32 defaultq_to_udpen; 7191 __be64 r9; 7192 __be64 r10; 7193 } basicvirtual; 7194 } u; 7195}; 7196 7197#define S_FW_RSS_VI_CONFIG_CMD_VIID 0 7198#define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 7199#define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 7200#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 7201 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 7202 7203#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 7204#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 7205#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7206 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7207#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 7208 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 7209 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 7210 7211#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 7212#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 7213#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7214 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7215#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 7216 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 7217 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 7218#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 7219 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 7220 7221#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 7222#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 7223#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7224 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7225#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 7226 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 7227 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 7228#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 7229 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 7230 7231#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 7232#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 7233#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7234 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7235#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 7236 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 7237 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 7238#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 7239 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 7240 7241#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 7242#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 7243#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7244 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7245#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 7246 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 7247 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 7248#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 7249 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 7250 7251#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 7252#define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 7253#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 7254#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 7255 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 7256#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 7257 7258enum fw_sched_sc { 7259 FW_SCHED_SC_CONFIG = 0, 7260 FW_SCHED_SC_PARAMS = 1, 7261}; 7262 7263enum fw_sched_type { 7264 FW_SCHED_TYPE_PKTSCHED = 0, 7265 FW_SCHED_TYPE_STREAMSCHED = 1, 7266}; 7267 7268enum fw_sched_params_level { 7269 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 7270 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 7271 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 7272}; 7273 7274enum fw_sched_params_mode { 7275 FW_SCHED_PARAMS_MODE_CLASS = 0, 7276 FW_SCHED_PARAMS_MODE_FLOW = 1, 7277}; 7278 7279enum fw_sched_params_unit { 7280 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 7281 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 7282}; 7283 7284enum fw_sched_params_rate { 7285 FW_SCHED_PARAMS_RATE_REL = 0, 7286 FW_SCHED_PARAMS_RATE_ABS = 1, 7287}; 7288 7289struct fw_sched_cmd { 7290 __be32 op_to_write; 7291 __be32 retval_len16; 7292 union fw_sched { 7293 struct fw_sched_config { 7294 __u8 sc; 7295 __u8 type; 7296 __u8 minmaxen; 7297 __u8 r3[5]; 7298 __u8 nclasses[4]; 7299 __be32 r4; 7300 } config; 7301 struct fw_sched_params { 7302 __u8 sc; 7303 __u8 type; 7304 __u8 level; 7305 __u8 mode; 7306 __u8 unit; 7307 __u8 rate; 7308 __u8 ch; 7309 __u8 cl; 7310 __be32 min; 7311 __be32 max; 7312 __be16 weight; 7313 __be16 pktsize; 7314 __be16 burstsize; 7315 __be16 r4; 7316 } params; 7317 } u; 7318}; 7319 7320/* 7321 * length of the formatting string 7322 */ 7323#define FW_DEVLOG_FMT_LEN 192 7324 7325/* 7326 * maximum number of the formatting string parameters 7327 */ 7328#define FW_DEVLOG_FMT_PARAMS_NUM 8 7329 7330/* 7331 * priority levels 7332 */ 7333enum fw_devlog_level { 7334 FW_DEVLOG_LEVEL_EMERG = 0x0, 7335 FW_DEVLOG_LEVEL_CRIT = 0x1, 7336 FW_DEVLOG_LEVEL_ERR = 0x2, 7337 FW_DEVLOG_LEVEL_NOTICE = 0x3, 7338 FW_DEVLOG_LEVEL_INFO = 0x4, 7339 FW_DEVLOG_LEVEL_DEBUG = 0x5, 7340 FW_DEVLOG_LEVEL_MAX = 0x5, 7341}; 7342 7343/* 7344 * facilities that may send a log message 7345 */ 7346enum fw_devlog_facility { 7347 FW_DEVLOG_FACILITY_CORE = 0x00, 7348 FW_DEVLOG_FACILITY_CF = 0x01, 7349 FW_DEVLOG_FACILITY_SCHED = 0x02, 7350 FW_DEVLOG_FACILITY_TIMER = 0x04, 7351 FW_DEVLOG_FACILITY_RES = 0x06, 7352 FW_DEVLOG_FACILITY_HW = 0x08, 7353 FW_DEVLOG_FACILITY_FLR = 0x10, 7354 FW_DEVLOG_FACILITY_DMAQ = 0x12, 7355 FW_DEVLOG_FACILITY_PHY = 0x14, 7356 FW_DEVLOG_FACILITY_MAC = 0x16, 7357 FW_DEVLOG_FACILITY_PORT = 0x18, 7358 FW_DEVLOG_FACILITY_VI = 0x1A, 7359 FW_DEVLOG_FACILITY_FILTER = 0x1C, 7360 FW_DEVLOG_FACILITY_ACL = 0x1E, 7361 FW_DEVLOG_FACILITY_TM = 0x20, 7362 FW_DEVLOG_FACILITY_QFC = 0x22, 7363 FW_DEVLOG_FACILITY_DCB = 0x24, 7364 FW_DEVLOG_FACILITY_ETH = 0x26, 7365 FW_DEVLOG_FACILITY_OFLD = 0x28, 7366 FW_DEVLOG_FACILITY_RI = 0x2A, 7367 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 7368 FW_DEVLOG_FACILITY_FCOE = 0x2E, 7369 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 7370 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 7371 FW_DEVLOG_FACILITY_CHNET = 0x34, 7372 FW_DEVLOG_FACILITY_MAX = 0x34 7373}; 7374 7375/* 7376 * log message format 7377 */ 7378struct fw_devlog_e { 7379 __be64 timestamp; 7380 __be32 seqno; 7381 __be16 reserved1; 7382 __u8 level; 7383 __u8 facility; 7384 __u8 fmt[FW_DEVLOG_FMT_LEN]; 7385 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 7386 __be32 reserved3[4]; 7387}; 7388 7389struct fw_devlog_cmd { 7390 __be32 op_to_write; 7391 __be32 retval_len16; 7392 __u8 level; 7393 __u8 r2[7]; 7394 __be32 memtype_devlog_memaddr16_devlog; 7395 __be32 memsize_devlog; 7396 __be32 r3[2]; 7397}; 7398 7399#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 7400#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 7401#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7402 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7403#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7404 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7405 7406#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 7407#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 7408#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7409 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7410#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7411 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 7412 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7413 7414enum fw_watchdog_actions { 7415 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 7416 FW_WATCHDOG_ACTION_FLR = 1, 7417 FW_WATCHDOG_ACTION_BYPASS = 2, 7418 FW_WATCHDOG_ACTION_TMPCHK = 3, 7419 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 7420 7421 FW_WATCHDOG_ACTION_MAX = 5, 7422}; 7423 7424#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 7425 7426struct fw_watchdog_cmd { 7427 __be32 op_to_vfn; 7428 __be32 retval_len16; 7429 __be32 timeout; 7430 __be32 action; 7431}; 7432 7433#define S_FW_WATCHDOG_CMD_PFN 8 7434#define M_FW_WATCHDOG_CMD_PFN 0x7 7435#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 7436#define G_FW_WATCHDOG_CMD_PFN(x) \ 7437 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 7438 7439#define S_FW_WATCHDOG_CMD_VFN 0 7440#define M_FW_WATCHDOG_CMD_VFN 0xff 7441#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 7442#define G_FW_WATCHDOG_CMD_VFN(x) \ 7443 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 7444 7445struct fw_clip_cmd { 7446 __be32 op_to_write; 7447 __be32 alloc_to_len16; 7448 __be64 ip_hi; 7449 __be64 ip_lo; 7450 __be32 r4[2]; 7451}; 7452 7453#define S_FW_CLIP_CMD_ALLOC 31 7454#define M_FW_CLIP_CMD_ALLOC 0x1 7455#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 7456#define G_FW_CLIP_CMD_ALLOC(x) \ 7457 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 7458#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 7459 7460#define S_FW_CLIP_CMD_FREE 30 7461#define M_FW_CLIP_CMD_FREE 0x1 7462#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 7463#define G_FW_CLIP_CMD_FREE(x) \ 7464 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 7465#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 7466 7467/****************************************************************************** 7468 * F O i S C S I C O M M A N D s 7469 **************************************/ 7470 7471#define FW_CHNET_IFACE_ADDR_MAX 3 7472 7473enum fw_chnet_iface_cmd_subop { 7474 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 7475 7476 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 7477 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 7478 7479 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 7480 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 7481 7482 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7483}; 7484 7485struct fw_chnet_iface_cmd { 7486 __be32 op_to_portid; 7487 __be32 retval_len16; 7488 __u8 subop; 7489 __u8 r2[3]; 7490 __be32 ifid_ifstate; 7491 __be16 mtu; 7492 __be16 vlanid; 7493 __be32 r3; 7494 __be16 r4; 7495 __u8 mac[6]; 7496}; 7497 7498#define S_FW_CHNET_IFACE_CMD_PORTID 0 7499#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7500#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7501#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7502 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7503 7504#define S_FW_CHNET_IFACE_CMD_IFID 8 7505#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7506#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7507#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7508 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7509 7510#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7511#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7512#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7513#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7514 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7515 7516struct fw_fcoe_res_info_cmd { 7517 __be32 op_to_read; 7518 __be32 retval_len16; 7519 __be16 e_d_tov; 7520 __be16 r_a_tov_seq; 7521 __be16 r_a_tov_els; 7522 __be16 r_r_tov; 7523 __be32 max_xchgs; 7524 __be32 max_ssns; 7525 __be32 used_xchgs; 7526 __be32 used_ssns; 7527 __be32 max_fcfs; 7528 __be32 max_vnps; 7529 __be32 used_fcfs; 7530 __be32 used_vnps; 7531}; 7532 7533struct fw_fcoe_link_cmd { 7534 __be32 op_to_portid; 7535 __be32 retval_len16; 7536 __be32 sub_opcode_fcfi; 7537 __u8 r3; 7538 __u8 lstatus; 7539 __be16 flags; 7540 __u8 r4; 7541 __u8 set_vlan; 7542 __be16 vlan_id; 7543 __be32 vnpi_pkd; 7544 __be16 r6; 7545 __u8 phy_mac[6]; 7546 __u8 vnport_wwnn[8]; 7547 __u8 vnport_wwpn[8]; 7548}; 7549 7550#define S_FW_FCOE_LINK_CMD_PORTID 0 7551#define M_FW_FCOE_LINK_CMD_PORTID 0xf 7552#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7553#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7554 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7555 7556#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7557#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7558#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7559 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7560#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7561 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7562 7563#define S_FW_FCOE_LINK_CMD_FCFI 0 7564#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7565#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7566#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7567 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7568 7569#define S_FW_FCOE_LINK_CMD_VNPI 0 7570#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7571#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7572#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7573 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7574 7575struct fw_fcoe_vnp_cmd { 7576 __be32 op_to_fcfi; 7577 __be32 alloc_to_len16; 7578 __be32 gen_wwn_to_vnpi; 7579 __be32 vf_id; 7580 __be16 iqid; 7581 __u8 vnport_mac[6]; 7582 __u8 vnport_wwnn[8]; 7583 __u8 vnport_wwpn[8]; 7584 __u8 cmn_srv_parms[16]; 7585 __u8 clsp_word_0_1[8]; 7586}; 7587 7588#define S_FW_FCOE_VNP_CMD_FCFI 0 7589#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7590#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7591#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7592 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7593 7594#define S_FW_FCOE_VNP_CMD_ALLOC 31 7595#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7596#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7597#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7598 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7599#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7600 7601#define S_FW_FCOE_VNP_CMD_FREE 30 7602#define M_FW_FCOE_VNP_CMD_FREE 0x1 7603#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7604#define G_FW_FCOE_VNP_CMD_FREE(x) \ 7605 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7606#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7607 7608#define S_FW_FCOE_VNP_CMD_MODIFY 29 7609#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7610#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7611#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7612 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7613#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7614 7615#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7616#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7617#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7618#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7619 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7620#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7621 7622#define S_FW_FCOE_VNP_CMD_PERSIST 21 7623#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7624#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7625#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7626 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7627#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7628 7629#define S_FW_FCOE_VNP_CMD_VFID_EN 20 7630#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7631#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7632#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7633 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7634#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7635 7636#define S_FW_FCOE_VNP_CMD_VNPI 0 7637#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7638#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7639#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7640 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7641 7642struct fw_fcoe_sparams_cmd { 7643 __be32 op_to_portid; 7644 __be32 retval_len16; 7645 __u8 r3[7]; 7646 __u8 cos; 7647 __u8 lport_wwnn[8]; 7648 __u8 lport_wwpn[8]; 7649 __u8 cmn_srv_parms[16]; 7650 __u8 cls_srv_parms[16]; 7651}; 7652 7653#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7654#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7655#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7656#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7657 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7658 7659struct fw_fcoe_stats_cmd { 7660 __be32 op_to_flowid; 7661 __be32 free_to_len16; 7662 union fw_fcoe_stats { 7663 struct fw_fcoe_stats_ctl { 7664 __u8 nstats_port; 7665 __u8 port_valid_ix; 7666 __be16 r6; 7667 __be32 r7; 7668 __be64 stat0; 7669 __be64 stat1; 7670 __be64 stat2; 7671 __be64 stat3; 7672 __be64 stat4; 7673 __be64 stat5; 7674 } ctl; 7675 struct fw_fcoe_port_stats { 7676 __be64 tx_bcast_bytes; 7677 __be64 tx_bcast_frames; 7678 __be64 tx_mcast_bytes; 7679 __be64 tx_mcast_frames; 7680 __be64 tx_ucast_bytes; 7681 __be64 tx_ucast_frames; 7682 __be64 tx_drop_frames; 7683 __be64 tx_offload_bytes; 7684 __be64 tx_offload_frames; 7685 __be64 rx_bcast_bytes; 7686 __be64 rx_bcast_frames; 7687 __be64 rx_mcast_bytes; 7688 __be64 rx_mcast_frames; 7689 __be64 rx_ucast_bytes; 7690 __be64 rx_ucast_frames; 7691 __be64 rx_err_frames; 7692 } port_stats; 7693 struct fw_fcoe_fcf_stats { 7694 __be32 fip_tx_bytes; 7695 __be32 fip_tx_fr; 7696 __be64 fcf_ka; 7697 __be64 mcast_adv_rcvd; 7698 __be16 ucast_adv_rcvd; 7699 __be16 sol_sent; 7700 __be16 vlan_req; 7701 __be16 vlan_rpl; 7702 __be16 clr_vlink; 7703 __be16 link_down; 7704 __be16 link_up; 7705 __be16 logo; 7706 __be16 flogi_req; 7707 __be16 flogi_rpl; 7708 __be16 fdisc_req; 7709 __be16 fdisc_rpl; 7710 __be16 fka_prd_chg; 7711 __be16 fc_map_chg; 7712 __be16 vfid_chg; 7713 __u8 no_fka_req; 7714 __u8 no_vnp; 7715 } fcf_stats; 7716 struct fw_fcoe_pcb_stats { 7717 __be64 tx_bytes; 7718 __be64 tx_frames; 7719 __be64 rx_bytes; 7720 __be64 rx_frames; 7721 __be32 vnp_ka; 7722 __be32 unsol_els_rcvd; 7723 __be64 unsol_cmd_rcvd; 7724 __be16 implicit_logo; 7725 __be16 flogi_inv_sparm; 7726 __be16 fdisc_inv_sparm; 7727 __be16 flogi_rjt; 7728 __be16 fdisc_rjt; 7729 __be16 no_ssn; 7730 __be16 mac_flt_fail; 7731 __be16 inv_fr_rcvd; 7732 } pcb_stats; 7733 struct fw_fcoe_scb_stats { 7734 __be64 tx_bytes; 7735 __be64 tx_frames; 7736 __be64 rx_bytes; 7737 __be64 rx_frames; 7738 __be32 host_abrt_req; 7739 __be32 adap_auto_abrt; 7740 __be32 adap_abrt_rsp; 7741 __be32 host_ios_req; 7742 __be16 ssn_offl_ios; 7743 __be16 ssn_not_rdy_ios; 7744 __u8 rx_data_ddp_err; 7745 __u8 ddp_flt_set_err; 7746 __be16 rx_data_fr_err; 7747 __u8 bad_st_abrt_req; 7748 __u8 no_io_abrt_req; 7749 __u8 abort_tmo; 7750 __u8 abort_tmo_2; 7751 __be32 abort_req; 7752 __u8 no_ppod_res_tmo; 7753 __u8 bp_tmo; 7754 __u8 adap_auto_cls; 7755 __u8 no_io_cls_req; 7756 __be32 host_cls_req; 7757 __be64 unsol_cmd_rcvd; 7758 __be32 plogi_req_rcvd; 7759 __be32 prli_req_rcvd; 7760 __be16 logo_req_rcvd; 7761 __be16 prlo_req_rcvd; 7762 __be16 plogi_rjt_rcvd; 7763 __be16 prli_rjt_rcvd; 7764 __be32 adisc_req_rcvd; 7765 __be32 rscn_rcvd; 7766 __be32 rrq_req_rcvd; 7767 __be32 unsol_els_rcvd; 7768 __u8 adisc_rjt_rcvd; 7769 __u8 scr_rjt; 7770 __u8 ct_rjt; 7771 __u8 inval_bls_rcvd; 7772 __be32 ba_rjt_rcvd; 7773 } scb_stats; 7774 } u; 7775}; 7776 7777#define S_FW_FCOE_STATS_CMD_FLOWID 0 7778#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7779#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7780#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7781 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7782 7783#define S_FW_FCOE_STATS_CMD_FREE 30 7784#define M_FW_FCOE_STATS_CMD_FREE 0x1 7785#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7786#define G_FW_FCOE_STATS_CMD_FREE(x) \ 7787 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7788#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7789 7790#define S_FW_FCOE_STATS_CMD_NSTATS 4 7791#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7792#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7793#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7794 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7795 7796#define S_FW_FCOE_STATS_CMD_PORT 0 7797#define M_FW_FCOE_STATS_CMD_PORT 0x3 7798#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7799#define G_FW_FCOE_STATS_CMD_PORT(x) \ 7800 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7801 7802#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7803#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7804#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7805 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7806#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7807 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7808#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7809 7810#define S_FW_FCOE_STATS_CMD_IX 0 7811#define M_FW_FCOE_STATS_CMD_IX 0x3f 7812#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7813#define G_FW_FCOE_STATS_CMD_IX(x) \ 7814 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7815 7816struct fw_fcoe_fcf_cmd { 7817 __be32 op_to_fcfi; 7818 __be32 retval_len16; 7819 __be16 priority_pkd; 7820 __u8 mac[6]; 7821 __u8 name_id[8]; 7822 __u8 fabric[8]; 7823 __be16 vf_id; 7824 __be16 max_fcoe_size; 7825 __u8 vlan_id; 7826 __u8 fc_map[3]; 7827 __be32 fka_adv; 7828 __be32 r6; 7829 __u8 r7_hi; 7830 __u8 fpma_to_portid; 7831 __u8 spma_mac[6]; 7832 __be64 r8; 7833}; 7834 7835#define S_FW_FCOE_FCF_CMD_FCFI 0 7836#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7837#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7838#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7839 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7840 7841#define S_FW_FCOE_FCF_CMD_PRIORITY 0 7842#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7843#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7844#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7845 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7846 7847#define S_FW_FCOE_FCF_CMD_FPMA 6 7848#define M_FW_FCOE_FCF_CMD_FPMA 0x1 7849#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7850#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7851 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7852#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7853 7854#define S_FW_FCOE_FCF_CMD_SPMA 5 7855#define M_FW_FCOE_FCF_CMD_SPMA 0x1 7856#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7857#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7858 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7859#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7860 7861#define S_FW_FCOE_FCF_CMD_LOGIN 4 7862#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7863#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7864#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7865 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7866#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7867 7868#define S_FW_FCOE_FCF_CMD_PORTID 0 7869#define M_FW_FCOE_FCF_CMD_PORTID 0xf 7870#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7871#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7872 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7873 7874/****************************************************************************** 7875 * E R R O R a n d D E B U G C O M M A N D s 7876 ******************************************************/ 7877 7878enum fw_error_type { 7879 FW_ERROR_TYPE_EXCEPTION = 0x0, 7880 FW_ERROR_TYPE_HWMODULE = 0x1, 7881 FW_ERROR_TYPE_WR = 0x2, 7882 FW_ERROR_TYPE_ACL = 0x3, 7883}; 7884 7885struct fw_error_cmd { 7886 __be32 op_to_type; 7887 __be32 len16_pkd; 7888 union fw_error { 7889 struct fw_error_exception { 7890 __be32 info[6]; 7891 } exception; 7892 struct fw_error_hwmodule { 7893 __be32 regaddr; 7894 __be32 regval; 7895 } hwmodule; 7896 struct fw_error_wr { 7897 __be16 cidx; 7898 __be16 pfn_vfn; 7899 __be32 eqid; 7900 __u8 wrhdr[16]; 7901 } wr; 7902 struct fw_error_acl { 7903 __be16 cidx; 7904 __be16 pfn_vfn; 7905 __be32 eqid; 7906 __be16 mv_pkd; 7907 __u8 val[6]; 7908 __be64 r4; 7909 } acl; 7910 } u; 7911}; 7912 7913#define S_FW_ERROR_CMD_FATAL 4 7914#define M_FW_ERROR_CMD_FATAL 0x1 7915#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7916#define G_FW_ERROR_CMD_FATAL(x) \ 7917 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7918#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7919 7920#define S_FW_ERROR_CMD_TYPE 0 7921#define M_FW_ERROR_CMD_TYPE 0xf 7922#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7923#define G_FW_ERROR_CMD_TYPE(x) \ 7924 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7925 7926#define S_FW_ERROR_CMD_PFN 8 7927#define M_FW_ERROR_CMD_PFN 0x7 7928#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7929#define G_FW_ERROR_CMD_PFN(x) \ 7930 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7931 7932#define S_FW_ERROR_CMD_VFN 0 7933#define M_FW_ERROR_CMD_VFN 0xff 7934#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7935#define G_FW_ERROR_CMD_VFN(x) \ 7936 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7937 7938#define S_FW_ERROR_CMD_PFN 8 7939#define M_FW_ERROR_CMD_PFN 0x7 7940#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7941#define G_FW_ERROR_CMD_PFN(x) \ 7942 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7943 7944#define S_FW_ERROR_CMD_VFN 0 7945#define M_FW_ERROR_CMD_VFN 0xff 7946#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7947#define G_FW_ERROR_CMD_VFN(x) \ 7948 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7949 7950#define S_FW_ERROR_CMD_MV 15 7951#define M_FW_ERROR_CMD_MV 0x1 7952#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7953#define G_FW_ERROR_CMD_MV(x) \ 7954 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7955#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7956 7957struct fw_debug_cmd { 7958 __be32 op_type; 7959 __be32 len16_pkd; 7960 union fw_debug { 7961 struct fw_debug_assert { 7962 __be32 fcid; 7963 __be32 line; 7964 __be32 x; 7965 __be32 y; 7966 __u8 filename_0_7[8]; 7967 __u8 filename_8_15[8]; 7968 __be64 r3; 7969 } assert; 7970 struct fw_debug_prt { 7971 __be16 dprtstridx; 7972 __be16 r3[3]; 7973 __be32 dprtstrparam0; 7974 __be32 dprtstrparam1; 7975 __be32 dprtstrparam2; 7976 __be32 dprtstrparam3; 7977 } prt; 7978 } u; 7979}; 7980 7981#define S_FW_DEBUG_CMD_TYPE 0 7982#define M_FW_DEBUG_CMD_TYPE 0xff 7983#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7984#define G_FW_DEBUG_CMD_TYPE(x) \ 7985 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7986 7987/****************************************************************************** 7988 * P C I E F W R E G I S T E R 7989 **************************************/ 7990 7991enum pcie_fw_eval { 7992 PCIE_FW_EVAL_CRASH = 0, 7993 PCIE_FW_EVAL_PREP = 1, 7994 PCIE_FW_EVAL_CONF = 2, 7995 PCIE_FW_EVAL_INIT = 3, 7996 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7997 PCIE_FW_EVAL_OVERHEAT = 5, 7998 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7999}; 8000 8001/** 8002 * Register definitions for the PCIE_FW register which the firmware uses 8003 * to retain status across RESETs. This register should be considered 8004 * as a READ-ONLY register for Host Software and only to be used to 8005 * track firmware initialization/error state, etc. 8006 */ 8007#define S_PCIE_FW_ERR 31 8008#define M_PCIE_FW_ERR 0x1 8009#define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 8010#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 8011#define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 8012 8013#define S_PCIE_FW_INIT 30 8014#define M_PCIE_FW_INIT 0x1 8015#define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 8016#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 8017#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 8018 8019#define S_PCIE_FW_HALT 29 8020#define M_PCIE_FW_HALT 0x1 8021#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 8022#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 8023#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 8024 8025#define S_PCIE_FW_EVAL 24 8026#define M_PCIE_FW_EVAL 0x7 8027#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 8028#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 8029 8030#define S_PCIE_FW_STAGE 21 8031#define M_PCIE_FW_STAGE 0x7 8032#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 8033#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 8034 8035#define S_PCIE_FW_ASYNCNOT_VLD 20 8036#define M_PCIE_FW_ASYNCNOT_VLD 0x1 8037#define V_PCIE_FW_ASYNCNOT_VLD(x) \ 8038 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 8039#define G_PCIE_FW_ASYNCNOT_VLD(x) \ 8040 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 8041#define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 8042 8043#define S_PCIE_FW_ASYNCNOTINT 19 8044#define M_PCIE_FW_ASYNCNOTINT 0x1 8045#define V_PCIE_FW_ASYNCNOTINT(x) \ 8046 ((x) << S_PCIE_FW_ASYNCNOTINT) 8047#define G_PCIE_FW_ASYNCNOTINT(x) \ 8048 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 8049#define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 8050 8051#define S_PCIE_FW_ASYNCNOT 16 8052#define M_PCIE_FW_ASYNCNOT 0x7 8053#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 8054#define G_PCIE_FW_ASYNCNOT(x) \ 8055 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 8056 8057#define S_PCIE_FW_MASTER_VLD 15 8058#define M_PCIE_FW_MASTER_VLD 0x1 8059#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 8060#define G_PCIE_FW_MASTER_VLD(x) \ 8061 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 8062#define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 8063 8064#define S_PCIE_FW_MASTER 12 8065#define M_PCIE_FW_MASTER 0x7 8066#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 8067#define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 8068 8069#define S_PCIE_FW_RESET_VLD 11 8070#define M_PCIE_FW_RESET_VLD 0x1 8071#define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 8072#define G_PCIE_FW_RESET_VLD(x) \ 8073 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 8074#define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 8075 8076#define S_PCIE_FW_RESET 8 8077#define M_PCIE_FW_RESET 0x7 8078#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 8079#define G_PCIE_FW_RESET(x) \ 8080 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 8081 8082#define S_PCIE_FW_REGISTERED 0 8083#define M_PCIE_FW_REGISTERED 0xff 8084#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 8085#define G_PCIE_FW_REGISTERED(x) \ 8086 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 8087 8088 8089/****************************************************************************** 8090 * P C I E F W P F 0 R E G I S T E R 8091 **********************************************/ 8092 8093/* 8094 * this register is available as 32-bit of persistent storage (accross 8095 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 8096 * will not write it) 8097 */ 8098 8099 8100/****************************************************************************** 8101 * P C I E F W P F 7 R E G I S T E R 8102 **********************************************/ 8103 8104/* 8105 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 8106 * access the "devlog" which needing to contact firmware. The encoding is 8107 * mostly the same as that returned by the DEVLOG command except for the size 8108 * which is encoded as the number of entries in multiples-1 of 128 here rather 8109 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 8110 * and 15 means 2048. This of course in turn constrains the allowed values 8111 * for the devlog size ... 8112 */ 8113#define PCIE_FW_PF_DEVLOG 7 8114 8115#define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 8116#define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 8117#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8118 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 8119#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 8120 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 8121 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 8122 8123#define S_PCIE_FW_PF_DEVLOG_ADDR16 4 8124#define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 8125#define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 8126#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 8127 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 8128 8129#define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 8130#define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 8131#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 8132#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 8133 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 8134 8135 8136/****************************************************************************** 8137 * B I N A R Y H E A D E R F O R M A T 8138 **********************************************/ 8139 8140/* 8141 * firmware binary header format 8142 */ 8143struct fw_hdr { 8144 __u8 ver; 8145 __u8 chip; /* terminator chip family */ 8146 __be16 len512; /* bin length in units of 512-bytes */ 8147 __be32 fw_ver; /* firmware version */ 8148 __be32 tp_microcode_ver; /* tcp processor microcode version */ 8149 __u8 intfver_nic; 8150 __u8 intfver_vnic; 8151 __u8 intfver_ofld; 8152 __u8 intfver_ri; 8153 __u8 intfver_iscsipdu; 8154 __u8 intfver_iscsi; 8155 __u8 intfver_fcoepdu; 8156 __u8 intfver_fcoe; 8157 __u32 reserved2; 8158 __u32 reserved3; 8159 __be32 magic; /* runtime or bootstrap fw */ 8160 __be32 flags; 8161 __be32 reserved6[23]; 8162}; 8163 8164enum fw_hdr_chip { 8165 FW_HDR_CHIP_T4, 8166 FW_HDR_CHIP_T5, 8167 FW_HDR_CHIP_T6 8168}; 8169 8170#define S_FW_HDR_FW_VER_MAJOR 24 8171#define M_FW_HDR_FW_VER_MAJOR 0xff 8172#define V_FW_HDR_FW_VER_MAJOR(x) \ 8173 ((x) << S_FW_HDR_FW_VER_MAJOR) 8174#define G_FW_HDR_FW_VER_MAJOR(x) \ 8175 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 8176 8177#define S_FW_HDR_FW_VER_MINOR 16 8178#define M_FW_HDR_FW_VER_MINOR 0xff 8179#define V_FW_HDR_FW_VER_MINOR(x) \ 8180 ((x) << S_FW_HDR_FW_VER_MINOR) 8181#define G_FW_HDR_FW_VER_MINOR(x) \ 8182 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 8183 8184#define S_FW_HDR_FW_VER_MICRO 8 8185#define M_FW_HDR_FW_VER_MICRO 0xff 8186#define V_FW_HDR_FW_VER_MICRO(x) \ 8187 ((x) << S_FW_HDR_FW_VER_MICRO) 8188#define G_FW_HDR_FW_VER_MICRO(x) \ 8189 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 8190 8191#define S_FW_HDR_FW_VER_BUILD 0 8192#define M_FW_HDR_FW_VER_BUILD 0xff 8193#define V_FW_HDR_FW_VER_BUILD(x) \ 8194 ((x) << S_FW_HDR_FW_VER_BUILD) 8195#define G_FW_HDR_FW_VER_BUILD(x) \ 8196 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 8197 8198enum { 8199 T4FW_VERSION_MAJOR = 0x01, 8200 T4FW_VERSION_MINOR = 0x0e, 8201 T4FW_VERSION_MICRO = 0x04, 8202 T4FW_VERSION_BUILD = 0x00, 8203 8204 T5FW_VERSION_MAJOR = 0x01, 8205 T5FW_VERSION_MINOR = 0x0e, 8206 T5FW_VERSION_MICRO = 0x04, 8207 T5FW_VERSION_BUILD = 0x00, 8208}; 8209 8210enum { 8211 /* T4 8212 */ 8213 T4FW_HDR_INTFVER_NIC = 0x00, 8214 T4FW_HDR_INTFVER_VNIC = 0x00, 8215 T4FW_HDR_INTFVER_OFLD = 0x00, 8216 T4FW_HDR_INTFVER_RI = 0x00, 8217 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 8218 T4FW_HDR_INTFVER_ISCSI = 0x00, 8219 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 8220 T4FW_HDR_INTFVER_FCOE = 0x00, 8221 8222 /* T5 8223 */ 8224 T5FW_HDR_INTFVER_NIC = 0x00, 8225 T5FW_HDR_INTFVER_VNIC = 0x00, 8226 T5FW_HDR_INTFVER_OFLD = 0x00, 8227 T5FW_HDR_INTFVER_RI = 0x00, 8228 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 8229 T5FW_HDR_INTFVER_ISCSI = 0x00, 8230 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 8231 T5FW_HDR_INTFVER_FCOE = 0x00, 8232 8233 /* T6 8234 */ 8235 T6FW_HDR_INTFVER_NIC = 0x00, 8236 T6FW_HDR_INTFVER_VNIC = 0x00, 8237 T6FW_HDR_INTFVER_OFLD = 0x00, 8238 T6FW_HDR_INTFVER_RI = 0x00, 8239 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 8240 T6FW_HDR_INTFVER_ISCSI = 0x00, 8241 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 8242 T6FW_HDR_INTFVER_FCOE = 0x00, 8243}; 8244 8245enum { 8246 FW_HDR_MAGIC_RUNTIME = 0x00000000, 8247 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 8248}; 8249 8250enum fw_hdr_flags { 8251 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 8252}; 8253 8254#endif /* _T4FW_INTERFACE_H_ */ 8255