t4fw_cfg_uwire.txt revision 286895
1# Chelsio T4 Factory Default configuration file. 2# 3# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8 9# This file provides the default, power-on configuration for 4-port T4-based 10# adapters shipped from the factory. These defaults are designed to address 11# the needs of the vast majority of T4 customers. The basic idea is to have 12# a default configuration which allows a customer to plug a T4 adapter in and 13# have it work regardless of OS, driver or application except in the most 14# unusual and/or demanding customer applications. 15# 16# Many of the T4 resources which are described by this configuration are 17# finite. This requires balancing the configuration/operation needs of 18# device drivers across OSes and a large number of customer application. 19# 20# Some of the more important resources to allocate and their constaints are: 21# 1. Virtual Interfaces: 128. 22# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23# must use a power of 2 Ingress Queues. 24# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25# power of 2 Egress Queues. 26# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27# Virtual Functions based off of a Physical Function all get the 28# same umber of MSI-X Vectors as the base Physical Function. 29# Additionally, regardless of whether Virtual Functions are enabled or 30# not, their MSI-X "needs" are counted by the PCI-E implementation. 31# And finally, all Physical Funcations capable of supporting Virtual 32# Functions (PF0-3) must have the same number of configured TotalVFs in 33# their SR-IOV Capabilities. 34# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35# address matching on Ingress Packets. 36# 37# Some of the important OS/Driver resource needs are: 38# 6. Some OS Drivers will manage all resources through a single Physical 39# Function (currently PF0 but it could be any Physical Function). Thus, 40# this "Unified PF" will need to have enough resources allocated to it 41# to allow for this. And because of the MSI-X resource allocation 42# constraints mentioned above, this probably means we'll either have to 43# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44# or we'll need to move the Unified PF into the PF4-7 range since those 45# Physical Functions don't have any Virtual Functions associated with 46# them. 47# 7. Some OS Drivers will manage different ports and functions (NIC, 48# storage, etc.) on different Physical Functions. For example, NIC 49# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50# 51# Some of the customer application needs which need to be accommodated: 52# 8. Some customers will want to support large CPU count systems with 53# good scaling. Thus, we'll need to accommodate a number of 54# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55# to be involved per port and per application function. For example, 56# in the case where all ports and application functions will be 57# managed via a single Unified PF and we want to accommodate scaling up 58# to 8 CPUs, we would want: 59# 60# 4 ports * 61# 3 application functions (NIC, FCoE, iSCSI) per port * 62# 8 Ingress Queue/MSI-X Vectors per application function 63# 64# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65# (Plus a few for Firmware Event Queues, etc.) 66# 67# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68# Virtual Machines to directly access T4 functionality via SR-IOV 69# Virtual Functions and "PCI Device Passthrough" -- this is especially 70# true for the NIC application functionality. (Note that there is 71# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72# Functions so this is in fact solely limited to NIC.) 73# 74 75 76# Global configuration settings. 77# 78[global] 79 rss_glb_config_mode = basicvirtual 80 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81 82 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 83 # Page Size and a 64B L1 Cache Line Size. It programs the 84 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 85 # If a Master PF Driver finds itself on a machine with different 86 # parameters, then the Master PF Driver is responsible for initializing 87 # these parameters to appropriate values. 88 # 89 # Notes: 90 # 1. The Free List Buffer Sizes below are raw and the firmware will 91 # round them up to the Ingress Padding Boundary. 92 # 2. The SGE Timer Values below are expressed below in microseconds. 93 # The firmware will convert these values to Core Clock Ticks when 94 # it processes the configuration parameters. 95 # 96 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 97 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 98 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 99 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 100 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 101 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 102 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 103 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 104 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 105 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 106 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 107 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 108 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 109 reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL 110 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 111 112 # enable TP_OUT_CONFIG.IPIDSPLITMODE 113 reg[0x7d04] = 0x00010000/0x00010000 114 115 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 116 117 # TP_VLAN_PRI_MAP to select filter tuples 118 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 119 # protocol, tos, vlan, vnic_id, port, fcoe 120 # valid filterModes are described the Terminator 4 Data Book 121 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 122 123 # filter tuples enforced in LE active region (equal to or subset of filterMode) 124 filterMask = protocol, fcoe 125 126 # Percentage of dynamic memory (in either the EDRAM or external MEM) 127 # to use for TP RX payload 128 tp_pmrx = 34 129 130 # TP RX payload page size 131 tp_pmrx_pagesize = 64K 132 133 # TP number of RX channels 134 tp_nrxch = 0 # 0 (auto) = 1 135 136 # Percentage of dynamic memory (in either the EDRAM or external MEM) 137 # to use for TP TX payload 138 tp_pmtx = 32 139 140 # TP TX payload page size 141 tp_pmtx_pagesize = 64K 142 143 # TP number of TX channels 144 tp_ntxch = 0 # 0 (auto) = equal number of ports 145 146 # TP OFLD MTUs 147 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 148 149 # ULPRX iSCSI Page Sizes 150 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 151 152# Some "definitions" to make the rest of this a bit more readable. We support 153# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 154# per function per port ... 155# 156# NMSIX = 1088 # available MSI-X Vectors 157# NVI = 128 # available Virtual Interfaces 158# NMPSTCAM = 336 # MPS TCAM entries 159# 160# NPORTS = 4 # ports 161# NCPUS = 8 # CPUs we want to support scalably 162# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 163 164# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 165# PF" which many OS Drivers will use to manage most or all functions. 166# 167# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 168# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 169# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 170# will be specified as the "Ingress Queue Asynchronous Destination Index." 171# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 172# than or equal to the number of Ingress Queues ... 173# 174# NVI_NIC = 4 # NIC access to NPORTS 175# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 176# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 177# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 178# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 179# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 180# 181# NVI_OFLD = 0 # Offload uses NIC function to access ports 182# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 183# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 184# NEQ_OFLD = 16 # Offload Egress Queues (FL) 185# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 186# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 187# 188# NVI_RDMA = 0 # RDMA uses NIC function to access ports 189# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 190# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 191# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 192# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 193# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 194# 195# NEQ_WD = 128 # Wire Direct TX Queues and FLs 196# NETHCTRL_WD = 64 # Wire Direct TX Queues 197# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 198# 199# NVI_ISCSI = 4 # ISCSI access to NPORTS 200# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 201# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 202# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 203# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 204# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 205# 206# NVI_FCOE = 4 # FCOE access to NPORTS 207# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 208# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 209# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 210# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 211# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 212 213# Two extra Ingress Queues per function for Firmware Events and Forwarded 214# Interrupts, and two extra interrupts per function for Firmware Events (or a 215# Forwarded Interrupt Queue) and General Interrupts per function. 216# 217# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 218# # Forwarded Interrupts 219# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 220# # General Interrupts 221 222# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 223# their interrupts forwarded to another set of Forwarded Interrupt Queues. 224# 225# NVI_HYPERV = 16 # VMs we want to support 226# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 227# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 228# NEQ_HYPERV = 32 # VIQs Free Lists 229# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 230# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 231 232# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 233# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 234# 235# NVI_UNIFIED = 28 236# NFLIQ_UNIFIED = 106 237# NETHCTRL_UNIFIED = 32 238# NEQ_UNIFIED = 124 239# NMPSTCAM_UNIFIED = 40 240# 241# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 242# that up to 128 to make sure the Unified PF doesn't run out of resources. 243# 244# NMSIX_UNIFIED = 128 245# 246# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 247# which is 34 but they're probably safe with 32. 248# 249# NMSIX_STORAGE = 32 250 251# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 252# associated with it. Thus, the MSI-X Vector allocations we give to the 253# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 254# provision many more Virtual Functions than we can if the UnifiedPF were 255# one of PF0-3. 256# 257 258# All of the below PCI-E parameters are actually stored in various *_init.txt 259# files. We include them below essentially as comments. 260# 261# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 262# ports 0-3. 263# 264# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 265# 266# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 267# storage applications across all four possible ports. 268# 269# Additionally, since the UnifiedPF isn't one of the per-port Physical 270# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 271# different PCI Device IDs which will allow Unified and Per-Port Drivers 272# to directly select the type of Physical Function to which they wish to be 273# attached. 274# 275# Note that the actual values used for the PCI-E Intelectual Property will be 276# 1 less than those below since that's the way it "counts" things. For 277# readability, we use the number we actually mean ... 278# 279# PF0_INT = 8 # NCPUS 280# PF1_INT = 8 # NCPUS 281# PF2_INT = 8 # NCPUS 282# PF3_INT = 8 # NCPUS 283# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 284# 285# PF4_INT = 128 # NMSIX_UNIFIED 286# PF5_INT = 32 # NMSIX_STORAGE 287# PF6_INT = 32 # NMSIX_STORAGE 288# PF7_INT = 0 # Nothing Assigned 289# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 290# 291# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 292# 293# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 294# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 295# 296# NVF = 16 297 298# For those OSes which manage different ports on different PFs, we need 299# only enough resources to support a single port's NIC application functions 300# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 301# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 302# managed on the "storage PFs" (see below). 303# 304[function "0"] 305 nvf = 16 # NVF on this function 306 wx_caps = all # write/execute permissions for all commands 307 r_caps = all # read permissions for all commands 308 nvi = 1 # 1 port 309 niqflint = 8 # NCPUS "Queue Sets" 310 nethctrl = 8 # NCPUS "Queue Sets" 311 neq = 16 # niqflint + nethctrl Egress Queues 312 nexactf = 8 # number of exact MPSTCAM MAC filters 313 cmask = all # access to all channels 314 pmask = 0x1 # access to only one port 315 316[function "1"] 317 nvf = 16 # NVF on this function 318 wx_caps = all # write/execute permissions for all commands 319 r_caps = all # read permissions for all commands 320 nvi = 1 # 1 port 321 niqflint = 8 # NCPUS "Queue Sets" 322 nethctrl = 8 # NCPUS "Queue Sets" 323 neq = 16 # niqflint + nethctrl Egress Queues 324 nexactf = 8 # number of exact MPSTCAM MAC filters 325 cmask = all # access to all channels 326 pmask = 0x2 # access to only one port 327 328[function "2"] 329 nvf = 16 # NVF on this function 330 wx_caps = all # write/execute permissions for all commands 331 r_caps = all # read permissions for all commands 332 nvi = 1 # 1 port 333 niqflint = 8 # NCPUS "Queue Sets" 334 nethctrl = 8 # NCPUS "Queue Sets" 335 neq = 16 # niqflint + nethctrl Egress Queues 336 nexactf = 8 # number of exact MPSTCAM MAC filters 337 cmask = all # access to all channels 338 pmask = 0x4 # access to only one port 339 340[function "3"] 341 nvf = 16 # NVF on this function 342 wx_caps = all # write/execute permissions for all commands 343 r_caps = all # read permissions for all commands 344 nvi = 1 # 1 port 345 niqflint = 8 # NCPUS "Queue Sets" 346 nethctrl = 8 # NCPUS "Queue Sets" 347 neq = 16 # niqflint + nethctrl Egress Queues 348 nexactf = 8 # number of exact MPSTCAM MAC filters 349 cmask = all # access to all channels 350 pmask = 0x8 # access to only one port 351 352# Some OS Drivers manage all application functions for all ports via PF4. 353# Thus we need to provide a large number of resources here. For Egress 354# Queues we need to account for both TX Queues as well as Free List Queues 355# (because the host is responsible for producing Free List Buffers for the 356# hardware to consume). 357# 358[function "4"] 359 wx_caps = all # write/execute permissions for all commands 360 r_caps = all # read permissions for all commands 361 nvi = 28 # NVI_UNIFIED 362 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 363 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 364 neq = 256 # NEQ_UNIFIED + NEQ_WD 365 nexactf = 40 # NMPSTCAM_UNIFIED 366 cmask = all # access to all channels 367 pmask = all # access to all four ports ... 368 nethofld = 1024 # number of user mode ethernet flow contexts 369 nroute = 32 # number of routing region entries 370 nclip = 32 # number of clip region entries 371 nfilter = 496 # number of filter region entries 372 nserver = 496 # number of server region entries 373 nhash = 12288 # number of hash region entries 374 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 375 tp_l2t = 3072 376 tp_ddp = 3 377 tp_ddp_iscsi = 2 378 tp_stag = 3 379 tp_pbl = 10 380 tp_rq = 13 381 382# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 383# need to have Virtual Interfaces on each of the four ports with up to NCPUS 384# "Queue Sets" each. 385# 386[function "5"] 387 wx_caps = all # write/execute permissions for all commands 388 r_caps = all # read permissions for all commands 389 nvi = 4 # NPORTS 390 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 391 nethctrl = 32 # NPORTS*NCPUS 392 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 393 nexactf = 4 # NPORTS 394 cmask = all # access to all channels 395 pmask = all # access to all four ports ... 396 nserver = 16 397 nhash = 2048 398 tp_l2t = 1020 399 protocol = iscsi_initiator_fofld 400 tp_ddp_iscsi = 2 401 iscsi_ntask = 2048 402 iscsi_nsess = 2048 403 iscsi_nconn_per_session = 1 404 iscsi_ninitiator_instance = 64 405 406[function "6"] 407 wx_caps = all # write/execute permissions for all commands 408 r_caps = all # read permissions for all commands 409 nvi = 4 # NPORTS 410 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 411 nethctrl = 32 # NPORTS*NCPUS 412 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 413 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 414 # which is OK since < MIN(SUM PF0..3, PF4) 415 # and we never load PF0..3 and PF4 concurrently 416 cmask = all # access to all channels 417 pmask = all # access to all four ports ... 418 nhash = 2048 419 tp_l2t = 4 420 protocol = fcoe_initiator 421 tp_ddp = 1 422 fcoe_nfcf = 16 423 fcoe_nvnp = 32 424 fcoe_nssn = 1024 425 426# The following function, 1023, is not an actual PCIE function but is used to 427# configure and reserve firmware internal resources that come from the global 428# resource pool. 429# 430[function "1023"] 431 wx_caps = all # write/execute permissions for all commands 432 r_caps = all # read permissions for all commands 433 nvi = 4 # NVI_UNIFIED 434 cmask = all # access to all channels 435 pmask = all # access to all four ports ... 436 nexactf = 8 # NPORTS + DCBX + 437 nfilter = 16 # number of filter region entries 438 439# For Virtual functions, we only allow NIC functionality and we only allow 440# access to one port (1 << PF). Note that because of limitations in the 441# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 442# and GTS registers, the number of Ingress and Egress Queues must be a power 443# of 2. 444# 445[function "0/*"] # NVF 446 wx_caps = 0x82 # DMAQ | VF 447 r_caps = 0x86 # DMAQ | VF | PORT 448 nvi = 1 # 1 port 449 niqflint = 4 # 2 "Queue Sets" + NXIQ 450 nethctrl = 2 # 2 "Queue Sets" 451 neq = 4 # 2 "Queue Sets" * 2 452 nexactf = 4 453 cmask = all # access to all channels 454 pmask = 0x1 # access to only one port ... 455 456[function "1/*"] # NVF 457 wx_caps = 0x82 # DMAQ | VF 458 r_caps = 0x86 # DMAQ | VF | PORT 459 nvi = 1 # 1 port 460 niqflint = 4 # 2 "Queue Sets" + NXIQ 461 nethctrl = 2 # 2 "Queue Sets" 462 neq = 4 # 2 "Queue Sets" * 2 463 nexactf = 4 464 cmask = all # access to all channels 465 pmask = 0x2 # access to only one port ... 466 467[function "2/*"] # NVF 468 wx_caps = 0x82 # DMAQ | VF 469 r_caps = 0x86 # DMAQ | VF | PORT 470 nvi = 1 # 1 port 471 niqflint = 4 # 2 "Queue Sets" + NXIQ 472 nethctrl = 2 # 2 "Queue Sets" 473 neq = 4 # 2 "Queue Sets" * 2 474 nexactf = 4 475 cmask = all # access to all channels 476 pmask = 0x4 # access to only one port ... 477 478[function "3/*"] # NVF 479 wx_caps = 0x82 # DMAQ | VF 480 r_caps = 0x86 # DMAQ | VF | PORT 481 nvi = 1 # 1 port 482 niqflint = 4 # 2 "Queue Sets" + NXIQ 483 nethctrl = 2 # 2 "Queue Sets" 484 neq = 4 # 2 "Queue Sets" * 2 485 nexactf = 4 486 cmask = all # access to all channels 487 pmask = 0x8 # access to only one port ... 488 489# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 490# for packets from the wire as well as the loopback path of the L2 switch. The 491# folling params control how the buffer memory is distributed and the L2 flow 492# control settings: 493# 494# bg_mem: %-age of mem to use for port/buffer group 495# lpbk_mem: %-age of port/bg mem to use for loopback 496# hwm: high watermark; bytes available when starting to send pause 497# frames (in units of 0.1 MTU) 498# lwm: low watermark; bytes remaining when sending 'unpause' frame 499# (in inuits of 0.1 MTU) 500# dwm: minimum delta between high and low watermark (in units of 100 501# Bytes) 502# 503# 504 505[port "0"] 506 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 507 bg_mem = 25 508 lpbk_mem = 25 509 hwm = 30 510 lwm = 15 511 dwm = 30 512 dcb_app_tlv[0] = 0x8906, ethertype, 3 513 dcb_app_tlv[1] = 0x8914, ethertype, 3 514 dcb_app_tlv[2] = 3260, socketnum, 5 515 516[port "1"] 517 dcb = ppp, dcbx 518 bg_mem = 25 519 lpbk_mem = 25 520 hwm = 30 521 lwm = 15 522 dwm = 30 523 dcb_app_tlv[0] = 0x8906, ethertype, 3 524 dcb_app_tlv[1] = 0x8914, ethertype, 3 525 dcb_app_tlv[2] = 3260, socketnum, 5 526 527[port "2"] 528 dcb = ppp, dcbx 529 bg_mem = 25 530 lpbk_mem = 25 531 hwm = 30 532 lwm = 15 533 dwm = 30 534 dcb_app_tlv[0] = 0x8906, ethertype, 3 535 dcb_app_tlv[1] = 0x8914, ethertype, 3 536 dcb_app_tlv[2] = 3260, socketnum, 5 537 538[port "3"] 539 dcb = ppp, dcbx 540 bg_mem = 25 541 lpbk_mem = 25 542 hwm = 30 543 lwm = 15 544 dwm = 30 545 dcb_app_tlv[0] = 0x8906, ethertype, 3 546 dcb_app_tlv[1] = 0x8914, ethertype, 3 547 dcb_app_tlv[2] = 3260, socketnum, 5 548 549[fini] 550 version = 0x1425001c 551 checksum = 0x63a652b3 552 553# Total resources used by above allocations: 554# Virtual Interfaces: 104 555# Ingress Queues/w Free Lists and Interrupts: 526 556# Egress Queues: 702 557# MPS TCAM Entries: 336 558# MSI-X Vectors: 736 559# Virtual Functions: 64 560# 561# $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt 286895 2015-08-18 18:54:45Z np $ 562# 563