common.h revision 308304
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/cxgbe/common/common.h 308304 2016-11-04 18:45:06Z jhb $ 27 * 28 */ 29 30#ifndef __CHELSIO_COMMON_H 31#define __CHELSIO_COMMON_H 32 33#include "t4_hw.h" 34 35#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 37 F_CPL_SWITCH | F_SGE | F_ULP_TX) 38 39enum { 40 MAX_NPORTS = 4, /* max # of ports */ 41 SERNUM_LEN = 24, /* Serial # length */ 42 EC_LEN = 16, /* E/C length */ 43 ID_LEN = 16, /* ID length */ 44 PN_LEN = 16, /* Part Number length */ 45 MACADDR_LEN = 12, /* MAC Address length */ 46}; 47 48enum { 49 T4_REGMAP_SIZE = (160 * 1024), 50 T5_REGMAP_SIZE = (332 * 1024), 51}; 52 53enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55enum { 56 MEMWIN0_APERTURE = 2048, 57 MEMWIN0_BASE = 0x1b800, 58 59 MEMWIN1_APERTURE = 32768, 60 MEMWIN1_BASE = 0x28000, 61 62 MEMWIN2_APERTURE_T4 = 65536, 63 MEMWIN2_BASE_T4 = 0x30000, 64 65 MEMWIN2_APERTURE_T5 = 128 * 1024, 66 MEMWIN2_BASE_T5 = 0x60000, 67}; 68 69enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 70 71enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 72 73enum { 74 PAUSE_RX = 1 << 0, 75 PAUSE_TX = 1 << 1, 76 PAUSE_AUTONEG = 1 << 2 77}; 78 79struct memwin { 80 uint32_t base; 81 uint32_t aperture; 82}; 83 84struct port_stats { 85 u64 tx_octets; /* total # of octets in good frames */ 86 u64 tx_frames; /* all good frames */ 87 u64 tx_bcast_frames; /* all broadcast frames */ 88 u64 tx_mcast_frames; /* all multicast frames */ 89 u64 tx_ucast_frames; /* all unicast frames */ 90 u64 tx_error_frames; /* all error frames */ 91 92 u64 tx_frames_64; /* # of Tx frames in a particular range */ 93 u64 tx_frames_65_127; 94 u64 tx_frames_128_255; 95 u64 tx_frames_256_511; 96 u64 tx_frames_512_1023; 97 u64 tx_frames_1024_1518; 98 u64 tx_frames_1519_max; 99 100 u64 tx_drop; /* # of dropped Tx frames */ 101 u64 tx_pause; /* # of transmitted pause frames */ 102 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 103 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 104 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 105 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 106 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 107 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 108 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 109 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 110 111 u64 rx_octets; /* total # of octets in good frames */ 112 u64 rx_frames; /* all good frames */ 113 u64 rx_bcast_frames; /* all broadcast frames */ 114 u64 rx_mcast_frames; /* all multicast frames */ 115 u64 rx_ucast_frames; /* all unicast frames */ 116 u64 rx_too_long; /* # of frames exceeding MTU */ 117 u64 rx_jabber; /* # of jabber frames */ 118 u64 rx_fcs_err; /* # of received frames with bad FCS */ 119 u64 rx_len_err; /* # of received frames with length error */ 120 u64 rx_symbol_err; /* symbol errors */ 121 u64 rx_runt; /* # of short frames */ 122 123 u64 rx_frames_64; /* # of Rx frames in a particular range */ 124 u64 rx_frames_65_127; 125 u64 rx_frames_128_255; 126 u64 rx_frames_256_511; 127 u64 rx_frames_512_1023; 128 u64 rx_frames_1024_1518; 129 u64 rx_frames_1519_max; 130 131 u64 rx_pause; /* # of received pause frames */ 132 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 133 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 134 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 135 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 136 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 137 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 138 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 139 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 140 141 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 142 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 143 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 144 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 145 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 146 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 147 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 148 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 149}; 150 151struct lb_port_stats { 152 u64 octets; 153 u64 frames; 154 u64 bcast_frames; 155 u64 mcast_frames; 156 u64 ucast_frames; 157 u64 error_frames; 158 159 u64 frames_64; 160 u64 frames_65_127; 161 u64 frames_128_255; 162 u64 frames_256_511; 163 u64 frames_512_1023; 164 u64 frames_1024_1518; 165 u64 frames_1519_max; 166 167 u64 drop; 168 169 u64 ovflow0; 170 u64 ovflow1; 171 u64 ovflow2; 172 u64 ovflow3; 173 u64 trunc0; 174 u64 trunc1; 175 u64 trunc2; 176 u64 trunc3; 177}; 178 179struct tp_tcp_stats { 180 u32 tcp_out_rsts; 181 u64 tcp_in_segs; 182 u64 tcp_out_segs; 183 u64 tcp_retrans_segs; 184}; 185 186struct tp_usm_stats { 187 u32 frames; 188 u32 drops; 189 u64 octets; 190}; 191 192struct tp_fcoe_stats { 193 u32 frames_ddp; 194 u32 frames_drop; 195 u64 octets_ddp; 196}; 197 198struct tp_err_stats { 199 u32 mac_in_errs[MAX_NCHAN]; 200 u32 hdr_in_errs[MAX_NCHAN]; 201 u32 tcp_in_errs[MAX_NCHAN]; 202 u32 tnl_cong_drops[MAX_NCHAN]; 203 u32 ofld_chan_drops[MAX_NCHAN]; 204 u32 tnl_tx_drops[MAX_NCHAN]; 205 u32 ofld_vlan_drops[MAX_NCHAN]; 206 u32 tcp6_in_errs[MAX_NCHAN]; 207 u32 ofld_no_neigh; 208 u32 ofld_cong_defer; 209}; 210 211struct tp_proxy_stats { 212 u32 proxy[MAX_NCHAN]; 213}; 214 215struct tp_cpl_stats { 216 u32 req[MAX_NCHAN]; 217 u32 rsp[MAX_NCHAN]; 218}; 219 220struct tp_rdma_stats { 221 u32 rqe_dfr_pkt; 222 u32 rqe_dfr_mod; 223}; 224 225struct sge_params { 226 int timer_val[SGE_NTIMERS]; 227 int counter_val[SGE_NCOUNTERS]; 228 int fl_starve_threshold; 229 int fl_starve_threshold2; 230 int page_shift; 231 int eq_s_qpp; 232 int iq_s_qpp; 233 int spg_len; 234 int pad_boundary; 235 int pack_boundary; 236 int fl_pktshift; 237}; 238 239struct tp_params { 240 unsigned int tre; /* log2 of core clocks per TP tick */ 241 unsigned int dack_re; /* DACK timer resolution */ 242 unsigned int la_mask; /* what events are recorded by TP LA */ 243 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 244 245 uint32_t vlan_pri_map; 246 uint32_t ingress_config; 247 uint32_t rx_pkt_encap; 248 249 int8_t fcoe_shift; 250 int8_t port_shift; 251 int8_t vnic_shift; 252 int8_t vlan_shift; 253 int8_t tos_shift; 254 int8_t protocol_shift; 255 int8_t ethertype_shift; 256 int8_t macmatch_shift; 257 int8_t matchtype_shift; 258 int8_t frag_shift; 259}; 260 261struct vpd_params { 262 unsigned int cclk; 263 u8 ec[EC_LEN + 1]; 264 u8 sn[SERNUM_LEN + 1]; 265 u8 id[ID_LEN + 1]; 266 u8 pn[PN_LEN + 1]; 267 u8 na[MACADDR_LEN + 1]; 268}; 269 270struct pci_params { 271 unsigned int vpd_cap_addr; 272 unsigned int mps; 273 unsigned short speed; 274 unsigned short width; 275}; 276 277/* 278 * Firmware device log. 279 */ 280struct devlog_params { 281 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 282 u32 start; /* start of log in firmware memory */ 283 u32 size; /* size of log */ 284}; 285 286/* Stores chip specific parameters */ 287struct chip_params { 288 u8 nchan; 289 u8 pm_stats_cnt; 290 u8 cng_ch_bits_log; /* congestion channel map bits width */ 291 u8 nsched_cls; 292 u8 cim_num_obq; 293 u16 mps_rplc_size; 294 u16 vfcount; 295 u32 sge_fl_db; 296 u16 mps_tcam_size; 297}; 298 299struct adapter_params { 300 struct sge_params sge; 301 struct tp_params tp; 302 struct vpd_params vpd; 303 struct pci_params pci; 304 struct devlog_params devlog; 305 306 unsigned int sf_size; /* serial flash size in bytes */ 307 unsigned int sf_nsec; /* # of flash sectors */ 308 309 unsigned int fw_vers; 310 unsigned int tp_vers; 311 312 unsigned short mtus[NMTUS]; 313 unsigned short a_wnd[NCCTRL_WIN]; 314 unsigned short b_wnd[NCCTRL_WIN]; 315 316 u_int ftid_min; 317 u_int ftid_max; 318 u_int etid_min; 319 u_int netids; 320 321 unsigned int cim_la_size; 322 323 uint8_t nports; /* # of ethernet ports */ 324 uint8_t portvec; 325 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 326 unsigned int rev:4; /* chip revision */ 327 unsigned int fpga:1; /* this is an FPGA */ 328 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 329 resources for TOE operation. */ 330 unsigned int bypass:1; /* this is a bypass card */ 331 unsigned int ethoffload:1; 332 333 unsigned int ofldq_wr_cred; 334 unsigned int eo_wr_cred; 335}; 336 337#define CHELSIO_T4 0x4 338#define CHELSIO_T5 0x5 339#define CHELSIO_T6 0x6 340 341/* 342 * State needed to monitor the forward progress of SGE Ingress DMA activities 343 * and possible hangs. 344 */ 345struct sge_idma_monitor_state { 346 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 347 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 348 unsigned int idma_state[2]; /* IDMA Hang detect state */ 349 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 350 unsigned int idma_warn[2]; /* time to warning in HZ */ 351}; 352 353struct trace_params { 354 u32 data[TRACE_LEN / 4]; 355 u32 mask[TRACE_LEN / 4]; 356 unsigned short snap_len; 357 unsigned short min_len; 358 unsigned char skip_ofst; 359 unsigned char skip_len; 360 unsigned char invert; 361 unsigned char port; 362}; 363 364struct link_config { 365 unsigned short supported; /* link capabilities */ 366 unsigned short advertising; /* advertised capabilities */ 367 unsigned short requested_speed; /* speed user has requested */ 368 unsigned short speed; /* actual link speed */ 369 unsigned char requested_fc; /* flow control user has requested */ 370 unsigned char fc; /* actual link flow control */ 371 unsigned char autoneg; /* autonegotiating? */ 372 unsigned char link_ok; /* link up? */ 373}; 374 375#include "adapter.h" 376 377#ifndef PCI_VENDOR_ID_CHELSIO 378# define PCI_VENDOR_ID_CHELSIO 0x1425 379#endif 380 381#define for_each_port(adapter, iter) \ 382 for (iter = 0; iter < (adapter)->params.nports; ++iter) 383 384static inline int is_ftid(const struct adapter *sc, u_int tid) 385{ 386 387 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 388} 389 390static inline int is_etid(const struct adapter *sc, u_int tid) 391{ 392 393 return (tid >= sc->params.etid_min); 394} 395 396static inline int is_offload(const struct adapter *adap) 397{ 398 return adap->params.offload; 399} 400 401static inline int is_ethoffload(const struct adapter *adap) 402{ 403 return adap->params.ethoffload; 404} 405 406static inline int chip_id(struct adapter *adap) 407{ 408 return adap->params.chipid; 409} 410 411static inline int chip_rev(struct adapter *adap) 412{ 413 return adap->params.rev; 414} 415 416static inline int is_t4(struct adapter *adap) 417{ 418 return adap->params.chipid == CHELSIO_T4; 419} 420 421static inline int is_t5(struct adapter *adap) 422{ 423 return adap->params.chipid == CHELSIO_T5; 424} 425 426static inline int is_t6(struct adapter *adap) 427{ 428 return adap->params.chipid == CHELSIO_T6; 429} 430 431static inline int is_fpga(struct adapter *adap) 432{ 433 return adap->params.fpga; 434} 435 436static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 437{ 438 return adap->params.vpd.cclk / 1000; 439} 440 441static inline unsigned int us_to_core_ticks(const struct adapter *adap, 442 unsigned int us) 443{ 444 return (us * adap->params.vpd.cclk) / 1000; 445} 446 447static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 448 unsigned int ticks) 449{ 450 /* add Core Clock / 2 to round ticks to nearest uS */ 451 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 452 adapter->params.vpd.cclk); 453} 454 455static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 456 unsigned int ticks) 457{ 458 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 459} 460 461void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 462 463int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 464 int size, void *rpl, bool sleep_ok, int timeout); 465int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 466 void *rpl, bool sleep_ok); 467 468static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 469 const void *cmd, int size, void *rpl, 470 int timeout) 471{ 472 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 473 timeout); 474} 475 476static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 477 int size, void *rpl) 478{ 479 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 480} 481 482static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 483 int size, void *rpl) 484{ 485 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 486} 487 488void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 489 unsigned int data_reg, u32 *vals, unsigned int nregs, 490 unsigned int start_idx); 491void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 492 unsigned int data_reg, const u32 *vals, 493 unsigned int nregs, unsigned int start_idx); 494 495u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 496 497struct fw_filter_wr; 498 499void t4_intr_enable(struct adapter *adapter); 500void t4_intr_disable(struct adapter *adapter); 501void t4_intr_clear(struct adapter *adapter); 502int t4_slow_intr_handler(struct adapter *adapter); 503 504int t4_hash_mac_addr(const u8 *addr); 505int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 506 struct link_config *lc); 507int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 508int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 509int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 510int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 511int t4_seeprom_wp(struct adapter *adapter, int enable); 512int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 513 u32 *data, int byte_oriented); 514int t4_write_flash(struct adapter *adapter, unsigned int addr, 515 unsigned int n, const u8 *data, int byte_oriented); 516int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 517int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 518int t5_fw_init_extern_mem(struct adapter *adap); 519int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 520int t4_load_boot(struct adapter *adap, u8 *boot_data, 521 unsigned int boot_addr, unsigned int size); 522int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 523int t4_flash_cfg_addr(struct adapter *adapter); 524int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 525int t4_get_fw_version(struct adapter *adapter, u32 *vers); 526int t4_get_tp_version(struct adapter *adapter, u32 *vers); 527int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 528int t4_init_hw(struct adapter *adapter, u32 fw_params); 529int t4_prep_adapter(struct adapter *adapter, u8 *buf); 530int t4_shutdown_adapter(struct adapter *adapter); 531int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 532int t4_init_sge_params(struct adapter *adapter); 533int t4_init_tp_params(struct adapter *adap); 534int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 535int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 536void t4_fatal_err(struct adapter *adapter); 537void t4_db_full(struct adapter *adapter); 538void t4_db_dropped(struct adapter *adapter); 539int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 540 int filter_index, int enable); 541void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 542 int filter_index, int *enabled); 543int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 544 int start, int n, const u16 *rspq, unsigned int nrspq); 545int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 546 unsigned int flags); 547int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 548 unsigned int flags, unsigned int defq); 549int t4_read_rss(struct adapter *adapter, u16 *entries); 550void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 551 unsigned int start_index, unsigned int rw); 552void t4_read_rss_key(struct adapter *adapter, u32 *key); 553void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 554void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); 555void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); 556void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 557 u32 *vfl, u32 *vfh); 558void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 559 u32 vfl, u32 vfh); 560u32 t4_read_rss_pf_map(struct adapter *adapter); 561void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 562u32 t4_read_rss_pf_mask(struct adapter *adapter); 563void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 564int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 565void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 566void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 567void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 568int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 569int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 570int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 571 unsigned int *valp); 572int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 573 const unsigned int *valp); 574int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 575 unsigned int *valp); 576int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 577void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 578 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 579void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 580int t4_get_flash_params(struct adapter *adapter); 581 582u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 583int t4_mc_read(struct adapter *adap, int idx, u32 addr, 584 __be32 *data, u64 *parity); 585int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 586int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 587 __be32 *data); 588void t4_idma_monitor_init(struct adapter *adapter, 589 struct sge_idma_monitor_state *idma); 590void t4_idma_monitor(struct adapter *adapter, 591 struct sge_idma_monitor_state *idma, 592 int hz, int ticks); 593 594unsigned int t4_get_regs_len(struct adapter *adapter); 595void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 596 597const char *t4_get_port_type_description(enum fw_port_type port_type); 598void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 599void t4_get_port_stats_offset(struct adapter *adap, int idx, 600 struct port_stats *stats, 601 struct port_stats *offset); 602void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 603void t4_clr_port_stats(struct adapter *adap, int idx); 604 605void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 606void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 607void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 608void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 609 unsigned int *ipg); 610void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 611 unsigned int mask, unsigned int val); 612void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 613void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 614void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 615void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 616void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 617void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 618void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 619 struct tp_tcp_stats *v6); 620void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 621 struct tp_fcoe_stats *st); 622void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 623 const unsigned short *alpha, const unsigned short *beta); 624 625void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 626 627int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 628int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 629int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 630 unsigned int start, unsigned int n); 631void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 632int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 633void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 634 635void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 636int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 637 u64 mask0, u64 mask1, unsigned int crc, bool enable); 638 639int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 640 enum dev_master master, enum dev_state *state); 641int t4_fw_bye(struct adapter *adap, unsigned int mbox); 642int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 643int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 644int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 645int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 646 const u8 *fw_data, unsigned int size, int force); 647int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 648int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 649 unsigned int vf, unsigned int nparams, const u32 *params, 650 u32 *val); 651int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 652 unsigned int vf, unsigned int nparams, const u32 *params, 653 u32 *val, int rw); 654int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 655 unsigned int pf, unsigned int vf, 656 unsigned int nparams, const u32 *params, 657 const u32 *val, int timeout); 658int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 659 unsigned int vf, unsigned int nparams, const u32 *params, 660 const u32 *val); 661int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 662 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 663 unsigned int rxqi, unsigned int rxq, unsigned int tc, 664 unsigned int vi, unsigned int cmask, unsigned int pmask, 665 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 666int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 667 unsigned int port, unsigned int pf, unsigned int vf, 668 unsigned int nmac, u8 *mac, u16 *rss_size, 669 unsigned int portfunc, unsigned int idstype); 670int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 671 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 672 u16 *rss_size); 673int t4_free_vi(struct adapter *adap, unsigned int mbox, 674 unsigned int pf, unsigned int vf, 675 unsigned int viid); 676int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 677 int mtu, int promisc, int all_multi, int bcast, int vlanex, 678 bool sleep_ok); 679int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 680 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 681 u64 *hash, bool sleep_ok); 682int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 683 int idx, const u8 *addr, bool persist, bool add_smt); 684int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 685 bool ucast, u64 vec, bool sleep_ok); 686int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 687 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 688int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 689 bool rx_en, bool tx_en); 690int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 691 unsigned int nblinks); 692int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 693 unsigned int mmd, unsigned int reg, unsigned int *valp); 694int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 695 unsigned int mmd, unsigned int reg, unsigned int val); 696int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 697 int port, unsigned int devid, 698 unsigned int offset, unsigned int len, 699 u8 *buf); 700int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 701 int port, unsigned int devid, 702 unsigned int offset, unsigned int len, 703 u8 *buf); 704int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 705 unsigned int vf, unsigned int iqtype, unsigned int iqid, 706 unsigned int fl0id, unsigned int fl1id); 707int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 708 unsigned int vf, unsigned int iqtype, unsigned int iqid, 709 unsigned int fl0id, unsigned int fl1id); 710int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 711 unsigned int vf, unsigned int eqid); 712int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 713 unsigned int vf, unsigned int eqid); 714int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 715 unsigned int vf, unsigned int eqid); 716int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 717 enum ctxt_type ctype, u32 *data); 718int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 719 u32 *data); 720int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 721const char *t4_link_down_rc_str(unsigned char link_down_rc); 722int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 723int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 724int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 725 int sleep_ok); 726int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 727 int rateunit, int ratemode, int channel, int cl, 728 int minrate, int maxrate, int weight, int pktsize, 729 int sleep_ok); 730int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 731 unsigned int pf, unsigned int vf, 732 unsigned int timeout, unsigned int action); 733int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 734int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 735void t4_sge_decode_idma_state(struct adapter *adapter, int state); 736#endif /* __CHELSIO_COMMON_H */ 737