adapter.h revision 353418
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 353418 2019-10-10 23:27:02Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "t4_ioctl.h" 52#include "common/t4_msg.h" 53#include "firmware/t4fw_interface.h" 54 55#define KTR_CXGBE KTR_SPARE3 56MALLOC_DECLARE(M_CXGBE); 57#define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60#if defined(__i386__) || defined(__amd64__) 61static __inline void 62prefetch(void *x) 63{ 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65} 66#else 67#define prefetch(x) 68#endif 69 70#ifndef SYSCTL_ADD_UQUAD 71#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72#define sysctl_handle_64 sysctl_handle_quad 73#define CTLTYPE_U64 CTLTYPE_QUAD 74#endif 75 76#if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78#define SBUF_DRAIN 1 79#endif 80 81struct adapter; 82typedef struct adapter adapter_t; 83 84enum { 85 /* 86 * All ingress queues use this entry size. Note that the firmware event 87 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 88 * be at least 64. 89 */ 90 IQ_ESIZE = 64, 91 92 /* Default queue sizes for all kinds of ingress queues */ 93 FW_IQ_QSIZE = 256, 94 RX_IQ_QSIZE = 1024, 95 96 /* All egress queues use this entry size */ 97 EQ_ESIZE = 64, 98 99 /* Default queue sizes for all kinds of egress queues */ 100 CTRL_EQ_QSIZE = 128, 101 TX_EQ_QSIZE = 1024, 102 103#if MJUMPAGESIZE != MCLBYTES 104 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 105#else 106 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 107#endif 108 CL_METADATA_SIZE = CACHE_LINE_SIZE, 109 110 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 111 TX_SGL_SEGS = 39, 112 TX_SGL_SEGS_TSO = 38, 113 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 114}; 115 116enum { 117 /* adapter intr_type */ 118 INTR_INTX = (1 << 0), 119 INTR_MSI = (1 << 1), 120 INTR_MSIX = (1 << 2) 121}; 122 123enum { 124 XGMAC_MTU = (1 << 0), 125 XGMAC_PROMISC = (1 << 1), 126 XGMAC_ALLMULTI = (1 << 2), 127 XGMAC_VLANEX = (1 << 3), 128 XGMAC_UCADDR = (1 << 4), 129 XGMAC_MCADDRS = (1 << 5), 130 131 XGMAC_ALL = 0xffff 132}; 133 134enum { 135 /* flags understood by begin_synchronized_op */ 136 HOLD_LOCK = (1 << 0), 137 SLEEP_OK = (1 << 1), 138 INTR_OK = (1 << 2), 139 140 /* flags understood by end_synchronized_op */ 141 LOCK_HELD = HOLD_LOCK, 142}; 143 144enum { 145 /* adapter flags */ 146 FULL_INIT_DONE = (1 << 0), 147 FW_OK = (1 << 1), 148 /* INTR_DIRECT = (1 << 2), No longer used. */ 149 MASTER_PF = (1 << 3), 150 ADAP_SYSCTL_CTX = (1 << 4), 151 /* TOM_INIT_DONE= (1 << 5), No longer used */ 152 BUF_PACKING_OK = (1 << 6), 153 IS_VF = (1 << 7), 154 155 CXGBE_BUSY = (1 << 9), 156 157 /* port flags */ 158 HAS_TRACEQ = (1 << 3), 159 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 160 161 /* VI flags */ 162 DOOMED = (1 << 0), 163 VI_INIT_DONE = (1 << 1), 164 VI_SYSCTL_CTX = (1 << 2), 165 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 166 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 167 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 168 169 /* adapter debug_flags */ 170 DF_DUMP_MBOX = (1 << 0), 171}; 172 173#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 174#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 175#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 176#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 177#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 178 179struct vi_info { 180 device_t dev; 181 struct port_info *pi; 182 183 struct ifnet *ifp; 184 185 unsigned long flags; 186 int if_flags; 187 188 uint16_t *rss, *nm_rss; 189 int smt_idx; /* for convenience */ 190 uint16_t viid; 191 int16_t xact_addr_filt;/* index of exact MAC address filter */ 192 uint16_t rss_size; /* size of VI's RSS table slice */ 193 uint16_t rss_base; /* start of VI's RSS table slice */ 194 195 eventhandler_tag vlan_c; 196 197 int nintr; 198 int first_intr; 199 200 /* These need to be int as they are used in sysctl */ 201 int ntxq; /* # of tx queues */ 202 int first_txq; /* index of first tx queue */ 203 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 204 int nrxq; /* # of rx queues */ 205 int first_rxq; /* index of first rx queue */ 206 int nofldtxq; /* # of offload tx queues */ 207 int first_ofld_txq; /* index of first offload tx queue */ 208 int nofldrxq; /* # of offload rx queues */ 209 int first_ofld_rxq; /* index of first offload rx queue */ 210 int nnmtxq; 211 int first_nm_txq; 212 int nnmrxq; 213 int first_nm_rxq; 214 int tmr_idx; 215 int pktc_idx; 216 int qsize_rxq; 217 int qsize_txq; 218 219 struct timeval last_refreshed; 220 struct fw_vi_stats_vf stats; 221 222 struct callout tick; 223 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 224 225 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 226}; 227 228struct tx_ch_rl_params { 229 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 230 uint32_t maxrate; 231}; 232 233enum { 234 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 235 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 236}; 237 238struct tx_cl_rl_params { 239 int refcount; 240 u_int flags; 241 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 242 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 243 enum fw_sched_params_mode mode; /* aggr or per-flow */ 244 uint32_t maxrate; 245 uint16_t pktsize; 246}; 247 248/* Tx scheduler parameters for a channel/port */ 249struct tx_sched_params { 250 /* Channel Rate Limiter */ 251 struct tx_ch_rl_params ch_rl; 252 253 /* Class WRR */ 254 /* XXX */ 255 256 /* Class Rate Limiter */ 257 struct tx_cl_rl_params cl_rl[]; 258}; 259 260struct port_info { 261 device_t dev; 262 struct adapter *adapter; 263 264 struct vi_info *vi; 265 int nvi; 266 int up_vis; 267 int uld_vis; 268 269 struct tx_sched_params *sched_params; 270 271 struct mtx pi_lock; 272 char lockname[16]; 273 unsigned long flags; 274 275 uint8_t lport; /* associated offload logical port */ 276 int8_t mdio_addr; 277 uint8_t port_type; 278 uint8_t mod_type; 279 uint8_t port_id; 280 uint8_t tx_chan; 281 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 282 283 struct link_config link_cfg; 284 struct link_config old_link_cfg; 285 struct ifmedia media; 286 287 struct timeval last_refreshed; 288 struct port_stats stats; 289 u_int tx_parse_error; 290 291 struct callout tick; 292}; 293 294#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 295 296/* Where the cluster came from, how it has been carved up. */ 297struct cluster_layout { 298 int8_t zidx; 299 int8_t hwidx; 300 uint16_t region1; /* mbufs laid out within this region */ 301 /* region2 is the DMA region */ 302 uint16_t region3; /* cluster_metadata within this region */ 303}; 304 305struct cluster_metadata { 306 u_int refcount; 307 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 308}; 309 310struct fl_sdesc { 311 caddr_t cl; 312 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 313 struct cluster_layout cll; 314}; 315 316struct tx_desc { 317 __be64 flit[8]; 318}; 319 320struct tx_sdesc { 321 struct mbuf *m; /* m_nextpkt linked chain of frames */ 322 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 323}; 324 325 326#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 327struct iq_desc { 328 struct rss_header rss; 329 uint8_t cpl[IQ_PAD]; 330 struct rsp_ctrl rsp; 331}; 332#undef IQ_PAD 333CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 334 335enum { 336 /* iq flags */ 337 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 338 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 339 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 340 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 341 342 /* iq state */ 343 IQS_DISABLED = 0, 344 IQS_BUSY = 1, 345 IQS_IDLE = 2, 346 347 /* netmap related flags */ 348 NM_OFF = 0, 349 NM_ON = 1, 350 NM_BUSY = 2, 351}; 352 353struct sge_iq; 354struct rss_header; 355typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 356 struct mbuf *); 357typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 358typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 359 360/* 361 * Ingress Queue: T4 is producer, driver is consumer. 362 */ 363struct sge_iq { 364 uint32_t flags; 365 volatile int state; 366 struct adapter *adapter; 367 cpl_handler_t set_tcb_rpl; 368 cpl_handler_t l2t_write_rpl; 369 struct iq_desc *desc; /* KVA of descriptor ring */ 370 int8_t intr_pktc_idx; /* packet count threshold index */ 371 uint8_t gen; /* generation bit */ 372 uint8_t intr_params; /* interrupt holdoff parameters */ 373 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 374 uint16_t qsize; /* size (# of entries) of the queue */ 375 uint16_t sidx; /* index of the entry with the status page */ 376 uint16_t cidx; /* consumer index */ 377 uint16_t cntxt_id; /* SGE context id for the iq */ 378 uint16_t abs_id; /* absolute SGE id for the iq */ 379 380 STAILQ_ENTRY(sge_iq) link; 381 382 bus_dma_tag_t desc_tag; 383 bus_dmamap_t desc_map; 384 bus_addr_t ba; /* bus address of descriptor ring */ 385}; 386 387enum { 388 EQ_CTRL = 1, 389 EQ_ETH = 2, 390 EQ_OFLD = 3, 391 392 /* eq flags */ 393 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 394 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 395 EQ_ENABLED = (1 << 3), /* open for business */ 396 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 397}; 398 399/* Listed in order of preference. Update t4_sysctls too if you change these */ 400enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 401 402/* 403 * Egress Queue: driver is producer, T4 is consumer. 404 * 405 * Note: A free list is an egress queue (driver produces the buffers and T4 406 * consumes them) but it's special enough to have its own struct (see sge_fl). 407 */ 408struct sge_eq { 409 unsigned int flags; /* MUST be first */ 410 unsigned int cntxt_id; /* SGE context id for the eq */ 411 unsigned int abs_id; /* absolute SGE id for the eq */ 412 struct mtx eq_lock; 413 414 struct tx_desc *desc; /* KVA of descriptor ring */ 415 uint16_t doorbells; 416 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 417 u_int udb_qid; /* relative qid within the doorbell page */ 418 uint16_t sidx; /* index of the entry with the status page */ 419 uint16_t cidx; /* consumer idx (desc idx) */ 420 uint16_t pidx; /* producer idx (desc idx) */ 421 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 422 uint16_t dbidx; /* pidx of the most recent doorbell */ 423 uint16_t iqid; /* iq that gets egr_update for the eq */ 424 uint8_t tx_chan; /* tx channel used by the eq */ 425 volatile u_int equiq; /* EQUIQ outstanding */ 426 427 bus_dma_tag_t desc_tag; 428 bus_dmamap_t desc_map; 429 bus_addr_t ba; /* bus address of descriptor ring */ 430 char lockname[16]; 431}; 432 433struct sw_zone_info { 434 uma_zone_t zone; /* zone that this cluster comes from */ 435 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 436 int type; /* EXT_xxx type of the cluster */ 437 int8_t head_hwidx; 438 int8_t tail_hwidx; 439}; 440 441struct hw_buf_info { 442 int8_t zidx; /* backpointer to zone; -ve means unused */ 443 int8_t next; /* next hwidx for this zone; -1 means no more */ 444 int size; 445}; 446 447enum { 448 NUM_MEMWIN = 3, 449 450 MEMWIN0_APERTURE = 2048, 451 MEMWIN0_BASE = 0x1b800, 452 453 MEMWIN1_APERTURE = 32768, 454 MEMWIN1_BASE = 0x28000, 455 456 MEMWIN2_APERTURE_T4 = 65536, 457 MEMWIN2_BASE_T4 = 0x30000, 458 459 MEMWIN2_APERTURE_T5 = 128 * 1024, 460 MEMWIN2_BASE_T5 = 0x60000, 461}; 462 463struct memwin { 464 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 465 uint32_t mw_base; /* constant after setup_memwin */ 466 uint32_t mw_aperture; /* ditto */ 467 uint32_t mw_curpos; /* protected by mw_lock */ 468}; 469 470enum { 471 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 472 FL_DOOMED = (1 << 1), /* about to be destroyed */ 473 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 474 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 475}; 476 477#define FL_RUNNING_LOW(fl) \ 478 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 479#define FL_NOT_RUNNING_LOW(fl) \ 480 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 481 482struct sge_fl { 483 struct mtx fl_lock; 484 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 485 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 486 struct cluster_layout cll_def; /* default refill zone, layout */ 487 uint16_t lowat; /* # of buffers <= this means fl needs help */ 488 int flags; 489 uint16_t buf_boundary; 490 491 /* The 16b idx all deal with hw descriptors */ 492 uint16_t dbidx; /* hw pidx after last doorbell */ 493 uint16_t sidx; /* index of status page */ 494 volatile uint16_t hw_cidx; 495 496 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 497 uint32_t cidx; /* consumer index */ 498 uint32_t pidx; /* producer index */ 499 500 uint32_t dbval; 501 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 502 volatile uint32_t *udb; 503 504 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 505 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 506 uint64_t cl_allocated; /* # of clusters allocated */ 507 uint64_t cl_recycled; /* # of clusters recycled */ 508 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 509 510 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 511 struct mbuf *m0; 512 struct mbuf **pnext; 513 u_int remaining; 514 515 uint16_t qsize; /* # of hw descriptors (status page included) */ 516 uint16_t cntxt_id; /* SGE context id for the freelist */ 517 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 518 bus_dma_tag_t desc_tag; 519 bus_dmamap_t desc_map; 520 char lockname[16]; 521 bus_addr_t ba; /* bus address of descriptor ring */ 522 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 523}; 524 525struct mp_ring; 526 527/* txq: SGE egress queue + what's needed for Ethernet NIC */ 528struct sge_txq { 529 struct sge_eq eq; /* MUST be first */ 530 531 struct ifnet *ifp; /* the interface this txq belongs to */ 532 struct mp_ring *r; /* tx software ring */ 533 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 534 struct sglist *gl; 535 __be32 cpl_ctrl0; /* for convenience */ 536 int tc_idx; /* traffic class */ 537 538 struct task tx_reclaim_task; 539 /* stats for common events first */ 540 541 uint64_t txcsum; /* # of times hardware assisted with checksum */ 542 uint64_t tso_wrs; /* # of TSO work requests */ 543 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 544 uint64_t imm_wrs; /* # of work requests with immediate data */ 545 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 546 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 547 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 548 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 549 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 550 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 551 552 /* stats for not-that-common events */ 553} __aligned(CACHE_LINE_SIZE); 554 555/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 556struct sge_rxq { 557 struct sge_iq iq; /* MUST be first */ 558 struct sge_fl fl; /* MUST follow iq */ 559 560 struct ifnet *ifp; /* the interface this rxq belongs to */ 561#if defined(INET) || defined(INET6) 562 struct lro_ctrl lro; /* LRO state */ 563#endif 564 565 /* stats for common events first */ 566 567 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 568 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 569 570 /* stats for not-that-common events */ 571 572} __aligned(CACHE_LINE_SIZE); 573 574static inline struct sge_rxq * 575iq_to_rxq(struct sge_iq *iq) 576{ 577 578 return (__containerof(iq, struct sge_rxq, iq)); 579} 580 581 582/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 583struct sge_ofld_rxq { 584 struct sge_iq iq; /* MUST be first */ 585 struct sge_fl fl; /* MUST follow iq */ 586} __aligned(CACHE_LINE_SIZE); 587 588static inline struct sge_ofld_rxq * 589iq_to_ofld_rxq(struct sge_iq *iq) 590{ 591 592 return (__containerof(iq, struct sge_ofld_rxq, iq)); 593} 594 595struct wrqe { 596 STAILQ_ENTRY(wrqe) link; 597 struct sge_wrq *wrq; 598 int wr_len; 599 char wr[] __aligned(16); 600}; 601 602struct wrq_cookie { 603 TAILQ_ENTRY(wrq_cookie) link; 604 int ndesc; 605 int pidx; 606}; 607 608/* 609 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 610 * and offload tx queues are of this type. 611 */ 612struct sge_wrq { 613 struct sge_eq eq; /* MUST be first */ 614 615 struct adapter *adapter; 616 struct task wrq_tx_task; 617 618 /* Tx desc reserved but WR not "committed" yet. */ 619 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 620 621 /* List of WRs ready to go out as soon as descriptors are available. */ 622 STAILQ_HEAD(, wrqe) wr_list; 623 u_int nwr_pending; 624 u_int ndesc_needed; 625 626 /* stats for common events first */ 627 628 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 629 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 630 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 631 632 /* stats for not-that-common events */ 633 634 /* 635 * Scratch space for work requests that wrap around after reaching the 636 * status page, and some infomation about the last WR that used it. 637 */ 638 uint16_t ss_pidx; 639 uint16_t ss_len; 640 uint8_t ss[SGE_MAX_WR_LEN]; 641 642} __aligned(CACHE_LINE_SIZE); 643 644 645struct sge_nm_rxq { 646 struct vi_info *vi; 647 648 struct iq_desc *iq_desc; 649 uint16_t iq_abs_id; 650 uint16_t iq_cntxt_id; 651 uint16_t iq_cidx; 652 uint16_t iq_sidx; 653 uint8_t iq_gen; 654 655 __be64 *fl_desc; 656 uint16_t fl_cntxt_id; 657 uint32_t fl_cidx; 658 uint32_t fl_pidx; 659 uint32_t fl_sidx; 660 uint32_t fl_db_val; 661 u_int fl_hwidx:4; 662 663 u_int nid; /* netmap ring # for this queue */ 664 665 /* infrequently used items after this */ 666 667 bus_dma_tag_t iq_desc_tag; 668 bus_dmamap_t iq_desc_map; 669 bus_addr_t iq_ba; 670 int intr_idx; 671 672 bus_dma_tag_t fl_desc_tag; 673 bus_dmamap_t fl_desc_map; 674 bus_addr_t fl_ba; 675} __aligned(CACHE_LINE_SIZE); 676 677struct sge_nm_txq { 678 struct tx_desc *desc; 679 uint16_t cidx; 680 uint16_t pidx; 681 uint16_t sidx; 682 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 683 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 684 uint16_t dbidx; /* pidx of the most recent doorbell */ 685 uint16_t doorbells; 686 volatile uint32_t *udb; 687 u_int udb_qid; 688 u_int cntxt_id; 689 __be32 cpl_ctrl0; /* for convenience */ 690 u_int nid; /* netmap ring # for this queue */ 691 692 /* infrequently used items after this */ 693 694 bus_dma_tag_t desc_tag; 695 bus_dmamap_t desc_map; 696 bus_addr_t ba; 697 int iqidx; 698} __aligned(CACHE_LINE_SIZE); 699 700struct sge { 701 int nrxq; /* total # of Ethernet rx queues */ 702 int ntxq; /* total # of Ethernet tx queues */ 703 int nofldrxq; /* total # of TOE rx queues */ 704 int nofldtxq; /* total # of TOE tx queues */ 705 int nnmrxq; /* total # of netmap rx queues */ 706 int nnmtxq; /* total # of netmap tx queues */ 707 int niq; /* total # of ingress queues */ 708 int neq; /* total # of egress queues */ 709 710 struct sge_iq fwq; /* Firmware event queue */ 711 struct sge_wrq mgmtq; /* Management queue (control queue) */ 712 struct sge_wrq *ctrlq; /* Control queues */ 713 struct sge_txq *txq; /* NIC tx queues */ 714 struct sge_rxq *rxq; /* NIC rx queues */ 715 struct sge_wrq *ofld_txq; /* TOE tx queues */ 716 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 717 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 718 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 719 720 uint16_t iq_start; /* first cntxt_id */ 721 uint16_t iq_base; /* first abs_id */ 722 int eq_start; /* first cntxt_id */ 723 int eq_base; /* first abs_id */ 724 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 725 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 726 727 int8_t safe_hwidx1; /* may not have room for metadata */ 728 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 729 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 730 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 731}; 732 733struct devnames { 734 const char *nexus_name; 735 const char *ifnet_name; 736 const char *vi_ifnet_name; 737 const char *pf03_drv_name; 738 const char *vf_nexus_name; 739 const char *vf_ifnet_name; 740}; 741 742struct adapter { 743 SLIST_ENTRY(adapter) link; 744 device_t dev; 745 struct cdev *cdev; 746 const struct devnames *names; 747 748 /* PCIe register resources */ 749 int regs_rid; 750 struct resource *regs_res; 751 int msix_rid; 752 struct resource *msix_res; 753 bus_space_handle_t bh; 754 bus_space_tag_t bt; 755 bus_size_t mmio_len; 756 int udbs_rid; 757 struct resource *udbs_res; 758 volatile uint8_t *udbs_base; 759 760 unsigned int pf; 761 unsigned int mbox; 762 unsigned int vpd_busy; 763 unsigned int vpd_flag; 764 765 /* Interrupt information */ 766 int intr_type; 767 int intr_count; 768 struct irq { 769 struct resource *res; 770 int rid; 771 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 772 void *tag; 773 struct sge_rxq *rxq; 774 struct sge_nm_rxq *nm_rxq; 775 } __aligned(CACHE_LINE_SIZE) *irq; 776 int sge_gts_reg; 777 int sge_kdoorbell_reg; 778 779 bus_dma_tag_t dmat; /* Parent DMA tag */ 780 781 struct sge sge; 782 int lro_timeout; 783 int sc_do_rxcopy; 784 785 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 786 struct port_info *port[MAX_NPORTS]; 787 uint8_t chan_map[MAX_NCHAN]; 788 789 void *tom_softc; /* (struct tom_data *) */ 790 struct tom_tunables tt; 791 void *iwarp_softc; /* (struct c4iw_dev *) */ 792 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 793 struct l2t_data *l2t; /* L2 table */ 794 struct tid_info tids; 795 796 uint16_t doorbells; 797 int offload_map; /* ports with IFCAP_TOE enabled */ 798 int active_ulds; /* ULDs activated on this adapter */ 799 int flags; 800 int debug_flags; 801 802 char ifp_lockname[16]; 803 struct mtx ifp_lock; 804 struct ifnet *ifp; /* tracer ifp */ 805 struct ifmedia media; 806 int traceq; /* iq used by all tracers, -1 if none */ 807 int tracer_valid; /* bitmap of valid tracers */ 808 int tracer_enabled; /* bitmap of enabled tracers */ 809 810 char fw_version[16]; 811 char tp_version[16]; 812 char er_version[16]; 813 char bs_version[16]; 814 char cfg_file[32]; 815 u_int cfcsum; 816 struct adapter_params params; 817 const struct chip_params *chip_params; 818 struct t4_virt_res vres; 819 820 uint16_t nbmcaps; 821 uint16_t linkcaps; 822 uint16_t switchcaps; 823 uint16_t niccaps; 824 uint16_t toecaps; 825 uint16_t rdmacaps; 826 uint16_t cryptocaps; 827 uint16_t iscsicaps; 828 uint16_t fcoecaps; 829 830 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 831 832 struct mtx sc_lock; 833 char lockname[16]; 834 835 /* Starving free lists */ 836 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 837 TAILQ_HEAD(, sge_fl) sfl; 838 struct callout sfl_callout; 839 840 struct mtx reg_lock; /* for indirect register access */ 841 842 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 843 844 struct mtx tc_lock; 845 struct task tc_task; 846 847 const char *last_op; 848 const void *last_op_thr; 849 int last_op_flags; 850}; 851 852#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 853#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 854#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 855#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 856 857#define ASSERT_SYNCHRONIZED_OP(sc) \ 858 KASSERT(IS_BUSY(sc) && \ 859 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 860 ("%s: operation not synchronized.", __func__)) 861 862#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 863#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 864#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 865#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 866 867#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 868#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 869#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 870#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 871#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 872 873#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 874#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 875#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 876#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 877 878#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 879#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 880#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 881#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 882#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 883 884#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 885#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 886#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 887#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 888#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 889 890#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 891 do { \ 892 if (sc->debug_flags & DF_DUMP_MBOX) { \ 893 log(LOG_NOTICE, \ 894 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 895 "%016llx %016llx %016llx %016llx\n", \ 896 device_get_nameunit(sc->dev), mbox, \ 897 (unsigned long long)t4_read_reg64(sc, data_reg), \ 898 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 899 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 900 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 901 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 902 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 903 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 904 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 905 } \ 906 } while (0) 907 908#define for_each_txq(vi, iter, q) \ 909 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 910 iter < vi->ntxq; ++iter, ++q) 911#define for_each_rxq(vi, iter, q) \ 912 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 913 iter < vi->nrxq; ++iter, ++q) 914#define for_each_ofld_txq(vi, iter, q) \ 915 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 916 iter < vi->nofldtxq; ++iter, ++q) 917#define for_each_ofld_rxq(vi, iter, q) \ 918 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 919 iter < vi->nofldrxq; ++iter, ++q) 920#define for_each_nm_txq(vi, iter, q) \ 921 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 922 iter < vi->nnmtxq; ++iter, ++q) 923#define for_each_nm_rxq(vi, iter, q) \ 924 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 925 iter < vi->nnmrxq; ++iter, ++q) 926#define for_each_vi(_pi, _iter, _vi) \ 927 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 928 ++(_iter), ++(_vi)) 929 930#define IDXINCR(idx, incr, wrap) do { \ 931 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 932} while (0) 933#define IDXDIFF(head, tail, wrap) \ 934 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 935 936/* One for errors, one for firmware events */ 937#define T4_EXTRA_INTR 2 938 939/* One for firmware events */ 940#define T4VF_EXTRA_INTR 1 941 942static inline uint32_t 943t4_read_reg(struct adapter *sc, uint32_t reg) 944{ 945 946 return bus_space_read_4(sc->bt, sc->bh, reg); 947} 948 949static inline void 950t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 951{ 952 953 bus_space_write_4(sc->bt, sc->bh, reg, val); 954} 955 956static inline uint64_t 957t4_read_reg64(struct adapter *sc, uint32_t reg) 958{ 959 960#if defined(__LP64__) && !defined(__ia64__) 961 return bus_space_read_8(sc->bt, sc->bh, reg); 962#else 963 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 964 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 965 966#endif 967} 968 969static inline void 970t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 971{ 972 973#if defined(__LP64__) && !defined(__ia64__) 974 bus_space_write_8(sc->bt, sc->bh, reg, val); 975#else 976 bus_space_write_4(sc->bt, sc->bh, reg, val); 977 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 978#endif 979} 980 981static inline void 982t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 983{ 984 985 *val = pci_read_config(sc->dev, reg, 1); 986} 987 988static inline void 989t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 990{ 991 992 pci_write_config(sc->dev, reg, val, 1); 993} 994 995static inline void 996t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 997{ 998 999 *val = pci_read_config(sc->dev, reg, 2); 1000} 1001 1002static inline void 1003t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1004{ 1005 1006 pci_write_config(sc->dev, reg, val, 2); 1007} 1008 1009static inline void 1010t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1011{ 1012 1013 *val = pci_read_config(sc->dev, reg, 4); 1014} 1015 1016static inline void 1017t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1018{ 1019 1020 pci_write_config(sc->dev, reg, val, 4); 1021} 1022 1023static inline struct port_info * 1024adap2pinfo(struct adapter *sc, int idx) 1025{ 1026 1027 return (sc->port[idx]); 1028} 1029 1030static inline void 1031t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1032{ 1033 1034 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1035} 1036 1037static inline bool 1038is_10G_port(const struct port_info *pi) 1039{ 1040 1041 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1042} 1043 1044static inline bool 1045is_25G_port(const struct port_info *pi) 1046{ 1047 1048 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1049} 1050 1051static inline bool 1052is_40G_port(const struct port_info *pi) 1053{ 1054 1055 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1056} 1057 1058static inline bool 1059is_100G_port(const struct port_info *pi) 1060{ 1061 1062 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1063} 1064 1065static inline int 1066port_top_speed(const struct port_info *pi) 1067{ 1068 1069 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1070 return (100); 1071 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1072 return (40); 1073 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1074 return (25); 1075 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1076 return (10); 1077 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1078 return (1); 1079 1080 return (0); 1081} 1082 1083static inline int 1084tx_resume_threshold(struct sge_eq *eq) 1085{ 1086 1087 /* not quite the same as qsize / 4, but this will do. */ 1088 return (eq->sidx / 4); 1089} 1090 1091static inline int 1092t4_use_ldst(struct adapter *sc) 1093{ 1094 1095#ifdef notyet 1096 return (sc->flags & FW_OK || !sc->use_bd); 1097#else 1098 return (0); 1099#endif 1100} 1101 1102/* t4_main.c */ 1103extern int t4_ntxq10g; 1104extern int t4_nrxq10g; 1105extern int t4_ntxq1g; 1106extern int t4_nrxq1g; 1107extern int t4_intr_types; 1108extern int t4_tmr_idx_10g; 1109extern int t4_pktc_idx_10g; 1110extern int t4_tmr_idx_1g; 1111extern int t4_pktc_idx_1g; 1112extern unsigned int t4_qsize_rxq; 1113extern unsigned int t4_qsize_txq; 1114extern device_method_t cxgbe_methods[]; 1115 1116int t4_os_find_pci_capability(struct adapter *, int); 1117int t4_os_pci_save_state(struct adapter *); 1118int t4_os_pci_restore_state(struct adapter *); 1119void t4_os_portmod_changed(struct port_info *); 1120void t4_os_link_changed(struct port_info *); 1121void t4_iterate(void (*)(struct adapter *, void *), void *); 1122void t4_init_devnames(struct adapter *); 1123void t4_add_adapter(struct adapter *); 1124int t4_detach_common(device_t); 1125int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1126int t4_map_bars_0_and_4(struct adapter *); 1127int t4_map_bar_2(struct adapter *); 1128int t4_setup_intr_handlers(struct adapter *); 1129void t4_sysctls(struct adapter *); 1130int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1131void doom_vi(struct adapter *, struct vi_info *); 1132void end_synchronized_op(struct adapter *, int); 1133int update_mac_settings(struct ifnet *, int); 1134int adapter_full_init(struct adapter *); 1135int adapter_full_uninit(struct adapter *); 1136uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1137int vi_full_init(struct vi_info *); 1138int vi_full_uninit(struct vi_info *); 1139void vi_sysctls(struct vi_info *); 1140void vi_tick(void *); 1141 1142#ifdef DEV_NETMAP 1143/* t4_netmap.c */ 1144void cxgbe_nm_attach(struct vi_info *); 1145void cxgbe_nm_detach(struct vi_info *); 1146void t4_nm_intr(void *); 1147#endif 1148 1149/* t4_sge.c */ 1150void t4_sge_modload(void); 1151void t4_sge_modunload(void); 1152uint64_t t4_sge_extfree_refs(void); 1153void t4_tweak_chip_settings(struct adapter *); 1154int t4_read_chip_settings(struct adapter *); 1155int t4_create_dma_tag(struct adapter *); 1156void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1157 struct sysctl_oid_list *); 1158int t4_destroy_dma_tag(struct adapter *); 1159int t4_setup_adapter_queues(struct adapter *); 1160int t4_teardown_adapter_queues(struct adapter *); 1161int t4_setup_vi_queues(struct vi_info *); 1162int t4_teardown_vi_queues(struct vi_info *); 1163void t4_intr_all(void *); 1164void t4_intr(void *); 1165void t4_vi_intr(void *); 1166void t4_intr_err(void *); 1167void t4_intr_evt(void *); 1168void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1169void t4_update_fl_bufsize(struct ifnet *); 1170int parse_pkt(struct adapter *, struct mbuf **); 1171void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1172void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1173int tnl_cong(struct port_info *, int); 1174int t4_register_an_handler(an_handler_t); 1175int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1176int t4_register_cpl_handler(int, cpl_handler_t); 1177 1178/* t4_tracer.c */ 1179struct t4_tracer; 1180void t4_tracer_modload(void); 1181void t4_tracer_modunload(void); 1182void t4_tracer_port_detach(struct adapter *); 1183int t4_get_tracer(struct adapter *, struct t4_tracer *); 1184int t4_set_tracer(struct adapter *, struct t4_tracer *); 1185int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1186int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1187 1188/* t4_sched.c */ 1189int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1190int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1191int t4_init_tx_sched(struct adapter *); 1192int t4_free_tx_sched(struct adapter *); 1193void t4_update_tx_sched(struct adapter *); 1194int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1195void t4_release_cl_rl_kbps(struct adapter *, int, int); 1196 1197static inline struct wrqe * 1198alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1199{ 1200 int len = offsetof(struct wrqe, wr) + wr_len; 1201 struct wrqe *wr; 1202 1203 wr = malloc(len, M_CXGBE, M_NOWAIT); 1204 if (__predict_false(wr == NULL)) 1205 return (NULL); 1206 wr->wr_len = wr_len; 1207 wr->wrq = wrq; 1208 return (wr); 1209} 1210 1211static inline void * 1212wrtod(struct wrqe *wr) 1213{ 1214 return (&wr->wr[0]); 1215} 1216 1217static inline void 1218free_wrqe(struct wrqe *wr) 1219{ 1220 free(wr, M_CXGBE); 1221} 1222 1223static inline void 1224t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1225{ 1226 struct sge_wrq *wrq = wr->wrq; 1227 1228 TXQ_LOCK(wrq); 1229 t4_wrq_tx_locked(sc, wrq, wr); 1230 TXQ_UNLOCK(wrq); 1231} 1232 1233#endif 1234