adapter.h revision 270297
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 270297 2014-08-21 19:54:02Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "common/t4_msg.h" 52#include "firmware/t4fw_interface.h" 53 54MALLOC_DECLARE(M_CXGBE); 55#define CXGBE_UNIMPLEMENTED(s) \ 56 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 57 58#if defined(__i386__) || defined(__amd64__) 59static __inline void 60prefetch(void *x) 61{ 62 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 63} 64#else 65#define prefetch(x) 66#endif 67 68#ifndef SYSCTL_ADD_UQUAD 69#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 70#define sysctl_handle_64 sysctl_handle_quad 71#define CTLTYPE_U64 CTLTYPE_QUAD 72#endif 73 74#if (__FreeBSD_version >= 900030) || \ 75 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 76#define SBUF_DRAIN 1 77#endif 78 79#ifdef __amd64__ 80/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 81static __inline uint64_t 82t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 83 bus_size_t offset) 84{ 85 KASSERT(tag == X86_BUS_SPACE_MEM, 86 ("%s: can only handle mem space", __func__)); 87 88 return (*(volatile uint64_t *)(handle + offset)); 89} 90 91static __inline void 92t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 93 bus_size_t offset, uint64_t value) 94{ 95 KASSERT(tag == X86_BUS_SPACE_MEM, 96 ("%s: can only handle mem space", __func__)); 97 98 *(volatile uint64_t *)(bsh + offset) = value; 99} 100#else 101static __inline uint64_t 102t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 103 bus_size_t offset) 104{ 105 return (uint64_t)bus_space_read_4(tag, handle, offset) + 106 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 107} 108 109static __inline void 110t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 111 bus_size_t offset, uint64_t value) 112{ 113 bus_space_write_4(tag, bsh, offset, value); 114 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 115} 116#endif 117 118struct adapter; 119typedef struct adapter adapter_t; 120 121enum { 122 /* 123 * All ingress queues use this entry size. Note that the firmware event 124 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 125 * be at least 64. 126 */ 127 IQ_ESIZE = 64, 128 129 /* Default queue sizes for all kinds of ingress queues */ 130 FW_IQ_QSIZE = 256, 131 RX_IQ_QSIZE = 1024, 132 133 /* All egress queues use this entry size */ 134 EQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of egress queues */ 137 CTRL_EQ_QSIZE = 128, 138 TX_EQ_QSIZE = 1024, 139 140#if MJUMPAGESIZE != MCLBYTES 141 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 142#else 143 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 144#endif 145 CL_METADATA_SIZE = CACHE_LINE_SIZE, 146 147 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 148 TX_SGL_SEGS = 36, 149 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 150}; 151 152enum { 153 /* adapter intr_type */ 154 INTR_INTX = (1 << 0), 155 INTR_MSI = (1 << 1), 156 INTR_MSIX = (1 << 2) 157}; 158 159enum { 160 XGMAC_MTU = (1 << 0), 161 XGMAC_PROMISC = (1 << 1), 162 XGMAC_ALLMULTI = (1 << 2), 163 XGMAC_VLANEX = (1 << 3), 164 XGMAC_UCADDR = (1 << 4), 165 XGMAC_MCADDRS = (1 << 5), 166 167 XGMAC_ALL = 0xffff 168}; 169 170enum { 171 /* flags understood by begin_synchronized_op */ 172 HOLD_LOCK = (1 << 0), 173 SLEEP_OK = (1 << 1), 174 INTR_OK = (1 << 2), 175 176 /* flags understood by end_synchronized_op */ 177 LOCK_HELD = HOLD_LOCK, 178}; 179 180enum { 181 /* adapter flags */ 182 FULL_INIT_DONE = (1 << 0), 183 FW_OK = (1 << 1), 184 /* INTR_DIRECT = (1 << 2), No longer used. */ 185 MASTER_PF = (1 << 3), 186 ADAP_SYSCTL_CTX = (1 << 4), 187 TOM_INIT_DONE = (1 << 5), 188 BUF_PACKING_OK = (1 << 6), 189 190 CXGBE_BUSY = (1 << 9), 191 192 /* port flags */ 193 DOOMED = (1 << 0), 194 PORT_INIT_DONE = (1 << 1), 195 PORT_SYSCTL_CTX = (1 << 2), 196 HAS_TRACEQ = (1 << 3), 197 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 198 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 199 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 200 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 201}; 202 203#define IS_DOOMED(pi) ((pi)->flags & DOOMED) 204#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 205#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 206#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 207#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 208 209struct port_info { 210 device_t dev; 211 struct adapter *adapter; 212 213 struct ifnet *ifp; 214 struct ifmedia media; 215 216 struct mtx pi_lock; 217 char lockname[16]; 218 unsigned long flags; 219 int if_flags; 220 221 uint16_t *rss; 222 uint16_t viid; 223 int16_t xact_addr_filt;/* index of exact MAC address filter */ 224 uint16_t rss_size; /* size of VI's RSS table slice */ 225 uint8_t lport; /* associated offload logical port */ 226 int8_t mdio_addr; 227 uint8_t port_type; 228 uint8_t mod_type; 229 uint8_t port_id; 230 uint8_t tx_chan; 231 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 232 233 /* These need to be int as they are used in sysctl */ 234 int ntxq; /* # of tx queues */ 235 int first_txq; /* index of first tx queue */ 236 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 237 int nrxq; /* # of rx queues */ 238 int first_rxq; /* index of first rx queue */ 239#ifdef TCP_OFFLOAD 240 int nofldtxq; /* # of offload tx queues */ 241 int first_ofld_txq; /* index of first offload tx queue */ 242 int nofldrxq; /* # of offload rx queues */ 243 int first_ofld_rxq; /* index of first offload rx queue */ 244#endif 245#ifdef DEV_NETMAP 246 int nnmtxq; /* # of netmap tx queues */ 247 int first_nm_txq; /* index of first netmap tx queue */ 248 int nnmrxq; /* # of netmap rx queues */ 249 int first_nm_rxq; /* index of first netmap rx queue */ 250 251 struct ifnet *nm_ifp; 252 struct ifmedia nm_media; 253 int nmif_flags; 254 uint16_t nm_viid; 255 int16_t nm_xact_addr_filt; 256 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 257#endif 258 int tmr_idx; 259 int pktc_idx; 260 int qsize_rxq; 261 int qsize_txq; 262 263 int linkdnrc; 264 struct link_config link_cfg; 265 struct port_stats stats; 266 267 eventhandler_tag vlan_c; 268 269 struct callout tick; 270 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 271 272 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 273}; 274 275/* Where the cluster came from, how it has been carved up. */ 276struct cluster_layout { 277 int8_t zidx; 278 int8_t hwidx; 279 uint16_t region1; /* mbufs laid out within this region */ 280 /* region2 is the DMA region */ 281 uint16_t region3; /* cluster_metadata within this region */ 282}; 283 284struct cluster_metadata { 285 u_int refcount; 286#ifdef INVARIANTS 287 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 288#endif 289}; 290 291struct fl_sdesc { 292 caddr_t cl; 293 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 294 struct cluster_layout cll; 295}; 296 297struct tx_desc { 298 __be64 flit[8]; 299}; 300 301struct tx_map { 302 struct mbuf *m; 303 bus_dmamap_t map; 304}; 305 306/* DMA maps used for tx */ 307struct tx_maps { 308 struct tx_map *maps; 309 uint32_t map_total; /* # of DMA maps */ 310 uint32_t map_pidx; /* next map to be used */ 311 uint32_t map_cidx; /* reclaimed up to this index */ 312 uint32_t map_avail; /* # of available maps */ 313}; 314 315struct tx_sdesc { 316 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 317 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 318}; 319 320 321#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 322struct iq_desc { 323 struct rss_header rss; 324 uint8_t cpl[IQ_PAD]; 325 struct rsp_ctrl rsp; 326}; 327#undef IQ_PAD 328CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 329 330enum { 331 /* iq flags */ 332 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 333 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 334 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 335 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 336 337 /* iq state */ 338 IQS_DISABLED = 0, 339 IQS_BUSY = 1, 340 IQS_IDLE = 2, 341}; 342 343/* 344 * Ingress Queue: T4 is producer, driver is consumer. 345 */ 346struct sge_iq { 347 uint32_t flags; 348 volatile int state; 349 struct adapter *adapter; 350 struct iq_desc *desc; /* KVA of descriptor ring */ 351 int8_t intr_pktc_idx; /* packet count threshold index */ 352 uint8_t gen; /* generation bit */ 353 uint8_t intr_params; /* interrupt holdoff parameters */ 354 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 355 uint16_t qsize; /* size (# of entries) of the queue */ 356 uint16_t sidx; /* index of the entry with the status page */ 357 uint16_t cidx; /* consumer index */ 358 uint16_t cntxt_id; /* SGE context id for the iq */ 359 uint16_t abs_id; /* absolute SGE id for the iq */ 360 361 STAILQ_ENTRY(sge_iq) link; 362 363 bus_dma_tag_t desc_tag; 364 bus_dmamap_t desc_map; 365 bus_addr_t ba; /* bus address of descriptor ring */ 366}; 367 368enum { 369 EQ_CTRL = 1, 370 EQ_ETH = 2, 371#ifdef TCP_OFFLOAD 372 EQ_OFLD = 3, 373#endif 374 375 /* eq flags */ 376 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 377 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 378 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 379 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 380 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 381}; 382 383/* Listed in order of preference. Update t4_sysctls too if you change these */ 384enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 385 386/* 387 * Egress Queue: driver is producer, T4 is consumer. 388 * 389 * Note: A free list is an egress queue (driver produces the buffers and T4 390 * consumes them) but it's special enough to have its own struct (see sge_fl). 391 */ 392struct sge_eq { 393 unsigned int flags; /* MUST be first */ 394 unsigned int cntxt_id; /* SGE context id for the eq */ 395 bus_dma_tag_t desc_tag; 396 bus_dmamap_t desc_map; 397 char lockname[16]; 398 struct mtx eq_lock; 399 400 struct tx_desc *desc; /* KVA of descriptor ring */ 401 bus_addr_t ba; /* bus address of descriptor ring */ 402 struct sge_qstat *spg; /* status page, for convenience */ 403 uint16_t doorbells; 404 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 405 u_int udb_qid; /* relative qid within the doorbell page */ 406 uint16_t cap; /* max # of desc, for convenience */ 407 uint16_t avail; /* available descriptors, for convenience */ 408 uint16_t qsize; /* size (# of entries) of the queue */ 409 uint16_t cidx; /* consumer idx (desc idx) */ 410 uint16_t pidx; /* producer idx (desc idx) */ 411 uint16_t pending; /* # of descriptors used since last doorbell */ 412 uint16_t iqid; /* iq that gets egr_update for the eq */ 413 uint8_t tx_chan; /* tx channel used by the eq */ 414 struct task tx_task; 415 struct callout tx_callout; 416 417 /* stats */ 418 419 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 420 uint32_t unstalled; /* recovered from stall */ 421}; 422 423struct sw_zone_info { 424 uma_zone_t zone; /* zone that this cluster comes from */ 425 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 426 int type; /* EXT_xxx type of the cluster */ 427 int8_t head_hwidx; 428 int8_t tail_hwidx; 429}; 430 431struct hw_buf_info { 432 int8_t zidx; /* backpointer to zone; -ve means unused */ 433 int8_t next; /* next hwidx for this zone; -1 means no more */ 434 int size; 435}; 436 437enum { 438 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 439 FL_DOOMED = (1 << 1), /* about to be destroyed */ 440 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 441 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 442}; 443 444#define FL_RUNNING_LOW(fl) \ 445 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 446#define FL_NOT_RUNNING_LOW(fl) \ 447 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 448 449struct sge_fl { 450 struct mtx fl_lock; 451 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 452 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 453 struct cluster_layout cll_def; /* default refill zone, layout */ 454 uint16_t lowat; /* # of buffers <= this means fl needs help */ 455 int flags; 456 uint16_t buf_boundary; 457 458 /* The 16b idx all deal with hw descriptors */ 459 uint16_t dbidx; /* hw pidx after last doorbell */ 460 uint16_t sidx; /* index of status page */ 461 volatile uint16_t hw_cidx; 462 463 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 464 uint32_t cidx; /* consumer index */ 465 uint32_t pidx; /* producer index */ 466 467 uint32_t dbval; 468 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 469 volatile uint32_t *udb; 470 471 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 472 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 473 uint64_t cl_allocated; /* # of clusters allocated */ 474 uint64_t cl_recycled; /* # of clusters recycled */ 475 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 476 477 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 478 struct mbuf *m0; 479 struct mbuf **pnext; 480 u_int remaining; 481 482 uint16_t qsize; /* # of hw descriptors (status page included) */ 483 uint16_t cntxt_id; /* SGE context id for the freelist */ 484 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 485 bus_dma_tag_t desc_tag; 486 bus_dmamap_t desc_map; 487 char lockname[16]; 488 bus_addr_t ba; /* bus address of descriptor ring */ 489 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 490}; 491 492/* txq: SGE egress queue + what's needed for Ethernet NIC */ 493struct sge_txq { 494 struct sge_eq eq; /* MUST be first */ 495 496 struct ifnet *ifp; /* the interface this txq belongs to */ 497 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 498 struct buf_ring *br; /* tx buffer ring */ 499 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 500 struct mbuf *m; /* held up due to temporary resource shortage */ 501 502 struct tx_maps txmaps; 503 504 /* stats for common events first */ 505 506 uint64_t txcsum; /* # of times hardware assisted with checksum */ 507 uint64_t tso_wrs; /* # of TSO work requests */ 508 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 509 uint64_t imm_wrs; /* # of work requests with immediate data */ 510 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 511 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 512 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 513 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 514 515 /* stats for not-that-common events */ 516 517 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 518 uint32_t no_desc; /* out of hardware descriptors */ 519} __aligned(CACHE_LINE_SIZE); 520 521/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 522struct sge_rxq { 523 struct sge_iq iq; /* MUST be first */ 524 struct sge_fl fl; /* MUST follow iq */ 525 526 struct ifnet *ifp; /* the interface this rxq belongs to */ 527#if defined(INET) || defined(INET6) 528 struct lro_ctrl lro; /* LRO state */ 529#endif 530 531 /* stats for common events first */ 532 533 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 534 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 535 536 /* stats for not-that-common events */ 537 538} __aligned(CACHE_LINE_SIZE); 539 540static inline struct sge_rxq * 541iq_to_rxq(struct sge_iq *iq) 542{ 543 544 return (__containerof(iq, struct sge_rxq, iq)); 545} 546 547 548#ifdef TCP_OFFLOAD 549/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 550struct sge_ofld_rxq { 551 struct sge_iq iq; /* MUST be first */ 552 struct sge_fl fl; /* MUST follow iq */ 553} __aligned(CACHE_LINE_SIZE); 554 555static inline struct sge_ofld_rxq * 556iq_to_ofld_rxq(struct sge_iq *iq) 557{ 558 559 return (__containerof(iq, struct sge_ofld_rxq, iq)); 560} 561#endif 562 563struct wrqe { 564 STAILQ_ENTRY(wrqe) link; 565 struct sge_wrq *wrq; 566 int wr_len; 567 uint64_t wr[] __aligned(16); 568}; 569 570/* 571 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 572 * and offload tx queues are of this type. 573 */ 574struct sge_wrq { 575 struct sge_eq eq; /* MUST be first */ 576 577 struct adapter *adapter; 578 579 /* List of WRs held up due to lack of tx descriptors */ 580 STAILQ_HEAD(, wrqe) wr_list; 581 582 /* stats for common events first */ 583 584 uint64_t tx_wrs; /* # of tx work requests */ 585 586 /* stats for not-that-common events */ 587 588 uint32_t no_desc; /* out of hardware descriptors */ 589} __aligned(CACHE_LINE_SIZE); 590 591 592#ifdef DEV_NETMAP 593struct sge_nm_rxq { 594 struct port_info *pi; 595 596 struct iq_desc *iq_desc; 597 uint16_t iq_abs_id; 598 uint16_t iq_cntxt_id; 599 uint16_t iq_cidx; 600 uint16_t iq_sidx; 601 uint8_t iq_gen; 602 603 __be64 *fl_desc; 604 uint16_t fl_cntxt_id; 605 uint32_t fl_cidx; 606 uint32_t fl_pidx; 607 uint32_t fl_sidx; 608 uint32_t fl_db_val; 609 u_int fl_hwidx:4; 610 611 u_int nid; /* netmap ring # for this queue */ 612 613 /* infrequently used items after this */ 614 615 bus_dma_tag_t iq_desc_tag; 616 bus_dmamap_t iq_desc_map; 617 bus_addr_t iq_ba; 618 int intr_idx; 619 620 bus_dma_tag_t fl_desc_tag; 621 bus_dmamap_t fl_desc_map; 622 bus_addr_t fl_ba; 623} __aligned(CACHE_LINE_SIZE); 624 625struct sge_nm_txq { 626 struct tx_desc *desc; 627 uint16_t cidx; 628 uint16_t pidx; 629 uint16_t sidx; 630 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 631 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 632 uint16_t dbidx; /* pidx of the most recent doorbell */ 633 uint16_t doorbells; 634 volatile uint32_t *udb; 635 u_int udb_qid; 636 u_int cntxt_id; 637 __be32 cpl_ctrl0; /* for convenience */ 638 u_int nid; /* netmap ring # for this queue */ 639 640 /* infrequently used items after this */ 641 642 bus_dma_tag_t desc_tag; 643 bus_dmamap_t desc_map; 644 bus_addr_t ba; 645 int iqidx; 646} __aligned(CACHE_LINE_SIZE); 647#endif 648 649struct sge { 650 int timer_val[SGE_NTIMERS]; 651 int counter_val[SGE_NCOUNTERS]; 652 int fl_starve_threshold; 653 int fl_starve_threshold2; 654 int eq_s_qpp; 655 int iq_s_qpp; 656 657 int nrxq; /* total # of Ethernet rx queues */ 658 int ntxq; /* total # of Ethernet tx tx queues */ 659#ifdef TCP_OFFLOAD 660 int nofldrxq; /* total # of TOE rx queues */ 661 int nofldtxq; /* total # of TOE tx queues */ 662#endif 663#ifdef DEV_NETMAP 664 int nnmrxq; /* total # of netmap rx queues */ 665 int nnmtxq; /* total # of netmap tx queues */ 666#endif 667 int niq; /* total # of ingress queues */ 668 int neq; /* total # of egress queues */ 669 670 struct sge_iq fwq; /* Firmware event queue */ 671 struct sge_wrq mgmtq; /* Management queue (control queue) */ 672 struct sge_wrq *ctrlq; /* Control queues */ 673 struct sge_txq *txq; /* NIC tx queues */ 674 struct sge_rxq *rxq; /* NIC rx queues */ 675#ifdef TCP_OFFLOAD 676 struct sge_wrq *ofld_txq; /* TOE tx queues */ 677 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 678#endif 679#ifdef DEV_NETMAP 680 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 681 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 682#endif 683 684 uint16_t iq_start; 685 int eq_start; 686 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 687 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 688 689 int pack_boundary; 690 int8_t safe_hwidx1; /* may not have room for metadata */ 691 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 692 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 693 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 694}; 695 696struct rss_header; 697typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 698 struct mbuf *); 699typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 700typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 701 702struct adapter { 703 SLIST_ENTRY(adapter) link; 704 device_t dev; 705 struct cdev *cdev; 706 707 /* PCIe register resources */ 708 int regs_rid; 709 struct resource *regs_res; 710 int msix_rid; 711 struct resource *msix_res; 712 bus_space_handle_t bh; 713 bus_space_tag_t bt; 714 bus_size_t mmio_len; 715 int udbs_rid; 716 struct resource *udbs_res; 717 volatile uint8_t *udbs_base; 718 719 unsigned int pf; 720 unsigned int mbox; 721 722 /* Interrupt information */ 723 int intr_type; 724 int intr_count; 725 struct irq { 726 struct resource *res; 727 int rid; 728 void *tag; 729 } *irq; 730 731 bus_dma_tag_t dmat; /* Parent DMA tag */ 732 733 struct sge sge; 734 int lro_timeout; 735 736 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 737 struct port_info *port[MAX_NPORTS]; 738 uint8_t chan_map[NCHAN]; 739 740#ifdef TCP_OFFLOAD 741 void *tom_softc; /* (struct tom_data *) */ 742 struct tom_tunables tt; 743 void *iwarp_softc; /* (struct c4iw_dev *) */ 744 void *iscsi_softc; 745#endif 746 struct l2t_data *l2t; /* L2 table */ 747 struct tid_info tids; 748 749 uint16_t doorbells; 750 int open_device_map; 751#ifdef TCP_OFFLOAD 752 int offload_map; 753#endif 754 int flags; 755 756 char ifp_lockname[16]; 757 struct mtx ifp_lock; 758 struct ifnet *ifp; /* tracer ifp */ 759 struct ifmedia media; 760 int traceq; /* iq used by all tracers, -1 if none */ 761 int tracer_valid; /* bitmap of valid tracers */ 762 int tracer_enabled; /* bitmap of enabled tracers */ 763 764 char fw_version[32]; 765 char cfg_file[32]; 766 u_int cfcsum; 767 struct adapter_params params; 768 struct t4_virt_res vres; 769 770 uint16_t linkcaps; 771 uint16_t niccaps; 772 uint16_t toecaps; 773 uint16_t rdmacaps; 774 uint16_t iscsicaps; 775 uint16_t fcoecaps; 776 777 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 778 779 struct mtx sc_lock; 780 char lockname[16]; 781 782 /* Starving free lists */ 783 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 784 TAILQ_HEAD(, sge_fl) sfl; 785 struct callout sfl_callout; 786 787 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 788 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 789 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 790 791#ifdef INVARIANTS 792 const char *last_op; 793 const void *last_op_thr; 794#endif 795 796 int sc_do_rxcopy; 797}; 798 799#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 800#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 801#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 802#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 803 804/* XXX: not bulletproof, but much better than nothing */ 805#define ASSERT_SYNCHRONIZED_OP(sc) \ 806 KASSERT(IS_BUSY(sc) && \ 807 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 808 ("%s: operation not synchronized.", __func__)) 809 810#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 811#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 812#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 813#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 814 815#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 816#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 817#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 818#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 819#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 820 821#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 822#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 823#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 824#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 825 826#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 827#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 828#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 829#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 830#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 831 832#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 833#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 834#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 835#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 836#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 837 838#define for_each_txq(pi, iter, q) \ 839 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 840 iter < pi->ntxq; ++iter, ++q) 841#define for_each_rxq(pi, iter, q) \ 842 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 843 iter < pi->nrxq; ++iter, ++q) 844#define for_each_ofld_txq(pi, iter, q) \ 845 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 846 iter < pi->nofldtxq; ++iter, ++q) 847#define for_each_ofld_rxq(pi, iter, q) \ 848 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 849 iter < pi->nofldrxq; ++iter, ++q) 850#define for_each_nm_txq(pi, iter, q) \ 851 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 852 iter < pi->nnmtxq; ++iter, ++q) 853#define for_each_nm_rxq(pi, iter, q) \ 854 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 855 iter < pi->nnmrxq; ++iter, ++q) 856 857#define IDXINCR(idx, incr, wrap) do { \ 858 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 859} while (0) 860#define IDXDIFF(head, tail, wrap) \ 861 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 862 863/* One for errors, one for firmware events */ 864#define T4_EXTRA_INTR 2 865 866static inline uint32_t 867t4_read_reg(struct adapter *sc, uint32_t reg) 868{ 869 870 return bus_space_read_4(sc->bt, sc->bh, reg); 871} 872 873static inline void 874t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 875{ 876 877 bus_space_write_4(sc->bt, sc->bh, reg, val); 878} 879 880static inline uint64_t 881t4_read_reg64(struct adapter *sc, uint32_t reg) 882{ 883 884 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 885} 886 887static inline void 888t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 889{ 890 891 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 892} 893 894static inline void 895t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 896{ 897 898 *val = pci_read_config(sc->dev, reg, 1); 899} 900 901static inline void 902t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 903{ 904 905 pci_write_config(sc->dev, reg, val, 1); 906} 907 908static inline void 909t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 910{ 911 912 *val = pci_read_config(sc->dev, reg, 2); 913} 914 915static inline void 916t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 917{ 918 919 pci_write_config(sc->dev, reg, val, 2); 920} 921 922static inline void 923t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 924{ 925 926 *val = pci_read_config(sc->dev, reg, 4); 927} 928 929static inline void 930t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 931{ 932 933 pci_write_config(sc->dev, reg, val, 4); 934} 935 936static inline struct port_info * 937adap2pinfo(struct adapter *sc, int idx) 938{ 939 940 return (sc->port[idx]); 941} 942 943static inline void 944t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 945{ 946 947 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 948} 949 950static inline bool 951is_10G_port(const struct port_info *pi) 952{ 953 954 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 955} 956 957static inline bool 958is_40G_port(const struct port_info *pi) 959{ 960 961 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 962} 963 964static inline int 965tx_resume_threshold(struct sge_eq *eq) 966{ 967 968 return (eq->qsize / 4); 969} 970 971/* t4_main.c */ 972void t4_tx_task(void *, int); 973void t4_tx_callout(void *); 974int t4_os_find_pci_capability(struct adapter *, int); 975int t4_os_pci_save_state(struct adapter *); 976int t4_os_pci_restore_state(struct adapter *); 977void t4_os_portmod_changed(const struct adapter *, int); 978void t4_os_link_changed(struct adapter *, int, int, int); 979void t4_iterate(void (*)(struct adapter *, void *), void *); 980int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 981int t4_register_an_handler(struct adapter *, an_handler_t); 982int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 983int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 984int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 985void end_synchronized_op(struct adapter *, int); 986int update_mac_settings(struct ifnet *, int); 987int adapter_full_init(struct adapter *); 988int adapter_full_uninit(struct adapter *); 989int port_full_init(struct port_info *); 990int port_full_uninit(struct port_info *); 991 992#ifdef DEV_NETMAP 993/* t4_netmap.c */ 994int create_netmap_ifnet(struct port_info *); 995int destroy_netmap_ifnet(struct port_info *); 996void t4_nm_intr(void *); 997#endif 998 999/* t4_sge.c */ 1000void t4_sge_modload(void); 1001void t4_sge_modunload(void); 1002uint64_t t4_sge_extfree_refs(void); 1003void t4_init_sge_cpl_handlers(struct adapter *); 1004void t4_tweak_chip_settings(struct adapter *); 1005int t4_read_chip_settings(struct adapter *); 1006int t4_create_dma_tag(struct adapter *); 1007void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1008 struct sysctl_oid_list *); 1009int t4_destroy_dma_tag(struct adapter *); 1010int t4_setup_adapter_queues(struct adapter *); 1011int t4_teardown_adapter_queues(struct adapter *); 1012int t4_setup_port_queues(struct port_info *); 1013int t4_teardown_port_queues(struct port_info *); 1014int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 1015void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 1016void t4_intr_all(void *); 1017void t4_intr(void *); 1018void t4_intr_err(void *); 1019void t4_intr_evt(void *); 1020void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1021int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 1022void t4_update_fl_bufsize(struct ifnet *); 1023int can_resume_tx(struct sge_eq *); 1024 1025/* t4_tracer.c */ 1026struct t4_tracer; 1027void t4_tracer_modload(void); 1028void t4_tracer_modunload(void); 1029void t4_tracer_port_detach(struct adapter *); 1030int t4_get_tracer(struct adapter *, struct t4_tracer *); 1031int t4_set_tracer(struct adapter *, struct t4_tracer *); 1032int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1033int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1034 1035static inline struct wrqe * 1036alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1037{ 1038 int len = offsetof(struct wrqe, wr) + wr_len; 1039 struct wrqe *wr; 1040 1041 wr = malloc(len, M_CXGBE, M_NOWAIT); 1042 if (__predict_false(wr == NULL)) 1043 return (NULL); 1044 wr->wr_len = wr_len; 1045 wr->wrq = wrq; 1046 return (wr); 1047} 1048 1049static inline void * 1050wrtod(struct wrqe *wr) 1051{ 1052 return (&wr->wr[0]); 1053} 1054 1055static inline void 1056free_wrqe(struct wrqe *wr) 1057{ 1058 free(wr, M_CXGBE); 1059} 1060 1061static inline void 1062t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1063{ 1064 struct sge_wrq *wrq = wr->wrq; 1065 1066 TXQ_LOCK(wrq); 1067 t4_wrq_tx_locked(sc, wrq, wr); 1068 TXQ_UNLOCK(wrq); 1069} 1070 1071#endif 1072