1189747Ssam/* 2189747Ssam * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3189747Ssam * Copyright (c) 2008 Atheros Communications, Inc. 4189747Ssam * 5189747Ssam * Permission to use, copy, modify, and/or distribute this software for any 6189747Ssam * purpose with or without fee is hereby granted, provided that the above 7189747Ssam * copyright notice and this permission notice appear in all copies. 8189747Ssam * 9189747Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10189747Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11189747Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12189747Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13189747Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14189747Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15189747Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16189747Ssam * 17189747Ssam * $FreeBSD$ 18189747Ssam */ 19189747Ssam#include "opt_ah.h" 20189747Ssam 21189747Ssam#include "ah.h" 22189747Ssam#include "ah_internal.h" 23189747Ssam#include "ah_devid.h" 24189747Ssam 25189747Ssam#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26189747Ssam 27217631Sadrian#include "ar9002/ar9280.h" 28189747Ssam#include "ar5416/ar5416reg.h" 29189747Ssam#include "ar5416/ar5416phy.h" 30189747Ssam 31217631Sadrian#include "ar9002/ar9280v1.ini" 32217631Sadrian#include "ar9002/ar9280v2.ini" 33219393Sadrian#include "ar9002/ar9280_olc.h" 34189747Ssam 35189747Ssamstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36189747Ssam .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 38189747Ssam .calCountMax = PER_MAX_LOG_COUNT, 39189747Ssam .calCollect = ar5416IQCalCollect, 40189747Ssam .calPostProc = ar5416IQCalibration 41189747Ssam}; 42189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43189747Ssam .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 45224515Sadrian .calCountMax = PER_MAX_LOG_COUNT, 46189747Ssam .calCollect = ar5416AdcGainCalCollect, 47189747Ssam .calPostProc = ar5416AdcGainCalibration 48189747Ssam}; 49189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50189747Ssam .calName = "ADC DC", .calType = ADC_DC_CAL, 51189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 52224515Sadrian .calCountMax = PER_MAX_LOG_COUNT, 53189747Ssam .calCollect = ar5416AdcDcCalCollect, 54189747Ssam .calPostProc = ar5416AdcDcCalibration 55189747Ssam}; 56189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57189747Ssam .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 59189747Ssam .calCountMax = INIT_LOG_COUNT, 60189747Ssam .calCollect = ar5416AdcDcCalCollect, 61189747Ssam .calPostProc = ar5416AdcDcCalibration 62189747Ssam}; 63189747Ssam 64235972Sadrianstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 65235972Sadrian HAL_BOOL power_off); 66235957Sadrianstatic void ar9280DisablePCIE(struct ath_hal *ah); 67189747Ssamstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 68189747Ssamstatic void ar9280WriteIni(struct ath_hal *ah, 69189747Ssam const struct ieee80211_channel *chan); 70189747Ssam 71189747Ssamstatic void 72189747Ssamar9280AniSetup(struct ath_hal *ah) 73189747Ssam{ 74218764Sadrian /* 75218764Sadrian * These are the parameters from the AR5416 ANI code; 76218764Sadrian * they likely need quite a bit of adjustment for the 77218764Sadrian * AR9280. 78218764Sadrian */ 79218764Sadrian static const struct ar5212AniParams aniparams = { 80218764Sadrian .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 81218764Sadrian .totalSizeDesired = { -55, -55, -55, -55, -62 }, 82218764Sadrian .coarseHigh = { -14, -14, -14, -14, -12 }, 83218764Sadrian .coarseLow = { -64, -64, -64, -64, -70 }, 84218764Sadrian .firpwr = { -78, -78, -78, -78, -80 }, 85242408Sadrian .maxSpurImmunityLevel = 7, 86242408Sadrian .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 87218764Sadrian .maxFirstepLevel = 2, /* levels 0..2 */ 88218764Sadrian .firstep = { 0, 4, 8 }, 89218764Sadrian .ofdmTrigHigh = 500, 90218764Sadrian .ofdmTrigLow = 200, 91218764Sadrian .cckTrigHigh = 200, 92218764Sadrian .cckTrigLow = 100, 93218764Sadrian .rssiThrHigh = 40, 94218764Sadrian .rssiThrLow = 7, 95218764Sadrian .period = 100, 96218764Sadrian }; 97218764Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 98222276Sadrian AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 99218764Sadrian 100218764Sadrian /* NB: ANI is not enabled yet */ 101219979Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 102189747Ssam} 103189747Ssam 104224243Sadrianvoid 105224243Sadrianar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 106224243Sadrian{ 107224243Sadrian uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 108224243Sadrian 109224243Sadrian if (AR_SREV_MERLIN_20(ah) && 110224243Sadrian chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 111224243Sadrian /* 112224243Sadrian * PLL WAR for Merlin 2.0/2.1 113224243Sadrian * When doing fast clock, set PLL to 0x142c 114224243Sadrian * Else, set PLL to 0x2850 to prevent reset-to-reset variation 115224243Sadrian */ 116224243Sadrian pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 117240471Sadrian if (IEEE80211_IS_CHAN_HALF(chan)) 118240471Sadrian pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 119240471Sadrian else if (IEEE80211_IS_CHAN_QUARTER(chan)) 120240471Sadrian pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 121224243Sadrian } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 122224243Sadrian pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 123224243Sadrian if (chan != AH_NULL) { 124224243Sadrian if (IEEE80211_IS_CHAN_HALF(chan)) 125224243Sadrian pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 126224243Sadrian else if (IEEE80211_IS_CHAN_QUARTER(chan)) 127224243Sadrian pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 128224243Sadrian if (IEEE80211_IS_CHAN_5GHZ(chan)) 129224243Sadrian pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 130224243Sadrian else 131224243Sadrian pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 132224243Sadrian } else 133224243Sadrian pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 134224243Sadrian } 135224243Sadrian 136224243Sadrian OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 137224243Sadrian OS_DELAY(RTC_PLL_SETTLE_DELAY); 138224243Sadrian OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 139224243Sadrian} 140224243Sadrian 141221875Sadrian/* XXX shouldn't be here! */ 142221875Sadrian#define EEP_MINOR(_ah) \ 143221875Sadrian (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 144221875Sadrian 145189747Ssam/* 146189747Ssam * Attach for an AR9280 part. 147189747Ssam */ 148189747Ssamstatic struct ath_hal * 149189747Ssamar9280Attach(uint16_t devid, HAL_SOFTC sc, 150217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 151217624Sadrian HAL_STATUS *status) 152189747Ssam{ 153189747Ssam struct ath_hal_9280 *ahp9280; 154189747Ssam struct ath_hal_5212 *ahp; 155189747Ssam struct ath_hal *ah; 156189747Ssam uint32_t val; 157189747Ssam HAL_STATUS ecode; 158189747Ssam HAL_BOOL rfStatus; 159219393Sadrian int8_t pwr_table_offset; 160219441Sadrian uint8_t pwr; 161189747Ssam 162225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 163189747Ssam __func__, sc, (void*) st, (void*) sh); 164189747Ssam 165189747Ssam /* NB: memory is returned zero'd */ 166189747Ssam ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 167189747Ssam if (ahp9280 == AH_NULL) { 168225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 169189747Ssam "%s: cannot allocate memory for state block\n", __func__); 170189747Ssam *status = HAL_ENOMEM; 171189747Ssam return AH_NULL; 172189747Ssam } 173189747Ssam ahp = AH5212(ahp9280); 174189747Ssam ah = &ahp->ah_priv.h; 175189747Ssam 176189747Ssam ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 177189747Ssam 178230147Sadrian /* 179230147Sadrian * Use the "local" EEPROM data given to us by the higher layers. 180230147Sadrian * This is a private copy out of system flash. The Linux ath9k 181230147Sadrian * commit for the initial AR9130 support mentions MMIO flash 182230147Sadrian * access is "unreliable." -adrian 183230147Sadrian */ 184230147Sadrian if (eepromdata != AH_NULL) { 185230147Sadrian AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 186230147Sadrian AH_PRIVATE((ah))->ah_eepromWrite = NULL; 187230147Sadrian ah->ah_eepromdata = eepromdata; 188234510Sadrian } 189230147Sadrian 190189747Ssam /* XXX override with 9280 specific state */ 191189747Ssam /* override 5416 methods for our needs */ 192224243Sadrian AH5416(ah)->ah_initPLL = ar9280InitPLL; 193224243Sadrian 194189747Ssam ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 195189747Ssam ah->ah_configPCIE = ar9280ConfigPCIE; 196235957Sadrian ah->ah_disablePCIE = ar9280DisablePCIE; 197189747Ssam 198189747Ssam AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 199189747Ssam AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 200189747Ssam AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 201189747Ssam AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 202189747Ssam AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 203189747Ssam 204189747Ssam AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 205189747Ssam AH5416(ah)->ah_writeIni = ar9280WriteIni; 206219393Sadrian AH5416(ah)->ah_olcInit = ar9280olcInit; 207219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 208219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 209219393Sadrian 210189747Ssam AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 211189747Ssam AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 212189747Ssam 213189747Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 214189747Ssam /* reset chip */ 215189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 216189747Ssam __func__); 217189747Ssam ecode = HAL_EIO; 218189747Ssam goto bad; 219189747Ssam } 220189747Ssam 221189747Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 222189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 223189747Ssam __func__); 224189747Ssam ecode = HAL_EIO; 225189747Ssam goto bad; 226189747Ssam } 227189747Ssam /* Read Revisions from Chips before taking out of reset */ 228189747Ssam val = OS_REG_READ(ah, AR_SREV); 229189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 230189747Ssam "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 231189747Ssam __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 232189747Ssam MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 233189747Ssam /* NB: include chip type to differentiate from pre-Sowl versions */ 234189747Ssam AH_PRIVATE(ah)->ah_macVersion = 235189747Ssam (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 236189747Ssam AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 237189747Ssam AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 238189747Ssam 239189747Ssam /* setup common ini data; rf backends handle remainder */ 240203882Srpaulo if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 241189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 242189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 243189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 244189747Ssam ar9280PciePhy_clkreq_always_on_L1_v2, 2); 245189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 246189747Ssam ar9280Modes_fast_clock_v2, 3); 247189747Ssam } else { 248189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 249189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 250189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 251189747Ssam ar9280PciePhy_v1, 2); 252189747Ssam } 253189747Ssam ar5416AttachPCIE(ah); 254189747Ssam 255203882Srpaulo ecode = ath_hal_v14EepromAttach(ah); 256189747Ssam if (ecode != HAL_OK) 257189747Ssam goto bad; 258189747Ssam 259189747Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 260189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 261189747Ssam ecode = HAL_EIO; 262189747Ssam goto bad; 263189747Ssam } 264189747Ssam 265189747Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 266189747Ssam 267189747Ssam if (!ar5212ChipTest(ah)) { 268189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 269189747Ssam __func__); 270189747Ssam ecode = HAL_ESELFTEST; 271189747Ssam goto bad; 272189747Ssam } 273189747Ssam 274189747Ssam /* 275189747Ssam * Set correct Baseband to analog shift 276189747Ssam * setting to access analog chips. 277189747Ssam */ 278189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 279189747Ssam 280189747Ssam /* Read Radio Chip Rev Extract */ 281189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 282189747Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 283189747Ssam case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 284189747Ssam case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 285189747Ssam break; 286189747Ssam default: 287189747Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 288189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 289189747Ssam AR_RAD5133_SREV_MAJOR; 290189747Ssam break; 291189747Ssam } 292189747Ssam#ifdef AH_DEBUG 293189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 294189747Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 295189747Ssam "this driver\n", __func__, 296189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 297189747Ssam ecode = HAL_ENOTSUPP; 298189747Ssam goto bad; 299189747Ssam#endif 300189747Ssam } 301189747Ssam rfStatus = ar9280RfAttach(ah, &ecode); 302189747Ssam if (!rfStatus) { 303189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 304189747Ssam __func__, ecode); 305189747Ssam goto bad; 306189747Ssam } 307189747Ssam 308219441Sadrian /* Enable fixup for AR_AN_TOP2 if necessary */ 309219441Sadrian /* 310219441Sadrian * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 311219441Sadrian * by the EEPROM version. 312219441Sadrian * 313219441Sadrian * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 314219441Sadrian * the abstracted EEPROM access layer. 315219441Sadrian */ 316219441Sadrian ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 317219441Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 318219441Sadrian printf("[ath] enabling AN_TOP2_FIXUP\n"); 319219441Sadrian AH5416(ah)->ah_need_an_top2_fixup = 1; 320219441Sadrian } 321219441Sadrian 322219393Sadrian /* 323219393Sadrian * Check whether the power table offset isn't the default. 324219393Sadrian * This can occur with eeprom minor V21 or greater on Merlin. 325219393Sadrian */ 326219393Sadrian (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 327219445Sadrian if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 328219445Sadrian ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 329219393Sadrian AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 330219393Sadrian 331221875Sadrian /* XXX check for >= minor ver 17 */ 332221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 333189747Ssam /* setup rxgain table */ 334189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 335189747Ssam case AR5416_EEP_RXGAIN_13dB_BACKOFF: 336189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 337189747Ssam ar9280Modes_backoff_13db_rxgain_v2, 6); 338189747Ssam break; 339189747Ssam case AR5416_EEP_RXGAIN_23dB_BACKOFF: 340189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 341189747Ssam ar9280Modes_backoff_23db_rxgain_v2, 6); 342189747Ssam break; 343189747Ssam case AR5416_EEP_RXGAIN_ORIG: 344189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 345189747Ssam ar9280Modes_original_rxgain_v2, 6); 346189747Ssam break; 347189747Ssam default: 348189747Ssam HALASSERT(AH_FALSE); 349189747Ssam goto bad; /* XXX ? try to continue */ 350189747Ssam } 351189747Ssam } 352221875Sadrian 353221875Sadrian /* XXX check for >= minor ver 19 */ 354221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 355189747Ssam /* setp txgain table */ 356189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 357189747Ssam case AR5416_EEP_TXGAIN_HIGH_POWER: 358189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 359189747Ssam ar9280Modes_high_power_tx_gain_v2, 6); 360189747Ssam break; 361189747Ssam case AR5416_EEP_TXGAIN_ORIG: 362189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 363189747Ssam ar9280Modes_original_tx_gain_v2, 6); 364189747Ssam break; 365189747Ssam default: 366189747Ssam HALASSERT(AH_FALSE); 367189747Ssam goto bad; /* XXX ? try to continue */ 368189747Ssam } 369189747Ssam } 370189747Ssam 371189747Ssam /* 372189747Ssam * Got everything we need now to setup the capabilities. 373189747Ssam */ 374189747Ssam if (!ar9280FillCapabilityInfo(ah)) { 375189747Ssam ecode = HAL_EEREAD; 376189747Ssam goto bad; 377189747Ssam } 378189747Ssam 379189747Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 380189747Ssam if (ecode != HAL_OK) { 381189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 382189747Ssam "%s: error getting mac address from EEPROM\n", __func__); 383189747Ssam goto bad; 384189747Ssam } 385189747Ssam /* XXX How about the serial number ? */ 386189747Ssam /* Read Reg Domain */ 387189747Ssam AH_PRIVATE(ah)->ah_currentRD = 388189747Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 389221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 390221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 391189747Ssam 392189747Ssam /* 393189747Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 394189747Ssam * starting from griffin. Set here to make sure that 395189747Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 396189747Ssam * placed into hardware. 397189747Ssam */ 398189747Ssam if (ahp->ah_miscMode != 0) 399219852Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 400189747Ssam 401189747Ssam ar9280AniSetup(ah); /* Anti Noise Immunity */ 402218068Sadrian 403218068Sadrian /* Setup noise floor min/max/nominal values */ 404218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 405218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 406218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 407218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 408218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 409218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 410218068Sadrian 411203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 412189747Ssam 413189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 414189747Ssam 415189747Ssam return ah; 416189747Ssambad: 417189747Ssam if (ah != AH_NULL) 418189747Ssam ah->ah_detach(ah); 419189747Ssam if (status) 420189747Ssam *status = ecode; 421189747Ssam return AH_NULL; 422189747Ssam} 423189747Ssam 424189747Ssamstatic void 425235972Sadrianar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 426189747Ssam{ 427236039Sadrian uint32_t val; 428236039Sadrian 429189747Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 430189747Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 431189747Ssam OS_DELAY(1000); 432236039Sadrian } 433236039Sadrian 434236039Sadrian 435236039Sadrian /* 436236039Sadrian * Set PCIe workaround bits 437236039Sadrian * 438236039Sadrian * NOTE: 439236039Sadrian * 440236039Sadrian * In Merlin and Kite, bit 14 in WA register (disable L1) should only 441236039Sadrian * be set when device enters D3 and be cleared when device comes back 442236039Sadrian * to D0. 443236039Sadrian */ 444236039Sadrian if (power_off) { /* Power-off */ 445236039Sadrian OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 446236039Sadrian 447236039Sadrian val = OS_REG_READ(ah, AR_WA); 448236039Sadrian 449236039Sadrian /* 450236039Sadrian * Disable bit 6 and 7 before entering D3 to prevent 451236039Sadrian * system hang. 452236039Sadrian */ 453236039Sadrian val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 454236039Sadrian 455236039Sadrian /* 456236039Sadrian * XXX Not sure, is specified in the reference HAL. 457236039Sadrian */ 458236039Sadrian val |= AR_WA_BIT22; 459236039Sadrian 460236039Sadrian /* 461236039Sadrian * See above: set AR_WA_D3_L1_DISABLE when entering D3 state. 462236039Sadrian * 463236039Sadrian * XXX The reference HAL does it this way - it only sets 464236039Sadrian * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT, 465236039Sadrian * which it (currently) isn't. So the following statement 466236039Sadrian * is currently a NOP. 467236039Sadrian */ 468236039Sadrian if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) 469236039Sadrian val |= AR_WA_D3_L1_DISABLE; 470236039Sadrian 471236039Sadrian OS_REG_WRITE(ah, AR_WA, val); 472236039Sadrian } else { /* Power-on */ 473236039Sadrian val = AR9280_WA_DEFAULT; 474236039Sadrian 475236039Sadrian /* 476236039Sadrian * See note above: make sure L1_DISABLE is not set. 477236039Sadrian */ 478236039Sadrian val &= (~AR_WA_D3_L1_DISABLE); 479236039Sadrian OS_REG_WRITE(ah, AR_WA, val); 480236039Sadrian 481236039Sadrian /* set bit 19 to allow forcing of pcie core into L1 state */ 482189747Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 483189747Ssam } 484189747Ssam} 485189747Ssam 486189747Ssamstatic void 487235957Sadrianar9280DisablePCIE(struct ath_hal *ah) 488235957Sadrian{ 489235957Sadrian} 490235957Sadrian 491235957Sadrianstatic void 492189747Ssamar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 493189747Ssam{ 494189747Ssam u_int modesIndex, freqIndex; 495189747Ssam int regWrites = 0; 496219441Sadrian int i; 497219441Sadrian const HAL_INI_ARRAY *ia; 498189747Ssam 499189747Ssam /* Setup the indices for the next set of register array writes */ 500189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 501189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 502189747Ssam freqIndex = 2; 503189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 504189747Ssam modesIndex = 3; 505189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 506189747Ssam modesIndex = 5; 507189747Ssam else 508189747Ssam modesIndex = 4; 509189747Ssam } else { 510189747Ssam freqIndex = 1; 511189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 512189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 513189747Ssam modesIndex = 2; 514189747Ssam else 515189747Ssam modesIndex = 1; 516189747Ssam } 517189747Ssam 518189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 519189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 520189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 521189747Ssam 522219441Sadrian /* 523219441Sadrian * This is unwound because at the moment, there's a requirement 524219441Sadrian * for Merlin (and later, perhaps) to have a specific bit fixed 525219441Sadrian * in the AR_AN_TOP2 register before writing it. 526219441Sadrian */ 527219441Sadrian ia = &AH5212(ah)->ah_ini_modes; 528219441Sadrian#if 0 529189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 530189747Ssam modesIndex, regWrites); 531219441Sadrian#endif 532219441Sadrian HALASSERT(modesIndex < ia->cols); 533219441Sadrian for (i = 0; i < ia->rows; i++) { 534219441Sadrian uint32_t reg = HAL_INI_VAL(ia, i, 0); 535219441Sadrian uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 536219441Sadrian 537219441Sadrian if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 538219441Sadrian val &= ~AR_AN_TOP2_PWDCLKIND; 539219441Sadrian 540219441Sadrian OS_REG_WRITE(ah, reg, val); 541219441Sadrian 542219441Sadrian /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 543222157Sadrian if (reg >= 0x7800 && reg < 0x7900) 544219441Sadrian OS_DELAY(100); 545219441Sadrian 546219441Sadrian DMA_YIELD(regWrites); 547219441Sadrian } 548219441Sadrian 549189747Ssam if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 550189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 551189747Ssam modesIndex, regWrites); 552189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 553189747Ssam modesIndex, regWrites); 554189747Ssam } 555189747Ssam /* XXX Merlin 100us delay for shift registers */ 556189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 557189747Ssam 1, regWrites); 558189747Ssam 559189747Ssam if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 560189747Ssam /* 5GHz channels w/ Fast Clock use different modal values */ 561189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 562189747Ssam modesIndex, regWrites); 563189747Ssam } 564189747Ssam} 565189747Ssam 566189747Ssam#define AR_BASE_FREQ_2GHZ 2300 567189747Ssam#define AR_BASE_FREQ_5GHZ 4900 568189747Ssam#define AR_SPUR_FEEQ_BOUND_HT40 19 569189747Ssam#define AR_SPUR_FEEQ_BOUND_HT20 10 570189747Ssam 571203930Srpaulovoid 572189747Ssamar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 573189747Ssam{ 574189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 575189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 576189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 577189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 578189747Ssam static int inc[4] = { 0, 100, 0, 0 }; 579189747Ssam 580189747Ssam int bb_spur = AR_NO_SPUR; 581189747Ssam int freq; 582189747Ssam int bin, cur_bin; 583189747Ssam int bb_spur_off, spur_subchannel_sd; 584189747Ssam int spur_freq_sd; 585189747Ssam int spur_delta_phase; 586189747Ssam int denominator; 587189747Ssam int upper, lower, cur_vit_mask; 588189747Ssam int tmp, newVal; 589189747Ssam int i; 590189747Ssam CHAN_CENTERS centers; 591189747Ssam 592189747Ssam int8_t mask_m[123]; 593189747Ssam int8_t mask_p[123]; 594189747Ssam int8_t mask_amt; 595189747Ssam int tmp_mask; 596189747Ssam int cur_bb_spur; 597189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 598189747Ssam 599189747Ssam OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 600189747Ssam OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 601189747Ssam 602189747Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 603189747Ssam freq = centers.synth_center; 604189747Ssam 605189747Ssam /* 606189747Ssam * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 607189747Ssam * otherwise spur is out-of-band and can be ignored. 608189747Ssam */ 609189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 610189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 611189747Ssam /* Get actual spur freq in MHz from EEPROM read value */ 612189747Ssam if (is2GHz) { 613189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 614189747Ssam } else { 615189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 616189747Ssam } 617189747Ssam 618189747Ssam if (AR_NO_SPUR == cur_bb_spur) 619189747Ssam break; 620189747Ssam cur_bb_spur = cur_bb_spur - freq; 621189747Ssam 622189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 623189747Ssam if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 624189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 625189747Ssam bb_spur = cur_bb_spur; 626189747Ssam break; 627189747Ssam } 628189747Ssam } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 629189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 630189747Ssam bb_spur = cur_bb_spur; 631189747Ssam break; 632189747Ssam } 633189747Ssam } 634189747Ssam 635189747Ssam if (AR_NO_SPUR == bb_spur) { 636189747Ssam#if 1 637189747Ssam /* 638189747Ssam * MRC CCK can interfere with beacon detection and cause deaf/mute. 639189747Ssam * Disable MRC CCK for now. 640189747Ssam */ 641189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 642189747Ssam#else 643189747Ssam /* Enable MRC CCK if no spur is found in this channel. */ 644189747Ssam OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 645189747Ssam#endif 646189747Ssam return; 647189747Ssam } else { 648189747Ssam /* 649189747Ssam * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 650189747Ssam * is found in this channel. 651189747Ssam */ 652189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 653189747Ssam } 654189747Ssam 655189747Ssam bin = bb_spur * 320; 656189747Ssam 657189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 658189747Ssam 659189747Ssam newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 660189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 661189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 662189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 663189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 664189747Ssam 665189747Ssam newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 666189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 667189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 668189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 669189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 670189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 671189747Ssam 672189747Ssam /* Pick control or extn channel to cancel the spur */ 673189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 674189747Ssam if (bb_spur < 0) { 675189747Ssam spur_subchannel_sd = 1; 676189747Ssam bb_spur_off = bb_spur + 10; 677189747Ssam } else { 678189747Ssam spur_subchannel_sd = 0; 679189747Ssam bb_spur_off = bb_spur - 10; 680189747Ssam } 681189747Ssam } else { 682189747Ssam spur_subchannel_sd = 0; 683189747Ssam bb_spur_off = bb_spur; 684189747Ssam } 685189747Ssam 686189747Ssam /* 687189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 688189747Ssam * /80 for dyn2040. 689189747Ssam */ 690189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 691189747Ssam spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 692189747Ssam else 693189747Ssam spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 694189747Ssam 695189747Ssam /* 696189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 697189747Ssam * it should be 44 in 11G 698189747Ssam */ 699189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 700189747Ssam spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 701189747Ssam 702189747Ssam newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 703189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 704189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 705189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 706189747Ssam 707189747Ssam /* Choose to cancel between control and extension channels */ 708189747Ssam newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 709189747Ssam OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 710189747Ssam 711189747Ssam /* 712189747Ssam * ============================================ 713189747Ssam * Set Pilot and Channel Masks 714189747Ssam * 715189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 716189747Ssam * pilot mask 2 [19:0] = +26..+7 717189747Ssam * 718189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 719189747Ssam * channel mask 2 [19:0] = +26..+7 720189747Ssam */ 721189747Ssam cur_bin = -6000; 722189747Ssam upper = bin + 100; 723189747Ssam lower = bin - 100; 724189747Ssam 725189747Ssam for (i = 0; i < 4; i++) { 726189747Ssam int pilot_mask = 0; 727189747Ssam int chan_mask = 0; 728189747Ssam int bp = 0; 729189747Ssam for (bp = 0; bp < 30; bp++) { 730189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 731189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 732189747Ssam chan_mask = chan_mask | 0x1 << bp; 733189747Ssam } 734189747Ssam cur_bin += 100; 735189747Ssam } 736189747Ssam cur_bin += inc[i]; 737189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 738189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 739189747Ssam } 740189747Ssam 741189747Ssam /* ================================================= 742189747Ssam * viterbi mask 1 based on channel magnitude 743189747Ssam * four levels 0-3 744189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 745189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 746189747Ssam * - enable_mask_ppm, all bins move with freq 747189747Ssam * 748189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 749189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 750189747Ssam * choose which mask to use mask or mask2 751189747Ssam */ 752189747Ssam 753189747Ssam /* 754189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 755189747Ssam * four levels 0-3 756189747Ssam * - mask_select, 8 bits for rates (reg 67) 757189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 758189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 759189747Ssam */ 760189747Ssam cur_vit_mask = 6100; 761189747Ssam upper = bin + 120; 762189747Ssam lower = bin - 120; 763189747Ssam 764189747Ssam for (i = 0; i < 123; i++) { 765189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 766189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 767189747Ssam mask_amt = 1; 768189747Ssam } else { 769189747Ssam mask_amt = 0; 770189747Ssam } 771189747Ssam if (cur_vit_mask < 0) { 772189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 773189747Ssam } else { 774189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 775189747Ssam } 776189747Ssam } 777189747Ssam cur_vit_mask -= 100; 778189747Ssam } 779189747Ssam 780189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 781189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 782189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 783189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 784189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 785189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 786189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 787189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 788189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 789189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 790189747Ssam 791189747Ssam tmp_mask = (mask_m[31] << 28) 792189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 793189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 794189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 795189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 796189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 797189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 798189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 799189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 800189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 801189747Ssam 802189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 803189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 804189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 805189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 806189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 807189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 808189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 809189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 810189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 811189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 812189747Ssam 813189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 814189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 815189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 816189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 817189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 818189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 819189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 820189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 821189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 822189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 823189747Ssam 824189747Ssam tmp_mask = (mask_p[15] << 28) 825189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 826189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 827189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 828189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 829189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 830189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 831189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 832189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 833189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 834189747Ssam 835189747Ssam tmp_mask = (mask_p[30] << 28) 836189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 837189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 838189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 839189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 840189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 841189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 842189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 843189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 844189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 845189747Ssam 846189747Ssam tmp_mask = (mask_p[45] << 28) 847189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 848189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 849189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 850189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 851189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 852189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 853189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 854189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 855189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 856189747Ssam 857189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 858189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 859189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 860189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 861189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 862189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 863189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 864189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 865189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 866189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 867189747Ssam} 868189747Ssam 869189747Ssam/* 870189747Ssam * Fill all software cached or static hardware state information. 871189747Ssam * Return failure if capabilities are to come from EEPROM and 872189747Ssam * cannot be read. 873189747Ssam */ 874189747Ssamstatic HAL_BOOL 875189747Ssamar9280FillCapabilityInfo(struct ath_hal *ah) 876189747Ssam{ 877189747Ssam HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 878189747Ssam 879189747Ssam if (!ar5416FillCapabilityInfo(ah)) 880189747Ssam return AH_FALSE; 881203882Srpaulo pCap->halNumGpioPins = 10; 882189747Ssam pCap->halWowSupport = AH_TRUE; 883189747Ssam pCap->halWowMatchPatternExact = AH_TRUE; 884189747Ssam#if 0 885189747Ssam pCap->halWowMatchPatternDword = AH_TRUE; 886189747Ssam#endif 887189747Ssam pCap->halCSTSupport = AH_TRUE; 888189747Ssam pCap->halRifsRxSupport = AH_TRUE; 889189747Ssam pCap->halRifsTxSupport = AH_TRUE; 890189747Ssam pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 891189747Ssam pCap->halExtChanDfsSupport = AH_TRUE; 892222584Sadrian pCap->halUseCombinedRadarRssi = AH_TRUE; 893189747Ssam#if 0 894189747Ssam /* XXX bluetooth */ 895189747Ssam pCap->halBtCoexSupport = AH_TRUE; 896189747Ssam#endif 897189747Ssam pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 898189747Ssam pCap->hal4kbSplitTransSupport = AH_FALSE; 899220325Sadrian /* Disable this so Block-ACK works correctly */ 900220325Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 901221603Sadrian pCap->halMbssidAggrSupport = AH_TRUE; 902221603Sadrian pCap->hal4AddrAggrSupport = AH_TRUE; 903244943Sadrian pCap->halSpectralScanSupport = AH_TRUE; 904221603Sadrian 905221667Sadrian if (AR_SREV_MERLIN_20(ah)) { 906221603Sadrian pCap->halPSPollBroken = AH_FALSE; 907221667Sadrian /* 908221667Sadrian * This just enables the support; it doesn't 909221667Sadrian * state 5ghz fast clock will always be used. 910221667Sadrian */ 911221667Sadrian pCap->halSupportsFastClock5GHz = AH_TRUE; 912221667Sadrian } 913189747Ssam pCap->halRxStbcSupport = 1; 914189747Ssam pCap->halTxStbcSupport = 1; 915222584Sadrian pCap->halEnhancedDfsSupport = AH_TRUE; 916189747Ssam 917189747Ssam return AH_TRUE; 918189747Ssam} 919189747Ssam 920218708Sadrian/* 921218708Sadrian * This has been disabled - having the HAL flip chainmasks on/off 922218708Sadrian * when attempting to implement 11n disrupts things. For now, just 923218708Sadrian * leave this flipped off and worry about implementing TX diversity 924218708Sadrian * for legacy and MCS0-7 when 11n is fully functioning. 925218708Sadrian */ 926189747SsamHAL_BOOL 927189747Ssamar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 928189747Ssam{ 929189747Ssam#define ANTENNA0_CHAINMASK 0x1 930189747Ssam#define ANTENNA1_CHAINMASK 0x2 931218708Sadrian#if 0 932189747Ssam struct ath_hal_5416 *ahp = AH5416(ah); 933189747Ssam 934189747Ssam /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 935189747Ssam switch (settings) { 936189747Ssam case HAL_ANT_FIXED_A: 937189747Ssam /* Enable first antenna only */ 938189747Ssam ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 939189747Ssam ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 940189747Ssam break; 941189747Ssam case HAL_ANT_FIXED_B: 942189747Ssam /* Enable second antenna only, after checking capability */ 943189747Ssam if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 944189747Ssam ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 945189747Ssam ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 946189747Ssam break; 947189747Ssam case HAL_ANT_VARIABLE: 948189747Ssam /* Restore original chainmask settings */ 949189747Ssam /* XXX */ 950217641Sadrian ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 951217641Sadrian ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 952189747Ssam break; 953189747Ssam } 954217684Sadrian 955217684Sadrian HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 956217684Sadrian __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 957217684Sadrian 958218708Sadrian#endif 959189747Ssam return AH_TRUE; 960189747Ssam#undef ANTENNA0_CHAINMASK 961189747Ssam#undef ANTENNA1_CHAINMASK 962189747Ssam} 963189747Ssam 964189747Ssamstatic const char* 965189747Ssamar9280Probe(uint16_t vendorid, uint16_t devid) 966189747Ssam{ 967227373Sadrian if (vendorid == ATHEROS_VENDOR_ID) { 968227373Sadrian if (devid == AR9280_DEVID_PCI) 969227373Sadrian return "Atheros 9220"; 970227373Sadrian if (devid == AR9280_DEVID_PCIE) 971227373Sadrian return "Atheros 9280"; 972227373Sadrian } 973189747Ssam return AH_NULL; 974189747Ssam} 975189747SsamAH_CHIP(AR9280, ar9280Probe, ar9280Attach); 976