1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203158Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25185377Ssam 26185377Ssam#include "ar5416/ar5416.h" 27185377Ssam#include "ar5416/ar5416reg.h" 28185377Ssam#include "ar5416/ar5416phy.h" 29185377Ssam 30231368Sadrian#include "ah_eeprom_v14.h" /* for owl_get_ntxchains() */ 31231368Sadrian 32185377Ssam/* 33203750Srpaulo * Return the wireless modes (a,b,g,n,t) supported by hardware. 34185377Ssam * 35185377Ssam * This value is what is actually supported by the hardware 36185377Ssam * and is unaffected by regulatory/country code settings. 37185377Ssam * 38185377Ssam */ 39185377Ssamu_int 40185377Ssamar5416GetWirelessModes(struct ath_hal *ah) 41185377Ssam{ 42185377Ssam u_int mode; 43217634Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 44217634Sadrian HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 45185377Ssam 46185377Ssam mode = ar5212GetWirelessModes(ah); 47217634Sadrian 48217634Sadrian /* Only enable HT modes if the NIC supports HT */ 49217634Sadrian if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 50185377Ssam mode |= HAL_MODE_11NA_HT20 51185377Ssam | HAL_MODE_11NA_HT40PLUS 52185377Ssam | HAL_MODE_11NA_HT40MINUS 53185377Ssam ; 54217634Sadrian if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 55185377Ssam mode |= HAL_MODE_11NG_HT20 56185377Ssam | HAL_MODE_11NG_HT40PLUS 57185377Ssam | HAL_MODE_11NG_HT40MINUS 58185377Ssam ; 59185377Ssam return mode; 60185377Ssam} 61185377Ssam 62185377Ssam/* 63185377Ssam * Change the LED blinking pattern to correspond to the connectivity 64185377Ssam */ 65185377Ssamvoid 66185377Ssamar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 67185377Ssam{ 68185377Ssam static const uint32_t ledbits[8] = { 69185377Ssam AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 70185377Ssam AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 71185377Ssam AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 72185377Ssam AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 73185377Ssam AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 74185377Ssam AR_MAC_LED_ASSOC_NONE, 75185377Ssam AR_MAC_LED_ASSOC_NONE, 76185377Ssam AR_MAC_LED_ASSOC_NONE, 77185377Ssam }; 78185377Ssam 79221163Sadrian if (AR_SREV_HOWL(ah)) 80221163Sadrian return; 81221163Sadrian 82228889Sadrian /* 83228889Sadrian * Set the blink operating mode. 84228889Sadrian */ 85228837Sadrian OS_REG_RMW_FIELD(ah, AR_MAC_LED, 86228837Sadrian AR_MAC_LED_ASSOC, ledbits[state & 0x7]); 87228837Sadrian 88228889Sadrian /* XXX Blink slow mode? */ 89228889Sadrian /* XXX Blink threshold? */ 90228889Sadrian /* XXX Blink sleep hystersis? */ 91228889Sadrian 92228837Sadrian /* 93228889Sadrian * Set the LED blink configuration to be proportional 94228889Sadrian * to the current TX and RX filter bytes. (Ie, RX'ed 95228889Sadrian * frames that don't match the filter are ignored.) 96228889Sadrian * This means that higher TX/RX throughput will result 97228889Sadrian * in the blink rate increasing. 98228837Sadrian */ 99228889Sadrian OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE, 100228889Sadrian AR_MAC_LED_MODE_PROP); 101185377Ssam} 102185377Ssam 103185377Ssam/* 104225444Sadrian * Get the current hardware tsf for stamlme 105225444Sadrian */ 106225444Sadrianuint64_t 107225444Sadrianar5416GetTsf64(struct ath_hal *ah) 108225444Sadrian{ 109225444Sadrian uint32_t low1, low2, u32; 110225444Sadrian 111225444Sadrian /* sync multi-word read */ 112225444Sadrian low1 = OS_REG_READ(ah, AR_TSF_L32); 113225444Sadrian u32 = OS_REG_READ(ah, AR_TSF_U32); 114225444Sadrian low2 = OS_REG_READ(ah, AR_TSF_L32); 115225444Sadrian if (low2 < low1) { /* roll over */ 116225444Sadrian /* 117225444Sadrian * If we are not preempted this will work. If we are 118225444Sadrian * then we re-reading AR_TSF_U32 does no good as the 119225444Sadrian * low bits will be meaningless. Likewise reading 120225444Sadrian * L32, U32, U32, then comparing the last two reads 121225444Sadrian * to check for rollover doesn't help if preempted--so 122225444Sadrian * we take this approach as it costs one less PCI read 123225444Sadrian * which can be noticeable when doing things like 124225444Sadrian * timestamping packets in monitor mode. 125225444Sadrian */ 126225444Sadrian u32++; 127225444Sadrian } 128225444Sadrian return (((uint64_t) u32) << 32) | ((uint64_t) low2); 129225444Sadrian} 130225444Sadrian 131243472Sadrian/* 132243472Sadrian * Update the TSF. 133243472Sadrian * 134243472Sadrian * The full TSF is only updated once the upper 32 bits have 135243472Sadrian * been written. Writing only the lower 32 bits of the TSF 136243472Sadrian * will not actually correctly update the TSF. 137243472Sadrian * 138243472Sadrian * The #if 0'ed code is to check whether the previous TSF 139243472Sadrian * reset or write has completed before writing to the 140243472Sadrian * TSF. Strictly speaking, it should be also checked before 141243472Sadrian * reading the TSF as the write/reset may not have completed. 142243472Sadrian */ 143225444Sadrianvoid 144225444Sadrianar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64) 145225444Sadrian{ 146243424Sadrian /* XXX check if this is correct! */ 147243424Sadrian#if 0 148243424Sadrian int i; 149243424Sadrian uint32_t v; 150243424Sadrian 151243424Sadrian for (i = 0; i < 10; i++) { 152243424Sadrian v = OS_REG_READ(ah, AR_SLP32_MODE); 153243424Sadrian if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 154243424Sadrian break; 155243424Sadrian OS_DELAY(10); 156243424Sadrian } 157243424Sadrian if (i == 10) 158243424Sadrian ath_hal_printf(ah, "%s: couldn't slew things right!\n", __func__); 159243424Sadrian#endif 160243424Sadrian 161225444Sadrian OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 162225444Sadrian OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 163225444Sadrian} 164225444Sadrian 165225444Sadrian/* 166185377Ssam * Reset the current hardware tsf for stamlme. 167185377Ssam */ 168185377Ssamvoid 169185377Ssamar5416ResetTsf(struct ath_hal *ah) 170185377Ssam{ 171185377Ssam uint32_t v; 172185377Ssam int i; 173185377Ssam 174185377Ssam for (i = 0; i < 10; i++) { 175185377Ssam v = OS_REG_READ(ah, AR_SLP32_MODE); 176185377Ssam if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 177185377Ssam break; 178185377Ssam OS_DELAY(10); 179185377Ssam } 180185377Ssam OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 181185377Ssam} 182185377Ssam 183225957Sadrianuint32_t 184225957Sadrianar5416GetCurRssi(struct ath_hal *ah) 185225957Sadrian{ 186225957Sadrian if (AR_SREV_OWL(ah)) 187225957Sadrian return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); 188225957Sadrian return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff); 189225957Sadrian} 190225957Sadrian 191185377SsamHAL_BOOL 192185377Ssamar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 193185377Ssam{ 194185377Ssam return AH_TRUE; 195185377Ssam} 196185377Ssam 197185377Ssam/* Setup decompression for given key index */ 198185377SsamHAL_BOOL 199185377Ssamar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 200185377Ssam{ 201228817Sadrian return AH_TRUE; 202185377Ssam} 203185377Ssam 204185377Ssam/* Setup coverage class */ 205185377Ssamvoid 206185377Ssamar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 207185377Ssam{ 208240446Sadrian 209240446Sadrian ar5212SetCoverageClass(ah, coverageclass, now); 210185377Ssam} 211185377Ssam 212185377Ssam/* 213227374Sadrian * Return the busy for rx_frame, rx_clear, and tx_frame 214227374Sadrian */ 215234873SadrianHAL_BOOL 216234752Sadrianar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 217227374Sadrian{ 218227374Sadrian struct ath_hal_5416 *ahp = AH5416(ah); 219234873Sadrian u_int32_t good = AH_TRUE; 220227374Sadrian 221227374Sadrian /* XXX freeze/unfreeze mib counters */ 222227374Sadrian uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 223227374Sadrian uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 224227374Sadrian uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 225227374Sadrian uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 226227374Sadrian uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 227227374Sadrian 228227374Sadrian if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 229227374Sadrian /* 230227374Sadrian * Cycle counter wrap (or initial call); it's not possible 231227374Sadrian * to accurately calculate a value because the registers 232227374Sadrian * right shift rather than wrap--so punt and return 0. 233227374Sadrian */ 234227374Sadrian HALDEBUG(ah, HAL_DEBUG_ANY, 235227374Sadrian "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 236234873Sadrian good = AH_FALSE; 237227374Sadrian } else { 238234752Sadrian hsample->cycle_count = cc - ahp->ah_cycleCount; 239234752Sadrian hsample->chan_busy = rc - ahp->ah_ctlBusy; 240234752Sadrian hsample->ext_chan_busy = ec - ahp->ah_extBusy; 241234752Sadrian hsample->rx_busy = rf - ahp->ah_rxBusy; 242234752Sadrian hsample->tx_busy = tf - ahp->ah_txBusy; 243234752Sadrian } 244227374Sadrian 245234752Sadrian /* 246234752Sadrian * Keep a copy of the MIB results so the next sample has something 247234752Sadrian * to work from. 248234752Sadrian */ 249227374Sadrian ahp->ah_cycleCount = cc; 250227374Sadrian ahp->ah_rxBusy = rf; 251227374Sadrian ahp->ah_ctlBusy = rc; 252227374Sadrian ahp->ah_txBusy = tf; 253227374Sadrian ahp->ah_extBusy = ec; 254227374Sadrian 255234873Sadrian return (good); 256227374Sadrian} 257227374Sadrian 258227374Sadrian/* 259247286Sadrian * Setup the TX/RX chainmasks - this needs to be done before a call 260247286Sadrian * to the reset method as it doesn't update the hardware. 261247286Sadrian */ 262247286Sadrianvoid 263247286Sadrianar5416SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask, 264247286Sadrian uint32_t rx_chainmask) 265247286Sadrian{ 266247286Sadrian HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 267247286Sadrian 268247286Sadrian AH5416(ah)->ah_tx_chainmask = tx_chainmask & pCap->halTxChainMask; 269247286Sadrian AH5416(ah)->ah_rx_chainmask = rx_chainmask & pCap->halRxChainMask; 270247286Sadrian} 271247286Sadrian 272247286Sadrian/* 273185377Ssam * Return approximation of extension channel busy over an time interval 274185377Ssam * 0% (clear) -> 100% (busy) 275185377Ssam * 276234752Sadrian * XXX TODO: update this to correctly sample all the counters, 277234752Sadrian * rather than a subset of it. 278185377Ssam */ 279185377Ssamuint32_t 280185377Ssamar5416Get11nExtBusy(struct ath_hal *ah) 281185377Ssam{ 282185377Ssam struct ath_hal_5416 *ahp = AH5416(ah); 283185377Ssam uint32_t busy; /* percentage */ 284185377Ssam uint32_t cycleCount, ctlBusy, extBusy; 285185377Ssam 286185377Ssam ctlBusy = OS_REG_READ(ah, AR_RCCNT); 287185377Ssam extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 288185377Ssam cycleCount = OS_REG_READ(ah, AR_CCCNT); 289185377Ssam 290185377Ssam if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 291185377Ssam /* 292185377Ssam * Cycle counter wrap (or initial call); it's not possible 293185377Ssam * to accurately calculate a value because the registers 294185377Ssam * right shift rather than wrap--so punt and return 0. 295185377Ssam */ 296185377Ssam busy = 0; 297185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 298185377Ssam __func__); 299185377Ssam 300185377Ssam } else { 301185377Ssam uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 302185377Ssam uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 303185377Ssam uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 304185377Ssam uint32_t ctlClearDelta = 0; 305185377Ssam 306185377Ssam /* Compute control channel rxclear. 307185377Ssam * The cycle delta may be less than the control channel delta. 308185377Ssam * This could be solved by freezing the timers (or an atomic read, 309185377Ssam * if one was available). Checking for the condition should be 310185377Ssam * sufficient. 311185377Ssam */ 312185377Ssam if (cycleDelta > ctlBusyDelta) { 313185377Ssam ctlClearDelta = cycleDelta - ctlBusyDelta; 314185377Ssam } 315185377Ssam 316185377Ssam /* Compute ratio of extension channel busy to control channel clear 317185377Ssam * as an approximation to extension channel cleanliness. 318185377Ssam * 319185377Ssam * According to the hardware folks, ext rxclear is undefined 320185377Ssam * if the ctrl rxclear is de-asserted (i.e. busy) 321185377Ssam */ 322185377Ssam if (ctlClearDelta) { 323185377Ssam busy = (extBusyDelta * 100) / ctlClearDelta; 324185377Ssam } else { 325185377Ssam busy = 100; 326185377Ssam } 327185377Ssam if (busy > 100) { 328185377Ssam busy = 100; 329185377Ssam } 330185377Ssam#if 0 331185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 332185377Ssam "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 333185377Ssam "busy %d\n", 334185377Ssam __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 335185377Ssam#endif 336185377Ssam } 337185377Ssam 338185377Ssam ahp->ah_cycleCount = cycleCount; 339185377Ssam ahp->ah_ctlBusy = ctlBusy; 340185377Ssam ahp->ah_extBusy = extBusy; 341185377Ssam 342185377Ssam return busy; 343185377Ssam} 344185377Ssam 345185377Ssam/* 346185377Ssam * Configure 20/40 operation 347185377Ssam * 348185377Ssam * 20/40 = joint rx clear (control and extension) 349185377Ssam * 20 = rx clear (control) 350185377Ssam * 351185377Ssam * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 352185377Ssam * from 20/40 => 20 only 353185377Ssam */ 354185377Ssamvoid 355185377Ssamar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 356185377Ssam{ 357185377Ssam uint32_t macmode; 358185377Ssam 359185377Ssam /* Configure MAC for 20/40 operation */ 360185377Ssam if (mode == HAL_HT_MACMODE_2040) { 361185377Ssam macmode = AR_2040_JOINED_RX_CLEAR; 362185377Ssam } else { 363185377Ssam macmode = 0; 364185377Ssam } 365185377Ssam OS_REG_WRITE(ah, AR_2040_MODE, macmode); 366185377Ssam} 367185377Ssam 368185377Ssam/* 369185377Ssam * Get Rx clear (control/extension channel) 370185377Ssam * 371185377Ssam * Returns active low (busy) for ctrl/ext channel 372185377Ssam * Owl 2.0 373185377Ssam */ 374185377SsamHAL_HT_RXCLEAR 375185377Ssamar5416Get11nRxClear(struct ath_hal *ah) 376185377Ssam{ 377185377Ssam HAL_HT_RXCLEAR rxclear = 0; 378185377Ssam uint32_t val; 379185377Ssam 380185377Ssam val = OS_REG_READ(ah, AR_DIAG_SW); 381185377Ssam 382185377Ssam /* control channel */ 383185377Ssam if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 384185377Ssam rxclear |= HAL_RX_CLEAR_CTL_LOW; 385185377Ssam } 386185377Ssam /* extension channel */ 387226761Sadrian if (val & AR_DIAG_RXCLEAR_EXT_LOW) { 388185377Ssam rxclear |= HAL_RX_CLEAR_EXT_LOW; 389185377Ssam } 390185377Ssam return rxclear; 391185377Ssam} 392185377Ssam 393185377Ssam/* 394185377Ssam * Set Rx clear (control/extension channel) 395185377Ssam * 396185377Ssam * Useful for forcing the channel to appear busy for 397185377Ssam * debugging/diagnostics 398185377Ssam * Owl 2.0 399185377Ssam */ 400185377Ssamvoid 401185377Ssamar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 402185377Ssam{ 403185377Ssam /* control channel */ 404185377Ssam if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 405185377Ssam OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 406185377Ssam } else { 407185377Ssam OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 408185377Ssam } 409185377Ssam /* extension channel */ 410185377Ssam if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 411185377Ssam OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 412185377Ssam } else { 413185377Ssam OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 414185377Ssam } 415185377Ssam} 416185377Ssam 417222644Sadrian/* XXX shouldn't be here! */ 418222644Sadrian#define TU_TO_USEC(_tu) ((_tu) << 10) 419222644Sadrian 420185377SsamHAL_STATUS 421222644Sadrianar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 422222644Sadrian uint32_t nextStart, HAL_QUIET_FLAG flag) 423222644Sadrian{ 424222644Sadrian uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */ 425222644Sadrian uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */ 426222644Sadrian if (flag & HAL_QUIET_ENABLE) { 427222644Sadrian if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 428222644Sadrian /* Add the nextStart offset to the current TSF */ 429222644Sadrian nextStart_us += OS_REG_READ(ah, AR_TSF_L32); 430222644Sadrian } 431222644Sadrian if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 432223459Sadrian nextStart_us += ah->ah_config.ah_sw_beacon_response_time; 433222644Sadrian } 434222644Sadrian OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 435222644Sadrian OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 436222644Sadrian OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us); 437222644Sadrian OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us); 438222644Sadrian OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 439222644Sadrian } else { 440222644Sadrian OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 441222644Sadrian } 442222644Sadrian return HAL_OK; 443222644Sadrian} 444222644Sadrian#undef TU_TO_USEC 445222644Sadrian 446222644SadrianHAL_STATUS 447185377Ssamar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 448185377Ssam uint32_t capability, uint32_t *result) 449185377Ssam{ 450185377Ssam switch (type) { 451185377Ssam case HAL_CAP_BB_HANG: 452185377Ssam switch (capability) { 453185377Ssam case HAL_BB_HANG_RIFS: 454221580Sadrian return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 455185377Ssam case HAL_BB_HANG_DFS: 456221580Sadrian return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 457185377Ssam case HAL_BB_HANG_RX_CLEAR: 458185377Ssam return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 459185377Ssam } 460185377Ssam break; 461185377Ssam case HAL_CAP_MAC_HANG: 462185377Ssam return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 463185377Ssam (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 464221580Sadrian AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 465185380Ssam HAL_OK : HAL_ENOTSUPP; 466220718Sadrian case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 467220718Sadrian return HAL_ENXIO; 468243743Sadrian case HAL_CAP_ENFORCE_TXOP: 469250841Sadrian if (capability == 0) 470250841Sadrian return (HAL_OK); 471250841Sadrian if (capability != 1) 472250841Sadrian return (HAL_ENOTSUPP); 473243743Sadrian (*result) = 474243743Sadrian !! (AH5212(ah)->ah_miscMode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 475243743Sadrian return (HAL_OK); 476185377Ssam default: 477185377Ssam break; 478185377Ssam } 479185377Ssam return ar5212GetCapability(ah, type, capability, result); 480185377Ssam} 481185377Ssam 482231368SadrianHAL_BOOL 483231368Sadrianar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 484231368Sadrian u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 485231368Sadrian{ 486231368Sadrian HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 487231368Sadrian 488231368Sadrian switch (type) { 489231368Sadrian case HAL_CAP_RX_CHAINMASK: 490231371Sadrian setting &= ath_hal_eepromGet(ah, AR_EEP_RXMASK, NULL); 491231368Sadrian pCap->halRxChainMask = setting; 492231368Sadrian if (owl_get_ntxchains(setting) > 2) 493231368Sadrian pCap->halRxStreams = 2; 494231368Sadrian else 495231368Sadrian pCap->halRxStreams = 1; 496231864Sadrian return AH_TRUE; 497231368Sadrian case HAL_CAP_TX_CHAINMASK: 498231371Sadrian setting &= ath_hal_eepromGet(ah, AR_EEP_TXMASK, NULL); 499231368Sadrian pCap->halTxChainMask = setting; 500231368Sadrian if (owl_get_ntxchains(setting) > 2) 501231368Sadrian pCap->halTxStreams = 2; 502231368Sadrian else 503231368Sadrian pCap->halTxStreams = 1; 504231864Sadrian return AH_TRUE; 505243743Sadrian case HAL_CAP_ENFORCE_TXOP: 506250841Sadrian if (capability != 1) 507250856Sadrian return AH_FALSE; 508243743Sadrian if (setting) { 509243743Sadrian AH5212(ah)->ah_miscMode 510243743Sadrian |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 511243743Sadrian OS_REG_SET_BIT(ah, AR_MISC_MODE, 512243743Sadrian AR_PCU_TXOP_TBTT_LIMIT_ENA); 513243743Sadrian } else { 514243743Sadrian AH5212(ah)->ah_miscMode 515243743Sadrian &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 516243743Sadrian OS_REG_CLR_BIT(ah, AR_MISC_MODE, 517243743Sadrian AR_PCU_TXOP_TBTT_LIMIT_ENA); 518243743Sadrian } 519243743Sadrian return AH_TRUE; 520231368Sadrian default: 521231368Sadrian break; 522231368Sadrian } 523231368Sadrian return ar5212SetCapability(ah, type, capability, setting, status); 524231368Sadrian} 525231368Sadrian 526185377Ssamstatic int ar5416DetectMacHang(struct ath_hal *ah); 527185377Ssamstatic int ar5416DetectBBHang(struct ath_hal *ah); 528185377Ssam 529185377SsamHAL_BOOL 530185377Ssamar5416GetDiagState(struct ath_hal *ah, int request, 531185377Ssam const void *args, uint32_t argsize, 532185377Ssam void **result, uint32_t *resultsize) 533185377Ssam{ 534185377Ssam struct ath_hal_5416 *ahp = AH5416(ah); 535185377Ssam int hangs; 536185377Ssam 537185377Ssam if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 538185377Ssam return AH_TRUE; 539185377Ssam switch (request) { 540185377Ssam case HAL_DIAG_EEPROM: 541185377Ssam return ath_hal_eepromDiag(ah, request, 542185377Ssam args, argsize, result, resultsize); 543185377Ssam case HAL_DIAG_CHECK_HANGS: 544185377Ssam if (argsize != sizeof(int)) 545185377Ssam return AH_FALSE; 546185377Ssam hangs = *(const int *) args; 547185377Ssam ahp->ah_hangs = 0; 548185377Ssam if (hangs & HAL_BB_HANGS) 549185377Ssam ahp->ah_hangs |= ar5416DetectBBHang(ah); 550185380Ssam /* NB: if BB is hung MAC will be hung too so skip check */ 551185377Ssam if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 552185377Ssam ahp->ah_hangs |= ar5416DetectMacHang(ah); 553185377Ssam *result = &ahp->ah_hangs; 554185377Ssam *resultsize = sizeof(ahp->ah_hangs); 555185377Ssam return AH_TRUE; 556185377Ssam } 557185377Ssam return ar5212GetDiagState(ah, request, 558185377Ssam args, argsize, result, resultsize); 559185377Ssam} 560185377Ssam 561221535SadrianHAL_BOOL 562221878Sadrianar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, 563221878Sadrian HAL_BOOL enable) 564221535Sadrian{ 565221535Sadrian uint32_t val; 566221878Sadrian HAL_BOOL is_chan_2g = AH_FALSE; 567221878Sadrian HAL_BOOL is_ht40 = AH_FALSE; 568221535Sadrian 569221878Sadrian if (chan) 570221878Sadrian is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan); 571221878Sadrian 572221878Sadrian if (chan) 573221878Sadrian is_ht40 = IEEE80211_IS_CHAN_HT40(chan); 574221878Sadrian 575221535Sadrian /* Only support disabling RIFS delay for now */ 576221535Sadrian HALASSERT(enable == AH_FALSE); 577221535Sadrian 578221535Sadrian if (enable == AH_TRUE) 579221535Sadrian return AH_FALSE; 580221535Sadrian 581221535Sadrian /* Change RIFS init delay to 0 */ 582221535Sadrian val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 583221535Sadrian val &= ~AR_PHY_RIFS_INIT_DELAY; 584221535Sadrian OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 585221535Sadrian 586221878Sadrian /* 587221878Sadrian * For Owl, RIFS RX parameters are controlled differently; 588221878Sadrian * it isn't enabled in the inivals by default. 589221878Sadrian * 590221878Sadrian * For Sowl/Howl, RIFS RX is enabled in the inivals by default; 591221878Sadrian * the following code sets them back to non-RIFS values. 592221878Sadrian * 593221878Sadrian * For > Sowl/Howl, RIFS RX can be left on by default and so 594221878Sadrian * this function shouldn't be called. 595221878Sadrian */ 596221878Sadrian if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah))) 597221878Sadrian return AH_TRUE; 598221878Sadrian 599221878Sadrian /* Reset search delay to default values */ 600221878Sadrian if (is_chan_2g) 601221878Sadrian if (is_ht40) 602221878Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268); 603221878Sadrian else 604221878Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134); 605221878Sadrian else 606221878Sadrian if (is_ht40) 607221878Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370); 608221878Sadrian else 609221878Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8); 610221878Sadrian 611221535Sadrian return AH_TRUE; 612221535Sadrian} 613221535Sadrian 614185377Ssamstatic HAL_BOOL 615185377Ssamar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 616185377Ssam const hal_mac_hang_check_t *check) 617185377Ssam{ 618185377Ssam int found_states; 619185377Ssam 620185377Ssam found_states = 0; 621185377Ssam if (check->states & dcu_chain_state) { 622185377Ssam int i; 623185377Ssam 624185377Ssam for (i = 0; i < 6; i++) { 625185377Ssam if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 626185377Ssam check->dcu_chain_state) 627185377Ssam found_states |= dcu_chain_state; 628185377Ssam } 629185377Ssam for (i = 0; i < 4; i++) { 630185377Ssam if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 631185377Ssam check->dcu_chain_state) 632185377Ssam found_states |= dcu_chain_state; 633185377Ssam } 634185377Ssam } 635185377Ssam if (check->states & dcu_complete_state) { 636185377Ssam if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 637185377Ssam found_states |= dcu_complete_state; 638185377Ssam } 639185377Ssam if (check->states & qcu_stitch_state) { 640185377Ssam if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 641185377Ssam found_states |= qcu_stitch_state; 642185377Ssam } 643185377Ssam if (check->states & qcu_fetch_state) { 644185377Ssam if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 645185377Ssam found_states |= qcu_fetch_state; 646185377Ssam } 647185377Ssam if (check->states & qcu_complete_state) { 648185377Ssam if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 649185377Ssam found_states |= qcu_complete_state; 650185377Ssam } 651185377Ssam return (found_states == check->states); 652185377Ssam} 653185377Ssam 654185377Ssam#define NUM_STATUS_READS 50 655185377Ssam 656185377Ssamstatic int 657185377Ssamar5416DetectMacHang(struct ath_hal *ah) 658185377Ssam{ 659185377Ssam static const hal_mac_hang_check_t hang_sig1 = { 660185377Ssam .dcu_chain_state = 0x6, 661185377Ssam .dcu_complete_state = 0x1, 662185377Ssam .states = dcu_chain_state 663185377Ssam | dcu_complete_state, 664185377Ssam }; 665185377Ssam static const hal_mac_hang_check_t hang_sig2 = { 666185377Ssam .qcu_stitch_state = 0x9, 667185377Ssam .qcu_fetch_state = 0x8, 668185377Ssam .qcu_complete_state = 0x4, 669185377Ssam .states = qcu_stitch_state 670185377Ssam | qcu_fetch_state 671185377Ssam | qcu_complete_state, 672185377Ssam }; 673185377Ssam mac_dbg_regs_t mac_dbg; 674185377Ssam int i; 675185377Ssam 676185377Ssam mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 677185377Ssam mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 678185377Ssam mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 679185377Ssam mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 680185377Ssam for (i = 1; i <= NUM_STATUS_READS; i++) { 681185377Ssam if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 682185377Ssam mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 683185377Ssam mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 684185377Ssam mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 685185377Ssam return 0; 686185377Ssam } 687185377Ssam 688185377Ssam if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 689185377Ssam return HAL_MAC_HANG_SIG1; 690185377Ssam if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 691185377Ssam return HAL_MAC_HANG_SIG2; 692185377Ssam 693221580Sadrian HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 694185377Ssam "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 695185377Ssam __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 696185377Ssam mac_dbg.dma_dbg_6); 697185377Ssam 698221582Sadrian return 0; 699185377Ssam} 700185377Ssam 701185377Ssam/* 702185377Ssam * Determine if the baseband using the Observation Bus Register 703185377Ssam */ 704185377Ssamstatic int 705185377Ssamar5416DetectBBHang(struct ath_hal *ah) 706185377Ssam{ 707185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 708185377Ssam /* 709185377Ssam * Check the PCU Observation Bus 1 register (0x806c) 710185377Ssam * NUM_STATUS_READS times 711185377Ssam * 712185377Ssam * 4 known BB hang signatures - 713185377Ssam * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 714185377Ssam * [2] bits 8,9 are 1, bit 11 is 0. State machine state 715185377Ssam * (bits 25-31) is 0x52 716185377Ssam * [3] bits 8,9 are 1, bit 11 is 0. State machine state 717185377Ssam * (bits 25-31) is 0x18 718185377Ssam * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 719185377Ssam * Rx State (bits 20-24) is 0x7. 720185377Ssam */ 721185377Ssam static const struct { 722185377Ssam uint32_t val; 723185377Ssam uint32_t mask; 724185377Ssam int code; 725185377Ssam } hang_list[] = { 726185377Ssam /* Reg Value Reg Mask Hang Code XXX */ 727185377Ssam { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 728185377Ssam { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 729185377Ssam { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 730185377Ssam { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 731185377Ssam }; 732185377Ssam uint32_t hang_sig; 733185377Ssam int i; 734185377Ssam 735185377Ssam hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 736185377Ssam for (i = 1; i <= NUM_STATUS_READS; i++) { 737185377Ssam if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 738185377Ssam return 0; 739185377Ssam } 740185377Ssam for (i = 0; i < N(hang_list); i++) 741185377Ssam if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 742221580Sadrian HALDEBUG(ah, HAL_DEBUG_HANG, 743185377Ssam "%s BB hang, signature 0x%x, code 0x%x\n", 744185377Ssam __func__, hang_sig, hang_list[i].code); 745185377Ssam return hang_list[i].code; 746185377Ssam } 747185377Ssam 748221580Sadrian HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 749185377Ssam "<0x806c>=0x%x\n", __func__, hang_sig); 750185377Ssam 751221582Sadrian return 0; 752185377Ssam#undef N 753185377Ssam} 754185377Ssam#undef NUM_STATUS_READS 755