ata-all.h revision 287016
1259698Sdim/*- 2259698Sdim * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3259698Sdim * All rights reserved. 4259698Sdim * 5259698Sdim * Redistribution and use in source and binary forms, with or without 6259698Sdim * modification, are permitted provided that the following conditions 7259698Sdim * are met: 8259698Sdim * 1. Redistributions of source code must retain the above copyright 9259698Sdim * notice, this list of conditions and the following disclaimer, 10259698Sdim * without modification, immediately at the beginning of the file. 11259698Sdim * 2. Redistributions in binary form must reproduce the above copyright 12259698Sdim * notice, this list of conditions and the following disclaimer in the 13259698Sdim * documentation and/or other materials provided with the distribution. 14259698Sdim * 15259698Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16259698Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17259698Sdim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18259698Sdim * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19259698Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20259698Sdim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21259698Sdim * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22259698Sdim * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23259698Sdim * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24259698Sdim * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25259698Sdim * 26259698Sdim * $FreeBSD: stable/10/sys/dev/ata/ata-all.h 287016 2015-08-22 07:32:47Z mav $ 27259698Sdim */ 28259698Sdim 29259698Sdim#if 0 30259698Sdim#define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 31259698Sdim * some modern devices */ 32259698Sdim#endif 33259698Sdim 34259698Sdim/* ATA register defines */ 35259698Sdim#define ATA_DATA 0 /* (RW) data */ 36259698Sdim 37259698Sdim#define ATA_FEATURE 1 /* (W) feature */ 38259698Sdim#define ATA_F_DMA 0x01 /* enable DMA */ 39259698Sdim#define ATA_F_OVL 0x02 /* enable overlap */ 40259698Sdim 41259698Sdim#define ATA_COUNT 2 /* (W) sector count */ 42259698Sdim 43259698Sdim#define ATA_SECTOR 3 /* (RW) sector # */ 44259698Sdim#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 45259698Sdim#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 46259698Sdim#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 47259698Sdim#define ATA_D_LBA 0x40 /* use LBA addressing */ 48259698Sdim#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 49259698Sdim 50259698Sdim#define ATA_COMMAND 7 /* (W) command */ 51259698Sdim 52259698Sdim#define ATA_ERROR 8 /* (R) error */ 53259698Sdim#define ATA_E_ILI 0x01 /* illegal length */ 54259698Sdim#define ATA_E_NM 0x02 /* no media */ 55259698Sdim#define ATA_E_ABORT 0x04 /* command aborted */ 56259698Sdim#define ATA_E_MCR 0x08 /* media change request */ 57259698Sdim#define ATA_E_IDNF 0x10 /* ID not found */ 58259698Sdim#define ATA_E_MC 0x20 /* media changed */ 59259698Sdim#define ATA_E_UNC 0x40 /* uncorrectable data */ 60259698Sdim#define ATA_E_ICRC 0x80 /* UDMA crc error */ 61259698Sdim#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 62259698Sdim 63259698Sdim#define ATA_IREASON 9 /* (R) interrupt reason */ 64259698Sdim#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 65259698Sdim#define ATA_I_IN 0x02 /* read (1) | write (0) */ 66259698Sdim#define ATA_I_RELEASE 0x04 /* released bus (1) */ 67259698Sdim#define ATA_I_TAGMASK 0xf8 /* tag mask */ 68259698Sdim 69259698Sdim#define ATA_STATUS 10 /* (R) status */ 70259698Sdim#define ATA_ALTSTAT 11 /* (R) alternate status */ 71259698Sdim#define ATA_S_ERROR 0x01 /* error */ 72259698Sdim#define ATA_S_INDEX 0x02 /* index */ 73259698Sdim#define ATA_S_CORR 0x04 /* data corrected */ 74259698Sdim#define ATA_S_DRQ 0x08 /* data request */ 75259698Sdim#define ATA_S_DSC 0x10 /* drive seek completed */ 76259698Sdim#define ATA_S_SERVICE 0x10 /* drive needs service */ 77259698Sdim#define ATA_S_DWF 0x20 /* drive write fault */ 78259698Sdim#define ATA_S_DMA 0x20 /* DMA ready */ 79259698Sdim#define ATA_S_READY 0x40 /* drive ready */ 80259698Sdim#define ATA_S_BUSY 0x80 /* busy */ 81259698Sdim 82259698Sdim#define ATA_CONTROL 12 /* (W) control */ 83259698Sdim 84259698Sdim#define ATA_CTLOFFSET 0x206 /* control register offset */ 85259698Sdim#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 86259698Sdim#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 87259698Sdim#define ATA_A_IDS 0x02 /* disable interrupts */ 88259698Sdim#define ATA_A_RESET 0x04 /* RESET controller */ 89259698Sdim#ifdef ATA_LEGACY_SUPPORT 90259698Sdim#define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 91259698Sdim#else 92259698Sdim#define ATA_A_4BIT 0x00 93259698Sdim#endif 94259698Sdim#define ATA_A_HOB 0x80 /* High Order Byte enable */ 95259698Sdim 96259698Sdim/* SATA register defines */ 97259698Sdim#define ATA_SSTATUS 13 98259698Sdim#define ATA_SS_DET_MASK 0x0000000f 99259698Sdim#define ATA_SS_DET_NO_DEVICE 0x00000000 100259698Sdim#define ATA_SS_DET_DEV_PRESENT 0x00000001 101259698Sdim#define ATA_SS_DET_PHY_ONLINE 0x00000003 102259698Sdim#define ATA_SS_DET_PHY_OFFLINE 0x00000004 103259698Sdim 104259698Sdim#define ATA_SS_SPD_MASK 0x000000f0 105259698Sdim#define ATA_SS_SPD_NO_SPEED 0x00000000 106259698Sdim#define ATA_SS_SPD_GEN1 0x00000010 107259698Sdim#define ATA_SS_SPD_GEN2 0x00000020 108259698Sdim#define ATA_SS_SPD_GEN3 0x00000030 109259698Sdim 110259698Sdim#define ATA_SS_IPM_MASK 0x00000f00 111259698Sdim#define ATA_SS_IPM_NO_DEVICE 0x00000000 112259698Sdim#define ATA_SS_IPM_ACTIVE 0x00000100 113259698Sdim#define ATA_SS_IPM_PARTIAL 0x00000200 114259698Sdim#define ATA_SS_IPM_SLUMBER 0x00000600 115259698Sdim 116259698Sdim#define ATA_SERROR 14 117259698Sdim#define ATA_SE_DATA_CORRECTED 0x00000001 118259698Sdim#define ATA_SE_COMM_CORRECTED 0x00000002 119#define ATA_SE_DATA_ERR 0x00000100 120#define ATA_SE_COMM_ERR 0x00000200 121#define ATA_SE_PROT_ERR 0x00000400 122#define ATA_SE_HOST_ERR 0x00000800 123#define ATA_SE_PHY_CHANGED 0x00010000 124#define ATA_SE_PHY_IERROR 0x00020000 125#define ATA_SE_COMM_WAKE 0x00040000 126#define ATA_SE_DECODE_ERR 0x00080000 127#define ATA_SE_PARITY_ERR 0x00100000 128#define ATA_SE_CRC_ERR 0x00200000 129#define ATA_SE_HANDSHAKE_ERR 0x00400000 130#define ATA_SE_LINKSEQ_ERR 0x00800000 131#define ATA_SE_TRANSPORT_ERR 0x01000000 132#define ATA_SE_UNKNOWN_FIS 0x02000000 133 134#define ATA_SCONTROL 15 135#define ATA_SC_DET_MASK 0x0000000f 136#define ATA_SC_DET_IDLE 0x00000000 137#define ATA_SC_DET_RESET 0x00000001 138#define ATA_SC_DET_DISABLE 0x00000004 139 140#define ATA_SC_SPD_MASK 0x000000f0 141#define ATA_SC_SPD_NO_SPEED 0x00000000 142#define ATA_SC_SPD_SPEED_GEN1 0x00000010 143#define ATA_SC_SPD_SPEED_GEN2 0x00000020 144#define ATA_SC_SPD_SPEED_GEN3 0x00000030 145 146#define ATA_SC_IPM_MASK 0x00000f00 147#define ATA_SC_IPM_NONE 0x00000000 148#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 149#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 150 151#define ATA_SACTIVE 16 152 153/* DMA register defines */ 154#define ATA_DMA_ENTRIES 256 155#define ATA_DMA_EOT 0x80000000 156 157#define ATA_BMCMD_PORT 17 158#define ATA_BMCMD_START_STOP 0x01 159#define ATA_BMCMD_WRITE_READ 0x08 160 161#define ATA_BMDEVSPEC_0 18 162#define ATA_BMSTAT_PORT 19 163#define ATA_BMSTAT_ACTIVE 0x01 164#define ATA_BMSTAT_ERROR 0x02 165#define ATA_BMSTAT_INTERRUPT 0x04 166#define ATA_BMSTAT_MASK 0x07 167#define ATA_BMSTAT_DMA_MASTER 0x20 168#define ATA_BMSTAT_DMA_SLAVE 0x40 169#define ATA_BMSTAT_DMA_SIMPLEX 0x80 170 171#define ATA_BMDEVSPEC_1 20 172#define ATA_BMDTP_PORT 21 173 174#define ATA_IDX_ADDR 22 175#define ATA_IDX_DATA 23 176#define ATA_MAX_RES 24 177 178/* misc defines */ 179#define ATA_PRIMARY 0x1f0 180#define ATA_SECONDARY 0x170 181#define ATA_PC98_BANK 0x432 182#define ATA_IOSIZE 0x08 183#define ATA_PC98_IOSIZE 0x10 184#define ATA_CTLIOSIZE 0x01 185#define ATA_BMIOSIZE 0x08 186#define ATA_PC98_BANKIOSIZE 0x01 187#define ATA_IOADDR_RID 0 188#define ATA_CTLADDR_RID 1 189#define ATA_BMADDR_RID 0x20 190#define ATA_PC98_CTLADDR_RID 8 191#define ATA_PC98_BANKADDR_RID 9 192#define ATA_IRQ_RID 0 193#define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 194#define ATA_CFA_MAGIC1 0x844A 195#define ATA_CFA_MAGIC2 0x848A 196#define ATA_CFA_MAGIC3 0x8400 197#define ATAPI_MAGIC_LSB 0x14 198#define ATAPI_MAGIC_MSB 0xeb 199#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 200#define ATAPI_P_WRITE (ATA_S_DRQ) 201#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 202#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 203#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 204#define ATAPI_P_ABORT 0 205#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 206#define ATA_OP_CONTINUES 0 207#define ATA_OP_FINISHED 1 208#define ATA_MAX_28BIT_LBA 268435455UL 209 210#ifndef ATA_REQUEST_TIMEOUT 211#define ATA_REQUEST_TIMEOUT 10 212#endif 213 214/* structure used for composite atomic operations */ 215#define MAX_COMPOSITES 32 /* u_int32_t bits */ 216struct ata_composite { 217 struct mtx lock; /* control lock */ 218 u_int32_t rd_needed; /* needed read subdisks */ 219 u_int32_t rd_done; /* done read subdisks */ 220 u_int32_t wr_needed; /* needed write subdisks */ 221 u_int32_t wr_depend; /* write depends on subdisks */ 222 u_int32_t wr_done; /* done write subdisks */ 223 struct ata_request *request[MAX_COMPOSITES]; 224 u_int32_t residual; /* bytes still to transfer */ 225 caddr_t data_1; 226 caddr_t data_2; 227}; 228 229/* structure used to queue an ATA/ATAPI request */ 230struct ata_request { 231 device_t dev; /* device handle */ 232 device_t parent; /* channel handle */ 233 int unit; /* physical unit */ 234 union { 235 struct { 236 u_int8_t command; /* command reg */ 237 u_int16_t feature; /* feature reg */ 238 u_int16_t count; /* count reg */ 239 u_int64_t lba; /* lba reg */ 240 } ata; 241 struct { 242 u_int8_t ccb[16]; /* ATAPI command block */ 243 struct atapi_sense sense; /* ATAPI request sense data */ 244 u_int8_t saved_cmd; /* ATAPI saved command */ 245 } atapi; 246 } u; 247 u_int32_t bytecount; /* bytes to transfer */ 248 u_int32_t transfersize; /* bytes pr transfer */ 249 caddr_t data; /* pointer to data buf */ 250 u_int32_t tag; /* HW tag of this request */ 251 int flags; 252#define ATA_R_CONTROL 0x00000001 253#define ATA_R_READ 0x00000002 254#define ATA_R_WRITE 0x00000004 255#define ATA_R_ATAPI 0x00000008 256#define ATA_R_DMA 0x00000010 257#define ATA_R_QUIET 0x00000020 258#define ATA_R_TIMEOUT 0x00000040 259#define ATA_R_48BIT 0x00000080 260 261#define ATA_R_ORDERED 0x00000100 262#define ATA_R_AT_HEAD 0x00000200 263#define ATA_R_REQUEUE 0x00000400 264#define ATA_R_THREAD 0x00000800 265#define ATA_R_DIRECT 0x00001000 266#define ATA_R_NEEDRESULT 0x00002000 267#define ATA_R_DATA_IN_CCB 0x00004000 268 269#define ATA_R_ATAPI16 0x00010000 270#define ATA_R_ATAPI_INTR 0x00020000 271 272#define ATA_R_DEBUG 0x10000000 273#define ATA_R_DANGER1 0x20000000 274#define ATA_R_DANGER2 0x40000000 275 276 struct ata_dmaslot *dma; /* DMA slot of this request */ 277 u_int8_t status; /* ATA status */ 278 u_int8_t error; /* ATA error */ 279 u_int32_t donecount; /* bytes transferred */ 280 int result; /* result error code */ 281 void (*callback)(struct ata_request *request); 282 struct sema done; /* request done sema */ 283 int retries; /* retry count */ 284 int timeout; /* timeout for this cmd */ 285 struct callout callout; /* callout management */ 286 struct task task; /* task management */ 287 struct bio *bio; /* bio for this request */ 288 int this; /* this request ID */ 289 struct ata_composite *composite; /* for composite atomic ops */ 290 void *driver; /* driver specific */ 291 TAILQ_ENTRY(ata_request) chain; /* list management */ 292 union ccb *ccb; 293}; 294 295/* define this for debugging request processing */ 296#if 0 297#define ATA_DEBUG_RQ(request, string) \ 298 { \ 299 if (request->flags & ATA_R_DEBUG) \ 300 device_printf(request->parent, "req=%p %s " string "\n", \ 301 request, ata_cmd2str(request)); \ 302 } 303#else 304#define ATA_DEBUG_RQ(request, string) 305#endif 306 307 308/* structure describing an ATA/ATAPI device */ 309struct ata_device { 310 device_t dev; /* device handle */ 311 int unit; /* physical unit */ 312#define ATA_MASTER 0x00 313#define ATA_SLAVE 0x01 314#define ATA_PM 0x0f 315 316 struct ata_params param; /* ata param structure */ 317 int mode; /* current transfermode */ 318 u_int32_t max_iosize; /* max IO size */ 319 int spindown; /* idle spindown timeout */ 320 struct callout spindown_timer; 321 int spindown_state; 322 int flags; 323#define ATA_D_USE_CHS 0x0001 324#define ATA_D_MEDIA_CHANGED 0x0002 325#define ATA_D_ENC_PRESENT 0x0004 326}; 327 328/* structure for holding DMA Physical Region Descriptors (PRD) entries */ 329struct ata_dma_prdentry { 330 u_int32_t addr; 331 u_int32_t count; 332}; 333 334/* structure used by the setprd function */ 335struct ata_dmasetprd_args { 336 void *dmatab; 337 int nsegs; 338 int error; 339}; 340 341struct ata_dmaslot { 342 u_int8_t status; /* DMA status */ 343 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 344 bus_dmamap_t sg_map; /* SG list DMA map */ 345 void *sg; /* DMA transfer table */ 346 bus_addr_t sg_bus; /* bus address of dmatab */ 347 bus_dma_tag_t data_tag; /* data DMA tag */ 348 bus_dmamap_t data_map; /* data DMA map */ 349}; 350 351/* structure holding DMA related information */ 352struct ata_dma { 353 bus_dma_tag_t dmatag; /* parent DMA tag */ 354 bus_dma_tag_t work_tag; /* workspace DMA tag */ 355 bus_dmamap_t work_map; /* workspace DMA map */ 356 u_int8_t *work; /* workspace */ 357 bus_addr_t work_bus; /* bus address of dmatab */ 358 359#define ATA_DMA_SLOTS 1 360 int dma_slots; /* DMA slots allocated */ 361 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 362 u_int32_t alignment; /* DMA SG list alignment */ 363 u_int32_t boundary; /* DMA SG list boundary */ 364 u_int32_t segsize; /* DMA SG list segment size */ 365 u_int32_t max_iosize; /* DMA data max IO size */ 366 u_int64_t max_address; /* highest DMA'able address */ 367 int flags; 368#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 369 370 void (*alloc)(device_t dev); 371 void (*free)(device_t dev); 372 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 373 int (*load)(struct ata_request *request, void *addr, int *nsegs); 374 int (*unload)(struct ata_request *request); 375 int (*start)(struct ata_request *request); 376 int (*stop)(struct ata_request *request); 377 void (*reset)(device_t dev); 378}; 379 380/* structure holding lowlevel functions */ 381struct ata_lowlevel { 382 u_int32_t (*softreset)(device_t dev, int pmport); 383 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 384 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 385 int (*status)(device_t dev); 386 int (*begin_transaction)(struct ata_request *request); 387 int (*end_transaction)(struct ata_request *request); 388 int (*command)(struct ata_request *request); 389 void (*tf_read)(struct ata_request *request); 390 void (*tf_write)(struct ata_request *request); 391}; 392 393/* structure holding resources for an ATA channel */ 394struct ata_resource { 395 struct resource *res; 396 int offset; 397}; 398 399struct ata_cam_device { 400 u_int revision; 401 int mode; 402 u_int bytecount; 403 u_int atapi; 404 u_int caps; 405}; 406 407/* structure describing an ATA channel */ 408struct ata_channel { 409 device_t dev; /* device handle */ 410 int unit; /* physical channel */ 411 int attached; /* channel is attached */ 412 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 413 struct resource *r_irq; /* interrupt of this channel */ 414 void *ih; /* interrupt handle */ 415 struct ata_lowlevel hw; /* lowlevel HW functions */ 416 struct ata_dma dma; /* DMA data / functions */ 417 int flags; /* channel flags */ 418#define ATA_NO_SLAVE 0x01 419#define ATA_USE_16BIT 0x02 420#define ATA_ATAPI_DMA_RO 0x04 421#define ATA_NO_48BIT_DMA 0x08 422#define ATA_ALWAYS_DMASTAT 0x10 423#define ATA_CHECKS_CABLE 0x20 424#define ATA_NO_ATAPI_DMA 0x40 425#define ATA_SATA 0x80 426#define ATA_DMA_BEFORE_CMD 0x100 427#define ATA_KNOWN_PRESENCE 0x200 428#define ATA_STATUS_IS_LONG 0x400 429#define ATA_PERIODIC_POLL 0x800 430 431 int pm_level; /* power management level */ 432 int devices; /* what is present */ 433#define ATA_ATA_MASTER 0x00000001 434#define ATA_ATA_SLAVE 0x00000002 435#define ATA_PORTMULTIPLIER 0x00008000 436#define ATA_ATAPI_MASTER 0x00010000 437#define ATA_ATAPI_SLAVE 0x00020000 438 439 struct mtx state_mtx; /* state lock */ 440 int state; /* ATA channel state */ 441#define ATA_IDLE 0x0000 442#define ATA_ACTIVE 0x0001 443#define ATA_STALL_QUEUE 0x0002 444 445 struct ata_request *running; /* currently running request */ 446 struct task conntask; /* PHY events handling task */ 447 struct cam_sim *sim; 448 struct cam_path *path; 449 struct ata_cam_device user[16]; /* User-specified settings */ 450 struct ata_cam_device curr[16]; /* Current settings */ 451 int requestsense; /* CCB waiting for SENSE. */ 452 struct callout poll_callout; /* Periodic status poll. */ 453}; 454 455/* disk bay/enclosure related */ 456#define ATA_LED_OFF 0x00 457#define ATA_LED_RED 0x01 458#define ATA_LED_GREEN 0x02 459#define ATA_LED_ORANGE 0x03 460#define ATA_LED_MASK 0x03 461 462/* externs */ 463extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 464extern struct intr_config_hook *ata_delayed_attach; 465extern devclass_t ata_devclass; 466extern int ata_wc; 467extern int ata_setmax; 468extern int ata_dma_check_80pin; 469 470/* public prototypes */ 471/* ata-all.c: */ 472int ata_probe(device_t dev); 473int ata_attach(device_t dev); 474int ata_detach(device_t dev); 475int ata_reinit(device_t dev); 476int ata_suspend(device_t dev); 477int ata_resume(device_t dev); 478void ata_interrupt(void *data); 479int ata_getparam(struct ata_device *atadev, int init); 480void ata_default_registers(device_t dev); 481void ata_udelay(int interval); 482const char *ata_cmd2str(struct ata_request *request); 483const char *ata_mode2str(int mode); 484void ata_setmode(device_t dev); 485void ata_print_cable(device_t dev, u_int8_t *who); 486int ata_atapi(device_t dev, int target); 487void ata_timeout(struct ata_request *); 488 489/* ata-lowlevel.c: */ 490void ata_generic_hw(device_t dev); 491int ata_begin_transaction(struct ata_request *); 492int ata_end_transaction(struct ata_request *); 493void ata_generic_reset(device_t dev); 494int ata_generic_command(struct ata_request *request); 495 496/* ata-dma.c: */ 497void ata_dmainit(device_t); 498void ata_dmafini(device_t dev); 499 500/* ata-sata.c: */ 501void ata_sata_phy_check_events(device_t dev, int port); 502int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 503int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 504int ata_sata_phy_reset(device_t dev, int port, int quick); 505int ata_sata_setmode(device_t dev, int target, int mode); 506int ata_sata_getrev(device_t dev, int target); 507int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 508void ata_pm_identify(device_t dev); 509 510/* macros for alloc/free of struct ata_request */ 511extern uma_zone_t ata_request_zone; 512#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 513#define ata_free_request(request) { \ 514 if (!(request->flags & ATA_R_DANGER2)) \ 515 uma_zfree(ata_request_zone, request); \ 516 } 517 518MALLOC_DECLARE(M_ATA); 519 520/* misc newbus defines */ 521#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 522 523/* macros to hide busspace uglyness */ 524#define ATA_INB(res, offset) \ 525 bus_read_1((res), (offset)) 526 527#define ATA_INW(res, offset) \ 528 bus_read_2((res), (offset)) 529#define ATA_INW_STRM(res, offset) \ 530 bus_read_stream_2((res), (offset)) 531#define ATA_INL(res, offset) \ 532 bus_read_4((res), (offset)) 533#define ATA_INSW(res, offset, addr, count) \ 534 bus_read_multi_2((res), (offset), (addr), (count)) 535#define ATA_INSW_STRM(res, offset, addr, count) \ 536 bus_read_multi_stream_2((res), (offset), (addr), (count)) 537#define ATA_INSL(res, offset, addr, count) \ 538 bus_read_multi_4((res), (offset), (addr), (count)) 539#define ATA_INSL_STRM(res, offset, addr, count) \ 540 bus_read_multi_stream_4((res), (offset), (addr), (count)) 541#define ATA_OUTB(res, offset, value) \ 542 bus_write_1((res), (offset), (value)) 543#define ATA_OUTW(res, offset, value) \ 544 bus_write_2((res), (offset), (value)) 545#define ATA_OUTW_STRM(res, offset, value) \ 546 bus_write_stream_2((res), (offset), (value)) 547#define ATA_OUTL(res, offset, value) \ 548 bus_write_4((res), (offset), (value)) 549#define ATA_OUTSW(res, offset, addr, count) \ 550 bus_write_multi_2((res), (offset), (addr), (count)) 551#define ATA_OUTSW_STRM(res, offset, addr, count) \ 552 bus_write_multi_stream_2((res), (offset), (addr), (count)) 553#define ATA_OUTSL(res, offset, addr, count) \ 554 bus_write_multi_4((res), (offset), (addr), (count)) 555#define ATA_OUTSL_STRM(res, offset, addr, count) \ 556 bus_write_multi_stream_4((res), (offset), (addr), (count)) 557 558#define ATA_IDX_INB(ch, idx) \ 559 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 560 561#define ATA_IDX_INW(ch, idx) \ 562 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 563 564#define ATA_IDX_INW_STRM(ch, idx) \ 565 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 566 567#define ATA_IDX_INL(ch, idx) \ 568 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 569 570#define ATA_IDX_INSW(ch, idx, addr, count) \ 571 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 572 573#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 574 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 575 576#define ATA_IDX_INSL(ch, idx, addr, count) \ 577 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 578 579#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 580 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 581 582#define ATA_IDX_OUTB(ch, idx, value) \ 583 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 584 585#define ATA_IDX_OUTW(ch, idx, value) \ 586 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 587 588#define ATA_IDX_OUTW_STRM(ch, idx, value) \ 589 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 590 591#define ATA_IDX_OUTL(ch, idx, value) \ 592 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 593 594#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 595 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 596 597#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 598 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 599 600#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 601 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 602 603#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 604 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 605