arcmsr.c revision 315813
1/* 2******************************************************************************** 3** OS : FreeBSD 4** FILE NAME : arcmsr.c 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8** SATA/SAS RAID HOST Adapter 9******************************************************************************** 10******************************************************************************** 11** 12** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13** 14** Redistribution and use in source and binary forms, with or without 15** modification, are permitted provided that the following conditions 16** are met: 17** 1. Redistributions of source code must retain the above copyright 18** notice, this list of conditions and the following disclaimer. 19** 2. Redistributions in binary form must reproduce the above copyright 20** notice, this list of conditions and the following disclaimer in the 21** documentation and/or other materials provided with the distribution. 22** 3. The name of the author may not be used to endorse or promote products 23** derived from this software without specific prior written permission. 24** 25** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35******************************************************************************** 36** History 37** 38** REV# DATE NAME DESCRIPTION 39** 1.00.00.00 03/31/2004 Erich Chen First release 40** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42** clean unused function 43** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44** firmware version check 45** and firmware update notify for hardware bug fix 46** handling if none zero high part physical address 47** of srb resource 48** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49** add iop message xfer 50** with scsi pass-through command 51** add new device id of sas raid adapters 52** code fit for SPARC64 & PPC 53** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54** and cause g_vfs_done() read write error 55** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57** bus_dmamem_alloc() with BUS_DMA_ZERO 58** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60** prevent cam_periph_error removing all LUN devices of one Target id 61** for any one LUN device failed 62** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67** 02/14/2011 Ching Huang Modified pktRequestCount 68** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 76** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 77** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 78** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 79** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 80****************************************************************************************** 81*/ 82 83#include <sys/cdefs.h> 84__FBSDID("$FreeBSD: stable/10/sys/dev/arcmsr/arcmsr.c 315813 2017-03-23 06:41:13Z mav $"); 85 86#if 0 87#define ARCMSR_DEBUG1 1 88#endif 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/bus.h> 94#include <sys/queue.h> 95#include <sys/stat.h> 96#include <sys/devicestat.h> 97#include <sys/kthread.h> 98#include <sys/module.h> 99#include <sys/proc.h> 100#include <sys/lock.h> 101#include <sys/sysctl.h> 102#include <sys/poll.h> 103#include <sys/ioccom.h> 104#include <vm/vm.h> 105#include <vm/vm_param.h> 106#include <vm/pmap.h> 107 108#include <isa/rtc.h> 109 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <machine/atomic.h> 113#include <sys/conf.h> 114#include <sys/rman.h> 115 116#include <cam/cam.h> 117#include <cam/cam_ccb.h> 118#include <cam/cam_sim.h> 119#include <cam/cam_periph.h> 120#include <cam/cam_xpt_periph.h> 121#include <cam/cam_xpt_sim.h> 122#include <cam/cam_debug.h> 123#include <cam/scsi/scsi_all.h> 124#include <cam/scsi/scsi_message.h> 125/* 126************************************************************************** 127************************************************************************** 128*/ 129#if __FreeBSD_version >= 500005 130 #include <sys/selinfo.h> 131 #include <sys/mutex.h> 132 #include <sys/endian.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcireg.h> 135#else 136 #include <sys/select.h> 137 #include <pci/pcivar.h> 138 #include <pci/pcireg.h> 139#endif 140 141#if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 142#define CAM_NEW_TRAN_CODE 1 143#endif 144 145#if __FreeBSD_version > 500000 146#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 147#else 148#define arcmsr_callout_init(a) callout_init(a); 149#endif 150 151#define ARCMSR_DRIVER_VERSION "arcmsr version 1.30.00.00 2015-11-30" 152#include <dev/arcmsr/arcmsr.h> 153/* 154************************************************************************** 155************************************************************************** 156*/ 157static void arcmsr_free_srb(struct CommandControlBlock *srb); 158static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 159static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 160static int arcmsr_probe(device_t dev); 161static int arcmsr_attach(device_t dev); 162static int arcmsr_detach(device_t dev); 163static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 164static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 165static int arcmsr_shutdown(device_t dev); 166static void arcmsr_interrupt(struct AdapterControlBlock *acb); 167static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 168static void arcmsr_free_resource(struct AdapterControlBlock *acb); 169static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 170static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 171static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 172static void arcmsr_iop_init(struct AdapterControlBlock *acb); 173static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 174static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 175static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 176static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 177static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 178static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 179static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 180static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 181static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 182static int arcmsr_resume(device_t dev); 183static int arcmsr_suspend(device_t dev); 184static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 185static void arcmsr_polling_devmap(void *arg); 186static void arcmsr_srb_timeout(void *arg); 187static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 188#ifdef ARCMSR_DEBUG1 189static void arcmsr_dump_data(struct AdapterControlBlock *acb); 190#endif 191/* 192************************************************************************** 193************************************************************************** 194*/ 195static void UDELAY(u_int32_t us) { DELAY(us); } 196/* 197************************************************************************** 198************************************************************************** 199*/ 200static bus_dmamap_callback_t arcmsr_map_free_srb; 201static bus_dmamap_callback_t arcmsr_execute_srb; 202/* 203************************************************************************** 204************************************************************************** 205*/ 206static d_open_t arcmsr_open; 207static d_close_t arcmsr_close; 208static d_ioctl_t arcmsr_ioctl; 209 210static device_method_t arcmsr_methods[]={ 211 DEVMETHOD(device_probe, arcmsr_probe), 212 DEVMETHOD(device_attach, arcmsr_attach), 213 DEVMETHOD(device_detach, arcmsr_detach), 214 DEVMETHOD(device_shutdown, arcmsr_shutdown), 215 DEVMETHOD(device_suspend, arcmsr_suspend), 216 DEVMETHOD(device_resume, arcmsr_resume), 217 218#if __FreeBSD_version >= 803000 219 DEVMETHOD_END 220#else 221 { 0, 0 } 222#endif 223}; 224 225static driver_t arcmsr_driver={ 226 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 227}; 228 229static devclass_t arcmsr_devclass; 230DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 231MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 232MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 233#ifndef BUS_DMA_COHERENT 234 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 235#endif 236#if __FreeBSD_version >= 501000 237static struct cdevsw arcmsr_cdevsw={ 238 #if __FreeBSD_version >= 503000 239 .d_version = D_VERSION, 240 #endif 241 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 242 .d_flags = D_NEEDGIANT, 243 #endif 244 .d_open = arcmsr_open, /* open */ 245 .d_close = arcmsr_close, /* close */ 246 .d_ioctl = arcmsr_ioctl, /* ioctl */ 247 .d_name = "arcmsr", /* name */ 248 }; 249#else 250 #define ARCMSR_CDEV_MAJOR 180 251 252static struct cdevsw arcmsr_cdevsw = { 253 arcmsr_open, /* open */ 254 arcmsr_close, /* close */ 255 noread, /* read */ 256 nowrite, /* write */ 257 arcmsr_ioctl, /* ioctl */ 258 nopoll, /* poll */ 259 nommap, /* mmap */ 260 nostrategy, /* strategy */ 261 "arcmsr", /* name */ 262 ARCMSR_CDEV_MAJOR, /* major */ 263 nodump, /* dump */ 264 nopsize, /* psize */ 265 0 /* flags */ 266 }; 267#endif 268/* 269************************************************************************** 270************************************************************************** 271*/ 272#if __FreeBSD_version < 500005 273 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 274#else 275 #if __FreeBSD_version < 503000 276 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 277 #else 278 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 279 #endif 280#endif 281{ 282 #if __FreeBSD_version < 503000 283 struct AdapterControlBlock *acb = dev->si_drv1; 284 #else 285 int unit = dev2unit(dev); 286 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 287 #endif 288 if(acb == NULL) { 289 return ENXIO; 290 } 291 return (0); 292} 293/* 294************************************************************************** 295************************************************************************** 296*/ 297#if __FreeBSD_version < 500005 298 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 299#else 300 #if __FreeBSD_version < 503000 301 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 302 #else 303 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 304 #endif 305#endif 306{ 307 #if __FreeBSD_version < 503000 308 struct AdapterControlBlock *acb = dev->si_drv1; 309 #else 310 int unit = dev2unit(dev); 311 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 312 #endif 313 if(acb == NULL) { 314 return ENXIO; 315 } 316 return 0; 317} 318/* 319************************************************************************** 320************************************************************************** 321*/ 322#if __FreeBSD_version < 500005 323 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 324#else 325 #if __FreeBSD_version < 503000 326 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 327 #else 328 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 329 #endif 330#endif 331{ 332 #if __FreeBSD_version < 503000 333 struct AdapterControlBlock *acb = dev->si_drv1; 334 #else 335 int unit = dev2unit(dev); 336 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 337 #endif 338 339 if(acb == NULL) { 340 return ENXIO; 341 } 342 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 343} 344/* 345********************************************************************** 346********************************************************************** 347*/ 348static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 349{ 350 u_int32_t intmask_org = 0; 351 352 switch (acb->adapter_type) { 353 case ACB_ADAPTER_TYPE_A: { 354 /* disable all outbound interrupt */ 355 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 356 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 357 } 358 break; 359 case ACB_ADAPTER_TYPE_B: { 360 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 361 /* disable all outbound interrupt */ 362 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 363 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 364 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 365 } 366 break; 367 case ACB_ADAPTER_TYPE_C: { 368 /* disable all outbound interrupt */ 369 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 370 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 371 } 372 break; 373 case ACB_ADAPTER_TYPE_D: { 374 /* disable all outbound interrupt */ 375 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 376 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 377 } 378 break; 379 } 380 return (intmask_org); 381} 382/* 383********************************************************************** 384********************************************************************** 385*/ 386static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 387{ 388 u_int32_t mask; 389 390 switch (acb->adapter_type) { 391 case ACB_ADAPTER_TYPE_A: { 392 /* enable outbound Post Queue, outbound doorbell Interrupt */ 393 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 394 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 395 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 396 } 397 break; 398 case ACB_ADAPTER_TYPE_B: { 399 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 400 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 401 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 402 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 403 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 404 } 405 break; 406 case ACB_ADAPTER_TYPE_C: { 407 /* enable outbound Post Queue, outbound doorbell Interrupt */ 408 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 410 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 411 } 412 break; 413 case ACB_ADAPTER_TYPE_D: { 414 /* enable outbound Post Queue, outbound doorbell Interrupt */ 415 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 416 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 417 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 418 acb->outbound_int_enable = mask; 419 } 420 break; 421 } 422} 423/* 424********************************************************************** 425********************************************************************** 426*/ 427static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 428{ 429 u_int32_t Index; 430 u_int8_t Retries = 0x00; 431 432 do { 433 for(Index=0; Index < 100; Index++) { 434 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 435 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 436 return TRUE; 437 } 438 UDELAY(10000); 439 }/*max 1 seconds*/ 440 }while(Retries++ < 20);/*max 20 sec*/ 441 return (FALSE); 442} 443/* 444********************************************************************** 445********************************************************************** 446*/ 447static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 448{ 449 u_int32_t Index; 450 u_int8_t Retries = 0x00; 451 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 452 453 do { 454 for(Index=0; Index < 100; Index++) { 455 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 456 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 457 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 458 return TRUE; 459 } 460 UDELAY(10000); 461 }/*max 1 seconds*/ 462 }while(Retries++ < 20);/*max 20 sec*/ 463 return (FALSE); 464} 465/* 466********************************************************************** 467********************************************************************** 468*/ 469static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 470{ 471 u_int32_t Index; 472 u_int8_t Retries = 0x00; 473 474 do { 475 for(Index=0; Index < 100; Index++) { 476 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 477 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 478 return TRUE; 479 } 480 UDELAY(10000); 481 }/*max 1 seconds*/ 482 }while(Retries++ < 20);/*max 20 sec*/ 483 return (FALSE); 484} 485/* 486********************************************************************** 487********************************************************************** 488*/ 489static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 490{ 491 u_int32_t Index; 492 u_int8_t Retries = 0x00; 493 494 do { 495 for(Index=0; Index < 100; Index++) { 496 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 497 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 498 return TRUE; 499 } 500 UDELAY(10000); 501 }/*max 1 seconds*/ 502 }while(Retries++ < 20);/*max 20 sec*/ 503 return (FALSE); 504} 505/* 506************************************************************************ 507************************************************************************ 508*/ 509static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 510{ 511 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 512 513 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 514 do { 515 if(arcmsr_hba_wait_msgint_ready(acb)) { 516 break; 517 } else { 518 retry_count--; 519 } 520 }while(retry_count != 0); 521} 522/* 523************************************************************************ 524************************************************************************ 525*/ 526static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 527{ 528 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 529 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 530 531 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 532 do { 533 if(arcmsr_hbb_wait_msgint_ready(acb)) { 534 break; 535 } else { 536 retry_count--; 537 } 538 }while(retry_count != 0); 539} 540/* 541************************************************************************ 542************************************************************************ 543*/ 544static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 545{ 546 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 547 548 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 549 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 550 do { 551 if(arcmsr_hbc_wait_msgint_ready(acb)) { 552 break; 553 } else { 554 retry_count--; 555 } 556 }while(retry_count != 0); 557} 558/* 559************************************************************************ 560************************************************************************ 561*/ 562static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 563{ 564 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 565 566 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 567 do { 568 if(arcmsr_hbd_wait_msgint_ready(acb)) { 569 break; 570 } else { 571 retry_count--; 572 } 573 }while(retry_count != 0); 574} 575/* 576************************************************************************ 577************************************************************************ 578*/ 579static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 580{ 581 switch (acb->adapter_type) { 582 case ACB_ADAPTER_TYPE_A: { 583 arcmsr_flush_hba_cache(acb); 584 } 585 break; 586 case ACB_ADAPTER_TYPE_B: { 587 arcmsr_flush_hbb_cache(acb); 588 } 589 break; 590 case ACB_ADAPTER_TYPE_C: { 591 arcmsr_flush_hbc_cache(acb); 592 } 593 break; 594 case ACB_ADAPTER_TYPE_D: { 595 arcmsr_flush_hbd_cache(acb); 596 } 597 break; 598 } 599} 600/* 601******************************************************************************* 602******************************************************************************* 603*/ 604static int arcmsr_suspend(device_t dev) 605{ 606 struct AdapterControlBlock *acb = device_get_softc(dev); 607 608 /* flush controller */ 609 arcmsr_iop_parking(acb); 610 /* disable all outbound interrupt */ 611 arcmsr_disable_allintr(acb); 612 return(0); 613} 614/* 615******************************************************************************* 616******************************************************************************* 617*/ 618static int arcmsr_resume(device_t dev) 619{ 620 struct AdapterControlBlock *acb = device_get_softc(dev); 621 622 arcmsr_iop_init(acb); 623 return(0); 624} 625/* 626********************************************************************************* 627********************************************************************************* 628*/ 629static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 630{ 631 struct AdapterControlBlock *acb; 632 u_int8_t target_id, target_lun; 633 struct cam_sim *sim; 634 635 sim = (struct cam_sim *) cb_arg; 636 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 637 switch (code) { 638 case AC_LOST_DEVICE: 639 target_id = xpt_path_target_id(path); 640 target_lun = xpt_path_lun_id(path); 641 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 642 break; 643 } 644 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 645 break; 646 default: 647 break; 648 } 649} 650/* 651********************************************************************** 652********************************************************************** 653*/ 654static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 655{ 656 union ccb *pccb = srb->pccb; 657 658 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 659 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 660 if(pccb->csio.sense_len) { 661 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 662 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 663 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 664 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 665 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 666 } 667} 668/* 669********************************************************************* 670********************************************************************* 671*/ 672static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 673{ 674 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 675 if(!arcmsr_hba_wait_msgint_ready(acb)) { 676 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 677 } 678} 679/* 680********************************************************************* 681********************************************************************* 682*/ 683static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 684{ 685 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 686 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 687 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 688 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 689 } 690} 691/* 692********************************************************************* 693********************************************************************* 694*/ 695static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 696{ 697 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 698 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 699 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 700 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 701 } 702} 703/* 704********************************************************************* 705********************************************************************* 706*/ 707static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 708{ 709 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 710 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 711 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 712 } 713} 714/* 715********************************************************************* 716********************************************************************* 717*/ 718static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 719{ 720 switch (acb->adapter_type) { 721 case ACB_ADAPTER_TYPE_A: { 722 arcmsr_abort_hba_allcmd(acb); 723 } 724 break; 725 case ACB_ADAPTER_TYPE_B: { 726 arcmsr_abort_hbb_allcmd(acb); 727 } 728 break; 729 case ACB_ADAPTER_TYPE_C: { 730 arcmsr_abort_hbc_allcmd(acb); 731 } 732 break; 733 case ACB_ADAPTER_TYPE_D: { 734 arcmsr_abort_hbd_allcmd(acb); 735 } 736 break; 737 } 738} 739/* 740********************************************************************** 741********************************************************************** 742*/ 743static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 744{ 745 struct AdapterControlBlock *acb = srb->acb; 746 union ccb *pccb = srb->pccb; 747 748 if(srb->srb_flags & SRB_FLAG_TIMER_START) 749 callout_stop(&srb->ccb_callout); 750 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 751 bus_dmasync_op_t op; 752 753 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 754 op = BUS_DMASYNC_POSTREAD; 755 } else { 756 op = BUS_DMASYNC_POSTWRITE; 757 } 758 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 759 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 760 } 761 if(stand_flag == 1) { 762 atomic_subtract_int(&acb->srboutstandingcount, 1); 763 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 764 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 765 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 766 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 767 } 768 } 769 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 770 arcmsr_free_srb(srb); 771 acb->pktReturnCount++; 772 xpt_done(pccb); 773} 774/* 775************************************************************************** 776************************************************************************** 777*/ 778static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 779{ 780 int target, lun; 781 782 target = srb->pccb->ccb_h.target_id; 783 lun = srb->pccb->ccb_h.target_lun; 784 if(error == FALSE) { 785 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 786 acb->devstate[target][lun] = ARECA_RAID_GOOD; 787 } 788 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 789 arcmsr_srb_complete(srb, 1); 790 } else { 791 switch(srb->arcmsr_cdb.DeviceStatus) { 792 case ARCMSR_DEV_SELECT_TIMEOUT: { 793 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 794 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 795 } 796 acb->devstate[target][lun] = ARECA_RAID_GONE; 797 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 798 arcmsr_srb_complete(srb, 1); 799 } 800 break; 801 case ARCMSR_DEV_ABORTED: 802 case ARCMSR_DEV_INIT_FAIL: { 803 acb->devstate[target][lun] = ARECA_RAID_GONE; 804 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 805 arcmsr_srb_complete(srb, 1); 806 } 807 break; 808 case SCSISTAT_CHECK_CONDITION: { 809 acb->devstate[target][lun] = ARECA_RAID_GOOD; 810 arcmsr_report_sense_info(srb); 811 arcmsr_srb_complete(srb, 1); 812 } 813 break; 814 default: 815 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 816 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 817 acb->devstate[target][lun] = ARECA_RAID_GONE; 818 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 819 /*unknown error or crc error just for retry*/ 820 arcmsr_srb_complete(srb, 1); 821 break; 822 } 823 } 824} 825/* 826************************************************************************** 827************************************************************************** 828*/ 829static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 830{ 831 struct CommandControlBlock *srb; 832 833 /* check if command done with no error*/ 834 switch (acb->adapter_type) { 835 case ACB_ADAPTER_TYPE_C: 836 case ACB_ADAPTER_TYPE_D: 837 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 838 break; 839 case ACB_ADAPTER_TYPE_A: 840 case ACB_ADAPTER_TYPE_B: 841 default: 842 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 843 break; 844 } 845 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 846 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 847 arcmsr_free_srb(srb); 848 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 849 return; 850 } 851 printf("arcmsr%d: return srb has been completed\n" 852 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 853 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 854 return; 855 } 856 arcmsr_report_srb_state(acb, srb, error); 857} 858/* 859************************************************************************** 860************************************************************************** 861*/ 862static void arcmsr_srb_timeout(void *arg) 863{ 864 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 865 struct AdapterControlBlock *acb; 866 int target, lun; 867 u_int8_t cmd; 868 869 target = srb->pccb->ccb_h.target_id; 870 lun = srb->pccb->ccb_h.target_lun; 871 acb = srb->acb; 872 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 873 if(srb->srb_state == ARCMSR_SRB_START) 874 { 875 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 876 srb->srb_state = ARCMSR_SRB_TIMEOUT; 877 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 878 arcmsr_srb_complete(srb, 1); 879 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 880 acb->pci_unit, target, lun, cmd, srb); 881 } 882 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 883#ifdef ARCMSR_DEBUG1 884 arcmsr_dump_data(acb); 885#endif 886} 887 888/* 889********************************************************************** 890********************************************************************** 891*/ 892static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 893{ 894 int i=0; 895 u_int32_t flag_srb; 896 u_int16_t error; 897 898 switch (acb->adapter_type) { 899 case ACB_ADAPTER_TYPE_A: { 900 u_int32_t outbound_intstatus; 901 902 /*clear and abort all outbound posted Q*/ 903 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 904 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 905 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 906 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 907 arcmsr_drain_donequeue(acb, flag_srb, error); 908 } 909 } 910 break; 911 case ACB_ADAPTER_TYPE_B: { 912 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 913 914 /*clear all outbound posted Q*/ 915 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 916 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 917 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 918 phbbmu->done_qbuffer[i] = 0; 919 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 920 arcmsr_drain_donequeue(acb, flag_srb, error); 921 } 922 phbbmu->post_qbuffer[i] = 0; 923 }/*drain reply FIFO*/ 924 phbbmu->doneq_index = 0; 925 phbbmu->postq_index = 0; 926 } 927 break; 928 case ACB_ADAPTER_TYPE_C: { 929 930 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 931 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 932 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 933 arcmsr_drain_donequeue(acb, flag_srb, error); 934 } 935 } 936 break; 937 case ACB_ADAPTER_TYPE_D: { 938 arcmsr_hbd_postqueue_isr(acb); 939 } 940 break; 941 } 942} 943/* 944**************************************************************************** 945**************************************************************************** 946*/ 947static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 948{ 949 struct CommandControlBlock *srb; 950 u_int32_t intmask_org; 951 u_int32_t i=0; 952 953 if(acb->srboutstandingcount>0) { 954 /* disable all outbound interrupt */ 955 intmask_org = arcmsr_disable_allintr(acb); 956 /*clear and abort all outbound posted Q*/ 957 arcmsr_done4abort_postqueue(acb); 958 /* talk to iop 331 outstanding command aborted*/ 959 arcmsr_abort_allcmd(acb); 960 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 961 srb = acb->psrb_pool[i]; 962 if(srb->srb_state == ARCMSR_SRB_START) { 963 srb->srb_state = ARCMSR_SRB_ABORTED; 964 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 965 arcmsr_srb_complete(srb, 1); 966 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 967 , acb->pci_unit, srb->pccb->ccb_h.target_id 968 , srb->pccb->ccb_h.target_lun, srb); 969 } 970 } 971 /* enable all outbound interrupt */ 972 arcmsr_enable_allintr(acb, intmask_org); 973 } 974 acb->srboutstandingcount = 0; 975 acb->workingsrb_doneindex = 0; 976 acb->workingsrb_startindex = 0; 977 acb->pktRequestCount = 0; 978 acb->pktReturnCount = 0; 979} 980/* 981********************************************************************** 982********************************************************************** 983*/ 984static void arcmsr_build_srb(struct CommandControlBlock *srb, 985 bus_dma_segment_t *dm_segs, u_int32_t nseg) 986{ 987 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 988 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 989 u_int32_t address_lo, address_hi; 990 union ccb *pccb = srb->pccb; 991 struct ccb_scsiio *pcsio = &pccb->csio; 992 u_int32_t arccdbsize = 0x30; 993 994 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 995 arcmsr_cdb->Bus = 0; 996 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 997 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 998 arcmsr_cdb->Function = 1; 999 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1000 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1001 if(nseg != 0) { 1002 struct AdapterControlBlock *acb = srb->acb; 1003 bus_dmasync_op_t op; 1004 u_int32_t length, i, cdb_sgcount = 0; 1005 1006 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1007 op = BUS_DMASYNC_PREREAD; 1008 } else { 1009 op = BUS_DMASYNC_PREWRITE; 1010 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1011 srb->srb_flags |= SRB_FLAG_WRITE; 1012 } 1013 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1014 for(i=0; i < nseg; i++) { 1015 /* Get the physical address of the current data pointer */ 1016 length = arcmsr_htole32(dm_segs[i].ds_len); 1017 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1018 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1019 if(address_hi == 0) { 1020 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1021 pdma_sg->address = address_lo; 1022 pdma_sg->length = length; 1023 psge += sizeof(struct SG32ENTRY); 1024 arccdbsize += sizeof(struct SG32ENTRY); 1025 } else { 1026 u_int32_t sg64s_size = 0, tmplength = length; 1027 1028 while(1) { 1029 u_int64_t span4G, length0; 1030 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1031 1032 span4G = (u_int64_t)address_lo + tmplength; 1033 pdma_sg->addresshigh = address_hi; 1034 pdma_sg->address = address_lo; 1035 if(span4G > 0x100000000) { 1036 /*see if cross 4G boundary*/ 1037 length0 = 0x100000000-address_lo; 1038 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1039 address_hi = address_hi+1; 1040 address_lo = 0; 1041 tmplength = tmplength - (u_int32_t)length0; 1042 sg64s_size += sizeof(struct SG64ENTRY); 1043 psge += sizeof(struct SG64ENTRY); 1044 cdb_sgcount++; 1045 } else { 1046 pdma_sg->length = tmplength | IS_SG64_ADDR; 1047 sg64s_size += sizeof(struct SG64ENTRY); 1048 psge += sizeof(struct SG64ENTRY); 1049 break; 1050 } 1051 } 1052 arccdbsize += sg64s_size; 1053 } 1054 cdb_sgcount++; 1055 } 1056 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1057 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1058 if( arccdbsize > 256) { 1059 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1060 } 1061 } else { 1062 arcmsr_cdb->DataLength = 0; 1063 } 1064 srb->arc_cdb_size = arccdbsize; 1065 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1066} 1067/* 1068************************************************************************** 1069************************************************************************** 1070*/ 1071static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1072{ 1073 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1074 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1075 1076 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1077 atomic_add_int(&acb->srboutstandingcount, 1); 1078 srb->srb_state = ARCMSR_SRB_START; 1079 1080 switch (acb->adapter_type) { 1081 case ACB_ADAPTER_TYPE_A: { 1082 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1083 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1084 } else { 1085 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1086 } 1087 } 1088 break; 1089 case ACB_ADAPTER_TYPE_B: { 1090 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1091 int ending_index, index; 1092 1093 index = phbbmu->postq_index; 1094 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1095 phbbmu->post_qbuffer[ending_index] = 0; 1096 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1097 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1098 } else { 1099 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1100 } 1101 index++; 1102 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1103 phbbmu->postq_index = index; 1104 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1105 } 1106 break; 1107 case ACB_ADAPTER_TYPE_C: { 1108 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1109 1110 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1111 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1112 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1113 if(cdb_phyaddr_hi32) 1114 { 1115 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1116 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1117 } 1118 else 1119 { 1120 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1121 } 1122 } 1123 break; 1124 case ACB_ADAPTER_TYPE_D: { 1125 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1126 u_int16_t index_stripped; 1127 u_int16_t postq_index; 1128 struct InBound_SRB *pinbound_srb; 1129 1130 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1131 postq_index = phbdmu->postq_index; 1132 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1133 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1134 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1135 pinbound_srb->length = srb->arc_cdb_size >> 2; 1136 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1137 if (postq_index & 0x4000) { 1138 index_stripped = postq_index & 0xFF; 1139 index_stripped += 1; 1140 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1141 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1142 } else { 1143 index_stripped = postq_index; 1144 index_stripped += 1; 1145 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1146 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1147 } 1148 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1149 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1150 } 1151 break; 1152 } 1153} 1154/* 1155************************************************************************ 1156************************************************************************ 1157*/ 1158static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1159{ 1160 struct QBUFFER *qbuffer=NULL; 1161 1162 switch (acb->adapter_type) { 1163 case ACB_ADAPTER_TYPE_A: { 1164 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1165 1166 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1167 } 1168 break; 1169 case ACB_ADAPTER_TYPE_B: { 1170 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1171 1172 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1173 } 1174 break; 1175 case ACB_ADAPTER_TYPE_C: { 1176 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1177 1178 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1179 } 1180 break; 1181 case ACB_ADAPTER_TYPE_D: { 1182 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1183 1184 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1185 } 1186 break; 1187 } 1188 return(qbuffer); 1189} 1190/* 1191************************************************************************ 1192************************************************************************ 1193*/ 1194static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1195{ 1196 struct QBUFFER *qbuffer = NULL; 1197 1198 switch (acb->adapter_type) { 1199 case ACB_ADAPTER_TYPE_A: { 1200 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1201 1202 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1203 } 1204 break; 1205 case ACB_ADAPTER_TYPE_B: { 1206 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1207 1208 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1209 } 1210 break; 1211 case ACB_ADAPTER_TYPE_C: { 1212 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1213 1214 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1215 } 1216 break; 1217 case ACB_ADAPTER_TYPE_D: { 1218 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1219 1220 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1221 } 1222 break; 1223 } 1224 return(qbuffer); 1225} 1226/* 1227************************************************************************** 1228************************************************************************** 1229*/ 1230static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1231{ 1232 switch (acb->adapter_type) { 1233 case ACB_ADAPTER_TYPE_A: { 1234 /* let IOP know data has been read */ 1235 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1236 } 1237 break; 1238 case ACB_ADAPTER_TYPE_B: { 1239 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1240 /* let IOP know data has been read */ 1241 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1242 } 1243 break; 1244 case ACB_ADAPTER_TYPE_C: { 1245 /* let IOP know data has been read */ 1246 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1247 } 1248 break; 1249 case ACB_ADAPTER_TYPE_D: { 1250 /* let IOP know data has been read */ 1251 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1252 } 1253 break; 1254 } 1255} 1256/* 1257************************************************************************** 1258************************************************************************** 1259*/ 1260static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1261{ 1262 switch (acb->adapter_type) { 1263 case ACB_ADAPTER_TYPE_A: { 1264 /* 1265 ** push inbound doorbell tell iop, driver data write ok 1266 ** and wait reply on next hwinterrupt for next Qbuffer post 1267 */ 1268 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1269 } 1270 break; 1271 case ACB_ADAPTER_TYPE_B: { 1272 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1273 /* 1274 ** push inbound doorbell tell iop, driver data write ok 1275 ** and wait reply on next hwinterrupt for next Qbuffer post 1276 */ 1277 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1278 } 1279 break; 1280 case ACB_ADAPTER_TYPE_C: { 1281 /* 1282 ** push inbound doorbell tell iop, driver data write ok 1283 ** and wait reply on next hwinterrupt for next Qbuffer post 1284 */ 1285 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1286 } 1287 break; 1288 case ACB_ADAPTER_TYPE_D: { 1289 /* 1290 ** push inbound doorbell tell iop, driver data write ok 1291 ** and wait reply on next hwinterrupt for next Qbuffer post 1292 */ 1293 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1294 } 1295 break; 1296 } 1297} 1298/* 1299************************************************************************ 1300************************************************************************ 1301*/ 1302static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1303{ 1304 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1305 CHIP_REG_WRITE32(HBA_MessageUnit, 1306 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1307 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1308 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1309 , acb->pci_unit); 1310 } 1311} 1312/* 1313************************************************************************ 1314************************************************************************ 1315*/ 1316static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1317{ 1318 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1319 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1320 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1321 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1322 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1323 , acb->pci_unit); 1324 } 1325} 1326/* 1327************************************************************************ 1328************************************************************************ 1329*/ 1330static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1331{ 1332 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1333 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1334 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1335 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1336 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1337 } 1338} 1339/* 1340************************************************************************ 1341************************************************************************ 1342*/ 1343static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1344{ 1345 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1347 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1348 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1349 } 1350} 1351/* 1352************************************************************************ 1353************************************************************************ 1354*/ 1355static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1356{ 1357 switch (acb->adapter_type) { 1358 case ACB_ADAPTER_TYPE_A: { 1359 arcmsr_stop_hba_bgrb(acb); 1360 } 1361 break; 1362 case ACB_ADAPTER_TYPE_B: { 1363 arcmsr_stop_hbb_bgrb(acb); 1364 } 1365 break; 1366 case ACB_ADAPTER_TYPE_C: { 1367 arcmsr_stop_hbc_bgrb(acb); 1368 } 1369 break; 1370 case ACB_ADAPTER_TYPE_D: { 1371 arcmsr_stop_hbd_bgrb(acb); 1372 } 1373 break; 1374 } 1375} 1376/* 1377************************************************************************ 1378************************************************************************ 1379*/ 1380static void arcmsr_poll(struct cam_sim *psim) 1381{ 1382 struct AdapterControlBlock *acb; 1383 int mutex; 1384 1385 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1386 mutex = mtx_owned(&acb->isr_lock); 1387 if( mutex == 0 ) 1388 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1389 arcmsr_interrupt(acb); 1390 if( mutex == 0 ) 1391 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1392} 1393/* 1394************************************************************************** 1395************************************************************************** 1396*/ 1397static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1398 struct QBUFFER *prbuffer) { 1399 1400 u_int8_t *pQbuffer; 1401 u_int8_t *buf1 = 0; 1402 u_int32_t *iop_data, *buf2 = 0; 1403 u_int32_t iop_len, data_len; 1404 1405 iop_data = (u_int32_t *)prbuffer->data; 1406 iop_len = (u_int32_t)prbuffer->data_len; 1407 if ( iop_len > 0 ) 1408 { 1409 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1410 buf2 = (u_int32_t *)buf1; 1411 if( buf1 == NULL) 1412 return (0); 1413 data_len = iop_len; 1414 while(data_len >= 4) 1415 { 1416 *buf2++ = *iop_data++; 1417 data_len -= 4; 1418 } 1419 if(data_len) 1420 *buf2 = *iop_data; 1421 buf2 = (u_int32_t *)buf1; 1422 } 1423 while (iop_len > 0) { 1424 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1425 *pQbuffer = *buf1; 1426 acb->rqbuf_lastindex++; 1427 /* if last, index number set it to 0 */ 1428 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1429 buf1++; 1430 iop_len--; 1431 } 1432 if(buf2) 1433 free( (u_int8_t *)buf2, M_DEVBUF); 1434 /* let IOP know data has been read */ 1435 arcmsr_iop_message_read(acb); 1436 return (1); 1437} 1438/* 1439************************************************************************** 1440************************************************************************** 1441*/ 1442static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1443 struct QBUFFER *prbuffer) { 1444 1445 u_int8_t *pQbuffer; 1446 u_int8_t *iop_data; 1447 u_int32_t iop_len; 1448 1449 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) { 1450 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1451 } 1452 iop_data = (u_int8_t *)prbuffer->data; 1453 iop_len = (u_int32_t)prbuffer->data_len; 1454 while (iop_len > 0) { 1455 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1456 *pQbuffer = *iop_data; 1457 acb->rqbuf_lastindex++; 1458 /* if last, index number set it to 0 */ 1459 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1460 iop_data++; 1461 iop_len--; 1462 } 1463 /* let IOP know data has been read */ 1464 arcmsr_iop_message_read(acb); 1465 return (1); 1466} 1467/* 1468************************************************************************** 1469************************************************************************** 1470*/ 1471static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1472{ 1473 struct QBUFFER *prbuffer; 1474 int my_empty_len; 1475 1476 /*check this iop data if overflow my rqbuffer*/ 1477 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1478 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1479 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1480 (ARCMSR_MAX_QBUFFER-1); 1481 if(my_empty_len >= prbuffer->data_len) { 1482 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1483 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1484 } else { 1485 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1486 } 1487 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1488} 1489/* 1490********************************************************************** 1491********************************************************************** 1492*/ 1493static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1494{ 1495 u_int8_t *pQbuffer; 1496 struct QBUFFER *pwbuffer; 1497 u_int8_t *buf1 = 0; 1498 u_int32_t *iop_data, *buf2 = 0; 1499 u_int32_t allxfer_len = 0, data_len; 1500 1501 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1502 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1503 buf2 = (u_int32_t *)buf1; 1504 if( buf1 == NULL) 1505 return; 1506 1507 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1508 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1509 iop_data = (u_int32_t *)pwbuffer->data; 1510 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1511 && (allxfer_len < 124)) { 1512 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1513 *buf1 = *pQbuffer; 1514 acb->wqbuf_firstindex++; 1515 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1516 buf1++; 1517 allxfer_len++; 1518 } 1519 pwbuffer->data_len = allxfer_len; 1520 data_len = allxfer_len; 1521 buf1 = (u_int8_t *)buf2; 1522 while(data_len >= 4) 1523 { 1524 *iop_data++ = *buf2++; 1525 data_len -= 4; 1526 } 1527 if(data_len) 1528 *iop_data = *buf2; 1529 free( buf1, M_DEVBUF); 1530 arcmsr_iop_message_wrote(acb); 1531 } 1532} 1533/* 1534********************************************************************** 1535********************************************************************** 1536*/ 1537static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1538{ 1539 u_int8_t *pQbuffer; 1540 struct QBUFFER *pwbuffer; 1541 u_int8_t *iop_data; 1542 int32_t allxfer_len=0; 1543 1544 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) { 1545 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1546 return; 1547 } 1548 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1549 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1550 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1551 iop_data = (u_int8_t *)pwbuffer->data; 1552 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1553 && (allxfer_len < 124)) { 1554 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1555 *iop_data = *pQbuffer; 1556 acb->wqbuf_firstindex++; 1557 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1558 iop_data++; 1559 allxfer_len++; 1560 } 1561 pwbuffer->data_len = allxfer_len; 1562 arcmsr_iop_message_wrote(acb); 1563 } 1564} 1565/* 1566************************************************************************** 1567************************************************************************** 1568*/ 1569static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1570{ 1571 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1572 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1573 /* 1574 ***************************************************************** 1575 ** check if there are any mail packages from user space program 1576 ** in my post bag, now is the time to send them into Areca's firmware 1577 ***************************************************************** 1578 */ 1579 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1580 arcmsr_Write_data_2iop_wqbuffer(acb); 1581 } 1582 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1583 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1584 } 1585 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1586} 1587/* 1588************************************************************************** 1589************************************************************************** 1590*/ 1591static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1592{ 1593/* 1594 if (ccb->ccb_h.status != CAM_REQ_CMP) 1595 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1596 "failure status=%x\n", ccb->ccb_h.target_id, 1597 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1598 else 1599 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1600*/ 1601 xpt_free_path(ccb->ccb_h.path); 1602 xpt_free_ccb(ccb); 1603} 1604 1605static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1606{ 1607 struct cam_path *path; 1608 union ccb *ccb; 1609 1610 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1611 return; 1612 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1613 { 1614 xpt_free_ccb(ccb); 1615 return; 1616 } 1617/* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1618 bzero(ccb, sizeof(union ccb)); 1619 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1620 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1621 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1622 ccb->crcn.flags = CAM_FLAG_NONE; 1623 xpt_action(ccb); 1624} 1625 1626 1627static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1628{ 1629 struct CommandControlBlock *srb; 1630 u_int32_t intmask_org; 1631 int i; 1632 1633 /* disable all outbound interrupts */ 1634 intmask_org = arcmsr_disable_allintr(acb); 1635 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1636 { 1637 srb = acb->psrb_pool[i]; 1638 if (srb->srb_state == ARCMSR_SRB_START) 1639 { 1640 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1641 { 1642 srb->srb_state = ARCMSR_SRB_ABORTED; 1643 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1644 arcmsr_srb_complete(srb, 1); 1645 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1646 } 1647 } 1648 } 1649 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1650 arcmsr_enable_allintr(acb, intmask_org); 1651} 1652/* 1653************************************************************************** 1654************************************************************************** 1655*/ 1656static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1657 u_int32_t devicemap; 1658 u_int32_t target, lun; 1659 u_int32_t deviceMapCurrent[4]={0}; 1660 u_int8_t *pDevMap; 1661 1662 switch (acb->adapter_type) { 1663 case ACB_ADAPTER_TYPE_A: 1664 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1665 for (target = 0; target < 4; target++) 1666 { 1667 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1668 devicemap += 4; 1669 } 1670 break; 1671 1672 case ACB_ADAPTER_TYPE_B: 1673 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1674 for (target = 0; target < 4; target++) 1675 { 1676 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1677 devicemap += 4; 1678 } 1679 break; 1680 1681 case ACB_ADAPTER_TYPE_C: 1682 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1683 for (target = 0; target < 4; target++) 1684 { 1685 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1686 devicemap += 4; 1687 } 1688 break; 1689 case ACB_ADAPTER_TYPE_D: 1690 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1691 for (target = 0; target < 4; target++) 1692 { 1693 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1694 devicemap += 4; 1695 } 1696 break; 1697 } 1698 1699 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1700 { 1701 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1702 } 1703 /* 1704 ** adapter posted CONFIG message 1705 ** copy the new map, note if there are differences with the current map 1706 */ 1707 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1708 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1709 { 1710 if (*pDevMap != acb->device_map[target]) 1711 { 1712 u_int8_t difference, bit_check; 1713 1714 difference = *pDevMap ^ acb->device_map[target]; 1715 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1716 { 1717 bit_check = (1 << lun); /*check bit from 0....31*/ 1718 if(difference & bit_check) 1719 { 1720 if(acb->device_map[target] & bit_check) 1721 {/* unit departed */ 1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1723 arcmsr_abort_dr_ccbs(acb, target, lun); 1724 arcmsr_rescan_lun(acb, target, lun); 1725 acb->devstate[target][lun] = ARECA_RAID_GONE; 1726 } 1727 else 1728 {/* unit arrived */ 1729 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1730 arcmsr_rescan_lun(acb, target, lun); 1731 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1732 } 1733 } 1734 } 1735/* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1736 acb->device_map[target] = *pDevMap; 1737 } 1738 pDevMap++; 1739 } 1740} 1741/* 1742************************************************************************** 1743************************************************************************** 1744*/ 1745static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1746 u_int32_t outbound_message; 1747 1748 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1749 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1750 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1751 arcmsr_dr_handle( acb ); 1752} 1753/* 1754************************************************************************** 1755************************************************************************** 1756*/ 1757static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1758 u_int32_t outbound_message; 1759 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1760 1761 /* clear interrupts */ 1762 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1763 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1764 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1765 arcmsr_dr_handle( acb ); 1766} 1767/* 1768************************************************************************** 1769************************************************************************** 1770*/ 1771static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1772 u_int32_t outbound_message; 1773 1774 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1775 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1776 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1777 arcmsr_dr_handle( acb ); 1778} 1779/* 1780************************************************************************** 1781************************************************************************** 1782*/ 1783static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1784 u_int32_t outbound_message; 1785 1786 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1787 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1788 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1789 arcmsr_dr_handle( acb ); 1790} 1791/* 1792************************************************************************** 1793************************************************************************** 1794*/ 1795static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1796{ 1797 u_int32_t doorbell_status; 1798 1799 /* 1800 ******************************************************************* 1801 ** Maybe here we need to check wrqbuffer_lock is lock or not 1802 ** DOORBELL: din! don! 1803 ** check if there are any mail need to pack from firmware 1804 ******************************************************************* 1805 */ 1806 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1807 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1808 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1809 arcmsr_iop2drv_data_wrote_handle(acb); 1810 } 1811 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1812 arcmsr_iop2drv_data_read_handle(acb); 1813 } 1814} 1815/* 1816************************************************************************** 1817************************************************************************** 1818*/ 1819static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1820{ 1821 u_int32_t doorbell_status; 1822 1823 /* 1824 ******************************************************************* 1825 ** Maybe here we need to check wrqbuffer_lock is lock or not 1826 ** DOORBELL: din! don! 1827 ** check if there are any mail need to pack from firmware 1828 ******************************************************************* 1829 */ 1830 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1831 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1832 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1833 arcmsr_iop2drv_data_wrote_handle(acb); 1834 } 1835 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1836 arcmsr_iop2drv_data_read_handle(acb); 1837 } 1838 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1839 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1840 } 1841} 1842/* 1843************************************************************************** 1844************************************************************************** 1845*/ 1846static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1847{ 1848 u_int32_t doorbell_status; 1849 1850 /* 1851 ******************************************************************* 1852 ** Maybe here we need to check wrqbuffer_lock is lock or not 1853 ** DOORBELL: din! don! 1854 ** check if there are any mail need to pack from firmware 1855 ******************************************************************* 1856 */ 1857 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1858 if(doorbell_status) 1859 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1860 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1861 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1862 arcmsr_iop2drv_data_wrote_handle(acb); 1863 } 1864 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1865 arcmsr_iop2drv_data_read_handle(acb); 1866 } 1867 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1868 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1869 } 1870 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1871 if(doorbell_status) 1872 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1873 } 1874} 1875/* 1876************************************************************************** 1877************************************************************************** 1878*/ 1879static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1880{ 1881 u_int32_t flag_srb; 1882 u_int16_t error; 1883 1884 /* 1885 ***************************************************************************** 1886 ** areca cdb command done 1887 ***************************************************************************** 1888 */ 1889 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1890 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1891 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1892 0, outbound_queueport)) != 0xFFFFFFFF) { 1893 /* check if command done with no error*/ 1894 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1895 arcmsr_drain_donequeue(acb, flag_srb, error); 1896 } /*drain reply FIFO*/ 1897} 1898/* 1899************************************************************************** 1900************************************************************************** 1901*/ 1902static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1903{ 1904 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1905 u_int32_t flag_srb; 1906 int index; 1907 u_int16_t error; 1908 1909 /* 1910 ***************************************************************************** 1911 ** areca cdb command done 1912 ***************************************************************************** 1913 */ 1914 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1915 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1916 index = phbbmu->doneq_index; 1917 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1918 phbbmu->done_qbuffer[index] = 0; 1919 index++; 1920 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1921 phbbmu->doneq_index = index; 1922 /* check if command done with no error*/ 1923 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1924 arcmsr_drain_donequeue(acb, flag_srb, error); 1925 } /*drain reply FIFO*/ 1926} 1927/* 1928************************************************************************** 1929************************************************************************** 1930*/ 1931static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1932{ 1933 u_int32_t flag_srb,throttling = 0; 1934 u_int16_t error; 1935 1936 /* 1937 ***************************************************************************** 1938 ** areca cdb command done 1939 ***************************************************************************** 1940 */ 1941 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1942 do { 1943 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1944 if (flag_srb == 0xFFFFFFFF) 1945 break; 1946 /* check if command done with no error*/ 1947 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1948 arcmsr_drain_donequeue(acb, flag_srb, error); 1949 throttling++; 1950 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1951 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1952 throttling = 0; 1953 } 1954 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 1955} 1956/* 1957********************************************************************** 1958** 1959********************************************************************** 1960*/ 1961static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1962{ 1963 uint16_t doneq_index, index_stripped; 1964 1965 doneq_index = phbdmu->doneq_index; 1966 if (doneq_index & 0x4000) { 1967 index_stripped = doneq_index & 0xFF; 1968 index_stripped += 1; 1969 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1970 phbdmu->doneq_index = index_stripped ? 1971 (index_stripped | 0x4000) : index_stripped; 1972 } else { 1973 index_stripped = doneq_index; 1974 index_stripped += 1; 1975 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1976 phbdmu->doneq_index = index_stripped ? 1977 index_stripped : (index_stripped | 0x4000); 1978 } 1979 return (phbdmu->doneq_index); 1980} 1981/* 1982************************************************************************** 1983************************************************************************** 1984*/ 1985static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1986{ 1987 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1988 u_int32_t outbound_write_pointer; 1989 u_int32_t addressLow; 1990 uint16_t doneq_index; 1991 u_int16_t error; 1992 /* 1993 ***************************************************************************** 1994 ** areca cdb command done 1995 ***************************************************************************** 1996 */ 1997 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1998 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1999 return; 2000 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2001 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2002 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2003 doneq_index = phbdmu->doneq_index; 2004 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2005 doneq_index = arcmsr_get_doneq_index(phbdmu); 2006 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2007 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2008 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2009 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2010 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2011 } 2012 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2013 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2014} 2015/* 2016********************************************************************** 2017********************************************************************** 2018*/ 2019static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2020{ 2021 u_int32_t outbound_intStatus; 2022 /* 2023 ********************************************* 2024 ** check outbound intstatus 2025 ********************************************* 2026 */ 2027 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2028 if(!outbound_intStatus) { 2029 /*it must be share irq*/ 2030 return; 2031 } 2032 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2033 /* MU doorbell interrupts*/ 2034 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2035 arcmsr_hba_doorbell_isr(acb); 2036 } 2037 /* MU post queue interrupts*/ 2038 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2039 arcmsr_hba_postqueue_isr(acb); 2040 } 2041 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2042 arcmsr_hba_message_isr(acb); 2043 } 2044} 2045/* 2046********************************************************************** 2047********************************************************************** 2048*/ 2049static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2050{ 2051 u_int32_t outbound_doorbell; 2052 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2053 /* 2054 ********************************************* 2055 ** check outbound intstatus 2056 ********************************************* 2057 */ 2058 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2059 if(!outbound_doorbell) { 2060 /*it must be share irq*/ 2061 return; 2062 } 2063 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2064 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2065 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2066 /* MU ioctl transfer doorbell interrupts*/ 2067 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2068 arcmsr_iop2drv_data_wrote_handle(acb); 2069 } 2070 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2071 arcmsr_iop2drv_data_read_handle(acb); 2072 } 2073 /* MU post queue interrupts*/ 2074 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2075 arcmsr_hbb_postqueue_isr(acb); 2076 } 2077 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2078 arcmsr_hbb_message_isr(acb); 2079 } 2080} 2081/* 2082********************************************************************** 2083********************************************************************** 2084*/ 2085static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2086{ 2087 u_int32_t host_interrupt_status; 2088 /* 2089 ********************************************* 2090 ** check outbound intstatus 2091 ********************************************* 2092 */ 2093 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2094 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2095 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2096 if(!host_interrupt_status) { 2097 /*it must be share irq*/ 2098 return; 2099 } 2100 do { 2101 /* MU doorbell interrupts*/ 2102 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2103 arcmsr_hbc_doorbell_isr(acb); 2104 } 2105 /* MU post queue interrupts*/ 2106 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2107 arcmsr_hbc_postqueue_isr(acb); 2108 } 2109 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2110 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2111} 2112/* 2113********************************************************************** 2114********************************************************************** 2115*/ 2116static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2117{ 2118 u_int32_t host_interrupt_status; 2119 u_int32_t intmask_org; 2120 /* 2121 ********************************************* 2122 ** check outbound intstatus 2123 ********************************************* 2124 */ 2125 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2126 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2127 /*it must be share irq*/ 2128 return; 2129 } 2130 /* disable outbound interrupt */ 2131 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2132 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2133 /* MU doorbell interrupts*/ 2134 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2135 arcmsr_hbd_doorbell_isr(acb); 2136 } 2137 /* MU post queue interrupts*/ 2138 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2139 arcmsr_hbd_postqueue_isr(acb); 2140 } 2141 /* enable all outbound interrupt */ 2142 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2143// CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2144} 2145/* 2146****************************************************************************** 2147****************************************************************************** 2148*/ 2149static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2150{ 2151 switch (acb->adapter_type) { 2152 case ACB_ADAPTER_TYPE_A: 2153 arcmsr_handle_hba_isr(acb); 2154 break; 2155 case ACB_ADAPTER_TYPE_B: 2156 arcmsr_handle_hbb_isr(acb); 2157 break; 2158 case ACB_ADAPTER_TYPE_C: 2159 arcmsr_handle_hbc_isr(acb); 2160 break; 2161 case ACB_ADAPTER_TYPE_D: 2162 arcmsr_handle_hbd_isr(acb); 2163 break; 2164 default: 2165 printf("arcmsr%d: interrupt service," 2166 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2167 break; 2168 } 2169} 2170/* 2171********************************************************************** 2172********************************************************************** 2173*/ 2174static void arcmsr_intr_handler(void *arg) 2175{ 2176 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2177 2178 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2179 arcmsr_interrupt(acb); 2180 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2181} 2182/* 2183****************************************************************************** 2184****************************************************************************** 2185*/ 2186static void arcmsr_polling_devmap(void *arg) 2187{ 2188 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2189 switch (acb->adapter_type) { 2190 case ACB_ADAPTER_TYPE_A: 2191 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2192 break; 2193 2194 case ACB_ADAPTER_TYPE_B: { 2195 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2196 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2197 } 2198 break; 2199 2200 case ACB_ADAPTER_TYPE_C: 2201 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2202 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2203 break; 2204 2205 case ACB_ADAPTER_TYPE_D: 2206 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2207 break; 2208 } 2209 2210 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2211 { 2212 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2213 } 2214} 2215 2216/* 2217******************************************************************************* 2218** 2219******************************************************************************* 2220*/ 2221static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2222{ 2223 u_int32_t intmask_org; 2224 2225 if(acb != NULL) { 2226 /* stop adapter background rebuild */ 2227 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2228 intmask_org = arcmsr_disable_allintr(acb); 2229 arcmsr_stop_adapter_bgrb(acb); 2230 arcmsr_flush_adapter_cache(acb); 2231 arcmsr_enable_allintr(acb, intmask_org); 2232 } 2233 } 2234} 2235/* 2236*********************************************************************** 2237** 2238************************************************************************ 2239*/ 2240u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2241{ 2242 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2243 u_int32_t retvalue = EINVAL; 2244 2245 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2246 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2247 return retvalue; 2248 } 2249 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2250 switch(ioctl_cmd) { 2251 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2252 u_int8_t *pQbuffer; 2253 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2254 u_int32_t allxfer_len=0; 2255 2256 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2257 && (allxfer_len < 1031)) { 2258 /*copy READ QBUFFER to srb*/ 2259 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2260 *ptmpQbuffer = *pQbuffer; 2261 acb->rqbuf_firstindex++; 2262 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2263 /*if last index number set it to 0 */ 2264 ptmpQbuffer++; 2265 allxfer_len++; 2266 } 2267 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2268 struct QBUFFER *prbuffer; 2269 2270 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2271 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2272 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2273 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2274 } 2275 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2276 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2277 retvalue = ARCMSR_MESSAGE_SUCCESS; 2278 } 2279 break; 2280 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2281 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2282 u_int8_t *pQbuffer; 2283 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2284 2285 user_len = pcmdmessagefld->cmdmessage.Length; 2286 /*check if data xfer length of this request will overflow my array qbuffer */ 2287 wqbuf_lastindex = acb->wqbuf_lastindex; 2288 wqbuf_firstindex = acb->wqbuf_firstindex; 2289 if(wqbuf_lastindex != wqbuf_firstindex) { 2290 arcmsr_Write_data_2iop_wqbuffer(acb); 2291 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2292 } else { 2293 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2294 (ARCMSR_MAX_QBUFFER - 1); 2295 if(my_empty_len >= user_len) { 2296 while(user_len > 0) { 2297 /*copy srb data to wqbuffer*/ 2298 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2299 *pQbuffer = *ptmpuserbuffer; 2300 acb->wqbuf_lastindex++; 2301 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2302 /*if last index number set it to 0 */ 2303 ptmpuserbuffer++; 2304 user_len--; 2305 } 2306 /*post fist Qbuffer*/ 2307 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2308 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2309 arcmsr_Write_data_2iop_wqbuffer(acb); 2310 } 2311 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2312 } else { 2313 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2314 } 2315 } 2316 retvalue = ARCMSR_MESSAGE_SUCCESS; 2317 } 2318 break; 2319 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2320 u_int8_t *pQbuffer = acb->rqbuffer; 2321 2322 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2323 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2324 arcmsr_iop_message_read(acb); 2325 /*signature, let IOP know data has been readed */ 2326 } 2327 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2328 acb->rqbuf_firstindex = 0; 2329 acb->rqbuf_lastindex = 0; 2330 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2331 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2332 retvalue = ARCMSR_MESSAGE_SUCCESS; 2333 } 2334 break; 2335 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2336 { 2337 u_int8_t *pQbuffer = acb->wqbuffer; 2338 2339 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2340 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2341 arcmsr_iop_message_read(acb); 2342 /*signature, let IOP know data has been readed */ 2343 } 2344 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2345 acb->wqbuf_firstindex = 0; 2346 acb->wqbuf_lastindex = 0; 2347 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2348 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2349 retvalue = ARCMSR_MESSAGE_SUCCESS; 2350 } 2351 break; 2352 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2353 u_int8_t *pQbuffer; 2354 2355 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2356 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2357 arcmsr_iop_message_read(acb); 2358 /*signature, let IOP know data has been readed */ 2359 } 2360 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2361 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2362 |ACB_F_MESSAGE_WQBUFFER_READ); 2363 acb->rqbuf_firstindex = 0; 2364 acb->rqbuf_lastindex = 0; 2365 acb->wqbuf_firstindex = 0; 2366 acb->wqbuf_lastindex = 0; 2367 pQbuffer = acb->rqbuffer; 2368 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2369 pQbuffer = acb->wqbuffer; 2370 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2371 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2372 retvalue = ARCMSR_MESSAGE_SUCCESS; 2373 } 2374 break; 2375 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2376 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2377 retvalue = ARCMSR_MESSAGE_SUCCESS; 2378 } 2379 break; 2380 case ARCMSR_MESSAGE_SAY_HELLO: { 2381 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2382 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2383 2384 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2385 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2386 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2387 return ENOIOCTL; 2388 } 2389 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2390 retvalue = ARCMSR_MESSAGE_SUCCESS; 2391 } 2392 break; 2393 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2394 arcmsr_iop_parking(acb); 2395 retvalue = ARCMSR_MESSAGE_SUCCESS; 2396 } 2397 break; 2398 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2399 arcmsr_flush_adapter_cache(acb); 2400 retvalue = ARCMSR_MESSAGE_SUCCESS; 2401 } 2402 break; 2403 } 2404 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2405 return (retvalue); 2406} 2407/* 2408************************************************************************** 2409************************************************************************** 2410*/ 2411static void arcmsr_free_srb(struct CommandControlBlock *srb) 2412{ 2413 struct AdapterControlBlock *acb; 2414 2415 acb = srb->acb; 2416 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2417 srb->srb_state = ARCMSR_SRB_DONE; 2418 srb->srb_flags = 0; 2419 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2420 acb->workingsrb_doneindex++; 2421 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2422 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2423} 2424/* 2425************************************************************************** 2426************************************************************************** 2427*/ 2428struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2429{ 2430 struct CommandControlBlock *srb = NULL; 2431 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2432 2433 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2434 workingsrb_doneindex = acb->workingsrb_doneindex; 2435 workingsrb_startindex = acb->workingsrb_startindex; 2436 srb = acb->srbworkingQ[workingsrb_startindex]; 2437 workingsrb_startindex++; 2438 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2439 if(workingsrb_doneindex != workingsrb_startindex) { 2440 acb->workingsrb_startindex = workingsrb_startindex; 2441 } else { 2442 srb = NULL; 2443 } 2444 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2445 return(srb); 2446} 2447/* 2448************************************************************************** 2449************************************************************************** 2450*/ 2451static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2452{ 2453 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2454 int retvalue = 0, transfer_len = 0; 2455 char *buffer; 2456 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2457 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2458 (u_int32_t ) ptr[6] << 16 | 2459 (u_int32_t ) ptr[7] << 8 | 2460 (u_int32_t ) ptr[8]; 2461 /* 4 bytes: Areca io control code */ 2462 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2463 buffer = pccb->csio.data_ptr; 2464 transfer_len = pccb->csio.dxfer_len; 2465 } else { 2466 retvalue = ARCMSR_MESSAGE_FAIL; 2467 goto message_out; 2468 } 2469 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2470 retvalue = ARCMSR_MESSAGE_FAIL; 2471 goto message_out; 2472 } 2473 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2474 switch(controlcode) { 2475 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2476 u_int8_t *pQbuffer; 2477 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2478 int32_t allxfer_len = 0; 2479 2480 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2481 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2482 && (allxfer_len < 1031)) { 2483 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2484 *ptmpQbuffer = *pQbuffer; 2485 acb->rqbuf_firstindex++; 2486 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2487 ptmpQbuffer++; 2488 allxfer_len++; 2489 } 2490 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2491 struct QBUFFER *prbuffer; 2492 2493 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2494 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2495 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2496 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2497 } 2498 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2499 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2500 retvalue = ARCMSR_MESSAGE_SUCCESS; 2501 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2502 } 2503 break; 2504 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2505 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2506 u_int8_t *pQbuffer; 2507 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2508 2509 user_len = pcmdmessagefld->cmdmessage.Length; 2510 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2511 wqbuf_lastindex = acb->wqbuf_lastindex; 2512 wqbuf_firstindex = acb->wqbuf_firstindex; 2513 if (wqbuf_lastindex != wqbuf_firstindex) { 2514 arcmsr_Write_data_2iop_wqbuffer(acb); 2515 /* has error report sensedata */ 2516 if(pccb->csio.sense_len) { 2517 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2518 /* Valid,ErrorCode */ 2519 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2520 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2521 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2522 /* AdditionalSenseLength */ 2523 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2524 /* AdditionalSenseCode */ 2525 } 2526 retvalue = ARCMSR_MESSAGE_FAIL; 2527 } else { 2528 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2529 &(ARCMSR_MAX_QBUFFER - 1); 2530 if (my_empty_len >= user_len) { 2531 while (user_len > 0) { 2532 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2533 *pQbuffer = *ptmpuserbuffer; 2534 acb->wqbuf_lastindex++; 2535 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2536 ptmpuserbuffer++; 2537 user_len--; 2538 } 2539 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2540 acb->acb_flags &= 2541 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2542 arcmsr_Write_data_2iop_wqbuffer(acb); 2543 } 2544 } else { 2545 /* has error report sensedata */ 2546 if(pccb->csio.sense_len) { 2547 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2548 /* Valid,ErrorCode */ 2549 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2550 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2551 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2552 /* AdditionalSenseLength */ 2553 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2554 /* AdditionalSenseCode */ 2555 } 2556 retvalue = ARCMSR_MESSAGE_FAIL; 2557 } 2558 } 2559 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2560 } 2561 break; 2562 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2563 u_int8_t *pQbuffer = acb->rqbuffer; 2564 2565 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2566 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2567 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2568 arcmsr_iop_message_read(acb); 2569 } 2570 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2571 acb->rqbuf_firstindex = 0; 2572 acb->rqbuf_lastindex = 0; 2573 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2574 pcmdmessagefld->cmdmessage.ReturnCode = 2575 ARCMSR_MESSAGE_RETURNCODE_OK; 2576 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2577 } 2578 break; 2579 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2580 u_int8_t *pQbuffer = acb->wqbuffer; 2581 2582 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2583 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2584 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2585 arcmsr_iop_message_read(acb); 2586 } 2587 acb->acb_flags |= 2588 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2589 ACB_F_MESSAGE_WQBUFFER_READ); 2590 acb->wqbuf_firstindex = 0; 2591 acb->wqbuf_lastindex = 0; 2592 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2593 pcmdmessagefld->cmdmessage.ReturnCode = 2594 ARCMSR_MESSAGE_RETURNCODE_OK; 2595 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2596 } 2597 break; 2598 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2599 u_int8_t *pQbuffer; 2600 2601 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2602 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2603 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2604 arcmsr_iop_message_read(acb); 2605 } 2606 acb->acb_flags |= 2607 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2608 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2609 | ACB_F_MESSAGE_WQBUFFER_READ); 2610 acb->rqbuf_firstindex = 0; 2611 acb->rqbuf_lastindex = 0; 2612 acb->wqbuf_firstindex = 0; 2613 acb->wqbuf_lastindex = 0; 2614 pQbuffer = acb->rqbuffer; 2615 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2616 pQbuffer = acb->wqbuffer; 2617 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2618 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2619 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2620 } 2621 break; 2622 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2623 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2624 } 2625 break; 2626 case ARCMSR_MESSAGE_SAY_HELLO: { 2627 int8_t *hello_string = "Hello! I am ARCMSR"; 2628 2629 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2630 , (int16_t)strlen(hello_string)); 2631 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2632 } 2633 break; 2634 case ARCMSR_MESSAGE_SAY_GOODBYE: 2635 arcmsr_iop_parking(acb); 2636 break; 2637 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2638 arcmsr_flush_adapter_cache(acb); 2639 break; 2640 default: 2641 retvalue = ARCMSR_MESSAGE_FAIL; 2642 } 2643message_out: 2644 return (retvalue); 2645} 2646/* 2647********************************************************************* 2648********************************************************************* 2649*/ 2650static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2651{ 2652 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2653 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2654 union ccb *pccb; 2655 int target, lun; 2656 2657 pccb = srb->pccb; 2658 target = pccb->ccb_h.target_id; 2659 lun = pccb->ccb_h.target_lun; 2660 acb->pktRequestCount++; 2661 if(error != 0) { 2662 if(error != EFBIG) { 2663 printf("arcmsr%d: unexpected error %x" 2664 " returned from 'bus_dmamap_load' \n" 2665 , acb->pci_unit, error); 2666 } 2667 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2668 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2669 } 2670 arcmsr_srb_complete(srb, 0); 2671 return; 2672 } 2673 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2674 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2675 arcmsr_srb_complete(srb, 0); 2676 return; 2677 } 2678 if(acb->acb_flags & ACB_F_BUS_RESET) { 2679 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2680 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2681 arcmsr_srb_complete(srb, 0); 2682 return; 2683 } 2684 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2685 u_int8_t block_cmd, cmd; 2686 2687 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2688 block_cmd = cmd & 0x0f; 2689 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2690 printf("arcmsr%d:block 'read/write' command " 2691 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2692 , acb->pci_unit, cmd, target, lun); 2693 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2694 arcmsr_srb_complete(srb, 0); 2695 return; 2696 } 2697 } 2698 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2699 if(nseg != 0) { 2700 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2701 } 2702 arcmsr_srb_complete(srb, 0); 2703 return; 2704 } 2705 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2706 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2707 { 2708 xpt_freeze_simq(acb->psim, 1); 2709 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2710 } 2711 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2712 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2713 arcmsr_srb_complete(srb, 0); 2714 return; 2715 } 2716 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2717 arcmsr_build_srb(srb, dm_segs, nseg); 2718 arcmsr_post_srb(acb, srb); 2719 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2720 { 2721 arcmsr_callout_init(&srb->ccb_callout); 2722 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 2723 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 2724 arcmsr_srb_timeout, srb, 0); 2725 srb->srb_flags |= SRB_FLAG_TIMER_START; 2726 } 2727} 2728/* 2729***************************************************************************************** 2730***************************************************************************************** 2731*/ 2732static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2733{ 2734 struct CommandControlBlock *srb; 2735 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2736 u_int32_t intmask_org; 2737 int i = 0; 2738 2739 acb->num_aborts++; 2740 /* 2741 *************************************************************************** 2742 ** It is the upper layer do abort command this lock just prior to calling us. 2743 ** First determine if we currently own this command. 2744 ** Start by searching the device queue. If not found 2745 ** at all, and the system wanted us to just abort the 2746 ** command return success. 2747 *************************************************************************** 2748 */ 2749 if(acb->srboutstandingcount != 0) { 2750 /* disable all outbound interrupt */ 2751 intmask_org = arcmsr_disable_allintr(acb); 2752 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2753 srb = acb->psrb_pool[i]; 2754 if(srb->srb_state == ARCMSR_SRB_START) { 2755 if(srb->pccb == abortccb) { 2756 srb->srb_state = ARCMSR_SRB_ABORTED; 2757 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2758 "outstanding command \n" 2759 , acb->pci_unit, abortccb->ccb_h.target_id 2760 , abortccb->ccb_h.target_lun, srb); 2761 arcmsr_polling_srbdone(acb, srb); 2762 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2763 arcmsr_enable_allintr(acb, intmask_org); 2764 return (TRUE); 2765 } 2766 } 2767 } 2768 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2769 arcmsr_enable_allintr(acb, intmask_org); 2770 } 2771 return(FALSE); 2772} 2773/* 2774**************************************************************************** 2775**************************************************************************** 2776*/ 2777static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2778{ 2779 int retry = 0; 2780 2781 acb->num_resets++; 2782 acb->acb_flags |= ACB_F_BUS_RESET; 2783 while(acb->srboutstandingcount != 0 && retry < 400) { 2784 arcmsr_interrupt(acb); 2785 UDELAY(25000); 2786 retry++; 2787 } 2788 arcmsr_iop_reset(acb); 2789 acb->acb_flags &= ~ACB_F_BUS_RESET; 2790} 2791/* 2792************************************************************************** 2793************************************************************************** 2794*/ 2795static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2796 union ccb *pccb) 2797{ 2798 if (pccb->ccb_h.target_lun) { 2799 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2800 xpt_done(pccb); 2801 return; 2802 } 2803 pccb->ccb_h.status |= CAM_REQ_CMP; 2804 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 2805 case INQUIRY: { 2806 unsigned char inqdata[36]; 2807 char *buffer = pccb->csio.data_ptr; 2808 2809 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2810 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2811 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2812 inqdata[3] = 0; 2813 inqdata[4] = 31; /* length of additional data */ 2814 inqdata[5] = 0; 2815 inqdata[6] = 0; 2816 inqdata[7] = 0; 2817 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2818 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2819 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2820 memcpy(buffer, inqdata, sizeof(inqdata)); 2821 xpt_done(pccb); 2822 } 2823 break; 2824 case WRITE_BUFFER: 2825 case READ_BUFFER: { 2826 if (arcmsr_iop_message_xfer(acb, pccb)) { 2827 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2828 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2829 } 2830 xpt_done(pccb); 2831 } 2832 break; 2833 default: 2834 xpt_done(pccb); 2835 } 2836} 2837/* 2838********************************************************************* 2839********************************************************************* 2840*/ 2841static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2842{ 2843 struct AdapterControlBlock *acb; 2844 2845 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2846 if(acb == NULL) { 2847 pccb->ccb_h.status |= CAM_REQ_INVALID; 2848 xpt_done(pccb); 2849 return; 2850 } 2851 switch (pccb->ccb_h.func_code) { 2852 case XPT_SCSI_IO: { 2853 struct CommandControlBlock *srb; 2854 int target = pccb->ccb_h.target_id; 2855 int error; 2856 2857 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 2858 pccb->ccb_h.status = CAM_REQ_INVALID; 2859 xpt_done(pccb); 2860 return; 2861 } 2862 2863 if(target == 16) { 2864 /* virtual device for iop message transfer */ 2865 arcmsr_handle_virtual_command(acb, pccb); 2866 return; 2867 } 2868 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2869 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2870 xpt_done(pccb); 2871 return; 2872 } 2873 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2874 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2875 srb->pccb = pccb; 2876 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2877 , srb->dm_segs_dmamap 2878 , pccb 2879 , arcmsr_execute_srb, srb, /*flags*/0); 2880 if(error == EINPROGRESS) { 2881 xpt_freeze_simq(acb->psim, 1); 2882 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2883 } 2884 break; 2885 } 2886 case XPT_TARGET_IO: { 2887 /* target mode not yet support vendor specific commands. */ 2888 pccb->ccb_h.status |= CAM_REQ_CMP; 2889 xpt_done(pccb); 2890 break; 2891 } 2892 case XPT_PATH_INQ: { 2893 struct ccb_pathinq *cpi = &pccb->cpi; 2894 2895 cpi->version_num = 1; 2896 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2897 cpi->target_sprt = 0; 2898 cpi->hba_misc = 0; 2899 cpi->hba_eng_cnt = 0; 2900 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2901 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2902 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2903 cpi->bus_id = cam_sim_bus(psim); 2904 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2905 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2906 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2907 cpi->unit_number = cam_sim_unit(psim); 2908 #ifdef CAM_NEW_TRAN_CODE 2909 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 2910 cpi->base_transfer_speed = 1200000; 2911 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2912 cpi->base_transfer_speed = 600000; 2913 else 2914 cpi->base_transfer_speed = 300000; 2915 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2916 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2917 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2918 { 2919 cpi->transport = XPORT_SAS; 2920 cpi->transport_version = 0; 2921 cpi->protocol_version = SCSI_REV_SPC2; 2922 } 2923 else 2924 { 2925 cpi->transport = XPORT_SPI; 2926 cpi->transport_version = 2; 2927 cpi->protocol_version = SCSI_REV_2; 2928 } 2929 cpi->protocol = PROTO_SCSI; 2930 #endif 2931 cpi->ccb_h.status |= CAM_REQ_CMP; 2932 xpt_done(pccb); 2933 break; 2934 } 2935 case XPT_ABORT: { 2936 union ccb *pabort_ccb; 2937 2938 pabort_ccb = pccb->cab.abort_ccb; 2939 switch (pabort_ccb->ccb_h.func_code) { 2940 case XPT_ACCEPT_TARGET_IO: 2941 case XPT_IMMED_NOTIFY: 2942 case XPT_CONT_TARGET_IO: 2943 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2944 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2945 xpt_done(pabort_ccb); 2946 pccb->ccb_h.status |= CAM_REQ_CMP; 2947 } else { 2948 xpt_print_path(pabort_ccb->ccb_h.path); 2949 printf("Not found\n"); 2950 pccb->ccb_h.status |= CAM_PATH_INVALID; 2951 } 2952 break; 2953 case XPT_SCSI_IO: 2954 pccb->ccb_h.status |= CAM_UA_ABORT; 2955 break; 2956 default: 2957 pccb->ccb_h.status |= CAM_REQ_INVALID; 2958 break; 2959 } 2960 xpt_done(pccb); 2961 break; 2962 } 2963 case XPT_RESET_BUS: 2964 case XPT_RESET_DEV: { 2965 u_int32_t i; 2966 2967 arcmsr_bus_reset(acb); 2968 for (i=0; i < 500; i++) { 2969 DELAY(1000); 2970 } 2971 pccb->ccb_h.status |= CAM_REQ_CMP; 2972 xpt_done(pccb); 2973 break; 2974 } 2975 case XPT_TERM_IO: { 2976 pccb->ccb_h.status |= CAM_REQ_INVALID; 2977 xpt_done(pccb); 2978 break; 2979 } 2980 case XPT_GET_TRAN_SETTINGS: { 2981 struct ccb_trans_settings *cts; 2982 2983 if(pccb->ccb_h.target_id == 16) { 2984 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2985 xpt_done(pccb); 2986 break; 2987 } 2988 cts = &pccb->cts; 2989 #ifdef CAM_NEW_TRAN_CODE 2990 { 2991 struct ccb_trans_settings_scsi *scsi; 2992 struct ccb_trans_settings_spi *spi; 2993 struct ccb_trans_settings_sas *sas; 2994 2995 scsi = &cts->proto_specific.scsi; 2996 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2997 scsi->valid = CTS_SCSI_VALID_TQ; 2998 cts->protocol = PROTO_SCSI; 2999 3000 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3001 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3002 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3003 { 3004 cts->protocol_version = SCSI_REV_SPC2; 3005 cts->transport_version = 0; 3006 cts->transport = XPORT_SAS; 3007 sas = &cts->xport_specific.sas; 3008 sas->valid = CTS_SAS_VALID_SPEED; 3009 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3010 sas->bitrate = 1200000; 3011 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3012 sas->bitrate = 600000; 3013 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3014 sas->bitrate = 300000; 3015 } 3016 else 3017 { 3018 cts->protocol_version = SCSI_REV_2; 3019 cts->transport_version = 2; 3020 cts->transport = XPORT_SPI; 3021 spi = &cts->xport_specific.spi; 3022 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3023 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3024 spi->sync_period = 1; 3025 else 3026 spi->sync_period = 2; 3027 spi->sync_offset = 32; 3028 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3029 spi->valid = CTS_SPI_VALID_DISC 3030 | CTS_SPI_VALID_SYNC_RATE 3031 | CTS_SPI_VALID_SYNC_OFFSET 3032 | CTS_SPI_VALID_BUS_WIDTH; 3033 } 3034 } 3035 #else 3036 { 3037 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3038 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3039 cts->sync_period = 1; 3040 else 3041 cts->sync_period = 2; 3042 cts->sync_offset = 32; 3043 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3044 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3045 CCB_TRANS_SYNC_OFFSET_VALID | 3046 CCB_TRANS_BUS_WIDTH_VALID | 3047 CCB_TRANS_DISC_VALID | 3048 CCB_TRANS_TQ_VALID; 3049 } 3050 #endif 3051 pccb->ccb_h.status |= CAM_REQ_CMP; 3052 xpt_done(pccb); 3053 break; 3054 } 3055 case XPT_SET_TRAN_SETTINGS: { 3056 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3057 xpt_done(pccb); 3058 break; 3059 } 3060 case XPT_CALC_GEOMETRY: 3061 if(pccb->ccb_h.target_id == 16) { 3062 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3063 xpt_done(pccb); 3064 break; 3065 } 3066#if __FreeBSD_version >= 500000 3067 cam_calc_geometry(&pccb->ccg, 1); 3068#else 3069 { 3070 struct ccb_calc_geometry *ccg; 3071 u_int32_t size_mb; 3072 u_int32_t secs_per_cylinder; 3073 3074 ccg = &pccb->ccg; 3075 if (ccg->block_size == 0) { 3076 pccb->ccb_h.status = CAM_REQ_INVALID; 3077 xpt_done(pccb); 3078 break; 3079 } 3080 if(((1024L * 1024L)/ccg->block_size) < 0) { 3081 pccb->ccb_h.status = CAM_REQ_INVALID; 3082 xpt_done(pccb); 3083 break; 3084 } 3085 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3086 if(size_mb > 1024 ) { 3087 ccg->heads = 255; 3088 ccg->secs_per_track = 63; 3089 } else { 3090 ccg->heads = 64; 3091 ccg->secs_per_track = 32; 3092 } 3093 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3094 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3095 pccb->ccb_h.status |= CAM_REQ_CMP; 3096 } 3097#endif 3098 xpt_done(pccb); 3099 break; 3100 default: 3101 pccb->ccb_h.status |= CAM_REQ_INVALID; 3102 xpt_done(pccb); 3103 break; 3104 } 3105} 3106/* 3107********************************************************************** 3108********************************************************************** 3109*/ 3110static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3111{ 3112 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3113 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3114 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3115 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3116 } 3117} 3118/* 3119********************************************************************** 3120********************************************************************** 3121*/ 3122static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3123{ 3124 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3125 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3126 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3127 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3128 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3129 } 3130} 3131/* 3132********************************************************************** 3133********************************************************************** 3134*/ 3135static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3136{ 3137 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3138 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3139 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3140 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3141 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3142 } 3143} 3144/* 3145********************************************************************** 3146********************************************************************** 3147*/ 3148static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3149{ 3150 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3151 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3152 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3153 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3154 } 3155} 3156/* 3157********************************************************************** 3158********************************************************************** 3159*/ 3160static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3161{ 3162 switch (acb->adapter_type) { 3163 case ACB_ADAPTER_TYPE_A: 3164 arcmsr_start_hba_bgrb(acb); 3165 break; 3166 case ACB_ADAPTER_TYPE_B: 3167 arcmsr_start_hbb_bgrb(acb); 3168 break; 3169 case ACB_ADAPTER_TYPE_C: 3170 arcmsr_start_hbc_bgrb(acb); 3171 break; 3172 case ACB_ADAPTER_TYPE_D: 3173 arcmsr_start_hbd_bgrb(acb); 3174 break; 3175 } 3176} 3177/* 3178********************************************************************** 3179** 3180********************************************************************** 3181*/ 3182static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3183{ 3184 struct CommandControlBlock *srb; 3185 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3186 u_int16_t error; 3187 3188polling_ccb_retry: 3189 poll_count++; 3190 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3191 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3192 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3193 while(1) { 3194 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3195 0, outbound_queueport)) == 0xFFFFFFFF) { 3196 if(poll_srb_done) { 3197 break;/*chip FIFO no ccb for completion already*/ 3198 } else { 3199 UDELAY(25000); 3200 if ((poll_count > 100) && (poll_srb != NULL)) { 3201 break; 3202 } 3203 goto polling_ccb_retry; 3204 } 3205 } 3206 /* check if command done with no error*/ 3207 srb = (struct CommandControlBlock *) 3208 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3209 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3210 poll_srb_done = (srb == poll_srb) ? 1:0; 3211 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3212 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3213 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3214 "poll command abort successfully \n" 3215 , acb->pci_unit 3216 , srb->pccb->ccb_h.target_id 3217 , srb->pccb->ccb_h.target_lun, srb); 3218 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3219 arcmsr_srb_complete(srb, 1); 3220 continue; 3221 } 3222 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3223 "srboutstandingcount=%d \n" 3224 , acb->pci_unit 3225 , srb, acb->srboutstandingcount); 3226 continue; 3227 } 3228 arcmsr_report_srb_state(acb, srb, error); 3229 } /*drain reply FIFO*/ 3230} 3231/* 3232********************************************************************** 3233** 3234********************************************************************** 3235*/ 3236static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3237{ 3238 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3239 struct CommandControlBlock *srb; 3240 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3241 int index; 3242 u_int16_t error; 3243 3244polling_ccb_retry: 3245 poll_count++; 3246 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3247 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3248 while(1) { 3249 index = phbbmu->doneq_index; 3250 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3251 if(poll_srb_done) { 3252 break;/*chip FIFO no ccb for completion already*/ 3253 } else { 3254 UDELAY(25000); 3255 if ((poll_count > 100) && (poll_srb != NULL)) { 3256 break; 3257 } 3258 goto polling_ccb_retry; 3259 } 3260 } 3261 phbbmu->done_qbuffer[index] = 0; 3262 index++; 3263 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3264 phbbmu->doneq_index = index; 3265 /* check if command done with no error*/ 3266 srb = (struct CommandControlBlock *) 3267 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3268 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3269 poll_srb_done = (srb == poll_srb) ? 1:0; 3270 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3271 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3272 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3273 "poll command abort successfully \n" 3274 , acb->pci_unit 3275 , srb->pccb->ccb_h.target_id 3276 , srb->pccb->ccb_h.target_lun, srb); 3277 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3278 arcmsr_srb_complete(srb, 1); 3279 continue; 3280 } 3281 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3282 "srboutstandingcount=%d \n" 3283 , acb->pci_unit 3284 , srb, acb->srboutstandingcount); 3285 continue; 3286 } 3287 arcmsr_report_srb_state(acb, srb, error); 3288 } /*drain reply FIFO*/ 3289} 3290/* 3291********************************************************************** 3292** 3293********************************************************************** 3294*/ 3295static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3296{ 3297 struct CommandControlBlock *srb; 3298 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3299 u_int16_t error; 3300 3301polling_ccb_retry: 3302 poll_count++; 3303 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3304 while(1) { 3305 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3306 if(poll_srb_done) { 3307 break;/*chip FIFO no ccb for completion already*/ 3308 } else { 3309 UDELAY(25000); 3310 if ((poll_count > 100) && (poll_srb != NULL)) { 3311 break; 3312 } 3313 if (acb->srboutstandingcount == 0) { 3314 break; 3315 } 3316 goto polling_ccb_retry; 3317 } 3318 } 3319 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3320 /* check if command done with no error*/ 3321 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3322 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3323 if (poll_srb != NULL) 3324 poll_srb_done = (srb == poll_srb) ? 1:0; 3325 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3326 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3327 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3328 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3329 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3330 arcmsr_srb_complete(srb, 1); 3331 continue; 3332 } 3333 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3334 , acb->pci_unit, srb, acb->srboutstandingcount); 3335 continue; 3336 } 3337 arcmsr_report_srb_state(acb, srb, error); 3338 } /*drain reply FIFO*/ 3339} 3340/* 3341********************************************************************** 3342** 3343********************************************************************** 3344*/ 3345static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3346{ 3347 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3348 struct CommandControlBlock *srb; 3349 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3350 u_int32_t outbound_write_pointer; 3351 u_int16_t error, doneq_index; 3352 3353polling_ccb_retry: 3354 poll_count++; 3355 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3356 while(1) { 3357 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3358 doneq_index = phbdmu->doneq_index; 3359 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3360 if(poll_srb_done) { 3361 break;/*chip FIFO no ccb for completion already*/ 3362 } else { 3363 UDELAY(25000); 3364 if ((poll_count > 100) && (poll_srb != NULL)) { 3365 break; 3366 } 3367 if (acb->srboutstandingcount == 0) { 3368 break; 3369 } 3370 goto polling_ccb_retry; 3371 } 3372 } 3373 doneq_index = arcmsr_get_doneq_index(phbdmu); 3374 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3375 /* check if command done with no error*/ 3376 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3377 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3378 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3379 if (poll_srb != NULL) 3380 poll_srb_done = (srb == poll_srb) ? 1:0; 3381 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3382 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3383 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3384 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3385 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3386 arcmsr_srb_complete(srb, 1); 3387 continue; 3388 } 3389 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3390 , acb->pci_unit, srb, acb->srboutstandingcount); 3391 continue; 3392 } 3393 arcmsr_report_srb_state(acb, srb, error); 3394 } /*drain reply FIFO*/ 3395} 3396/* 3397********************************************************************** 3398********************************************************************** 3399*/ 3400static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3401{ 3402 switch (acb->adapter_type) { 3403 case ACB_ADAPTER_TYPE_A: { 3404 arcmsr_polling_hba_srbdone(acb, poll_srb); 3405 } 3406 break; 3407 case ACB_ADAPTER_TYPE_B: { 3408 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3409 } 3410 break; 3411 case ACB_ADAPTER_TYPE_C: { 3412 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3413 } 3414 break; 3415 case ACB_ADAPTER_TYPE_D: { 3416 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3417 } 3418 break; 3419 } 3420} 3421/* 3422********************************************************************** 3423********************************************************************** 3424*/ 3425static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3426{ 3427 char *acb_firm_model = acb->firm_model; 3428 char *acb_firm_version = acb->firm_version; 3429 char *acb_device_map = acb->device_map; 3430 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3431 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3432 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3433 int i; 3434 3435 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3436 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3437 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3438 } 3439 i = 0; 3440 while(i < 8) { 3441 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3442 /* 8 bytes firm_model, 15, 60-67*/ 3443 acb_firm_model++; 3444 i++; 3445 } 3446 i=0; 3447 while(i < 16) { 3448 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3449 /* 16 bytes firm_version, 17, 68-83*/ 3450 acb_firm_version++; 3451 i++; 3452 } 3453 i=0; 3454 while(i < 16) { 3455 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3456 acb_device_map++; 3457 i++; 3458 } 3459 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3460 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3461 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3462 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3463 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3464 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3465 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3466 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3467 else 3468 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3469} 3470/* 3471********************************************************************** 3472********************************************************************** 3473*/ 3474static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3475{ 3476 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3477 char *acb_firm_model = acb->firm_model; 3478 char *acb_firm_version = acb->firm_version; 3479 char *acb_device_map = acb->device_map; 3480 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3481 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3482 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3483 int i; 3484 3485 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3486 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3487 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3488 } 3489 i = 0; 3490 while(i < 8) { 3491 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3492 /* 8 bytes firm_model, 15, 60-67*/ 3493 acb_firm_model++; 3494 i++; 3495 } 3496 i = 0; 3497 while(i < 16) { 3498 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3499 /* 16 bytes firm_version, 17, 68-83*/ 3500 acb_firm_version++; 3501 i++; 3502 } 3503 i = 0; 3504 while(i < 16) { 3505 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3506 acb_device_map++; 3507 i++; 3508 } 3509 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3510 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3511 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3512 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3513 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3514 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3515 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3516 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3517 else 3518 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3519} 3520/* 3521********************************************************************** 3522********************************************************************** 3523*/ 3524static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3525{ 3526 char *acb_firm_model = acb->firm_model; 3527 char *acb_firm_version = acb->firm_version; 3528 char *acb_device_map = acb->device_map; 3529 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3530 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3531 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3532 int i; 3533 3534 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3535 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3536 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3537 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3538 } 3539 i = 0; 3540 while(i < 8) { 3541 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3542 /* 8 bytes firm_model, 15, 60-67*/ 3543 acb_firm_model++; 3544 i++; 3545 } 3546 i = 0; 3547 while(i < 16) { 3548 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3549 /* 16 bytes firm_version, 17, 68-83*/ 3550 acb_firm_version++; 3551 i++; 3552 } 3553 i = 0; 3554 while(i < 16) { 3555 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3556 acb_device_map++; 3557 i++; 3558 } 3559 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3560 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3561 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3562 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3563 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3564 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3565 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3566 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3567 else 3568 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3569} 3570/* 3571********************************************************************** 3572********************************************************************** 3573*/ 3574static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3575{ 3576 char *acb_firm_model = acb->firm_model; 3577 char *acb_firm_version = acb->firm_version; 3578 char *acb_device_map = acb->device_map; 3579 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3580 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3581 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3582 int i; 3583 3584 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3585 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3586 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3587 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3588 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3589 } 3590 i = 0; 3591 while(i < 8) { 3592 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3593 /* 8 bytes firm_model, 15, 60-67*/ 3594 acb_firm_model++; 3595 i++; 3596 } 3597 i = 0; 3598 while(i < 16) { 3599 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3600 /* 16 bytes firm_version, 17, 68-83*/ 3601 acb_firm_version++; 3602 i++; 3603 } 3604 i = 0; 3605 while(i < 16) { 3606 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3607 acb_device_map++; 3608 i++; 3609 } 3610 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3611 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3612 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3613 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3614 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3615 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3616 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3617 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3618 else 3619 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3620} 3621/* 3622********************************************************************** 3623********************************************************************** 3624*/ 3625static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3626{ 3627 switch (acb->adapter_type) { 3628 case ACB_ADAPTER_TYPE_A: { 3629 arcmsr_get_hba_config(acb); 3630 } 3631 break; 3632 case ACB_ADAPTER_TYPE_B: { 3633 arcmsr_get_hbb_config(acb); 3634 } 3635 break; 3636 case ACB_ADAPTER_TYPE_C: { 3637 arcmsr_get_hbc_config(acb); 3638 } 3639 break; 3640 case ACB_ADAPTER_TYPE_D: { 3641 arcmsr_get_hbd_config(acb); 3642 } 3643 break; 3644 } 3645} 3646/* 3647********************************************************************** 3648********************************************************************** 3649*/ 3650static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3651{ 3652 int timeout=0; 3653 3654 switch (acb->adapter_type) { 3655 case ACB_ADAPTER_TYPE_A: { 3656 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3657 { 3658 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3659 { 3660 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3661 return; 3662 } 3663 UDELAY(15000); /* wait 15 milli-seconds */ 3664 } 3665 } 3666 break; 3667 case ACB_ADAPTER_TYPE_B: { 3668 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3669 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3670 { 3671 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3672 { 3673 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3674 return; 3675 } 3676 UDELAY(15000); /* wait 15 milli-seconds */ 3677 } 3678 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3679 } 3680 break; 3681 case ACB_ADAPTER_TYPE_C: { 3682 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3683 { 3684 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3685 { 3686 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3687 return; 3688 } 3689 UDELAY(15000); /* wait 15 milli-seconds */ 3690 } 3691 } 3692 break; 3693 case ACB_ADAPTER_TYPE_D: { 3694 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3695 { 3696 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3697 { 3698 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3699 return; 3700 } 3701 UDELAY(15000); /* wait 15 milli-seconds */ 3702 } 3703 } 3704 break; 3705 } 3706} 3707/* 3708********************************************************************** 3709********************************************************************** 3710*/ 3711static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3712{ 3713 u_int32_t outbound_doorbell; 3714 3715 switch (acb->adapter_type) { 3716 case ACB_ADAPTER_TYPE_A: { 3717 /* empty doorbell Qbuffer if door bell ringed */ 3718 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3719 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3720 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3721 3722 } 3723 break; 3724 case ACB_ADAPTER_TYPE_B: { 3725 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3726 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3727 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3728 /* let IOP know data has been read */ 3729 } 3730 break; 3731 case ACB_ADAPTER_TYPE_C: { 3732 /* empty doorbell Qbuffer if door bell ringed */ 3733 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3734 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3735 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3736 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3737 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3738 } 3739 break; 3740 case ACB_ADAPTER_TYPE_D: { 3741 /* empty doorbell Qbuffer if door bell ringed */ 3742 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3743 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3744 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3745 3746 } 3747 break; 3748 } 3749} 3750/* 3751************************************************************************ 3752************************************************************************ 3753*/ 3754static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3755{ 3756 unsigned long srb_phyaddr; 3757 u_int32_t srb_phyaddr_hi32; 3758 u_int32_t srb_phyaddr_lo32; 3759 3760 /* 3761 ******************************************************************** 3762 ** here we need to tell iop 331 our freesrb.HighPart 3763 ** if freesrb.HighPart is not zero 3764 ******************************************************************** 3765 */ 3766 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3767 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3768 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3769 switch (acb->adapter_type) { 3770 case ACB_ADAPTER_TYPE_A: { 3771 if(srb_phyaddr_hi32 != 0) { 3772 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3773 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3774 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3775 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3776 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3777 return FALSE; 3778 } 3779 } 3780 } 3781 break; 3782 /* 3783 *********************************************************************** 3784 ** if adapter type B, set window of "post command Q" 3785 *********************************************************************** 3786 */ 3787 case ACB_ADAPTER_TYPE_B: { 3788 u_int32_t post_queue_phyaddr; 3789 struct HBB_MessageUnit *phbbmu; 3790 3791 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3792 phbbmu->postq_index = 0; 3793 phbbmu->doneq_index = 0; 3794 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3795 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3796 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3797 return FALSE; 3798 } 3799 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3800 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3801 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3802 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3803 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3804 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3805 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3806 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3807 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3808 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3809 return FALSE; 3810 } 3811 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3812 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3813 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3814 return FALSE; 3815 } 3816 } 3817 break; 3818 case ACB_ADAPTER_TYPE_C: { 3819 if(srb_phyaddr_hi32 != 0) { 3820 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3821 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3822 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3823 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3824 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3825 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3826 return FALSE; 3827 } 3828 } 3829 } 3830 break; 3831 case ACB_ADAPTER_TYPE_D: { 3832 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3833 struct HBD_MessageUnit0 *phbdmu; 3834 3835 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3836 phbdmu->postq_index = 0; 3837 phbdmu->doneq_index = 0x40FF; 3838 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3839 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3840 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3841 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3842 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3843 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3844 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3845 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3846 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3847 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3848 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3849 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3850 return FALSE; 3851 } 3852 } 3853 break; 3854 } 3855 return (TRUE); 3856} 3857/* 3858************************************************************************ 3859************************************************************************ 3860*/ 3861static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3862{ 3863 switch (acb->adapter_type) 3864 { 3865 case ACB_ADAPTER_TYPE_A: 3866 case ACB_ADAPTER_TYPE_C: 3867 case ACB_ADAPTER_TYPE_D: 3868 break; 3869 case ACB_ADAPTER_TYPE_B: { 3870 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3871 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3872 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3873 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3874 return; 3875 } 3876 } 3877 break; 3878 } 3879} 3880/* 3881********************************************************************** 3882********************************************************************** 3883*/ 3884static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3885{ 3886 u_int32_t intmask_org; 3887 3888 /* disable all outbound interrupt */ 3889 intmask_org = arcmsr_disable_allintr(acb); 3890 arcmsr_wait_firmware_ready(acb); 3891 arcmsr_iop_confirm(acb); 3892 arcmsr_get_firmware_spec(acb); 3893 /*start background rebuild*/ 3894 arcmsr_start_adapter_bgrb(acb); 3895 /* empty doorbell Qbuffer if door bell ringed */ 3896 arcmsr_clear_doorbell_queue_buffer(acb); 3897 arcmsr_enable_eoi_mode(acb); 3898 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3899 arcmsr_enable_allintr(acb, intmask_org); 3900 acb->acb_flags |= ACB_F_IOP_INITED; 3901} 3902/* 3903********************************************************************** 3904********************************************************************** 3905*/ 3906static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3907{ 3908 struct AdapterControlBlock *acb = arg; 3909 struct CommandControlBlock *srb_tmp; 3910 u_int32_t i; 3911 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3912 3913 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3914 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3915 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3916 if(bus_dmamap_create(acb->dm_segs_dmat, 3917 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3918 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3919 printf("arcmsr%d:" 3920 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3921 return; 3922 } 3923 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3924 { 3925 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3926 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3927 } 3928 else 3929 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3930 srb_tmp->acb = acb; 3931 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3932 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3933 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3934 } 3935 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3936} 3937/* 3938************************************************************************ 3939************************************************************************ 3940*/ 3941static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3942{ 3943 /* remove the control device */ 3944 if(acb->ioctl_dev != NULL) { 3945 destroy_dev(acb->ioctl_dev); 3946 } 3947 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3948 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3949 bus_dma_tag_destroy(acb->srb_dmat); 3950 bus_dma_tag_destroy(acb->dm_segs_dmat); 3951 bus_dma_tag_destroy(acb->parent_dmat); 3952} 3953/* 3954************************************************************************ 3955************************************************************************ 3956*/ 3957static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3958{ 3959 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3960 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3961 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3962 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3963} 3964/* 3965************************************************************************ 3966************************************************************************ 3967*/ 3968static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3969{ 3970 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3971 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3972 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3973 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3974} 3975/* 3976************************************************************************ 3977************************************************************************ 3978*/ 3979static u_int32_t arcmsr_initialize(device_t dev) 3980{ 3981 struct AdapterControlBlock *acb = device_get_softc(dev); 3982 u_int16_t pci_command; 3983 int i, j,max_coherent_size; 3984 u_int32_t vendor_dev_id; 3985 3986 vendor_dev_id = pci_get_devid(dev); 3987 acb->vendor_device_id = vendor_dev_id; 3988 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 3989 switch (vendor_dev_id) { 3990 case PCIDevVenIDARC1880: 3991 case PCIDevVenIDARC1882: 3992 case PCIDevVenIDARC1213: 3993 case PCIDevVenIDARC1223: { 3994 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3995 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883) 3996 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 3997 else 3998 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3999 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4000 } 4001 break; 4002 case PCIDevVenIDARC1214: { 4003 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4004 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4005 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4006 } 4007 break; 4008 case PCIDevVenIDARC1200: 4009 case PCIDevVenIDARC1201: { 4010 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4011 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4012 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4013 } 4014 break; 4015 case PCIDevVenIDARC1203: { 4016 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4017 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4018 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4019 } 4020 break; 4021 case PCIDevVenIDARC1110: 4022 case PCIDevVenIDARC1120: 4023 case PCIDevVenIDARC1130: 4024 case PCIDevVenIDARC1160: 4025 case PCIDevVenIDARC1170: 4026 case PCIDevVenIDARC1210: 4027 case PCIDevVenIDARC1220: 4028 case PCIDevVenIDARC1230: 4029 case PCIDevVenIDARC1231: 4030 case PCIDevVenIDARC1260: 4031 case PCIDevVenIDARC1261: 4032 case PCIDevVenIDARC1270: 4033 case PCIDevVenIDARC1280: 4034 case PCIDevVenIDARC1212: 4035 case PCIDevVenIDARC1222: 4036 case PCIDevVenIDARC1380: 4037 case PCIDevVenIDARC1381: 4038 case PCIDevVenIDARC1680: 4039 case PCIDevVenIDARC1681: { 4040 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4041 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4042 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4043 } 4044 break; 4045 default: { 4046 printf("arcmsr%d:" 4047 " unknown RAID adapter type \n", device_get_unit(dev)); 4048 return ENOMEM; 4049 } 4050 } 4051#if __FreeBSD_version >= 700000 4052 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4053#else 4054 if(bus_dma_tag_create( /*PCI parent*/ NULL, 4055#endif 4056 /*alignemnt*/ 1, 4057 /*boundary*/ 0, 4058 /*lowaddr*/ BUS_SPACE_MAXADDR, 4059 /*highaddr*/ BUS_SPACE_MAXADDR, 4060 /*filter*/ NULL, 4061 /*filterarg*/ NULL, 4062 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4063 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4064 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4065 /*flags*/ 0, 4066#if __FreeBSD_version >= 501102 4067 /*lockfunc*/ NULL, 4068 /*lockarg*/ NULL, 4069#endif 4070 &acb->parent_dmat) != 0) 4071 { 4072 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4073 return ENOMEM; 4074 } 4075 4076 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4077 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4078 /*alignment*/ 1, 4079 /*boundary*/ 0, 4080#ifdef PAE 4081 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4082#else 4083 /*lowaddr*/ BUS_SPACE_MAXADDR, 4084#endif 4085 /*highaddr*/ BUS_SPACE_MAXADDR, 4086 /*filter*/ NULL, 4087 /*filterarg*/ NULL, 4088 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4089 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4090 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4091 /*flags*/ 0, 4092#if __FreeBSD_version >= 501102 4093 /*lockfunc*/ busdma_lock_mutex, 4094 /*lockarg*/ &acb->isr_lock, 4095#endif 4096 &acb->dm_segs_dmat) != 0) 4097 { 4098 bus_dma_tag_destroy(acb->parent_dmat); 4099 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4100 return ENOMEM; 4101 } 4102 4103 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4104 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4105 /*alignment*/ 0x20, 4106 /*boundary*/ 0, 4107 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4108 /*highaddr*/ BUS_SPACE_MAXADDR, 4109 /*filter*/ NULL, 4110 /*filterarg*/ NULL, 4111 /*maxsize*/ max_coherent_size, 4112 /*nsegments*/ 1, 4113 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4114 /*flags*/ 0, 4115#if __FreeBSD_version >= 501102 4116 /*lockfunc*/ NULL, 4117 /*lockarg*/ NULL, 4118#endif 4119 &acb->srb_dmat) != 0) 4120 { 4121 bus_dma_tag_destroy(acb->dm_segs_dmat); 4122 bus_dma_tag_destroy(acb->parent_dmat); 4123 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4124 return ENXIO; 4125 } 4126 /* Allocation for our srbs */ 4127 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4128 bus_dma_tag_destroy(acb->srb_dmat); 4129 bus_dma_tag_destroy(acb->dm_segs_dmat); 4130 bus_dma_tag_destroy(acb->parent_dmat); 4131 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4132 return ENXIO; 4133 } 4134 /* And permanently map them */ 4135 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4136 bus_dma_tag_destroy(acb->srb_dmat); 4137 bus_dma_tag_destroy(acb->dm_segs_dmat); 4138 bus_dma_tag_destroy(acb->parent_dmat); 4139 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4140 return ENXIO; 4141 } 4142 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4143 pci_command |= PCIM_CMD_BUSMASTEREN; 4144 pci_command |= PCIM_CMD_PERRESPEN; 4145 pci_command |= PCIM_CMD_MWRICEN; 4146 /* Enable Busmaster */ 4147 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4148 switch(acb->adapter_type) { 4149 case ACB_ADAPTER_TYPE_A: { 4150 u_int32_t rid0 = PCIR_BAR(0); 4151 vm_offset_t mem_base0; 4152 4153 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4154 if(acb->sys_res_arcmsr[0] == NULL) { 4155 arcmsr_free_resource(acb); 4156 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4157 return ENOMEM; 4158 } 4159 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4160 arcmsr_free_resource(acb); 4161 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4162 return ENXIO; 4163 } 4164 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4165 if(mem_base0 == 0) { 4166 arcmsr_free_resource(acb); 4167 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4168 return ENXIO; 4169 } 4170 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4171 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4172 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4173 } 4174 break; 4175 case ACB_ADAPTER_TYPE_B: { 4176 struct HBB_MessageUnit *phbbmu; 4177 struct CommandControlBlock *freesrb; 4178 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4179 vm_offset_t mem_base[]={0,0}; 4180 u_long size; 4181 if (vendor_dev_id == PCIDevVenIDARC1203) 4182 size = sizeof(struct HBB_DOORBELL_1203); 4183 else 4184 size = sizeof(struct HBB_DOORBELL); 4185 for(i=0; i < 2; i++) { 4186 if(i == 0) { 4187 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid[i], 4188 RF_ACTIVE); 4189 } else { 4190 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], 4191 RF_ACTIVE); 4192 } 4193 if(acb->sys_res_arcmsr[i] == NULL) { 4194 arcmsr_free_resource(acb); 4195 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4196 return ENOMEM; 4197 } 4198 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4199 arcmsr_free_resource(acb); 4200 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4201 return ENXIO; 4202 } 4203 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4204 if(mem_base[i] == 0) { 4205 arcmsr_free_resource(acb); 4206 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4207 return ENXIO; 4208 } 4209 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4210 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4211 } 4212 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4213 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4214 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4215 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4216 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4217 if (vendor_dev_id == PCIDevVenIDARC1203) { 4218 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4219 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4220 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4221 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4222 } else { 4223 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4224 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4225 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4226 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4227 } 4228 } 4229 break; 4230 case ACB_ADAPTER_TYPE_C: { 4231 u_int32_t rid0 = PCIR_BAR(1); 4232 vm_offset_t mem_base0; 4233 4234 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4235 if(acb->sys_res_arcmsr[0] == NULL) { 4236 arcmsr_free_resource(acb); 4237 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4238 return ENOMEM; 4239 } 4240 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4241 arcmsr_free_resource(acb); 4242 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4243 return ENXIO; 4244 } 4245 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4246 if(mem_base0 == 0) { 4247 arcmsr_free_resource(acb); 4248 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4249 return ENXIO; 4250 } 4251 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4252 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4253 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4254 } 4255 break; 4256 case ACB_ADAPTER_TYPE_D: { 4257 struct HBD_MessageUnit0 *phbdmu; 4258 u_int32_t rid0 = PCIR_BAR(0); 4259 vm_offset_t mem_base0; 4260 4261 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4262 if(acb->sys_res_arcmsr[0] == NULL) { 4263 arcmsr_free_resource(acb); 4264 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4265 return ENOMEM; 4266 } 4267 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4268 arcmsr_free_resource(acb); 4269 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4270 return ENXIO; 4271 } 4272 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4273 if(mem_base0 == 0) { 4274 arcmsr_free_resource(acb); 4275 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4276 return ENXIO; 4277 } 4278 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4279 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4280 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4281 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4282 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4283 } 4284 break; 4285 } 4286 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4287 arcmsr_free_resource(acb); 4288 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4289 return ENXIO; 4290 } 4291 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4292 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4293 /* 4294 ******************************************************************** 4295 ** init raid volume state 4296 ******************************************************************** 4297 */ 4298 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4299 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4300 acb->devstate[i][j] = ARECA_RAID_GONE; 4301 } 4302 } 4303 arcmsr_iop_init(acb); 4304 return(0); 4305} 4306/* 4307************************************************************************ 4308************************************************************************ 4309*/ 4310static int arcmsr_attach(device_t dev) 4311{ 4312 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4313 u_int32_t unit=device_get_unit(dev); 4314 struct ccb_setasync csa; 4315 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4316 struct resource *irqres; 4317 int rid; 4318 4319 if(acb == NULL) { 4320 printf("arcmsr%d: cannot allocate softc\n", unit); 4321 return (ENOMEM); 4322 } 4323 arcmsr_mutex_init(acb); 4324 acb->pci_dev = dev; 4325 acb->pci_unit = unit; 4326 if(arcmsr_initialize(dev)) { 4327 printf("arcmsr%d: initialize failure!\n", unit); 4328 arcmsr_mutex_destroy(acb); 4329 return ENXIO; 4330 } 4331 /* After setting up the adapter, map our interrupt */ 4332 rid = 0; 4333 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4334 if(irqres == NULL || 4335#if __FreeBSD_version >= 700025 4336 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4337#else 4338 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4339#endif 4340 arcmsr_free_resource(acb); 4341 arcmsr_mutex_destroy(acb); 4342 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4343 return ENXIO; 4344 } 4345 acb->irqres = irqres; 4346 /* 4347 * Now let the CAM generic SCSI layer find the SCSI devices on 4348 * the bus * start queue to reset to the idle loop. * 4349 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4350 * max_sim_transactions 4351 */ 4352 devq = cam_simq_alloc(acb->maxOutstanding); 4353 if(devq == NULL) { 4354 arcmsr_free_resource(acb); 4355 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4356 arcmsr_mutex_destroy(acb); 4357 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4358 return ENXIO; 4359 } 4360#if __FreeBSD_version >= 700025 4361 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4362#else 4363 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4364#endif 4365 if(acb->psim == NULL) { 4366 arcmsr_free_resource(acb); 4367 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4368 cam_simq_free(devq); 4369 arcmsr_mutex_destroy(acb); 4370 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4371 return ENXIO; 4372 } 4373 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4374#if __FreeBSD_version >= 700044 4375 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4376#else 4377 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4378#endif 4379 arcmsr_free_resource(acb); 4380 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4381 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4382 arcmsr_mutex_destroy(acb); 4383 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4384 return ENXIO; 4385 } 4386 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4387 arcmsr_free_resource(acb); 4388 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4389 xpt_bus_deregister(cam_sim_path(acb->psim)); 4390 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4391 arcmsr_mutex_destroy(acb); 4392 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4393 return ENXIO; 4394 } 4395 /* 4396 **************************************************** 4397 */ 4398 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4399 csa.ccb_h.func_code = XPT_SASYNC_CB; 4400 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4401 csa.callback = arcmsr_async; 4402 csa.callback_arg = acb->psim; 4403 xpt_action((union ccb *)&csa); 4404 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4405 /* Create the control device. */ 4406 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4407 4408#if __FreeBSD_version < 503000 4409 acb->ioctl_dev->si_drv1 = acb; 4410#endif 4411#if __FreeBSD_version > 500005 4412 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4413#endif 4414 arcmsr_callout_init(&acb->devmap_callout); 4415 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4416 return (0); 4417} 4418 4419/* 4420************************************************************************ 4421************************************************************************ 4422*/ 4423static int arcmsr_probe(device_t dev) 4424{ 4425 u_int32_t id; 4426 u_int16_t sub_device_id; 4427 static char buf[256]; 4428 char x_type[]={"unknown"}; 4429 char *type; 4430 int raid6 = 1; 4431 4432 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4433 return (ENXIO); 4434 } 4435 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4436 switch(id = pci_get_devid(dev)) { 4437 case PCIDevVenIDARC1110: 4438 case PCIDevVenIDARC1200: 4439 case PCIDevVenIDARC1201: 4440 case PCIDevVenIDARC1210: 4441 raid6 = 0; 4442 /*FALLTHRU*/ 4443 case PCIDevVenIDARC1120: 4444 case PCIDevVenIDARC1130: 4445 case PCIDevVenIDARC1160: 4446 case PCIDevVenIDARC1170: 4447 case PCIDevVenIDARC1220: 4448 case PCIDevVenIDARC1230: 4449 case PCIDevVenIDARC1231: 4450 case PCIDevVenIDARC1260: 4451 case PCIDevVenIDARC1261: 4452 case PCIDevVenIDARC1270: 4453 case PCIDevVenIDARC1280: 4454 type = "SATA 3G"; 4455 break; 4456 case PCIDevVenIDARC1212: 4457 case PCIDevVenIDARC1222: 4458 case PCIDevVenIDARC1380: 4459 case PCIDevVenIDARC1381: 4460 case PCIDevVenIDARC1680: 4461 case PCIDevVenIDARC1681: 4462 type = "SAS 3G"; 4463 break; 4464 case PCIDevVenIDARC1880: 4465 case PCIDevVenIDARC1882: 4466 case PCIDevVenIDARC1213: 4467 case PCIDevVenIDARC1223: 4468 if (sub_device_id == ARECA_SUB_DEV_ID_1883) 4469 type = "SAS 12G"; 4470 else 4471 type = "SAS 6G"; 4472 break; 4473 case PCIDevVenIDARC1214: 4474 case PCIDevVenIDARC1203: 4475 type = "SATA 6G"; 4476 break; 4477 default: 4478 type = x_type; 4479 raid6 = 0; 4480 break; 4481 } 4482 if(type == x_type) 4483 return(ENXIO); 4484 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 4485 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4486 device_set_desc_copy(dev, buf); 4487 return (BUS_PROBE_DEFAULT); 4488} 4489/* 4490************************************************************************ 4491************************************************************************ 4492*/ 4493static int arcmsr_shutdown(device_t dev) 4494{ 4495 u_int32_t i; 4496 u_int32_t intmask_org; 4497 struct CommandControlBlock *srb; 4498 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4499 4500 /* stop adapter background rebuild */ 4501 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4502 /* disable all outbound interrupt */ 4503 intmask_org = arcmsr_disable_allintr(acb); 4504 arcmsr_stop_adapter_bgrb(acb); 4505 arcmsr_flush_adapter_cache(acb); 4506 /* abort all outstanding command */ 4507 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4508 acb->acb_flags &= ~ACB_F_IOP_INITED; 4509 if(acb->srboutstandingcount != 0) { 4510 /*clear and abort all outbound posted Q*/ 4511 arcmsr_done4abort_postqueue(acb); 4512 /* talk to iop 331 outstanding command aborted*/ 4513 arcmsr_abort_allcmd(acb); 4514 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4515 srb = acb->psrb_pool[i]; 4516 if(srb->srb_state == ARCMSR_SRB_START) { 4517 srb->srb_state = ARCMSR_SRB_ABORTED; 4518 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4519 arcmsr_srb_complete(srb, 1); 4520 } 4521 } 4522 } 4523 acb->srboutstandingcount = 0; 4524 acb->workingsrb_doneindex = 0; 4525 acb->workingsrb_startindex = 0; 4526 acb->pktRequestCount = 0; 4527 acb->pktReturnCount = 0; 4528 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4529 return (0); 4530} 4531/* 4532************************************************************************ 4533************************************************************************ 4534*/ 4535static int arcmsr_detach(device_t dev) 4536{ 4537 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4538 int i; 4539 4540 callout_stop(&acb->devmap_callout); 4541 bus_teardown_intr(dev, acb->irqres, acb->ih); 4542 arcmsr_shutdown(dev); 4543 arcmsr_free_resource(acb); 4544 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4545 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4546 } 4547 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4548 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4549 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4550 xpt_free_path(acb->ppath); 4551 xpt_bus_deregister(cam_sim_path(acb->psim)); 4552 cam_sim_free(acb->psim, TRUE); 4553 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4554 arcmsr_mutex_destroy(acb); 4555 return (0); 4556} 4557 4558#ifdef ARCMSR_DEBUG1 4559static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4560{ 4561 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4562 return; 4563 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4564 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4565 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4566 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4567} 4568#endif 4569 4570