14Srgrimes/***********************license start***************
24Srgrimes * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
34Srgrimes * reserved.
44Srgrimes *
54Srgrimes *
64Srgrimes * Redistribution and use in source and binary forms, with or without
74Srgrimes * modification, are permitted provided that the following conditions are
84Srgrimes * met:
94Srgrimes *
104Srgrimes *   * Redistributions of source code must retain the above copyright
114Srgrimes *     notice, this list of conditions and the following disclaimer.
124Srgrimes *
134Srgrimes *   * Redistributions in binary form must reproduce the above
144Srgrimes *     copyright notice, this list of conditions and the following
154Srgrimes *     disclaimer in the documentation and/or other materials provided
164Srgrimes *     with the distribution.
174Srgrimes
184Srgrimes *   * Neither the name of Cavium Inc. nor the names of
194Srgrimes *     its contributors may be used to endorse or promote products
204Srgrimes *     derived from this software without specific prior written
214Srgrimes *     permission.
224Srgrimes
234Srgrimes * This Software, including technical data, may be subject to U.S. export  control
244Srgrimes * laws, including the U.S. Export Administration Act and its  associated
254Srgrimes * regulations, and may be subject to export or import  regulations in other
264Srgrimes * countries.
274Srgrimes
284Srgrimes * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
294Srgrimes * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
304Srgrimes * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
314Srgrimes * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32619Srgrimes * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
3350477Speter * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
344Srgrimes * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
354Srgrimes * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36720Swollman * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37720Swollman * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38720Swollman ***********************license end**************************************/
394Srgrimes
4037556Sphk
414Srgrimes
424Srgrimes
434Srgrimes
444Srgrimes
454Srgrimes
464Srgrimes
474Srgrimes#ifndef __OCTEON_PCI_CONSOLE_H__
484Srgrimes#define __OCTEON_PCI_CONSOLE_H__
494Srgrimes
504Srgrimes#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
514Srgrimes#include "cvmx-platform.h"
524Srgrimes#endif
532074Swollman
544Srgrimes/* Current versions */
554Srgrimes#define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1
5637556Sphk#define OCTEON_PCI_CONSOLE_MINOR_VERSION    0
572074Swollman
5837556Sphk#define OCTEON_PCI_CONSOLE_BLOCK_NAME   "__pci_console"
592074Swollman
602074Swollman
612074Swollman/* Structure that defines a single console.
622074Swollman
632074Swollman
642074Swollman* Note: when read_index == write_index, the buffer is empty.  The actual usable size
652074Swollman*       of each console is console_buf_size -1;
662074Swollman*/
672074Swollmantypedef struct {
682074Swollman    uint64_t input_base_addr;
692074Swollman    uint32_t input_read_index;
7037556Sphk    uint32_t input_write_index;
714Srgrimes    uint64_t output_base_addr;
724Srgrimes    uint32_t output_read_index;
7337556Sphk    uint32_t output_write_index;
742913Sache    uint32_t lock;
752913Sache    uint32_t buf_size;
762913Sache} octeon_pci_console_t;
772913Sache
782913Sache
792913Sache/* This is the main container structure that contains all the information
802074Swollmanabout all PCI consoles.  The address of this structure is passed to various
814Srgrimesroutines that operation on PCI consoles.
824Srgrimes*/
834Srgrimestypedef struct {
844Srgrimes    uint32_t major_version;
854Srgrimes    uint32_t minor_version;
864Srgrimes    uint32_t lock;
874Srgrimes    uint32_t flags;
884Srgrimes    uint32_t num_consoles;
8937556Sphk    uint32_t pad;
904Srgrimes    /* must be 64 bit aligned here... */
914Srgrimes    uint64_t console_addr_array[0];  /* Array of addresses of octeon_pci_console_t structures */
924Srgrimes    /* Implicit storage for console_addr_array */
934Srgrimes} octeon_pci_console_desc_t;
944Srgrimes
954Srgrimes
964Srgrimes/* Flag definitions for octeon_pci_console_desc_t */
974Srgrimesenum {
984Srgrimes    OCT_PCI_CON_DESC_FLAG_PERCPU = 1 << 0,  /* If set, output from core N will be sent to console N */
994Srgrimes};
1004Srgrimes
1014Srgrimes#if defined(OCTEON_TARGET) && !defined(__linux__)
102873Sache/**
1034Srgrimes * This is an internal-only function that is called from within the simple executive
10411375Sjoerg * C library, and is not intended for any other use.
1054968Sjoerg *
1064Srgrimes * @param fd
1074Srgrimes * @param buf
1084Srgrimes * @param nbytes
1094Srgrimes *
1104Srgrimes * @return
1114Srgrimes */
1122913Sacheint  __cvmx_pci_console_write (int fd, char *buf, int nbytes);
113178192Sphk#endif
114178192Sphk
115178192Sphk
116178192Sphk#ifdef CVMX_BUILD_FOR_UBOOT
117178192Sphkuint64_t octeon_pci_console_init(int num_consoles, int buffer_size);
118178192Sphk#endif
119178192Sphk
120178192Sphk/* Flag definitions for read/write functions */
121178192Sphkenum {
122178192Sphk    OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,  /* If set, read/write functions won't block waiting for space or data.
123178192Sphk                                          * For reads, 0 bytes may be read, and for writes not all of the
124720Swollman                                          * supplied data may be written.*/
125};
126
127#if !defined(__linux__) || defined(__KERNEL__)
128int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags);
129int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num);
130
131int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags);
132int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num);
133#endif
134
135#if !defined(OCTEON_TARGET) && defined(__linux__) && !defined(__KERNEL__)
136int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags);
137int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num);
138
139int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags);
140int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num);
141#endif
142#endif
143