1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-usbnx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon usbnx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_USBNX_DEFS_H__ 53232812Sjmallett#define __CVMX_USBNX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64215976Sjmallett cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id) 72215976Sjmallett{ 73215976Sjmallett if (!( 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79215976Sjmallett cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94215976Sjmallett cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id) 102215976Sjmallett{ 103215976Sjmallett if (!( 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 121215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 122215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 124215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull; 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id) 132215976Sjmallett{ 133215976Sjmallett if (!( 134215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 139215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull; 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id) 147215976Sjmallett{ 148215976Sjmallett if (!( 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull; 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id) 162215976Sjmallett{ 163215976Sjmallett if (!( 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 169215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 184215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id) 192215976Sjmallett{ 193215976Sjmallett if (!( 194215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 197215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 198215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 199215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull; 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id) 207215976Sjmallett{ 208215976Sjmallett if (!( 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 229215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 244215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id) 252215976Sjmallett{ 253215976Sjmallett if (!( 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull) 264215976Sjmallett#endif 265215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id) 267215976Sjmallett{ 268215976Sjmallett if (!( 269215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id) 282215976Sjmallett{ 283215976Sjmallett if (!( 284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id); 290215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id) 297215976Sjmallett{ 298215976Sjmallett if (!( 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id); 320215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull; 321215976Sjmallett} 322215976Sjmallett#else 323215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull) 324215976Sjmallett#endif 325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id) 327215976Sjmallett{ 328215976Sjmallett if (!( 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id) 342215976Sjmallett{ 343215976Sjmallett if (!( 344215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349215976Sjmallett cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id) 357215976Sjmallett{ 358215976Sjmallett if (!( 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364215976Sjmallett cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull; 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id) 372215976Sjmallett{ 373215976Sjmallett if (!( 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379215976Sjmallett cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394215976Sjmallett cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 395215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull) 399215976Sjmallett#endif 400215976Sjmallett 401215976Sjmallett/** 402215976Sjmallett * cvmx_usbn#_bist_status 403215976Sjmallett * 404215976Sjmallett * USBN_BIST_STATUS = USBN's Control and Status 405215976Sjmallett * 406215976Sjmallett * Contain general control bits and status information for the USBN. 407215976Sjmallett */ 408232812Sjmallettunion cvmx_usbnx_bist_status { 409215976Sjmallett uint64_t u64; 410232812Sjmallett struct cvmx_usbnx_bist_status_s { 411232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 412215976Sjmallett uint64_t reserved_7_63 : 57; 413215976Sjmallett uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */ 414215976Sjmallett uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */ 415215976Sjmallett uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */ 416215976Sjmallett uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */ 417215976Sjmallett uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 418215976Sjmallett uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 419215976Sjmallett uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 420215976Sjmallett#else 421215976Sjmallett uint64_t nof_bis : 1; 422215976Sjmallett uint64_t nif_bis : 1; 423215976Sjmallett uint64_t usbc_bis : 1; 424215976Sjmallett uint64_t n2uf_bis : 1; 425215976Sjmallett uint64_t e2hc_bis : 1; 426215976Sjmallett uint64_t u2nf_bis : 1; 427215976Sjmallett uint64_t u2nc_bis : 1; 428215976Sjmallett uint64_t reserved_7_63 : 57; 429215976Sjmallett#endif 430215976Sjmallett } s; 431232812Sjmallett struct cvmx_usbnx_bist_status_cn30xx { 432232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 433215976Sjmallett uint64_t reserved_3_63 : 61; 434215976Sjmallett uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 435215976Sjmallett uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 436215976Sjmallett uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 437215976Sjmallett#else 438215976Sjmallett uint64_t nof_bis : 1; 439215976Sjmallett uint64_t nif_bis : 1; 440215976Sjmallett uint64_t usbc_bis : 1; 441215976Sjmallett uint64_t reserved_3_63 : 61; 442215976Sjmallett#endif 443215976Sjmallett } cn30xx; 444215976Sjmallett struct cvmx_usbnx_bist_status_cn30xx cn31xx; 445215976Sjmallett struct cvmx_usbnx_bist_status_s cn50xx; 446215976Sjmallett struct cvmx_usbnx_bist_status_s cn52xx; 447215976Sjmallett struct cvmx_usbnx_bist_status_s cn52xxp1; 448215976Sjmallett struct cvmx_usbnx_bist_status_s cn56xx; 449215976Sjmallett struct cvmx_usbnx_bist_status_s cn56xxp1; 450215976Sjmallett}; 451215976Sjmalletttypedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t; 452215976Sjmallett 453215976Sjmallett/** 454215976Sjmallett * cvmx_usbn#_clk_ctl 455215976Sjmallett * 456215976Sjmallett * USBN_CLK_CTL = USBN's Clock Control 457215976Sjmallett * 458215976Sjmallett * This register is used to control the frequency of the hclk and the hreset and phy_rst signals. 459215976Sjmallett */ 460232812Sjmallettunion cvmx_usbnx_clk_ctl { 461215976Sjmallett uint64_t u64; 462232812Sjmallett struct cvmx_usbnx_clk_ctl_s { 463232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 464215976Sjmallett uint64_t reserved_20_63 : 44; 465215976Sjmallett uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 466215976Sjmallett from the eclk. 467215976Sjmallett Also see the field DIVIDE. DIVIDE2<1> must currently 468215976Sjmallett be zero because it is not implemented, so the maximum 469215976Sjmallett ratio of eclk/hclk is currently 16. 470215976Sjmallett The actual divide number for hclk is: 471215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1) */ 472215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 473215976Sjmallett generate the hclk in the USB Subsystem is held 474215976Sjmallett in reset. This bit must be set to '0' before 475215976Sjmallett changing the value os DIVIDE in this register. 476215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 477215976Sjmallett when core reset is asserted. */ 478215976Sjmallett uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 479215976Sjmallett '1' USB-PHY XO block is powered-down during 480215976Sjmallett suspend. 481215976Sjmallett '0' USB-PHY XO block is powered-up during 482215976Sjmallett suspend. 483215976Sjmallett The value of this field must be set while POR is 484215976Sjmallett active. */ 485215976Sjmallett uint64_t reserved_14_15 : 2; 486215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 487215976Sjmallett remain powered in Suspend Mode. 488215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 489215976Sjmallett powered down in suspend mode. 490215976Sjmallett The value of this field must be set while POR is 491215976Sjmallett active. */ 492215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 493215976Sjmallett Selects the reference clock / crystal frequency. 494215976Sjmallett '11': Reserved 495215976Sjmallett '10': 48 MHz (reserved when a crystal is used) 496215976Sjmallett '01': 24 MHz (reserved when a crystal is used) 497215976Sjmallett '00': 12 MHz 498215976Sjmallett The value of this field must be set while POR is 499215976Sjmallett active. 500215976Sjmallett NOTE: if a crystal is used as a reference clock, 501215976Sjmallett this field must be set to 12 MHz. */ 502215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 503215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 504215976Sjmallett in the USBC, for normal operation this must be '0'. */ 505215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 506215976Sjmallett to '1' transition. */ 507215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 508215976Sjmallett Resets all the PHYS registers and state machines. */ 509215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 510215976Sjmallett '0' the hclk will not be generated. SEE DIVIDE 511215976Sjmallett field of this register. */ 512215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 513215976Sjmallett the phy_clk functionality in the USB Subsystem is 514215976Sjmallett help in reset. This bit should not be set to '1' 515215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 516215976Sjmallett whichever is slower) has passed. Under normal 517215976Sjmallett operation once this bit is set to '1' it should not 518215976Sjmallett be set to '0'. */ 519215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 520215976Sjmallett the hclk functioanlity in the USB Subsystem is 521215976Sjmallett held in reset.This bit should not be set to '1' 522215976Sjmallett until 12ms after phy_clk is stable. Under normal 523215976Sjmallett operation, once this bit is set to '1' it should 524215976Sjmallett not be set to '0'. */ 525215976Sjmallett uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 526215976Sjmallett is the eclk frequency divided by the value of 527215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 528215976Sjmallett DIVIDE2 of this register. 529215976Sjmallett The hclk frequency should be less than 125Mhz. 530215976Sjmallett After writing a value to this field the SW should 531215976Sjmallett read the field for the value written. 532215976Sjmallett The ENABLE field of this register should not be set 533215976Sjmallett until AFTER this field is set and then read. */ 534215976Sjmallett#else 535215976Sjmallett uint64_t divide : 3; 536215976Sjmallett uint64_t hrst : 1; 537215976Sjmallett uint64_t prst : 1; 538215976Sjmallett uint64_t enable : 1; 539215976Sjmallett uint64_t por : 1; 540215976Sjmallett uint64_t s_bist : 1; 541215976Sjmallett uint64_t sd_mode : 2; 542215976Sjmallett uint64_t cdiv_byp : 1; 543215976Sjmallett uint64_t p_c_sel : 2; 544215976Sjmallett uint64_t p_com_on : 1; 545215976Sjmallett uint64_t reserved_14_15 : 2; 546215976Sjmallett uint64_t p_x_on : 1; 547215976Sjmallett uint64_t hclk_rst : 1; 548215976Sjmallett uint64_t divide2 : 2; 549215976Sjmallett uint64_t reserved_20_63 : 44; 550215976Sjmallett#endif 551215976Sjmallett } s; 552232812Sjmallett struct cvmx_usbnx_clk_ctl_cn30xx { 553232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 554215976Sjmallett uint64_t reserved_18_63 : 46; 555215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 556215976Sjmallett generate the hclk in the USB Subsystem is held 557215976Sjmallett in reset. This bit must be set to '0' before 558215976Sjmallett changing the value os DIVIDE in this register. 559215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 560215976Sjmallett when core reset is asserted. */ 561215976Sjmallett uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 562215976Sjmallett '1' USB-PHY XO block is powered-down during 563215976Sjmallett suspend. 564215976Sjmallett '0' USB-PHY XO block is powered-up during 565215976Sjmallett suspend. 566215976Sjmallett The value of this field must be set while POR is 567215976Sjmallett active. */ 568215976Sjmallett uint64_t p_rclk : 1; /**< Phy refrence clock enable. 569215976Sjmallett '1' The PHY PLL uses the XO block output as a 570215976Sjmallett reference. 571215976Sjmallett '0' Reserved. */ 572215976Sjmallett uint64_t p_xenbn : 1; /**< Phy external clock enable. 573215976Sjmallett '1' The XO block uses the clock from a crystal. 574215976Sjmallett '0' The XO block uses an external clock supplied 575215976Sjmallett on the XO pin. USB_XI should be tied to 576215976Sjmallett ground for this usage. */ 577215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 578215976Sjmallett remain powered in Suspend Mode. 579215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 580215976Sjmallett powered down in suspend mode. 581215976Sjmallett The value of this field must be set while POR is 582215976Sjmallett active. */ 583215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 584215976Sjmallett Selects the reference clock / crystal frequency. 585215976Sjmallett '11': Reserved 586215976Sjmallett '10': 48 MHz 587215976Sjmallett '01': 24 MHz 588215976Sjmallett '00': 12 MHz 589215976Sjmallett The value of this field must be set while POR is 590215976Sjmallett active. */ 591215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 592215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 593215976Sjmallett in the USBC, for normal operation this must be '0'. */ 594215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 595215976Sjmallett to '1' transition. */ 596215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 597215976Sjmallett Resets all the PHYS registers and state machines. */ 598215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 599215976Sjmallett '0' the hclk will not be generated. */ 600215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 601215976Sjmallett the phy_clk functionality in the USB Subsystem is 602215976Sjmallett help in reset. This bit should not be set to '1' 603215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 604215976Sjmallett whichever is slower) has passed. Under normal 605215976Sjmallett operation once this bit is set to '1' it should not 606215976Sjmallett be set to '0'. */ 607215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 608215976Sjmallett the hclk functioanlity in the USB Subsystem is 609215976Sjmallett held in reset.This bit should not be set to '1' 610215976Sjmallett until 12ms after phy_clk is stable. Under normal 611215976Sjmallett operation, once this bit is set to '1' it should 612215976Sjmallett not be set to '0'. */ 613215976Sjmallett uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived 614215976Sjmallett from the eclk. The eclk will be divided by the 615215976Sjmallett value of this field +1 to determine the hclk 616215976Sjmallett frequency. (Also see HRST of this register). 617215976Sjmallett The hclk frequency must be less than 125 MHz. */ 618215976Sjmallett#else 619215976Sjmallett uint64_t divide : 3; 620215976Sjmallett uint64_t hrst : 1; 621215976Sjmallett uint64_t prst : 1; 622215976Sjmallett uint64_t enable : 1; 623215976Sjmallett uint64_t por : 1; 624215976Sjmallett uint64_t s_bist : 1; 625215976Sjmallett uint64_t sd_mode : 2; 626215976Sjmallett uint64_t cdiv_byp : 1; 627215976Sjmallett uint64_t p_c_sel : 2; 628215976Sjmallett uint64_t p_com_on : 1; 629215976Sjmallett uint64_t p_xenbn : 1; 630215976Sjmallett uint64_t p_rclk : 1; 631215976Sjmallett uint64_t p_x_on : 1; 632215976Sjmallett uint64_t hclk_rst : 1; 633215976Sjmallett uint64_t reserved_18_63 : 46; 634215976Sjmallett#endif 635215976Sjmallett } cn30xx; 636215976Sjmallett struct cvmx_usbnx_clk_ctl_cn30xx cn31xx; 637232812Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx { 638232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 639215976Sjmallett uint64_t reserved_20_63 : 44; 640215976Sjmallett uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 641215976Sjmallett from the eclk. 642215976Sjmallett Also see the field DIVIDE. DIVIDE2<1> must currently 643215976Sjmallett be zero because it is not implemented, so the maximum 644215976Sjmallett ratio of eclk/hclk is currently 16. 645215976Sjmallett The actual divide number for hclk is: 646215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1) */ 647215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 648215976Sjmallett generate the hclk in the USB Subsystem is held 649215976Sjmallett in reset. This bit must be set to '0' before 650215976Sjmallett changing the value os DIVIDE in this register. 651215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 652215976Sjmallett when core reset is asserted. */ 653215976Sjmallett uint64_t reserved_16_16 : 1; 654215976Sjmallett uint64_t p_rtype : 2; /**< PHY reference clock type 655215976Sjmallett '0' The USB-PHY uses a 12MHz crystal as a clock 656215976Sjmallett source at the USB_XO and USB_XI pins 657215976Sjmallett '1' Reserved 658215976Sjmallett '2' The USB_PHY uses 12/24/48MHz 2.5V board clock 659215976Sjmallett at the USB_XO pin. USB_XI should be tied to 660215976Sjmallett ground in this case. 661215976Sjmallett '3' Reserved 662215976Sjmallett (bit 14 was P_XENBN on 3xxx) 663215976Sjmallett (bit 15 was P_RCLK on 3xxx) */ 664215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 665215976Sjmallett remain powered in Suspend Mode. 666215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 667215976Sjmallett powered down in suspend mode. 668215976Sjmallett The value of this field must be set while POR is 669215976Sjmallett active. */ 670215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 671215976Sjmallett Selects the reference clock / crystal frequency. 672215976Sjmallett '11': Reserved 673215976Sjmallett '10': 48 MHz (reserved when a crystal is used) 674215976Sjmallett '01': 24 MHz (reserved when a crystal is used) 675215976Sjmallett '00': 12 MHz 676215976Sjmallett The value of this field must be set while POR is 677215976Sjmallett active. 678215976Sjmallett NOTE: if a crystal is used as a reference clock, 679215976Sjmallett this field must be set to 12 MHz. */ 680215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 681215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 682215976Sjmallett in the USBC, for normal operation this must be '0'. */ 683215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 684215976Sjmallett to '1' transition. */ 685215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 686215976Sjmallett Resets all the PHYS registers and state machines. */ 687215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 688215976Sjmallett '0' the hclk will not be generated. SEE DIVIDE 689215976Sjmallett field of this register. */ 690215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 691215976Sjmallett the phy_clk functionality in the USB Subsystem is 692215976Sjmallett help in reset. This bit should not be set to '1' 693215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 694215976Sjmallett whichever is slower) has passed. Under normal 695215976Sjmallett operation once this bit is set to '1' it should not 696215976Sjmallett be set to '0'. */ 697215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 698215976Sjmallett the hclk functioanlity in the USB Subsystem is 699215976Sjmallett held in reset.This bit should not be set to '1' 700215976Sjmallett until 12ms after phy_clk is stable. Under normal 701215976Sjmallett operation, once this bit is set to '1' it should 702215976Sjmallett not be set to '0'. */ 703215976Sjmallett uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 704215976Sjmallett is the eclk frequency divided by the value of 705215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 706215976Sjmallett DIVIDE2 of this register. 707215976Sjmallett The hclk frequency should be less than 125Mhz. 708215976Sjmallett After writing a value to this field the SW should 709215976Sjmallett read the field for the value written. 710215976Sjmallett The ENABLE field of this register should not be set 711215976Sjmallett until AFTER this field is set and then read. */ 712215976Sjmallett#else 713215976Sjmallett uint64_t divide : 3; 714215976Sjmallett uint64_t hrst : 1; 715215976Sjmallett uint64_t prst : 1; 716215976Sjmallett uint64_t enable : 1; 717215976Sjmallett uint64_t por : 1; 718215976Sjmallett uint64_t s_bist : 1; 719215976Sjmallett uint64_t sd_mode : 2; 720215976Sjmallett uint64_t cdiv_byp : 1; 721215976Sjmallett uint64_t p_c_sel : 2; 722215976Sjmallett uint64_t p_com_on : 1; 723215976Sjmallett uint64_t p_rtype : 2; 724215976Sjmallett uint64_t reserved_16_16 : 1; 725215976Sjmallett uint64_t hclk_rst : 1; 726215976Sjmallett uint64_t divide2 : 2; 727215976Sjmallett uint64_t reserved_20_63 : 44; 728215976Sjmallett#endif 729215976Sjmallett } cn50xx; 730215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn52xx; 731215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1; 732215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn56xx; 733215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1; 734215976Sjmallett}; 735215976Sjmalletttypedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t; 736215976Sjmallett 737215976Sjmallett/** 738215976Sjmallett * cvmx_usbn#_ctl_status 739215976Sjmallett * 740215976Sjmallett * USBN_CTL_STATUS = USBN's Control And Status Register 741215976Sjmallett * 742215976Sjmallett * Contains general control and status information for the USBN block. 743215976Sjmallett */ 744232812Sjmallettunion cvmx_usbnx_ctl_status { 745215976Sjmallett uint64_t u64; 746232812Sjmallett struct cvmx_usbnx_ctl_status_s { 747232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 748215976Sjmallett uint64_t reserved_6_63 : 58; 749215976Sjmallett uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page 750215976Sjmallett bit in the L2C store operation to the IOB. */ 751215976Sjmallett uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */ 752215976Sjmallett uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode. 753215976Sjmallett For normal operation this bit should be '0'. */ 754215976Sjmallett uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB 755215976Sjmallett for USB-CORE FIFO access to be inverted. Also data 756215976Sjmallett writen to and read from the AHB will have it byte 757215976Sjmallett order swapped. If the orginal order was A-B-C-D the 758215976Sjmallett new byte order will be D-C-B-A. */ 759215976Sjmallett uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C. 760215976Sjmallett IN: A-B-C-D-E-F-G-H 761215976Sjmallett OUT0: A-B-C-D-E-F-G-H 762215976Sjmallett OUT1: H-G-F-E-D-C-B-A 763215976Sjmallett OUT2: D-C-B-A-H-G-F-E 764215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 765215976Sjmallett#else 766215976Sjmallett uint64_t l2c_emod : 2; 767215976Sjmallett uint64_t inv_a2 : 1; 768215976Sjmallett uint64_t dma_test : 1; 769215976Sjmallett uint64_t dma_stt : 1; 770215976Sjmallett uint64_t dma_0pag : 1; 771215976Sjmallett uint64_t reserved_6_63 : 58; 772215976Sjmallett#endif 773215976Sjmallett } s; 774215976Sjmallett struct cvmx_usbnx_ctl_status_s cn30xx; 775215976Sjmallett struct cvmx_usbnx_ctl_status_s cn31xx; 776215976Sjmallett struct cvmx_usbnx_ctl_status_s cn50xx; 777215976Sjmallett struct cvmx_usbnx_ctl_status_s cn52xx; 778215976Sjmallett struct cvmx_usbnx_ctl_status_s cn52xxp1; 779215976Sjmallett struct cvmx_usbnx_ctl_status_s cn56xx; 780215976Sjmallett struct cvmx_usbnx_ctl_status_s cn56xxp1; 781215976Sjmallett}; 782215976Sjmalletttypedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t; 783215976Sjmallett 784215976Sjmallett/** 785215976Sjmallett * cvmx_usbn#_dma0_inb_chn0 786215976Sjmallett * 787215976Sjmallett * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0 788215976Sjmallett * 789215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel0. 790215976Sjmallett * Writing of this register sets the base address. 791215976Sjmallett */ 792232812Sjmallettunion cvmx_usbnx_dma0_inb_chn0 { 793215976Sjmallett uint64_t u64; 794232812Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s { 795232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 796215976Sjmallett uint64_t reserved_36_63 : 28; 797215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 798215976Sjmallett#else 799215976Sjmallett uint64_t addr : 36; 800215976Sjmallett uint64_t reserved_36_63 : 28; 801215976Sjmallett#endif 802215976Sjmallett } s; 803215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn30xx; 804215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn31xx; 805215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn50xx; 806215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn52xx; 807215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1; 808215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn56xx; 809215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1; 810215976Sjmallett}; 811215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t; 812215976Sjmallett 813215976Sjmallett/** 814215976Sjmallett * cvmx_usbn#_dma0_inb_chn1 815215976Sjmallett * 816215976Sjmallett * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1 817215976Sjmallett * 818215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel1. 819215976Sjmallett * Writing of this register sets the base address. 820215976Sjmallett */ 821232812Sjmallettunion cvmx_usbnx_dma0_inb_chn1 { 822215976Sjmallett uint64_t u64; 823232812Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s { 824232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 825215976Sjmallett uint64_t reserved_36_63 : 28; 826215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 827215976Sjmallett#else 828215976Sjmallett uint64_t addr : 36; 829215976Sjmallett uint64_t reserved_36_63 : 28; 830215976Sjmallett#endif 831215976Sjmallett } s; 832215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn30xx; 833215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn31xx; 834215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn50xx; 835215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn52xx; 836215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1; 837215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn56xx; 838215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1; 839215976Sjmallett}; 840215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t; 841215976Sjmallett 842215976Sjmallett/** 843215976Sjmallett * cvmx_usbn#_dma0_inb_chn2 844215976Sjmallett * 845215976Sjmallett * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2 846215976Sjmallett * 847215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel2. 848215976Sjmallett * Writing of this register sets the base address. 849215976Sjmallett */ 850232812Sjmallettunion cvmx_usbnx_dma0_inb_chn2 { 851215976Sjmallett uint64_t u64; 852232812Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s { 853232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 854215976Sjmallett uint64_t reserved_36_63 : 28; 855215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 856215976Sjmallett#else 857215976Sjmallett uint64_t addr : 36; 858215976Sjmallett uint64_t reserved_36_63 : 28; 859215976Sjmallett#endif 860215976Sjmallett } s; 861215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn30xx; 862215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn31xx; 863215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn50xx; 864215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn52xx; 865215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1; 866215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn56xx; 867215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1; 868215976Sjmallett}; 869215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t; 870215976Sjmallett 871215976Sjmallett/** 872215976Sjmallett * cvmx_usbn#_dma0_inb_chn3 873215976Sjmallett * 874215976Sjmallett * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3 875215976Sjmallett * 876215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel3. 877215976Sjmallett * Writing of this register sets the base address. 878215976Sjmallett */ 879232812Sjmallettunion cvmx_usbnx_dma0_inb_chn3 { 880215976Sjmallett uint64_t u64; 881232812Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s { 882232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 883215976Sjmallett uint64_t reserved_36_63 : 28; 884215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 885215976Sjmallett#else 886215976Sjmallett uint64_t addr : 36; 887215976Sjmallett uint64_t reserved_36_63 : 28; 888215976Sjmallett#endif 889215976Sjmallett } s; 890215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn30xx; 891215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn31xx; 892215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn50xx; 893215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn52xx; 894215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1; 895215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn56xx; 896215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1; 897215976Sjmallett}; 898215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t; 899215976Sjmallett 900215976Sjmallett/** 901215976Sjmallett * cvmx_usbn#_dma0_inb_chn4 902215976Sjmallett * 903215976Sjmallett * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4 904215976Sjmallett * 905215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel4. 906215976Sjmallett * Writing of this register sets the base address. 907215976Sjmallett */ 908232812Sjmallettunion cvmx_usbnx_dma0_inb_chn4 { 909215976Sjmallett uint64_t u64; 910232812Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s { 911232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 912215976Sjmallett uint64_t reserved_36_63 : 28; 913215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 914215976Sjmallett#else 915215976Sjmallett uint64_t addr : 36; 916215976Sjmallett uint64_t reserved_36_63 : 28; 917215976Sjmallett#endif 918215976Sjmallett } s; 919215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn30xx; 920215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn31xx; 921215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn50xx; 922215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn52xx; 923215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1; 924215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn56xx; 925215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1; 926215976Sjmallett}; 927215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t; 928215976Sjmallett 929215976Sjmallett/** 930215976Sjmallett * cvmx_usbn#_dma0_inb_chn5 931215976Sjmallett * 932215976Sjmallett * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5 933215976Sjmallett * 934215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel5. 935215976Sjmallett * Writing of this register sets the base address. 936215976Sjmallett */ 937232812Sjmallettunion cvmx_usbnx_dma0_inb_chn5 { 938215976Sjmallett uint64_t u64; 939232812Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s { 940232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 941215976Sjmallett uint64_t reserved_36_63 : 28; 942215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 943215976Sjmallett#else 944215976Sjmallett uint64_t addr : 36; 945215976Sjmallett uint64_t reserved_36_63 : 28; 946215976Sjmallett#endif 947215976Sjmallett } s; 948215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn30xx; 949215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn31xx; 950215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn50xx; 951215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn52xx; 952215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1; 953215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn56xx; 954215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1; 955215976Sjmallett}; 956215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t; 957215976Sjmallett 958215976Sjmallett/** 959215976Sjmallett * cvmx_usbn#_dma0_inb_chn6 960215976Sjmallett * 961215976Sjmallett * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6 962215976Sjmallett * 963215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel6. 964215976Sjmallett * Writing of this register sets the base address. 965215976Sjmallett */ 966232812Sjmallettunion cvmx_usbnx_dma0_inb_chn6 { 967215976Sjmallett uint64_t u64; 968232812Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s { 969232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 970215976Sjmallett uint64_t reserved_36_63 : 28; 971215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 972215976Sjmallett#else 973215976Sjmallett uint64_t addr : 36; 974215976Sjmallett uint64_t reserved_36_63 : 28; 975215976Sjmallett#endif 976215976Sjmallett } s; 977215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn30xx; 978215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn31xx; 979215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn50xx; 980215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn52xx; 981215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1; 982215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn56xx; 983215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1; 984215976Sjmallett}; 985215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t; 986215976Sjmallett 987215976Sjmallett/** 988215976Sjmallett * cvmx_usbn#_dma0_inb_chn7 989215976Sjmallett * 990215976Sjmallett * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7 991215976Sjmallett * 992215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel7. 993215976Sjmallett * Writing of this register sets the base address. 994215976Sjmallett */ 995232812Sjmallettunion cvmx_usbnx_dma0_inb_chn7 { 996215976Sjmallett uint64_t u64; 997232812Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s { 998232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 999215976Sjmallett uint64_t reserved_36_63 : 28; 1000215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 1001215976Sjmallett#else 1002215976Sjmallett uint64_t addr : 36; 1003215976Sjmallett uint64_t reserved_36_63 : 28; 1004215976Sjmallett#endif 1005215976Sjmallett } s; 1006215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn30xx; 1007215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn31xx; 1008215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn50xx; 1009215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn52xx; 1010215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1; 1011215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn56xx; 1012215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1; 1013215976Sjmallett}; 1014215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t; 1015215976Sjmallett 1016215976Sjmallett/** 1017215976Sjmallett * cvmx_usbn#_dma0_outb_chn0 1018215976Sjmallett * 1019215976Sjmallett * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0 1020215976Sjmallett * 1021215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel0. 1022215976Sjmallett * Writing of this register sets the base address. 1023215976Sjmallett */ 1024232812Sjmallettunion cvmx_usbnx_dma0_outb_chn0 { 1025215976Sjmallett uint64_t u64; 1026232812Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s { 1027232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1028215976Sjmallett uint64_t reserved_36_63 : 28; 1029215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1030215976Sjmallett#else 1031215976Sjmallett uint64_t addr : 36; 1032215976Sjmallett uint64_t reserved_36_63 : 28; 1033215976Sjmallett#endif 1034215976Sjmallett } s; 1035215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn30xx; 1036215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn31xx; 1037215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn50xx; 1038215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn52xx; 1039215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1; 1040215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn56xx; 1041215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1; 1042215976Sjmallett}; 1043215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t; 1044215976Sjmallett 1045215976Sjmallett/** 1046215976Sjmallett * cvmx_usbn#_dma0_outb_chn1 1047215976Sjmallett * 1048215976Sjmallett * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1 1049215976Sjmallett * 1050215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel1. 1051215976Sjmallett * Writing of this register sets the base address. 1052215976Sjmallett */ 1053232812Sjmallettunion cvmx_usbnx_dma0_outb_chn1 { 1054215976Sjmallett uint64_t u64; 1055232812Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s { 1056232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1057215976Sjmallett uint64_t reserved_36_63 : 28; 1058215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1059215976Sjmallett#else 1060215976Sjmallett uint64_t addr : 36; 1061215976Sjmallett uint64_t reserved_36_63 : 28; 1062215976Sjmallett#endif 1063215976Sjmallett } s; 1064215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn30xx; 1065215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn31xx; 1066215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn50xx; 1067215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn52xx; 1068215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1; 1069215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn56xx; 1070215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1; 1071215976Sjmallett}; 1072215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t; 1073215976Sjmallett 1074215976Sjmallett/** 1075215976Sjmallett * cvmx_usbn#_dma0_outb_chn2 1076215976Sjmallett * 1077215976Sjmallett * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2 1078215976Sjmallett * 1079215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel2. 1080215976Sjmallett * Writing of this register sets the base address. 1081215976Sjmallett */ 1082232812Sjmallettunion cvmx_usbnx_dma0_outb_chn2 { 1083215976Sjmallett uint64_t u64; 1084232812Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s { 1085232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1086215976Sjmallett uint64_t reserved_36_63 : 28; 1087215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1088215976Sjmallett#else 1089215976Sjmallett uint64_t addr : 36; 1090215976Sjmallett uint64_t reserved_36_63 : 28; 1091215976Sjmallett#endif 1092215976Sjmallett } s; 1093215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn30xx; 1094215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn31xx; 1095215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn50xx; 1096215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn52xx; 1097215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1; 1098215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn56xx; 1099215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1; 1100215976Sjmallett}; 1101215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t; 1102215976Sjmallett 1103215976Sjmallett/** 1104215976Sjmallett * cvmx_usbn#_dma0_outb_chn3 1105215976Sjmallett * 1106215976Sjmallett * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3 1107215976Sjmallett * 1108215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel3. 1109215976Sjmallett * Writing of this register sets the base address. 1110215976Sjmallett */ 1111232812Sjmallettunion cvmx_usbnx_dma0_outb_chn3 { 1112215976Sjmallett uint64_t u64; 1113232812Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s { 1114232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1115215976Sjmallett uint64_t reserved_36_63 : 28; 1116215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1117215976Sjmallett#else 1118215976Sjmallett uint64_t addr : 36; 1119215976Sjmallett uint64_t reserved_36_63 : 28; 1120215976Sjmallett#endif 1121215976Sjmallett } s; 1122215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn30xx; 1123215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn31xx; 1124215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn50xx; 1125215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn52xx; 1126215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1; 1127215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn56xx; 1128215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1; 1129215976Sjmallett}; 1130215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t; 1131215976Sjmallett 1132215976Sjmallett/** 1133215976Sjmallett * cvmx_usbn#_dma0_outb_chn4 1134215976Sjmallett * 1135215976Sjmallett * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4 1136215976Sjmallett * 1137215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel4. 1138215976Sjmallett * Writing of this register sets the base address. 1139215976Sjmallett */ 1140232812Sjmallettunion cvmx_usbnx_dma0_outb_chn4 { 1141215976Sjmallett uint64_t u64; 1142232812Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s { 1143232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1144215976Sjmallett uint64_t reserved_36_63 : 28; 1145215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1146215976Sjmallett#else 1147215976Sjmallett uint64_t addr : 36; 1148215976Sjmallett uint64_t reserved_36_63 : 28; 1149215976Sjmallett#endif 1150215976Sjmallett } s; 1151215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn30xx; 1152215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn31xx; 1153215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn50xx; 1154215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn52xx; 1155215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1; 1156215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn56xx; 1157215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1; 1158215976Sjmallett}; 1159215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t; 1160215976Sjmallett 1161215976Sjmallett/** 1162215976Sjmallett * cvmx_usbn#_dma0_outb_chn5 1163215976Sjmallett * 1164215976Sjmallett * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5 1165215976Sjmallett * 1166215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel5. 1167215976Sjmallett * Writing of this register sets the base address. 1168215976Sjmallett */ 1169232812Sjmallettunion cvmx_usbnx_dma0_outb_chn5 { 1170215976Sjmallett uint64_t u64; 1171232812Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s { 1172232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1173215976Sjmallett uint64_t reserved_36_63 : 28; 1174215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1175215976Sjmallett#else 1176215976Sjmallett uint64_t addr : 36; 1177215976Sjmallett uint64_t reserved_36_63 : 28; 1178215976Sjmallett#endif 1179215976Sjmallett } s; 1180215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn30xx; 1181215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn31xx; 1182215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn50xx; 1183215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn52xx; 1184215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1; 1185215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn56xx; 1186215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1; 1187215976Sjmallett}; 1188215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t; 1189215976Sjmallett 1190215976Sjmallett/** 1191215976Sjmallett * cvmx_usbn#_dma0_outb_chn6 1192215976Sjmallett * 1193215976Sjmallett * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6 1194215976Sjmallett * 1195215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel6. 1196215976Sjmallett * Writing of this register sets the base address. 1197215976Sjmallett */ 1198232812Sjmallettunion cvmx_usbnx_dma0_outb_chn6 { 1199215976Sjmallett uint64_t u64; 1200232812Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s { 1201232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1202215976Sjmallett uint64_t reserved_36_63 : 28; 1203215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1204215976Sjmallett#else 1205215976Sjmallett uint64_t addr : 36; 1206215976Sjmallett uint64_t reserved_36_63 : 28; 1207215976Sjmallett#endif 1208215976Sjmallett } s; 1209215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn30xx; 1210215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn31xx; 1211215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn50xx; 1212215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn52xx; 1213215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1; 1214215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn56xx; 1215215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1; 1216215976Sjmallett}; 1217215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t; 1218215976Sjmallett 1219215976Sjmallett/** 1220215976Sjmallett * cvmx_usbn#_dma0_outb_chn7 1221215976Sjmallett * 1222215976Sjmallett * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7 1223215976Sjmallett * 1224215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel7. 1225215976Sjmallett * Writing of this register sets the base address. 1226215976Sjmallett */ 1227232812Sjmallettunion cvmx_usbnx_dma0_outb_chn7 { 1228215976Sjmallett uint64_t u64; 1229232812Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s { 1230232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1231215976Sjmallett uint64_t reserved_36_63 : 28; 1232215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1233215976Sjmallett#else 1234215976Sjmallett uint64_t addr : 36; 1235215976Sjmallett uint64_t reserved_36_63 : 28; 1236215976Sjmallett#endif 1237215976Sjmallett } s; 1238215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn30xx; 1239215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn31xx; 1240215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn50xx; 1241215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn52xx; 1242215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1; 1243215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn56xx; 1244215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1; 1245215976Sjmallett}; 1246215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t; 1247215976Sjmallett 1248215976Sjmallett/** 1249215976Sjmallett * cvmx_usbn#_dma_test 1250215976Sjmallett * 1251215976Sjmallett * USBN_DMA_TEST = USBN's DMA TestRegister 1252215976Sjmallett * 1253215976Sjmallett * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs 1254215976Sjmallett */ 1255232812Sjmallettunion cvmx_usbnx_dma_test { 1256215976Sjmallett uint64_t u64; 1257232812Sjmallett struct cvmx_usbnx_dma_test_s { 1258232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1259215976Sjmallett uint64_t reserved_40_63 : 24; 1260215976Sjmallett uint64_t done : 1; /**< This field is set when a DMA completes. Writing a 1261215976Sjmallett '1' to this field clears this bit. */ 1262215976Sjmallett uint64_t req : 1; /**< DMA Request. Writing a 1 to this register 1263215976Sjmallett will cause a DMA request as specified in the other 1264215976Sjmallett fields of this register to take place. This field 1265215976Sjmallett will always read as '0'. */ 1266215976Sjmallett uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */ 1267215976Sjmallett uint64_t count : 11; /**< DMA Request Count. */ 1268215976Sjmallett uint64_t channel : 5; /**< DMA Channel/Enpoint. */ 1269215976Sjmallett uint64_t burst : 4; /**< DMA Burst Size. */ 1270215976Sjmallett#else 1271215976Sjmallett uint64_t burst : 4; 1272215976Sjmallett uint64_t channel : 5; 1273215976Sjmallett uint64_t count : 11; 1274215976Sjmallett uint64_t f_addr : 18; 1275215976Sjmallett uint64_t req : 1; 1276215976Sjmallett uint64_t done : 1; 1277215976Sjmallett uint64_t reserved_40_63 : 24; 1278215976Sjmallett#endif 1279215976Sjmallett } s; 1280215976Sjmallett struct cvmx_usbnx_dma_test_s cn30xx; 1281215976Sjmallett struct cvmx_usbnx_dma_test_s cn31xx; 1282215976Sjmallett struct cvmx_usbnx_dma_test_s cn50xx; 1283215976Sjmallett struct cvmx_usbnx_dma_test_s cn52xx; 1284215976Sjmallett struct cvmx_usbnx_dma_test_s cn52xxp1; 1285215976Sjmallett struct cvmx_usbnx_dma_test_s cn56xx; 1286215976Sjmallett struct cvmx_usbnx_dma_test_s cn56xxp1; 1287215976Sjmallett}; 1288215976Sjmalletttypedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t; 1289215976Sjmallett 1290215976Sjmallett/** 1291215976Sjmallett * cvmx_usbn#_int_enb 1292215976Sjmallett * 1293215976Sjmallett * USBN_INT_ENB = USBN's Interrupt Enable 1294215976Sjmallett * 1295215976Sjmallett * The USBN's interrupt enable register. 1296215976Sjmallett */ 1297232812Sjmallettunion cvmx_usbnx_int_enb { 1298215976Sjmallett uint64_t u64; 1299232812Sjmallett struct cvmx_usbnx_int_enb_s { 1300232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1301215976Sjmallett uint64_t reserved_38_63 : 26; 1302215976Sjmallett uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1303215976Sjmallett register is asserted the USBN will assert an 1304215976Sjmallett interrupt. */ 1305215976Sjmallett uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1306215976Sjmallett register is asserted the USBN will assert an 1307215976Sjmallett interrupt. */ 1308215976Sjmallett uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1309215976Sjmallett register is asserted the USBN will assert an 1310215976Sjmallett interrupt. */ 1311215976Sjmallett uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1312215976Sjmallett register is asserted the USBN will assert an 1313215976Sjmallett interrupt. */ 1314215976Sjmallett uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1315215976Sjmallett register is asserted the USBN will assert an 1316215976Sjmallett interrupt. */ 1317215976Sjmallett uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1318215976Sjmallett register is asserted the USBN will assert an 1319215976Sjmallett interrupt. */ 1320215976Sjmallett uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM 1321215976Sjmallett register is asserted the USBN will assert an 1322215976Sjmallett interrupt. */ 1323215976Sjmallett uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM 1324215976Sjmallett register is asserted the USBN will assert an 1325215976Sjmallett interrupt. */ 1326215976Sjmallett uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM 1327215976Sjmallett register is asserted the USBN will assert an 1328215976Sjmallett interrupt. */ 1329215976Sjmallett uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM 1330215976Sjmallett register is asserted the USBN will assert an 1331215976Sjmallett interrupt. */ 1332215976Sjmallett uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM 1333215976Sjmallett register is asserted the USBN will assert an 1334215976Sjmallett interrupt. */ 1335215976Sjmallett uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM 1336215976Sjmallett register is asserted the USBN will assert an 1337215976Sjmallett interrupt. */ 1338215976Sjmallett uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1339215976Sjmallett register is asserted the USBN will assert an 1340215976Sjmallett interrupt. */ 1341215976Sjmallett uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1342215976Sjmallett register is asserted the USBN will assert an 1343215976Sjmallett interrupt. */ 1344215976Sjmallett uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1345215976Sjmallett register is asserted the USBN will assert an 1346215976Sjmallett interrupt. */ 1347215976Sjmallett uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1348215976Sjmallett register is asserted the USBN will assert an 1349215976Sjmallett interrupt. */ 1350215976Sjmallett uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1351215976Sjmallett register is asserted the USBN will assert an 1352215976Sjmallett interrupt. */ 1353215976Sjmallett uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1354215976Sjmallett register is asserted the USBN will assert an 1355215976Sjmallett interrupt. */ 1356215976Sjmallett uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1357215976Sjmallett register is asserted the USBN will assert an 1358215976Sjmallett interrupt. */ 1359215976Sjmallett uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1360215976Sjmallett register is asserted the USBN will assert an 1361215976Sjmallett interrupt. */ 1362215976Sjmallett uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1363215976Sjmallett register is asserted the USBN will assert an 1364215976Sjmallett interrupt. */ 1365215976Sjmallett uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1366215976Sjmallett register is asserted the USBN will assert an 1367215976Sjmallett interrupt. */ 1368215976Sjmallett uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1369215976Sjmallett register is asserted the USBN will assert an 1370215976Sjmallett interrupt. */ 1371215976Sjmallett uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1372215976Sjmallett register is asserted the USBN will assert an 1373215976Sjmallett interrupt. */ 1374215976Sjmallett uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1375215976Sjmallett register is asserted the USBN will assert an 1376215976Sjmallett interrupt. */ 1377215976Sjmallett uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1378215976Sjmallett register is asserted the USBN will assert an 1379215976Sjmallett interrupt. */ 1380215976Sjmallett uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1381215976Sjmallett register is asserted the USBN will assert an 1382215976Sjmallett interrupt. */ 1383215976Sjmallett uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1384215976Sjmallett register is asserted the USBN will assert an 1385215976Sjmallett interrupt. */ 1386215976Sjmallett uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1387215976Sjmallett register is asserted the USBN will assert an 1388215976Sjmallett interrupt. */ 1389215976Sjmallett uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1390215976Sjmallett register is asserted the USBN will assert an 1391215976Sjmallett interrupt. */ 1392215976Sjmallett uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1393215976Sjmallett register is asserted the USBN will assert an 1394215976Sjmallett interrupt. */ 1395215976Sjmallett uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1396215976Sjmallett register is asserted the USBN will assert an 1397215976Sjmallett interrupt. */ 1398215976Sjmallett uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1399215976Sjmallett register is asserted the USBN will assert an 1400215976Sjmallett interrupt. */ 1401215976Sjmallett uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1402215976Sjmallett register is asserted the USBN will assert an 1403215976Sjmallett interrupt. */ 1404215976Sjmallett uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1405215976Sjmallett register is asserted the USBN will assert an 1406215976Sjmallett interrupt. */ 1407215976Sjmallett uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1408215976Sjmallett register is asserted the USBN will assert an 1409215976Sjmallett interrupt. */ 1410215976Sjmallett uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1411215976Sjmallett register is asserted the USBN will assert an 1412215976Sjmallett interrupt. */ 1413215976Sjmallett uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1414215976Sjmallett register is asserted the USBN will assert an 1415215976Sjmallett interrupt. */ 1416215976Sjmallett#else 1417215976Sjmallett uint64_t pr_po_e : 1; 1418215976Sjmallett uint64_t pr_pu_f : 1; 1419215976Sjmallett uint64_t nr_po_e : 1; 1420215976Sjmallett uint64_t nr_pu_f : 1; 1421215976Sjmallett uint64_t lr_po_e : 1; 1422215976Sjmallett uint64_t lr_pu_f : 1; 1423215976Sjmallett uint64_t pt_po_e : 1; 1424215976Sjmallett uint64_t pt_pu_f : 1; 1425215976Sjmallett uint64_t nt_po_e : 1; 1426215976Sjmallett uint64_t nt_pu_f : 1; 1427215976Sjmallett uint64_t lt_po_e : 1; 1428215976Sjmallett uint64_t lt_pu_f : 1; 1429215976Sjmallett uint64_t dcred_e : 1; 1430215976Sjmallett uint64_t dcred_f : 1; 1431215976Sjmallett uint64_t l2c_s_e : 1; 1432215976Sjmallett uint64_t l2c_a_f : 1; 1433215976Sjmallett uint64_t l2_fi_e : 1; 1434215976Sjmallett uint64_t l2_fi_f : 1; 1435215976Sjmallett uint64_t rg_fi_e : 1; 1436215976Sjmallett uint64_t rg_fi_f : 1; 1437215976Sjmallett uint64_t rq_q2_f : 1; 1438215976Sjmallett uint64_t rq_q2_e : 1; 1439215976Sjmallett uint64_t rq_q3_f : 1; 1440215976Sjmallett uint64_t rq_q3_e : 1; 1441215976Sjmallett uint64_t uod_pe : 1; 1442215976Sjmallett uint64_t uod_pf : 1; 1443215976Sjmallett uint64_t n2u_pf : 1; 1444215976Sjmallett uint64_t n2u_pe : 1; 1445215976Sjmallett uint64_t u2n_d_pe : 1; 1446215976Sjmallett uint64_t u2n_d_pf : 1; 1447215976Sjmallett uint64_t u2n_c_pf : 1; 1448215976Sjmallett uint64_t u2n_c_pe : 1; 1449215976Sjmallett uint64_t ltl_f_pe : 1; 1450215976Sjmallett uint64_t ltl_f_pf : 1; 1451215976Sjmallett uint64_t nd4o_rpe : 1; 1452215976Sjmallett uint64_t nd4o_rpf : 1; 1453215976Sjmallett uint64_t nd4o_dpe : 1; 1454215976Sjmallett uint64_t nd4o_dpf : 1; 1455215976Sjmallett uint64_t reserved_38_63 : 26; 1456215976Sjmallett#endif 1457215976Sjmallett } s; 1458215976Sjmallett struct cvmx_usbnx_int_enb_s cn30xx; 1459215976Sjmallett struct cvmx_usbnx_int_enb_s cn31xx; 1460232812Sjmallett struct cvmx_usbnx_int_enb_cn50xx { 1461232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1462215976Sjmallett uint64_t reserved_38_63 : 26; 1463215976Sjmallett uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1464215976Sjmallett register is asserted the USBN will assert an 1465215976Sjmallett interrupt. */ 1466215976Sjmallett uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1467215976Sjmallett register is asserted the USBN will assert an 1468215976Sjmallett interrupt. */ 1469215976Sjmallett uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1470215976Sjmallett register is asserted the USBN will assert an 1471215976Sjmallett interrupt. */ 1472215976Sjmallett uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1473215976Sjmallett register is asserted the USBN will assert an 1474215976Sjmallett interrupt. */ 1475215976Sjmallett uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1476215976Sjmallett register is asserted the USBN will assert an 1477215976Sjmallett interrupt. */ 1478215976Sjmallett uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1479215976Sjmallett register is asserted the USBN will assert an 1480215976Sjmallett interrupt. */ 1481215976Sjmallett uint64_t reserved_26_31 : 6; 1482215976Sjmallett uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1483215976Sjmallett register is asserted the USBN will assert an 1484215976Sjmallett interrupt. */ 1485215976Sjmallett uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1486215976Sjmallett register is asserted the USBN will assert an 1487215976Sjmallett interrupt. */ 1488215976Sjmallett uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1489215976Sjmallett register is asserted the USBN will assert an 1490215976Sjmallett interrupt. */ 1491215976Sjmallett uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1492215976Sjmallett register is asserted the USBN will assert an 1493215976Sjmallett interrupt. */ 1494215976Sjmallett uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1495215976Sjmallett register is asserted the USBN will assert an 1496215976Sjmallett interrupt. */ 1497215976Sjmallett uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1498215976Sjmallett register is asserted the USBN will assert an 1499215976Sjmallett interrupt. */ 1500215976Sjmallett uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1501215976Sjmallett register is asserted the USBN will assert an 1502215976Sjmallett interrupt. */ 1503215976Sjmallett uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1504215976Sjmallett register is asserted the USBN will assert an 1505215976Sjmallett interrupt. */ 1506215976Sjmallett uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1507215976Sjmallett register is asserted the USBN will assert an 1508215976Sjmallett interrupt. */ 1509215976Sjmallett uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1510215976Sjmallett register is asserted the USBN will assert an 1511215976Sjmallett interrupt. */ 1512215976Sjmallett uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1513215976Sjmallett register is asserted the USBN will assert an 1514215976Sjmallett interrupt. */ 1515215976Sjmallett uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1516215976Sjmallett register is asserted the USBN will assert an 1517215976Sjmallett interrupt. */ 1518215976Sjmallett uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1519215976Sjmallett register is asserted the USBN will assert an 1520215976Sjmallett interrupt. */ 1521215976Sjmallett uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1522215976Sjmallett register is asserted the USBN will assert an 1523215976Sjmallett interrupt. */ 1524215976Sjmallett uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1525215976Sjmallett register is asserted the USBN will assert an 1526215976Sjmallett interrupt. */ 1527215976Sjmallett uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1528215976Sjmallett register is asserted the USBN will assert an 1529215976Sjmallett interrupt. */ 1530215976Sjmallett uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1531215976Sjmallett register is asserted the USBN will assert an 1532215976Sjmallett interrupt. */ 1533215976Sjmallett uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1534215976Sjmallett register is asserted the USBN will assert an 1535215976Sjmallett interrupt. */ 1536215976Sjmallett uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1537215976Sjmallett register is asserted the USBN will assert an 1538215976Sjmallett interrupt. */ 1539215976Sjmallett uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1540215976Sjmallett register is asserted the USBN will assert an 1541215976Sjmallett interrupt. */ 1542215976Sjmallett uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1543215976Sjmallett register is asserted the USBN will assert an 1544215976Sjmallett interrupt. */ 1545215976Sjmallett uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1546215976Sjmallett register is asserted the USBN will assert an 1547215976Sjmallett interrupt. */ 1548215976Sjmallett uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1549215976Sjmallett register is asserted the USBN will assert an 1550215976Sjmallett interrupt. */ 1551215976Sjmallett uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1552215976Sjmallett register is asserted the USBN will assert an 1553215976Sjmallett interrupt. */ 1554215976Sjmallett uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1555215976Sjmallett register is asserted the USBN will assert an 1556215976Sjmallett interrupt. */ 1557215976Sjmallett uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1558215976Sjmallett register is asserted the USBN will assert an 1559215976Sjmallett interrupt. */ 1560215976Sjmallett#else 1561215976Sjmallett uint64_t pr_po_e : 1; 1562215976Sjmallett uint64_t pr_pu_f : 1; 1563215976Sjmallett uint64_t nr_po_e : 1; 1564215976Sjmallett uint64_t nr_pu_f : 1; 1565215976Sjmallett uint64_t lr_po_e : 1; 1566215976Sjmallett uint64_t lr_pu_f : 1; 1567215976Sjmallett uint64_t pt_po_e : 1; 1568215976Sjmallett uint64_t pt_pu_f : 1; 1569215976Sjmallett uint64_t nt_po_e : 1; 1570215976Sjmallett uint64_t nt_pu_f : 1; 1571215976Sjmallett uint64_t lt_po_e : 1; 1572215976Sjmallett uint64_t lt_pu_f : 1; 1573215976Sjmallett uint64_t dcred_e : 1; 1574215976Sjmallett uint64_t dcred_f : 1; 1575215976Sjmallett uint64_t l2c_s_e : 1; 1576215976Sjmallett uint64_t l2c_a_f : 1; 1577215976Sjmallett uint64_t l2_fi_e : 1; 1578215976Sjmallett uint64_t l2_fi_f : 1; 1579215976Sjmallett uint64_t rg_fi_e : 1; 1580215976Sjmallett uint64_t rg_fi_f : 1; 1581215976Sjmallett uint64_t rq_q2_f : 1; 1582215976Sjmallett uint64_t rq_q2_e : 1; 1583215976Sjmallett uint64_t rq_q3_f : 1; 1584215976Sjmallett uint64_t rq_q3_e : 1; 1585215976Sjmallett uint64_t uod_pe : 1; 1586215976Sjmallett uint64_t uod_pf : 1; 1587215976Sjmallett uint64_t reserved_26_31 : 6; 1588215976Sjmallett uint64_t ltl_f_pe : 1; 1589215976Sjmallett uint64_t ltl_f_pf : 1; 1590215976Sjmallett uint64_t nd4o_rpe : 1; 1591215976Sjmallett uint64_t nd4o_rpf : 1; 1592215976Sjmallett uint64_t nd4o_dpe : 1; 1593215976Sjmallett uint64_t nd4o_dpf : 1; 1594215976Sjmallett uint64_t reserved_38_63 : 26; 1595215976Sjmallett#endif 1596215976Sjmallett } cn50xx; 1597215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn52xx; 1598215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn52xxp1; 1599215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn56xx; 1600215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn56xxp1; 1601215976Sjmallett}; 1602215976Sjmalletttypedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t; 1603215976Sjmallett 1604215976Sjmallett/** 1605215976Sjmallett * cvmx_usbn#_int_sum 1606215976Sjmallett * 1607215976Sjmallett * USBN_INT_SUM = USBN's Interrupt Summary Register 1608215976Sjmallett * 1609215976Sjmallett * Contains the diffrent interrupt summary bits of the USBN. 1610215976Sjmallett */ 1611232812Sjmallettunion cvmx_usbnx_int_sum { 1612215976Sjmallett uint64_t u64; 1613232812Sjmallett struct cvmx_usbnx_int_sum_s { 1614232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1615215976Sjmallett uint64_t reserved_38_63 : 26; 1616215976Sjmallett uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1617215976Sjmallett uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1618215976Sjmallett uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1619215976Sjmallett uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1620215976Sjmallett uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1621215976Sjmallett uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1622215976Sjmallett uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */ 1623215976Sjmallett uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */ 1624215976Sjmallett uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */ 1625215976Sjmallett uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */ 1626215976Sjmallett uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */ 1627215976Sjmallett uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */ 1628215976Sjmallett uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1629215976Sjmallett uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1630215976Sjmallett uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1631215976Sjmallett uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1632215976Sjmallett uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1633215976Sjmallett uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1634215976Sjmallett uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1635215976Sjmallett uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1636215976Sjmallett uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1637215976Sjmallett uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1638215976Sjmallett uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1639215976Sjmallett uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1640215976Sjmallett uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1641215976Sjmallett uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1642215976Sjmallett uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1643215976Sjmallett uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1644215976Sjmallett uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1645215976Sjmallett uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1646215976Sjmallett uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1647215976Sjmallett uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1648215976Sjmallett uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1649215976Sjmallett uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1650215976Sjmallett uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1651215976Sjmallett uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1652215976Sjmallett uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1653215976Sjmallett uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1654215976Sjmallett#else 1655215976Sjmallett uint64_t pr_po_e : 1; 1656215976Sjmallett uint64_t pr_pu_f : 1; 1657215976Sjmallett uint64_t nr_po_e : 1; 1658215976Sjmallett uint64_t nr_pu_f : 1; 1659215976Sjmallett uint64_t lr_po_e : 1; 1660215976Sjmallett uint64_t lr_pu_f : 1; 1661215976Sjmallett uint64_t pt_po_e : 1; 1662215976Sjmallett uint64_t pt_pu_f : 1; 1663215976Sjmallett uint64_t nt_po_e : 1; 1664215976Sjmallett uint64_t nt_pu_f : 1; 1665215976Sjmallett uint64_t lt_po_e : 1; 1666215976Sjmallett uint64_t lt_pu_f : 1; 1667215976Sjmallett uint64_t dcred_e : 1; 1668215976Sjmallett uint64_t dcred_f : 1; 1669215976Sjmallett uint64_t l2c_s_e : 1; 1670215976Sjmallett uint64_t l2c_a_f : 1; 1671215976Sjmallett uint64_t lt_fi_e : 1; 1672215976Sjmallett uint64_t lt_fi_f : 1; 1673215976Sjmallett uint64_t rg_fi_e : 1; 1674215976Sjmallett uint64_t rg_fi_f : 1; 1675215976Sjmallett uint64_t rq_q2_f : 1; 1676215976Sjmallett uint64_t rq_q2_e : 1; 1677215976Sjmallett uint64_t rq_q3_f : 1; 1678215976Sjmallett uint64_t rq_q3_e : 1; 1679215976Sjmallett uint64_t uod_pe : 1; 1680215976Sjmallett uint64_t uod_pf : 1; 1681215976Sjmallett uint64_t n2u_pf : 1; 1682215976Sjmallett uint64_t n2u_pe : 1; 1683215976Sjmallett uint64_t u2n_d_pe : 1; 1684215976Sjmallett uint64_t u2n_d_pf : 1; 1685215976Sjmallett uint64_t u2n_c_pf : 1; 1686215976Sjmallett uint64_t u2n_c_pe : 1; 1687215976Sjmallett uint64_t ltl_f_pe : 1; 1688215976Sjmallett uint64_t ltl_f_pf : 1; 1689215976Sjmallett uint64_t nd4o_rpe : 1; 1690215976Sjmallett uint64_t nd4o_rpf : 1; 1691215976Sjmallett uint64_t nd4o_dpe : 1; 1692215976Sjmallett uint64_t nd4o_dpf : 1; 1693215976Sjmallett uint64_t reserved_38_63 : 26; 1694215976Sjmallett#endif 1695215976Sjmallett } s; 1696215976Sjmallett struct cvmx_usbnx_int_sum_s cn30xx; 1697215976Sjmallett struct cvmx_usbnx_int_sum_s cn31xx; 1698232812Sjmallett struct cvmx_usbnx_int_sum_cn50xx { 1699232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1700215976Sjmallett uint64_t reserved_38_63 : 26; 1701215976Sjmallett uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1702215976Sjmallett uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1703215976Sjmallett uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1704215976Sjmallett uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1705215976Sjmallett uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1706215976Sjmallett uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1707215976Sjmallett uint64_t reserved_26_31 : 6; 1708215976Sjmallett uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1709215976Sjmallett uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1710215976Sjmallett uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1711215976Sjmallett uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1712215976Sjmallett uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1713215976Sjmallett uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1714215976Sjmallett uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1715215976Sjmallett uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1716215976Sjmallett uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1717215976Sjmallett uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1718215976Sjmallett uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1719215976Sjmallett uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1720215976Sjmallett uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1721215976Sjmallett uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1722215976Sjmallett uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1723215976Sjmallett uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1724215976Sjmallett uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1725215976Sjmallett uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1726215976Sjmallett uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1727215976Sjmallett uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1728215976Sjmallett uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1729215976Sjmallett uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1730215976Sjmallett uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1731215976Sjmallett uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1732215976Sjmallett uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1733215976Sjmallett uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1734215976Sjmallett#else 1735215976Sjmallett uint64_t pr_po_e : 1; 1736215976Sjmallett uint64_t pr_pu_f : 1; 1737215976Sjmallett uint64_t nr_po_e : 1; 1738215976Sjmallett uint64_t nr_pu_f : 1; 1739215976Sjmallett uint64_t lr_po_e : 1; 1740215976Sjmallett uint64_t lr_pu_f : 1; 1741215976Sjmallett uint64_t pt_po_e : 1; 1742215976Sjmallett uint64_t pt_pu_f : 1; 1743215976Sjmallett uint64_t nt_po_e : 1; 1744215976Sjmallett uint64_t nt_pu_f : 1; 1745215976Sjmallett uint64_t lt_po_e : 1; 1746215976Sjmallett uint64_t lt_pu_f : 1; 1747215976Sjmallett uint64_t dcred_e : 1; 1748215976Sjmallett uint64_t dcred_f : 1; 1749215976Sjmallett uint64_t l2c_s_e : 1; 1750215976Sjmallett uint64_t l2c_a_f : 1; 1751215976Sjmallett uint64_t lt_fi_e : 1; 1752215976Sjmallett uint64_t lt_fi_f : 1; 1753215976Sjmallett uint64_t rg_fi_e : 1; 1754215976Sjmallett uint64_t rg_fi_f : 1; 1755215976Sjmallett uint64_t rq_q2_f : 1; 1756215976Sjmallett uint64_t rq_q2_e : 1; 1757215976Sjmallett uint64_t rq_q3_f : 1; 1758215976Sjmallett uint64_t rq_q3_e : 1; 1759215976Sjmallett uint64_t uod_pe : 1; 1760215976Sjmallett uint64_t uod_pf : 1; 1761215976Sjmallett uint64_t reserved_26_31 : 6; 1762215976Sjmallett uint64_t ltl_f_pe : 1; 1763215976Sjmallett uint64_t ltl_f_pf : 1; 1764215976Sjmallett uint64_t nd4o_rpe : 1; 1765215976Sjmallett uint64_t nd4o_rpf : 1; 1766215976Sjmallett uint64_t nd4o_dpe : 1; 1767215976Sjmallett uint64_t nd4o_dpf : 1; 1768215976Sjmallett uint64_t reserved_38_63 : 26; 1769215976Sjmallett#endif 1770215976Sjmallett } cn50xx; 1771215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn52xx; 1772215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn52xxp1; 1773215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn56xx; 1774215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn56xxp1; 1775215976Sjmallett}; 1776215976Sjmalletttypedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t; 1777215976Sjmallett 1778215976Sjmallett/** 1779215976Sjmallett * cvmx_usbn#_usbp_ctl_status 1780215976Sjmallett * 1781215976Sjmallett * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1782215976Sjmallett * 1783215976Sjmallett * Contains general control and status information for the USBN block. 1784215976Sjmallett */ 1785232812Sjmallettunion cvmx_usbnx_usbp_ctl_status { 1786215976Sjmallett uint64_t u64; 1787232812Sjmallett struct cvmx_usbnx_usbp_ctl_status_s { 1788232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1789215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 1790215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 1791215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 1792215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 1793215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 1794215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 1795215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 1796215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 1797215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 1798215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 1799215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 1800215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 1801215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 1802215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 1803215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 1804215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 1805215976Sjmallett Indicates an internal error was detected during 1806215976Sjmallett the BIST sequence. */ 1807215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 1808215976Sjmallett Presents either internaly generated signals or 1809215976Sjmallett test register contents, based upon the value of 1810215976Sjmallett test_data_out_sel. */ 1811215976Sjmallett uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 1812215976Sjmallett Normally should be set to zero. 1813215976Sjmallett When customers have no intent to use USB PHY 1814215976Sjmallett interface, they should: 1815215976Sjmallett - still provide 3.3V to USB_VDD33, and 1816215976Sjmallett - tie USB_REXT to 3.3V supply, and 1817215976Sjmallett - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 1818215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 1819215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1820215976Sjmallett with byte-counts between packets. When set to 0 1821215976Sjmallett the L2C DMA address is incremented to the next 1822215976Sjmallett 4-byte aligned address after adding byte-count. */ 1823215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1824215976Sjmallett set to '0' for operation. */ 1825215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1826215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1827215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1828215976Sjmallett This signal enables the pull-down resistance on 1829215976Sjmallett the D+ line. '1' pull down-resistance is connected 1830215976Sjmallett to D+/ '0' pull down resistance is not connected 1831215976Sjmallett to D+. When an A/B device is acting as a host 1832215976Sjmallett (downstream-facing port), dp_pulldown and 1833215976Sjmallett dm_pulldown are enabled. This must not toggle 1834215976Sjmallett during normal opeartion. */ 1835215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1836215976Sjmallett This signal enables the pull-down resistance on 1837215976Sjmallett the D- line. '1' pull down-resistance is connected 1838215976Sjmallett to D-. '0' pull down resistance is not connected 1839215976Sjmallett to D-. When an A/B device is acting as a host 1840215976Sjmallett (downstream-facing port), dp_pulldown and 1841215976Sjmallett dm_pulldown are enabled. This must not toggle 1842215976Sjmallett during normal opeartion. */ 1843215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1844215976Sjmallett USB is acting as device. This field needs to be 1845215976Sjmallett set while the USB is in reset. */ 1846215976Sjmallett uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1847215976Sjmallett Tunes the current supply and rise/fall output 1848215976Sjmallett times for high-speed operation. 1849215976Sjmallett [20:19] == 11: Current supply increased 1850215976Sjmallett approximately 9% 1851215976Sjmallett [20:19] == 10: Current supply increased 1852215976Sjmallett approximately 4.5% 1853215976Sjmallett [20:19] == 01: Design default. 1854215976Sjmallett [20:19] == 00: Current supply decreased 1855215976Sjmallett approximately 4.5% 1856215976Sjmallett [22:21] == 11: Rise and fall times are increased. 1857215976Sjmallett [22:21] == 10: Design default. 1858215976Sjmallett [22:21] == 01: Rise and fall times are decreased. 1859215976Sjmallett [22:21] == 00: Rise and fall times are decreased 1860215976Sjmallett further as compared to the 01 setting. */ 1861215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1862215976Sjmallett Enables or disables bit stuffing on data[15:8] 1863215976Sjmallett when bit-stuffing is enabled. */ 1864215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1865215976Sjmallett Enables or disables bit stuffing on data[7:0] 1866215976Sjmallett when bit-stuffing is enabled. */ 1867215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 1868215976Sjmallett '1': During data transmission the receive is 1869215976Sjmallett enabled. 1870215976Sjmallett '0': During data transmission the receive is 1871215976Sjmallett disabled. 1872215976Sjmallett Must be '0' for normal operation. */ 1873215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 1874215976Sjmallett '1' The PHY's analog_test pin is enabled for the 1875215976Sjmallett input and output of applicable analog test signals. 1876215976Sjmallett '0' THe analog_test pin is disabled. */ 1877215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 1878215976Sjmallett Used to activate BIST in the PHY. */ 1879215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 1880215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 1881215976Sjmallett are output. '0' internaly generated signals are 1882215976Sjmallett output. */ 1883215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 1884215976Sjmallett Specifies the register address for writing to or 1885215976Sjmallett reading from the PHY test interface register. */ 1886215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 1887215976Sjmallett This is a test bus. Data is present on [3:0], 1888215976Sjmallett and its corresponding select (enable) is present 1889215976Sjmallett on bits [7:4]. */ 1890215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 1891215976Sjmallett This is a test signal. When the USB Core is 1892215976Sjmallett powered up (not in Susned Mode), an automatic 1893215976Sjmallett tester can use this to disable phy_clock and 1894215976Sjmallett free_clk, then re-eanable them with an aligned 1895215976Sjmallett phase. 1896215976Sjmallett '1': The phy_clk and free_clk outputs are 1897215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 1898215976Sjmallett are available within a specific period after the 1899215976Sjmallett de-assertion. */ 1900215976Sjmallett#else 1901215976Sjmallett uint64_t ate_reset : 1; 1902215976Sjmallett uint64_t tdata_in : 8; 1903215976Sjmallett uint64_t taddr_in : 4; 1904215976Sjmallett uint64_t tdata_sel : 1; 1905215976Sjmallett uint64_t bist_enb : 1; 1906215976Sjmallett uint64_t vtest_enb : 1; 1907215976Sjmallett uint64_t loop_enb : 1; 1908215976Sjmallett uint64_t tx_bs_en : 1; 1909215976Sjmallett uint64_t tx_bs_enh : 1; 1910215976Sjmallett uint64_t tuning : 4; 1911215976Sjmallett uint64_t hst_mode : 1; 1912215976Sjmallett uint64_t dm_pulld : 1; 1913215976Sjmallett uint64_t dp_pulld : 1; 1914215976Sjmallett uint64_t tclk : 1; 1915215976Sjmallett uint64_t usbp_bist : 1; 1916215976Sjmallett uint64_t usbc_end : 1; 1917215976Sjmallett uint64_t dma_bmode : 1; 1918215976Sjmallett uint64_t txpreemphasistune : 1; 1919215976Sjmallett uint64_t siddq : 1; 1920215976Sjmallett uint64_t tdata_out : 4; 1921215976Sjmallett uint64_t bist_err : 1; 1922215976Sjmallett uint64_t bist_done : 1; 1923215976Sjmallett uint64_t hsbist : 1; 1924215976Sjmallett uint64_t fsbist : 1; 1925215976Sjmallett uint64_t lsbist : 1; 1926215976Sjmallett uint64_t drvvbus : 1; 1927215976Sjmallett uint64_t portreset : 1; 1928215976Sjmallett uint64_t otgdisable : 1; 1929215976Sjmallett uint64_t otgtune : 3; 1930215976Sjmallett uint64_t compdistune : 3; 1931215976Sjmallett uint64_t sqrxtune : 3; 1932215976Sjmallett uint64_t txhsxvtune : 2; 1933215976Sjmallett uint64_t txfslstune : 4; 1934215976Sjmallett uint64_t txvreftune : 4; 1935215976Sjmallett uint64_t txrisetune : 1; 1936215976Sjmallett#endif 1937215976Sjmallett } s; 1938232812Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn30xx { 1939232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1940215976Sjmallett uint64_t reserved_38_63 : 26; 1941215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 1942215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 1943215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 1944215976Sjmallett Indicates an internal error was detected during 1945215976Sjmallett the BIST sequence. */ 1946215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 1947215976Sjmallett Presents either internaly generated signals or 1948215976Sjmallett test register contents, based upon the value of 1949215976Sjmallett test_data_out_sel. */ 1950215976Sjmallett uint64_t reserved_30_31 : 2; 1951215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1952215976Sjmallett with byte-counts between packets. When set to 0 1953215976Sjmallett the L2C DMA address is incremented to the next 1954215976Sjmallett 4-byte aligned address after adding byte-count. */ 1955215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1956215976Sjmallett set to '0' for operation. */ 1957215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1958215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1959215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1960215976Sjmallett This signal enables the pull-down resistance on 1961215976Sjmallett the D+ line. '1' pull down-resistance is connected 1962215976Sjmallett to D+/ '0' pull down resistance is not connected 1963215976Sjmallett to D+. When an A/B device is acting as a host 1964215976Sjmallett (downstream-facing port), dp_pulldown and 1965215976Sjmallett dm_pulldown are enabled. This must not toggle 1966215976Sjmallett during normal opeartion. */ 1967215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1968215976Sjmallett This signal enables the pull-down resistance on 1969215976Sjmallett the D- line. '1' pull down-resistance is connected 1970215976Sjmallett to D-. '0' pull down resistance is not connected 1971215976Sjmallett to D-. When an A/B device is acting as a host 1972215976Sjmallett (downstream-facing port), dp_pulldown and 1973215976Sjmallett dm_pulldown are enabled. This must not toggle 1974215976Sjmallett during normal opeartion. */ 1975215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1976215976Sjmallett USB is acting as device. This field needs to be 1977215976Sjmallett set while the USB is in reset. */ 1978215976Sjmallett uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1979215976Sjmallett Tunes the current supply and rise/fall output 1980215976Sjmallett times for high-speed operation. 1981215976Sjmallett [20:19] == 11: Current supply increased 1982215976Sjmallett approximately 9% 1983215976Sjmallett [20:19] == 10: Current supply increased 1984215976Sjmallett approximately 4.5% 1985215976Sjmallett [20:19] == 01: Design default. 1986215976Sjmallett [20:19] == 00: Current supply decreased 1987215976Sjmallett approximately 4.5% 1988215976Sjmallett [22:21] == 11: Rise and fall times are increased. 1989215976Sjmallett [22:21] == 10: Design default. 1990215976Sjmallett [22:21] == 01: Rise and fall times are decreased. 1991215976Sjmallett [22:21] == 00: Rise and fall times are decreased 1992215976Sjmallett further as compared to the 01 setting. */ 1993215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1994215976Sjmallett Enables or disables bit stuffing on data[15:8] 1995215976Sjmallett when bit-stuffing is enabled. */ 1996215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1997215976Sjmallett Enables or disables bit stuffing on data[7:0] 1998215976Sjmallett when bit-stuffing is enabled. */ 1999215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2000215976Sjmallett '1': During data transmission the receive is 2001215976Sjmallett enabled. 2002215976Sjmallett '0': During data transmission the receive is 2003215976Sjmallett disabled. 2004215976Sjmallett Must be '0' for normal operation. */ 2005215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2006215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2007215976Sjmallett input and output of applicable analog test signals. 2008215976Sjmallett '0' THe analog_test pin is disabled. */ 2009215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2010215976Sjmallett Used to activate BIST in the PHY. */ 2011215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2012215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2013215976Sjmallett are output. '0' internaly generated signals are 2014215976Sjmallett output. */ 2015215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2016215976Sjmallett Specifies the register address for writing to or 2017215976Sjmallett reading from the PHY test interface register. */ 2018215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2019215976Sjmallett This is a test bus. Data is present on [3:0], 2020215976Sjmallett and its corresponding select (enable) is present 2021215976Sjmallett on bits [7:4]. */ 2022215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2023215976Sjmallett This is a test signal. When the USB Core is 2024215976Sjmallett powered up (not in Susned Mode), an automatic 2025215976Sjmallett tester can use this to disable phy_clock and 2026215976Sjmallett free_clk, then re-eanable them with an aligned 2027215976Sjmallett phase. 2028215976Sjmallett '1': The phy_clk and free_clk outputs are 2029215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2030215976Sjmallett are available within a specific period after the 2031215976Sjmallett de-assertion. */ 2032215976Sjmallett#else 2033215976Sjmallett uint64_t ate_reset : 1; 2034215976Sjmallett uint64_t tdata_in : 8; 2035215976Sjmallett uint64_t taddr_in : 4; 2036215976Sjmallett uint64_t tdata_sel : 1; 2037215976Sjmallett uint64_t bist_enb : 1; 2038215976Sjmallett uint64_t vtest_enb : 1; 2039215976Sjmallett uint64_t loop_enb : 1; 2040215976Sjmallett uint64_t tx_bs_en : 1; 2041215976Sjmallett uint64_t tx_bs_enh : 1; 2042215976Sjmallett uint64_t tuning : 4; 2043215976Sjmallett uint64_t hst_mode : 1; 2044215976Sjmallett uint64_t dm_pulld : 1; 2045215976Sjmallett uint64_t dp_pulld : 1; 2046215976Sjmallett uint64_t tclk : 1; 2047215976Sjmallett uint64_t usbp_bist : 1; 2048215976Sjmallett uint64_t usbc_end : 1; 2049215976Sjmallett uint64_t dma_bmode : 1; 2050215976Sjmallett uint64_t reserved_30_31 : 2; 2051215976Sjmallett uint64_t tdata_out : 4; 2052215976Sjmallett uint64_t bist_err : 1; 2053215976Sjmallett uint64_t bist_done : 1; 2054215976Sjmallett uint64_t reserved_38_63 : 26; 2055215976Sjmallett#endif 2056215976Sjmallett } cn30xx; 2057215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx; 2058232812Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx { 2059232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2060215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2061215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2062215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2063215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2064215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2065215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2066215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2067215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 2068215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 2069215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 2070215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2071215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2072215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2073215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 2074215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 2075215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 2076215976Sjmallett Indicates an internal error was detected during 2077215976Sjmallett the BIST sequence. */ 2078215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 2079215976Sjmallett Presents either internaly generated signals or 2080215976Sjmallett test register contents, based upon the value of 2081215976Sjmallett test_data_out_sel. */ 2082215976Sjmallett uint64_t reserved_31_31 : 1; 2083215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2084215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2085215976Sjmallett with byte-counts between packets. When set to 0 2086215976Sjmallett the L2C DMA address is incremented to the next 2087215976Sjmallett 4-byte aligned address after adding byte-count. */ 2088215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2089215976Sjmallett set to '0' for operation. */ 2090215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2091215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2092215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2093215976Sjmallett This signal enables the pull-down resistance on 2094215976Sjmallett the D+ line. '1' pull down-resistance is connected 2095215976Sjmallett to D+/ '0' pull down resistance is not connected 2096215976Sjmallett to D+. When an A/B device is acting as a host 2097215976Sjmallett (downstream-facing port), dp_pulldown and 2098215976Sjmallett dm_pulldown are enabled. This must not toggle 2099215976Sjmallett during normal opeartion. */ 2100215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2101215976Sjmallett This signal enables the pull-down resistance on 2102215976Sjmallett the D- line. '1' pull down-resistance is connected 2103215976Sjmallett to D-. '0' pull down resistance is not connected 2104215976Sjmallett to D-. When an A/B device is acting as a host 2105215976Sjmallett (downstream-facing port), dp_pulldown and 2106215976Sjmallett dm_pulldown are enabled. This must not toggle 2107215976Sjmallett during normal opeartion. */ 2108215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2109215976Sjmallett USB is acting as device. This field needs to be 2110215976Sjmallett set while the USB is in reset. */ 2111215976Sjmallett uint64_t reserved_19_22 : 4; 2112215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2113215976Sjmallett Enables or disables bit stuffing on data[15:8] 2114215976Sjmallett when bit-stuffing is enabled. */ 2115215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2116215976Sjmallett Enables or disables bit stuffing on data[7:0] 2117215976Sjmallett when bit-stuffing is enabled. */ 2118215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2119215976Sjmallett '1': During data transmission the receive is 2120215976Sjmallett enabled. 2121215976Sjmallett '0': During data transmission the receive is 2122215976Sjmallett disabled. 2123215976Sjmallett Must be '0' for normal operation. */ 2124215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2125215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2126215976Sjmallett input and output of applicable analog test signals. 2127215976Sjmallett '0' THe analog_test pin is disabled. */ 2128215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2129215976Sjmallett Used to activate BIST in the PHY. */ 2130215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2131215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2132215976Sjmallett are output. '0' internaly generated signals are 2133215976Sjmallett output. */ 2134215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2135215976Sjmallett Specifies the register address for writing to or 2136215976Sjmallett reading from the PHY test interface register. */ 2137215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2138215976Sjmallett This is a test bus. Data is present on [3:0], 2139215976Sjmallett and its corresponding select (enable) is present 2140215976Sjmallett on bits [7:4]. */ 2141215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2142215976Sjmallett This is a test signal. When the USB Core is 2143215976Sjmallett powered up (not in Susned Mode), an automatic 2144215976Sjmallett tester can use this to disable phy_clock and 2145215976Sjmallett free_clk, then re-eanable them with an aligned 2146215976Sjmallett phase. 2147215976Sjmallett '1': The phy_clk and free_clk outputs are 2148215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2149215976Sjmallett are available within a specific period after the 2150215976Sjmallett de-assertion. */ 2151215976Sjmallett#else 2152215976Sjmallett uint64_t ate_reset : 1; 2153215976Sjmallett uint64_t tdata_in : 8; 2154215976Sjmallett uint64_t taddr_in : 4; 2155215976Sjmallett uint64_t tdata_sel : 1; 2156215976Sjmallett uint64_t bist_enb : 1; 2157215976Sjmallett uint64_t vtest_enb : 1; 2158215976Sjmallett uint64_t loop_enb : 1; 2159215976Sjmallett uint64_t tx_bs_en : 1; 2160215976Sjmallett uint64_t tx_bs_enh : 1; 2161215976Sjmallett uint64_t reserved_19_22 : 4; 2162215976Sjmallett uint64_t hst_mode : 1; 2163215976Sjmallett uint64_t dm_pulld : 1; 2164215976Sjmallett uint64_t dp_pulld : 1; 2165215976Sjmallett uint64_t tclk : 1; 2166215976Sjmallett uint64_t usbp_bist : 1; 2167215976Sjmallett uint64_t usbc_end : 1; 2168215976Sjmallett uint64_t dma_bmode : 1; 2169215976Sjmallett uint64_t txpreemphasistune : 1; 2170215976Sjmallett uint64_t reserved_31_31 : 1; 2171215976Sjmallett uint64_t tdata_out : 4; 2172215976Sjmallett uint64_t bist_err : 1; 2173215976Sjmallett uint64_t bist_done : 1; 2174215976Sjmallett uint64_t hsbist : 1; 2175215976Sjmallett uint64_t fsbist : 1; 2176215976Sjmallett uint64_t lsbist : 1; 2177215976Sjmallett uint64_t drvvbus : 1; 2178215976Sjmallett uint64_t portreset : 1; 2179215976Sjmallett uint64_t otgdisable : 1; 2180215976Sjmallett uint64_t otgtune : 3; 2181215976Sjmallett uint64_t compdistune : 3; 2182215976Sjmallett uint64_t sqrxtune : 3; 2183215976Sjmallett uint64_t txhsxvtune : 2; 2184215976Sjmallett uint64_t txfslstune : 4; 2185215976Sjmallett uint64_t txvreftune : 4; 2186215976Sjmallett uint64_t txrisetune : 1; 2187215976Sjmallett#endif 2188215976Sjmallett } cn50xx; 2189232812Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn52xx { 2190232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2191215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2192215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2193215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2194215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2195215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2196215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2197215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2198215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 2199215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 2200215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 2201215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2202215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2203215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2204215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 2205215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 2206215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 2207215976Sjmallett Indicates an internal error was detected during 2208215976Sjmallett the BIST sequence. */ 2209215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 2210215976Sjmallett Presents either internaly generated signals or 2211215976Sjmallett test register contents, based upon the value of 2212215976Sjmallett test_data_out_sel. */ 2213215976Sjmallett uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 2214215976Sjmallett Normally should be set to zero. 2215215976Sjmallett When customers have no intent to use USB PHY 2216215976Sjmallett interface, they should: 2217215976Sjmallett - still provide 3.3V to USB_VDD33, and 2218215976Sjmallett - tie USB_REXT to 3.3V supply, and 2219215976Sjmallett - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 2220215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2221215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2222215976Sjmallett with byte-counts between packets. When set to 0 2223215976Sjmallett the L2C DMA address is incremented to the next 2224215976Sjmallett 4-byte aligned address after adding byte-count. */ 2225215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2226215976Sjmallett set to '0' for operation. */ 2227215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2228215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2229215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2230215976Sjmallett This signal enables the pull-down resistance on 2231215976Sjmallett the D+ line. '1' pull down-resistance is connected 2232215976Sjmallett to D+/ '0' pull down resistance is not connected 2233215976Sjmallett to D+. When an A/B device is acting as a host 2234215976Sjmallett (downstream-facing port), dp_pulldown and 2235215976Sjmallett dm_pulldown are enabled. This must not toggle 2236215976Sjmallett during normal opeartion. */ 2237215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2238215976Sjmallett This signal enables the pull-down resistance on 2239215976Sjmallett the D- line. '1' pull down-resistance is connected 2240215976Sjmallett to D-. '0' pull down resistance is not connected 2241215976Sjmallett to D-. When an A/B device is acting as a host 2242215976Sjmallett (downstream-facing port), dp_pulldown and 2243215976Sjmallett dm_pulldown are enabled. This must not toggle 2244215976Sjmallett during normal opeartion. */ 2245215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2246215976Sjmallett USB is acting as device. This field needs to be 2247215976Sjmallett set while the USB is in reset. */ 2248215976Sjmallett uint64_t reserved_19_22 : 4; 2249215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2250215976Sjmallett Enables or disables bit stuffing on data[15:8] 2251215976Sjmallett when bit-stuffing is enabled. */ 2252215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2253215976Sjmallett Enables or disables bit stuffing on data[7:0] 2254215976Sjmallett when bit-stuffing is enabled. */ 2255215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2256215976Sjmallett '1': During data transmission the receive is 2257215976Sjmallett enabled. 2258215976Sjmallett '0': During data transmission the receive is 2259215976Sjmallett disabled. 2260215976Sjmallett Must be '0' for normal operation. */ 2261215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2262215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2263215976Sjmallett input and output of applicable analog test signals. 2264215976Sjmallett '0' THe analog_test pin is disabled. */ 2265215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2266215976Sjmallett Used to activate BIST in the PHY. */ 2267215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2268215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2269215976Sjmallett are output. '0' internaly generated signals are 2270215976Sjmallett output. */ 2271215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2272215976Sjmallett Specifies the register address for writing to or 2273215976Sjmallett reading from the PHY test interface register. */ 2274215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2275215976Sjmallett This is a test bus. Data is present on [3:0], 2276215976Sjmallett and its corresponding select (enable) is present 2277215976Sjmallett on bits [7:4]. */ 2278215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2279215976Sjmallett This is a test signal. When the USB Core is 2280215976Sjmallett powered up (not in Susned Mode), an automatic 2281215976Sjmallett tester can use this to disable phy_clock and 2282215976Sjmallett free_clk, then re-eanable them with an aligned 2283215976Sjmallett phase. 2284215976Sjmallett '1': The phy_clk and free_clk outputs are 2285215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2286215976Sjmallett are available within a specific period after the 2287215976Sjmallett de-assertion. */ 2288215976Sjmallett#else 2289215976Sjmallett uint64_t ate_reset : 1; 2290215976Sjmallett uint64_t tdata_in : 8; 2291215976Sjmallett uint64_t taddr_in : 4; 2292215976Sjmallett uint64_t tdata_sel : 1; 2293215976Sjmallett uint64_t bist_enb : 1; 2294215976Sjmallett uint64_t vtest_enb : 1; 2295215976Sjmallett uint64_t loop_enb : 1; 2296215976Sjmallett uint64_t tx_bs_en : 1; 2297215976Sjmallett uint64_t tx_bs_enh : 1; 2298215976Sjmallett uint64_t reserved_19_22 : 4; 2299215976Sjmallett uint64_t hst_mode : 1; 2300215976Sjmallett uint64_t dm_pulld : 1; 2301215976Sjmallett uint64_t dp_pulld : 1; 2302215976Sjmallett uint64_t tclk : 1; 2303215976Sjmallett uint64_t usbp_bist : 1; 2304215976Sjmallett uint64_t usbc_end : 1; 2305215976Sjmallett uint64_t dma_bmode : 1; 2306215976Sjmallett uint64_t txpreemphasistune : 1; 2307215976Sjmallett uint64_t siddq : 1; 2308215976Sjmallett uint64_t tdata_out : 4; 2309215976Sjmallett uint64_t bist_err : 1; 2310215976Sjmallett uint64_t bist_done : 1; 2311215976Sjmallett uint64_t hsbist : 1; 2312215976Sjmallett uint64_t fsbist : 1; 2313215976Sjmallett uint64_t lsbist : 1; 2314215976Sjmallett uint64_t drvvbus : 1; 2315215976Sjmallett uint64_t portreset : 1; 2316215976Sjmallett uint64_t otgdisable : 1; 2317215976Sjmallett uint64_t otgtune : 3; 2318215976Sjmallett uint64_t compdistune : 3; 2319215976Sjmallett uint64_t sqrxtune : 3; 2320215976Sjmallett uint64_t txhsxvtune : 2; 2321215976Sjmallett uint64_t txfslstune : 4; 2322215976Sjmallett uint64_t txvreftune : 4; 2323215976Sjmallett uint64_t txrisetune : 1; 2324215976Sjmallett#endif 2325215976Sjmallett } cn52xx; 2326215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1; 2327215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx; 2328215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1; 2329215976Sjmallett}; 2330215976Sjmalletttypedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t; 2331215976Sjmallett 2332215976Sjmallett#endif 2333