1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-uctlx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon uctlx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_UCTLX_DEFS_H__ 53232812Sjmallett#define __CVMX_UCTLX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 64215976Sjmallett cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F0000A0ull); 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id) 72215976Sjmallett{ 73215976Sjmallett if (!( 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 75232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 79215976Sjmallett cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000000ull); 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id) 87215976Sjmallett{ 88215976Sjmallett if (!( 89232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 90232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 94215976Sjmallett cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000080ull); 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull)) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id) 102215976Sjmallett{ 103215976Sjmallett if (!( 104232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 105232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 106232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 109215976Sjmallett cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F0000A8ull); 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull)) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 121232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 122232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 123232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 124215976Sjmallett cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000090ull); 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull)) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id) 132215976Sjmallett{ 133215976Sjmallett if (!( 134232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 135232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 138232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 139215976Sjmallett cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000030ull); 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull)) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id) 147215976Sjmallett{ 148215976Sjmallett if (!( 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 154215976Sjmallett cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000028ull); 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull)) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id) 162215976Sjmallett{ 163215976Sjmallett if (!( 164232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 165232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 169215976Sjmallett cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000020ull); 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull)) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 184215976Sjmallett cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000088ull); 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull)) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id) 192215976Sjmallett{ 193215976Sjmallett if (!( 194232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 195232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 196232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 198232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 199215976Sjmallett cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000098ull); 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull)) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id) 207215976Sjmallett{ 208215976Sjmallett if (!( 209232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 210232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 211232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 212232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 213215976Sjmallett cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id); 214215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000038ull); 215215976Sjmallett} 216215976Sjmallett#else 217215976Sjmallett#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull)) 218215976Sjmallett#endif 219215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220215976Sjmallettstatic inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id) 221215976Sjmallett{ 222215976Sjmallett if (!( 223232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 224232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 225232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 228215976Sjmallett cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 229215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000008ull); 230215976Sjmallett} 231215976Sjmallett#else 232215976Sjmallett#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull)) 233215976Sjmallett#endif 234215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 235215976Sjmallettstatic inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id) 236215976Sjmallett{ 237215976Sjmallett if (!( 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 1)) && ((block_id == 0)))) || 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0)))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 1)) && ((block_id == 0)))) || 242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 1)) && ((block_id == 0)))))) 243215976Sjmallett cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id); 244215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8; 245215976Sjmallett} 246215976Sjmallett#else 247215976Sjmallett#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 248215976Sjmallett#endif 249215976Sjmallett 250215976Sjmallett/** 251215976Sjmallett * cvmx_uctl#_bist_status 252215976Sjmallett * 253215976Sjmallett * UCTL_BIST_STATUS = UCTL Bist Status 254215976Sjmallett * 255215976Sjmallett * Results from BIST runs of UCTL's memories. 256215976Sjmallett */ 257232812Sjmallettunion cvmx_uctlx_bist_status { 258215976Sjmallett uint64_t u64; 259232812Sjmallett struct cvmx_uctlx_bist_status_s { 260232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 261215976Sjmallett uint64_t reserved_6_63 : 58; 262215976Sjmallett uint64_t data_bis : 1; /**< UAHC EHCI Data Ram Bist Status */ 263215976Sjmallett uint64_t desc_bis : 1; /**< UAHC EHCI Descriptor Ram Bist Status */ 264215976Sjmallett uint64_t erbm_bis : 1; /**< UCTL EHCI Read Buffer Memory Bist Status */ 265215976Sjmallett uint64_t orbm_bis : 1; /**< UCTL OHCI Read Buffer Memory Bist Status */ 266215976Sjmallett uint64_t wrbm_bis : 1; /**< UCTL Write Buffer Memory Bist Sta */ 267215976Sjmallett uint64_t ppaf_bis : 1; /**< PP Access FIFO Memory Bist Status */ 268215976Sjmallett#else 269215976Sjmallett uint64_t ppaf_bis : 1; 270215976Sjmallett uint64_t wrbm_bis : 1; 271215976Sjmallett uint64_t orbm_bis : 1; 272215976Sjmallett uint64_t erbm_bis : 1; 273215976Sjmallett uint64_t desc_bis : 1; 274215976Sjmallett uint64_t data_bis : 1; 275215976Sjmallett uint64_t reserved_6_63 : 58; 276215976Sjmallett#endif 277215976Sjmallett } s; 278232812Sjmallett struct cvmx_uctlx_bist_status_s cn61xx; 279215976Sjmallett struct cvmx_uctlx_bist_status_s cn63xx; 280215976Sjmallett struct cvmx_uctlx_bist_status_s cn63xxp1; 281232812Sjmallett struct cvmx_uctlx_bist_status_s cn66xx; 282232812Sjmallett struct cvmx_uctlx_bist_status_s cn68xx; 283232812Sjmallett struct cvmx_uctlx_bist_status_s cn68xxp1; 284232812Sjmallett struct cvmx_uctlx_bist_status_s cnf71xx; 285215976Sjmallett}; 286215976Sjmalletttypedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t; 287215976Sjmallett 288215976Sjmallett/** 289215976Sjmallett * cvmx_uctl#_clk_rst_ctl 290215976Sjmallett * 291215976Sjmallett * CLK_RST_CTL = Clock and Reset Control Reigster 292215976Sjmallett * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists. 293215976Sjmallett */ 294232812Sjmallettunion cvmx_uctlx_clk_rst_ctl { 295215976Sjmallett uint64_t u64; 296232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s { 297232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 298215976Sjmallett uint64_t reserved_25_63 : 39; 299215976Sjmallett uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */ 300215976Sjmallett uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1 301215976Sjmallett transition. */ 302215976Sjmallett uint64_t ehci_sm : 1; /**< Only set it during simulation time. When set to 1, 303215976Sjmallett this bit sets the PHY in a non-driving mode so the 304215976Sjmallett EHCI can detect device connection. 305215976Sjmallett Note: it must not be set to 1, during normal 306215976Sjmallett operation. */ 307215976Sjmallett uint64_t ohci_clkcktrst : 1; /**< Clear clock reset. Active low. OHCI initial reset 308215976Sjmallett signal for the DPLL block. This is only needed by 309215976Sjmallett simulation. The duration of the reset in simulation 310215976Sjmallett must be the same as HRST. 311215976Sjmallett Note: it must be set to 1 during normal operation. */ 312215976Sjmallett uint64_t ohci_sm : 1; /**< OHCI Simulation Mode. It selects the counter value 313215976Sjmallett for simulation or real time for 1 ms. 314215976Sjmallett - 0: counter full 1ms; 1: simulation time. */ 315215976Sjmallett uint64_t ohci_susp_lgcy : 1; /**< OHCI Clock Control Signal. Note: This bit must be 316215976Sjmallett set to 0 if the OHCI 48/12Mhz clocks must be 317215976Sjmallett suspended when the EHCI and OHCI controllers are 318215976Sjmallett not active. */ 319215976Sjmallett uint64_t app_start_clk : 1; /**< OHCI Clock Control Signal. When the OHCI clocks are 320215976Sjmallett suspended, the system has to assert this signal to 321215976Sjmallett start the clocks (12 and 48 Mhz). */ 322215976Sjmallett uint64_t o_clkdiv_rst : 1; /**< OHCI 12Mhz clock divider reset. Active low. When 323215976Sjmallett set to 0, divider is held in reset. 324215976Sjmallett The reset to the divider is also asserted when core 325215976Sjmallett reset is asserted. */ 326215976Sjmallett uint64_t h_clkdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV */ 327215976Sjmallett uint64_t h_clkdiv_rst : 1; /**< Host clock divider reset. Active low. When set to 0, 328215976Sjmallett divider is held in reset. This must be set to 0 329215976Sjmallett before change H_DIV0 and H_DIV1. 330215976Sjmallett The reset to the divider is also asserted when core 331215976Sjmallett reset is asserted. */ 332215976Sjmallett uint64_t h_clkdiv_en : 1; /**< Hclk enable. When set to 1, the hclk is gernerated. */ 333215976Sjmallett uint64_t o_clkdiv_en : 1; /**< OHCI 48Mhz/12MHz clock enable. When set to 1, the 334215976Sjmallett clocks are gernerated. */ 335215976Sjmallett uint64_t h_div : 4; /**< The hclk frequency is sclk frequency divided by 336215976Sjmallett H_DIV. The maximum frequency of hclk is 200Mhz. 337215976Sjmallett The minimum frequency of hclk is no less than the 338215976Sjmallett UTMI clock frequency which is 60Mhz. After writing a 339215976Sjmallett value to this field, the software should read the 340215976Sjmallett field for the value written. The [H_ENABLE] field of 341215976Sjmallett this register should not be set until after this 342215976Sjmallett field is set and then read. 343215976Sjmallett Only the following values are valid: 344215976Sjmallett 1, 2, 3, 4, 6, 8, 12. 345215976Sjmallett All other values are reserved and will be coded as 346215976Sjmallett following: 347215976Sjmallett 0 -> 1 348215976Sjmallett 5 -> 4 349215976Sjmallett 7 -> 6 350215976Sjmallett 9,10,11 -> 8 351215976Sjmallett 13,14,15 -> 12 */ 352215976Sjmallett uint64_t p_refclk_sel : 2; /**< PHY PLL Reference Clock Select. 353215976Sjmallett - 00: uses 12Mhz crystal at USB_XO and USB_XI; 354215976Sjmallett - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO. 355232812Sjmallett USB_XI should be tied to GND(Not Supported). 356215976Sjmallett 1x: Reserved. */ 357215976Sjmallett uint64_t p_refclk_div : 2; /**< PHY Reference Clock Frequency Select. 358232812Sjmallett - 00: 12MHz, 359232812Sjmallett - 01: 24Mhz (Not Supported), 360232812Sjmallett - 10: 48Mhz (Not Supported), 361232812Sjmallett - 11: Reserved. 362215976Sjmallett Note: This value must be set during POR is active. 363215976Sjmallett If a crystal is used as a reference clock,this field 364215976Sjmallett must be set to 12 MHz. Values 01 and 10 are reserved 365215976Sjmallett when a crystal is used. */ 366215976Sjmallett uint64_t reserved_4_4 : 1; 367215976Sjmallett uint64_t p_com_on : 1; /**< PHY Common Block Power-Down Control. 368215976Sjmallett - 1: The XO, Bias, and PLL blocks are powered down in 369215976Sjmallett Suspend mode. 370215976Sjmallett - 0: The XO, Bias, and PLL blocks remain powered in 371215976Sjmallett suspend mode. 372215976Sjmallett Note: This bit must be set to 0 during POR is active 373215976Sjmallett in current design. */ 374215976Sjmallett uint64_t p_por : 1; /**< Power on reset for PHY. Resets all the PHY's 375215976Sjmallett registers and state machines. */ 376215976Sjmallett uint64_t p_prst : 1; /**< PHY Clock Reset. The is the value for phy_rst_n, 377215976Sjmallett utmi_rst_n[1] and utmi_rst_n[0]. It is synchronized 378215976Sjmallett to each clock domain to generate the corresponding 379215976Sjmallett reset signal. This should not be set to 1 until the 380215976Sjmallett time it takes for six clock cycles (HCLK and 381215976Sjmallett PHY CLK, which ever is slower) has passed. */ 382215976Sjmallett uint64_t hrst : 1; /**< Host Clock Reset. This is the value for hreset_n. 383215976Sjmallett This should not be set to 1 until 12ms after PHY CLK 384215976Sjmallett is stable. */ 385215976Sjmallett#else 386215976Sjmallett uint64_t hrst : 1; 387215976Sjmallett uint64_t p_prst : 1; 388215976Sjmallett uint64_t p_por : 1; 389215976Sjmallett uint64_t p_com_on : 1; 390215976Sjmallett uint64_t reserved_4_4 : 1; 391215976Sjmallett uint64_t p_refclk_div : 2; 392215976Sjmallett uint64_t p_refclk_sel : 2; 393215976Sjmallett uint64_t h_div : 4; 394215976Sjmallett uint64_t o_clkdiv_en : 1; 395215976Sjmallett uint64_t h_clkdiv_en : 1; 396215976Sjmallett uint64_t h_clkdiv_rst : 1; 397215976Sjmallett uint64_t h_clkdiv_byp : 1; 398215976Sjmallett uint64_t o_clkdiv_rst : 1; 399215976Sjmallett uint64_t app_start_clk : 1; 400215976Sjmallett uint64_t ohci_susp_lgcy : 1; 401215976Sjmallett uint64_t ohci_sm : 1; 402215976Sjmallett uint64_t ohci_clkcktrst : 1; 403215976Sjmallett uint64_t ehci_sm : 1; 404215976Sjmallett uint64_t start_bist : 1; 405215976Sjmallett uint64_t clear_bist : 1; 406215976Sjmallett uint64_t reserved_25_63 : 39; 407215976Sjmallett#endif 408215976Sjmallett } s; 409232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn61xx; 410215976Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn63xx; 411215976Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; 412232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn66xx; 413232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn68xx; 414232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1; 415232812Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cnf71xx; 416215976Sjmallett}; 417215976Sjmalletttypedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t; 418215976Sjmallett 419215976Sjmallett/** 420215976Sjmallett * cvmx_uctl#_ehci_ctl 421215976Sjmallett * 422215976Sjmallett * UCTL_EHCI_CTL = UCTL EHCI Control Register 423215976Sjmallett * This register controls the general behavior of UCTL EHCI datapath. 424215976Sjmallett */ 425232812Sjmallettunion cvmx_uctlx_ehci_ctl { 426215976Sjmallett uint64_t u64; 427232812Sjmallett struct cvmx_uctlx_ehci_ctl_s { 428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 429215976Sjmallett uint64_t reserved_20_63 : 44; 430215976Sjmallett uint64_t desc_rbm : 1; /**< Descriptor Read Burst Mode on AHB bus 431215976Sjmallett - 1: A read burst can be interruprted after 16 AHB 432215976Sjmallett clock cycle 433215976Sjmallett - 0: A read burst will not be interrupted until it 434215976Sjmallett finishes or no more data available */ 435215976Sjmallett uint64_t reg_nb : 1; /**< 1: EHCI register access will not be blocked by EHCI 436215976Sjmallett buffer/descriptor access on AHB 437215976Sjmallett - 0: Buffer/descriptor and register access will be 438215976Sjmallett mutually exclusive */ 439215976Sjmallett uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 440215976Sjmallett store commands to L2C. */ 441215976Sjmallett uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 442215976Sjmallett store commands to L2C. */ 443215976Sjmallett uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 444215976Sjmallett command to L2C. */ 445215976Sjmallett uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 446215976Sjmallett uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 447215976Sjmallett IN: A-B-C-D-E-F-G-H 448215976Sjmallett OUT0: A-B-C-D-E-F-G-H 449215976Sjmallett OUT1: H-G-F-E-D-C-B-A 450215976Sjmallett OUT2: D-C-B-A-H-G-F-E 451215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 452215976Sjmallett uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 453215976Sjmallett IN: A-B-C-D-E-F-G-H 454215976Sjmallett OUT0: A-B-C-D-E-F-G-H 455215976Sjmallett OUT1: H-G-F-E-D-C-B-A 456215976Sjmallett OUT2: D-C-B-A-H-G-F-E 457215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 458215976Sjmallett uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 459215976Sjmallett for a 32-bit NCB I/O register access, the address 460215976Sjmallett offset will be flipped between 0x4 and 0x0. */ 461215976Sjmallett uint64_t ehci_64b_addr_en : 1; /**< EHCI AHB Master 64-bit Addressing Enable. 462215976Sjmallett - 1: enable ehci 64-bit addressing mode; 463215976Sjmallett - 0: disable ehci 64-bit addressing mode. 464215976Sjmallett When ehci 64-bit addressing mode is disabled, 465215976Sjmallett UCTL_EHCI_CTL[L2C_ADDR_MSB] is used as the address 466215976Sjmallett bit[39:32]. */ 467215976Sjmallett uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 468215976Sjmallett for ehci whenUCTL_EHCI_CFG[EHCI_64B_ADDR_EN=0]). */ 469215976Sjmallett#else 470215976Sjmallett uint64_t l2c_addr_msb : 8; 471215976Sjmallett uint64_t ehci_64b_addr_en : 1; 472215976Sjmallett uint64_t inv_reg_a2 : 1; 473215976Sjmallett uint64_t l2c_desc_emod : 2; 474215976Sjmallett uint64_t l2c_buff_emod : 2; 475215976Sjmallett uint64_t l2c_stt : 1; 476215976Sjmallett uint64_t l2c_0pag : 1; 477215976Sjmallett uint64_t l2c_bc : 1; 478215976Sjmallett uint64_t l2c_dc : 1; 479215976Sjmallett uint64_t reg_nb : 1; 480215976Sjmallett uint64_t desc_rbm : 1; 481215976Sjmallett uint64_t reserved_20_63 : 44; 482215976Sjmallett#endif 483215976Sjmallett } s; 484232812Sjmallett struct cvmx_uctlx_ehci_ctl_s cn61xx; 485215976Sjmallett struct cvmx_uctlx_ehci_ctl_s cn63xx; 486215976Sjmallett struct cvmx_uctlx_ehci_ctl_s cn63xxp1; 487232812Sjmallett struct cvmx_uctlx_ehci_ctl_s cn66xx; 488232812Sjmallett struct cvmx_uctlx_ehci_ctl_s cn68xx; 489232812Sjmallett struct cvmx_uctlx_ehci_ctl_s cn68xxp1; 490232812Sjmallett struct cvmx_uctlx_ehci_ctl_s cnf71xx; 491215976Sjmallett}; 492215976Sjmalletttypedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t; 493215976Sjmallett 494215976Sjmallett/** 495215976Sjmallett * cvmx_uctl#_ehci_fla 496215976Sjmallett * 497215976Sjmallett * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register 498215976Sjmallett * This register configures the EHCI Frame Length Adjustment. 499215976Sjmallett */ 500232812Sjmallettunion cvmx_uctlx_ehci_fla { 501215976Sjmallett uint64_t u64; 502232812Sjmallett struct cvmx_uctlx_ehci_fla_s { 503232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 504215976Sjmallett uint64_t reserved_6_63 : 58; 505215976Sjmallett uint64_t fla : 6; /**< EHCI Frame Length Adjustment. This feature 506215976Sjmallett adjusts any offset from the clock source that drives 507232812Sjmallett the uSOF counter. The uSOF cycle time (number of 508232812Sjmallett uSOF counter clock periods to generate a uSOF 509232812Sjmallett microframe length) is equal to 59,488 plus this value. 510232812Sjmallett The default value is 32(0x20), which gives an SOF cycle 511232812Sjmallett time of 60,000 (each microframe has 60,000 bit times). 512232812Sjmallett ------------------------------------------------- 513232812Sjmallett Frame Length (decimal) FLA Value 514232812Sjmallett ------------------------------------------------- 515232812Sjmallett 59488 0x00 516232812Sjmallett 59504 0x01 517232812Sjmallett 59520 0x02 518232812Sjmallett ... ... 519232812Sjmallett 59984 0x1F 520232812Sjmallett 60000 0x20 521232812Sjmallett 60016 0x21 522232812Sjmallett ... ... 523232812Sjmallett 60496 0x3F 524232812Sjmallett -------------------------------------------------- 525215976Sjmallett Note: keep this value to 0x20 (decimal 32) for no 526215976Sjmallett offset. */ 527215976Sjmallett#else 528215976Sjmallett uint64_t fla : 6; 529215976Sjmallett uint64_t reserved_6_63 : 58; 530215976Sjmallett#endif 531215976Sjmallett } s; 532232812Sjmallett struct cvmx_uctlx_ehci_fla_s cn61xx; 533215976Sjmallett struct cvmx_uctlx_ehci_fla_s cn63xx; 534215976Sjmallett struct cvmx_uctlx_ehci_fla_s cn63xxp1; 535232812Sjmallett struct cvmx_uctlx_ehci_fla_s cn66xx; 536232812Sjmallett struct cvmx_uctlx_ehci_fla_s cn68xx; 537232812Sjmallett struct cvmx_uctlx_ehci_fla_s cn68xxp1; 538232812Sjmallett struct cvmx_uctlx_ehci_fla_s cnf71xx; 539215976Sjmallett}; 540215976Sjmalletttypedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t; 541215976Sjmallett 542215976Sjmallett/** 543215976Sjmallett * cvmx_uctl#_erto_ctl 544215976Sjmallett * 545215976Sjmallett * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register 546215976Sjmallett * This register controls timeout for EHCI Readbuffer. 547215976Sjmallett */ 548232812Sjmallettunion cvmx_uctlx_erto_ctl { 549215976Sjmallett uint64_t u64; 550232812Sjmallett struct cvmx_uctlx_erto_ctl_s { 551232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 552215976Sjmallett uint64_t reserved_32_63 : 32; 553215976Sjmallett uint64_t to_val : 27; /**< Read buffer timeout value 554215976Sjmallett (value 0 means timeout disabled) */ 555215976Sjmallett uint64_t reserved_0_4 : 5; 556215976Sjmallett#else 557215976Sjmallett uint64_t reserved_0_4 : 5; 558215976Sjmallett uint64_t to_val : 27; 559215976Sjmallett uint64_t reserved_32_63 : 32; 560215976Sjmallett#endif 561215976Sjmallett } s; 562232812Sjmallett struct cvmx_uctlx_erto_ctl_s cn61xx; 563215976Sjmallett struct cvmx_uctlx_erto_ctl_s cn63xx; 564215976Sjmallett struct cvmx_uctlx_erto_ctl_s cn63xxp1; 565232812Sjmallett struct cvmx_uctlx_erto_ctl_s cn66xx; 566232812Sjmallett struct cvmx_uctlx_erto_ctl_s cn68xx; 567232812Sjmallett struct cvmx_uctlx_erto_ctl_s cn68xxp1; 568232812Sjmallett struct cvmx_uctlx_erto_ctl_s cnf71xx; 569215976Sjmallett}; 570215976Sjmalletttypedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t; 571215976Sjmallett 572215976Sjmallett/** 573215976Sjmallett * cvmx_uctl#_if_ena 574215976Sjmallett * 575215976Sjmallett * UCTL_IF_ENA = UCTL Interface Enable Register 576215976Sjmallett * 577215976Sjmallett * Register to enable the uctl interface clock. 578215976Sjmallett */ 579232812Sjmallettunion cvmx_uctlx_if_ena { 580215976Sjmallett uint64_t u64; 581232812Sjmallett struct cvmx_uctlx_if_ena_s { 582232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 583215976Sjmallett uint64_t reserved_1_63 : 63; 584215976Sjmallett uint64_t en : 1; /**< Turns on the USB UCTL interface clock */ 585215976Sjmallett#else 586215976Sjmallett uint64_t en : 1; 587215976Sjmallett uint64_t reserved_1_63 : 63; 588215976Sjmallett#endif 589215976Sjmallett } s; 590232812Sjmallett struct cvmx_uctlx_if_ena_s cn61xx; 591215976Sjmallett struct cvmx_uctlx_if_ena_s cn63xx; 592215976Sjmallett struct cvmx_uctlx_if_ena_s cn63xxp1; 593232812Sjmallett struct cvmx_uctlx_if_ena_s cn66xx; 594232812Sjmallett struct cvmx_uctlx_if_ena_s cn68xx; 595232812Sjmallett struct cvmx_uctlx_if_ena_s cn68xxp1; 596232812Sjmallett struct cvmx_uctlx_if_ena_s cnf71xx; 597215976Sjmallett}; 598215976Sjmalletttypedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t; 599215976Sjmallett 600215976Sjmallett/** 601215976Sjmallett * cvmx_uctl#_int_ena 602215976Sjmallett * 603215976Sjmallett * UCTL_INT_ENA = UCTL Interrupt Enable Register 604215976Sjmallett * 605215976Sjmallett * Register to enable individual interrupt source in corresponding to UCTL_INT_REG 606215976Sjmallett */ 607232812Sjmallettunion cvmx_uctlx_int_ena { 608215976Sjmallett uint64_t u64; 609232812Sjmallett struct cvmx_uctlx_int_ena_s { 610232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 611215976Sjmallett uint64_t reserved_8_63 : 56; 612215976Sjmallett uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error */ 613215976Sjmallett uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error */ 614215976Sjmallett uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 615215976Sjmallett uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 616215976Sjmallett uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 617215976Sjmallett uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 618215976Sjmallett uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 619215976Sjmallett uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 620215976Sjmallett#else 621215976Sjmallett uint64_t pp_psh_f : 1; 622215976Sjmallett uint64_t er_psh_f : 1; 623215976Sjmallett uint64_t or_psh_f : 1; 624215976Sjmallett uint64_t cf_psh_f : 1; 625215976Sjmallett uint64_t wb_psh_f : 1; 626215976Sjmallett uint64_t wb_pop_e : 1; 627215976Sjmallett uint64_t oc_ovf_e : 1; 628215976Sjmallett uint64_t ec_ovf_e : 1; 629215976Sjmallett uint64_t reserved_8_63 : 56; 630215976Sjmallett#endif 631215976Sjmallett } s; 632232812Sjmallett struct cvmx_uctlx_int_ena_s cn61xx; 633215976Sjmallett struct cvmx_uctlx_int_ena_s cn63xx; 634215976Sjmallett struct cvmx_uctlx_int_ena_s cn63xxp1; 635232812Sjmallett struct cvmx_uctlx_int_ena_s cn66xx; 636232812Sjmallett struct cvmx_uctlx_int_ena_s cn68xx; 637232812Sjmallett struct cvmx_uctlx_int_ena_s cn68xxp1; 638232812Sjmallett struct cvmx_uctlx_int_ena_s cnf71xx; 639215976Sjmallett}; 640215976Sjmalletttypedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t; 641215976Sjmallett 642215976Sjmallett/** 643215976Sjmallett * cvmx_uctl#_int_reg 644215976Sjmallett * 645215976Sjmallett * UCTL_INT_REG = UCTL Interrupt Register 646215976Sjmallett * 647215976Sjmallett * Summary of different bits of RSL interrupt status. 648215976Sjmallett */ 649232812Sjmallettunion cvmx_uctlx_int_reg { 650215976Sjmallett uint64_t u64; 651232812Sjmallett struct cvmx_uctlx_int_reg_s { 652232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 653215976Sjmallett uint64_t reserved_8_63 : 56; 654215976Sjmallett uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error 655215976Sjmallett When the error happenes, the whole NCB system needs 656215976Sjmallett to be reset. */ 657215976Sjmallett uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error 658215976Sjmallett When the error happenes, the whole NCB system needs 659215976Sjmallett to be reset. */ 660215976Sjmallett uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 661215976Sjmallett uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 662215976Sjmallett uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 663215976Sjmallett uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 664215976Sjmallett uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 665215976Sjmallett uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 666215976Sjmallett#else 667215976Sjmallett uint64_t pp_psh_f : 1; 668215976Sjmallett uint64_t er_psh_f : 1; 669215976Sjmallett uint64_t or_psh_f : 1; 670215976Sjmallett uint64_t cf_psh_f : 1; 671215976Sjmallett uint64_t wb_psh_f : 1; 672215976Sjmallett uint64_t wb_pop_e : 1; 673215976Sjmallett uint64_t oc_ovf_e : 1; 674215976Sjmallett uint64_t ec_ovf_e : 1; 675215976Sjmallett uint64_t reserved_8_63 : 56; 676215976Sjmallett#endif 677215976Sjmallett } s; 678232812Sjmallett struct cvmx_uctlx_int_reg_s cn61xx; 679215976Sjmallett struct cvmx_uctlx_int_reg_s cn63xx; 680215976Sjmallett struct cvmx_uctlx_int_reg_s cn63xxp1; 681232812Sjmallett struct cvmx_uctlx_int_reg_s cn66xx; 682232812Sjmallett struct cvmx_uctlx_int_reg_s cn68xx; 683232812Sjmallett struct cvmx_uctlx_int_reg_s cn68xxp1; 684232812Sjmallett struct cvmx_uctlx_int_reg_s cnf71xx; 685215976Sjmallett}; 686215976Sjmalletttypedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t; 687215976Sjmallett 688215976Sjmallett/** 689215976Sjmallett * cvmx_uctl#_ohci_ctl 690215976Sjmallett * 691215976Sjmallett * RSL registers starting from 0x10 can be accessed only after hclk is active and hreset is deasserted. 692215976Sjmallett * 693215976Sjmallett * UCTL_OHCI_CTL = UCTL OHCI Control Register 694215976Sjmallett * This register controls the general behavior of UCTL OHCI datapath. 695215976Sjmallett */ 696232812Sjmallettunion cvmx_uctlx_ohci_ctl { 697215976Sjmallett uint64_t u64; 698232812Sjmallett struct cvmx_uctlx_ohci_ctl_s { 699232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 700215976Sjmallett uint64_t reserved_19_63 : 45; 701215976Sjmallett uint64_t reg_nb : 1; /**< 1: OHCI register access will not be blocked by EHCI 702215976Sjmallett buffer/descriptor access on AHB 703215976Sjmallett - 0: Buffer/descriptor and register access will be 704215976Sjmallett mutually exclusive */ 705215976Sjmallett uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 706215976Sjmallett store commands to L2C. */ 707215976Sjmallett uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 708215976Sjmallett store commands to L2C. */ 709215976Sjmallett uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 710215976Sjmallett command to L2C. */ 711215976Sjmallett uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 712215976Sjmallett uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 713215976Sjmallett IN: A-B-C-D-E-F-G-H 714215976Sjmallett OUT0: A-B-C-D-E-F-G-H 715215976Sjmallett OUT1: H-G-F-E-D-C-B-A 716215976Sjmallett OUT2: D-C-B-A-H-G-F-E 717215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 718215976Sjmallett uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 719215976Sjmallett IN: A-B-C-D-E-F-G-H 720215976Sjmallett OUT0: A-B-C-D-E-F-G-H 721215976Sjmallett OUT1: H-G-F-E-D-C-B-A 722215976Sjmallett OUT2: D-C-B-A-H-G-F-E 723215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 724215976Sjmallett uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 725215976Sjmallett for a 32-bit NCB I/O register access, the address 726215976Sjmallett offset will be flipped between 0x4 and 0x0. */ 727215976Sjmallett uint64_t reserved_8_8 : 1; 728215976Sjmallett uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 729215976Sjmallett for ohci. */ 730215976Sjmallett#else 731215976Sjmallett uint64_t l2c_addr_msb : 8; 732215976Sjmallett uint64_t reserved_8_8 : 1; 733215976Sjmallett uint64_t inv_reg_a2 : 1; 734215976Sjmallett uint64_t l2c_desc_emod : 2; 735215976Sjmallett uint64_t l2c_buff_emod : 2; 736215976Sjmallett uint64_t l2c_stt : 1; 737215976Sjmallett uint64_t l2c_0pag : 1; 738215976Sjmallett uint64_t l2c_bc : 1; 739215976Sjmallett uint64_t l2c_dc : 1; 740215976Sjmallett uint64_t reg_nb : 1; 741215976Sjmallett uint64_t reserved_19_63 : 45; 742215976Sjmallett#endif 743215976Sjmallett } s; 744232812Sjmallett struct cvmx_uctlx_ohci_ctl_s cn61xx; 745215976Sjmallett struct cvmx_uctlx_ohci_ctl_s cn63xx; 746215976Sjmallett struct cvmx_uctlx_ohci_ctl_s cn63xxp1; 747232812Sjmallett struct cvmx_uctlx_ohci_ctl_s cn66xx; 748232812Sjmallett struct cvmx_uctlx_ohci_ctl_s cn68xx; 749232812Sjmallett struct cvmx_uctlx_ohci_ctl_s cn68xxp1; 750232812Sjmallett struct cvmx_uctlx_ohci_ctl_s cnf71xx; 751215976Sjmallett}; 752215976Sjmalletttypedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t; 753215976Sjmallett 754215976Sjmallett/** 755215976Sjmallett * cvmx_uctl#_orto_ctl 756215976Sjmallett * 757215976Sjmallett * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register 758215976Sjmallett * This register controls timeout for OHCI Readbuffer. 759215976Sjmallett */ 760232812Sjmallettunion cvmx_uctlx_orto_ctl { 761215976Sjmallett uint64_t u64; 762232812Sjmallett struct cvmx_uctlx_orto_ctl_s { 763232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 764215976Sjmallett uint64_t reserved_32_63 : 32; 765215976Sjmallett uint64_t to_val : 24; /**< Read buffer timeout value 766215976Sjmallett (value 0 means timeout disabled) */ 767215976Sjmallett uint64_t reserved_0_7 : 8; 768215976Sjmallett#else 769215976Sjmallett uint64_t reserved_0_7 : 8; 770215976Sjmallett uint64_t to_val : 24; 771215976Sjmallett uint64_t reserved_32_63 : 32; 772215976Sjmallett#endif 773215976Sjmallett } s; 774232812Sjmallett struct cvmx_uctlx_orto_ctl_s cn61xx; 775215976Sjmallett struct cvmx_uctlx_orto_ctl_s cn63xx; 776215976Sjmallett struct cvmx_uctlx_orto_ctl_s cn63xxp1; 777232812Sjmallett struct cvmx_uctlx_orto_ctl_s cn66xx; 778232812Sjmallett struct cvmx_uctlx_orto_ctl_s cn68xx; 779232812Sjmallett struct cvmx_uctlx_orto_ctl_s cn68xxp1; 780232812Sjmallett struct cvmx_uctlx_orto_ctl_s cnf71xx; 781215976Sjmallett}; 782215976Sjmalletttypedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t; 783215976Sjmallett 784215976Sjmallett/** 785215976Sjmallett * cvmx_uctl#_ppaf_wm 786215976Sjmallett * 787215976Sjmallett * UCTL_PPAF_WM = UCTL PP Access FIFO WaterMark Register 788215976Sjmallett * 789215976Sjmallett * Register to set PP access FIFO full watermark. 790215976Sjmallett */ 791232812Sjmallettunion cvmx_uctlx_ppaf_wm { 792215976Sjmallett uint64_t u64; 793232812Sjmallett struct cvmx_uctlx_ppaf_wm_s { 794232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 795215976Sjmallett uint64_t reserved_5_63 : 59; 796215976Sjmallett uint64_t wm : 5; /**< Number of entries when PP Access FIFO will assert 797215976Sjmallett full (back pressure) */ 798215976Sjmallett#else 799215976Sjmallett uint64_t wm : 5; 800215976Sjmallett uint64_t reserved_5_63 : 59; 801215976Sjmallett#endif 802215976Sjmallett } s; 803232812Sjmallett struct cvmx_uctlx_ppaf_wm_s cn61xx; 804215976Sjmallett struct cvmx_uctlx_ppaf_wm_s cn63xx; 805215976Sjmallett struct cvmx_uctlx_ppaf_wm_s cn63xxp1; 806232812Sjmallett struct cvmx_uctlx_ppaf_wm_s cn66xx; 807232812Sjmallett struct cvmx_uctlx_ppaf_wm_s cnf71xx; 808215976Sjmallett}; 809215976Sjmalletttypedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t; 810215976Sjmallett 811215976Sjmallett/** 812215976Sjmallett * cvmx_uctl#_uphy_ctl_status 813215976Sjmallett * 814215976Sjmallett * UPHY_CTL_STATUS = USB PHY Control and Status Reigster 815215976Sjmallett * This register controls the USB PHY test and Bist. 816215976Sjmallett */ 817232812Sjmallettunion cvmx_uctlx_uphy_ctl_status { 818215976Sjmallett uint64_t u64; 819232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s { 820232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 821215976Sjmallett uint64_t reserved_10_63 : 54; 822215976Sjmallett uint64_t bist_done : 1; /**< PHY BIST DONE. Asserted at the end of the PHY BIST 823215976Sjmallett sequence. */ 824215976Sjmallett uint64_t bist_err : 1; /**< PHY BIST Error. Valid when BIST_ENB is high. 825215976Sjmallett Indicates an internal error was detected during the 826215976Sjmallett BIST sequence. */ 827215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable */ 828215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable */ 829215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable */ 830215976Sjmallett uint64_t siddq : 1; /**< Drives the PHY SIDDQ input. Normally should be set 831215976Sjmallett to zero. Customers not using USB PHY interface 832215976Sjmallett should do the following: 833215976Sjmallett Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V 834215976Sjmallett supply and Set SIDDQ to 1. */ 835215976Sjmallett uint64_t vtest_en : 1; /**< Analog Test Pin Enable. 836232812Sjmallett 1 = The PHY's ANALOG_TEST pin is enabled for the 837215976Sjmallett input and output of applicable analog test 838215976Sjmallett signals. 839215976Sjmallett 0 = The ANALOG_TEST pin is disabled. */ 840215976Sjmallett uint64_t uphy_bist : 1; /**< When set to 1, it makes sure that during PHY BIST, 841215976Sjmallett utmi_txvld == 0. */ 842215976Sjmallett uint64_t bist_en : 1; /**< PHY BIST ENABLE */ 843215976Sjmallett uint64_t ate_reset : 1; /**< Reset Input from ATE. This is a test signal. When 844215976Sjmallett the USB core is powered up (not in suspend mode), an 845215976Sjmallett automatic tester can use this to disable PHYCLOCK 846215976Sjmallett and FREECLK, then re-enable them with an aligned 847215976Sjmallett phase. 848215976Sjmallett - 1: PHYCLOCKs and FREECLK outputs are disable. 849215976Sjmallett - 0: PHYCLOCKs and FREECLK are available within a 850215976Sjmallett specific period after ATERESET is de-asserted. */ 851215976Sjmallett#else 852215976Sjmallett uint64_t ate_reset : 1; 853215976Sjmallett uint64_t bist_en : 1; 854215976Sjmallett uint64_t uphy_bist : 1; 855215976Sjmallett uint64_t vtest_en : 1; 856215976Sjmallett uint64_t siddq : 1; 857215976Sjmallett uint64_t lsbist : 1; 858215976Sjmallett uint64_t fsbist : 1; 859215976Sjmallett uint64_t hsbist : 1; 860215976Sjmallett uint64_t bist_err : 1; 861215976Sjmallett uint64_t bist_done : 1; 862215976Sjmallett uint64_t reserved_10_63 : 54; 863215976Sjmallett#endif 864215976Sjmallett } s; 865232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn61xx; 866215976Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn63xx; 867215976Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; 868232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn66xx; 869232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn68xx; 870232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1; 871232812Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cnf71xx; 872215976Sjmallett}; 873215976Sjmalletttypedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t; 874215976Sjmallett 875215976Sjmallett/** 876215976Sjmallett * cvmx_uctl#_uphy_port#_ctl_status 877215976Sjmallett * 878215976Sjmallett * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters 879215976Sjmallett * This register controls the each port of the USB PHY. 880215976Sjmallett */ 881232812Sjmallettunion cvmx_uctlx_uphy_portx_ctl_status { 882215976Sjmallett uint64_t u64; 883232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s { 884232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 885215976Sjmallett uint64_t reserved_43_63 : 21; 886215976Sjmallett uint64_t tdata_out : 4; /**< PHY test data out. Presents either interlly 887215976Sjmallett generated signals or test register contenets, based 888215976Sjmallett upon the value of TDATA_SEL */ 889215976Sjmallett uint64_t txbiststuffenh : 1; /**< High-Byte Transmit Bit-Stuffing Enable. It must be 890215976Sjmallett set to 1'b1 in normal operation. */ 891215976Sjmallett uint64_t txbiststuffen : 1; /**< Low-Byte Transmit Bit-Stuffing Enable. It must be 892215976Sjmallett set to 1'b1 in normal operation. */ 893215976Sjmallett uint64_t dmpulldown : 1; /**< D- Pull-Down Resistor Enable. It must be set to 1'b1 894215976Sjmallett in normal operation. */ 895215976Sjmallett uint64_t dppulldown : 1; /**< D+ Pull-Down Resistor Enable. It must be set to 1'b1 896215976Sjmallett in normal operation. */ 897215976Sjmallett uint64_t vbusvldext : 1; /**< In host mode, this input is not used and can be tied 898215976Sjmallett to 1'b0. */ 899215976Sjmallett uint64_t portreset : 1; /**< Per-port reset */ 900215976Sjmallett uint64_t txhsvxtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 901232812Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment 902232812Sjmallett When the recommended 37.4 Ohm resistor is present 903232812Sjmallett on USB_REXT, the recommended TXVREFTUNE value is 15 */ 904232812Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment 905232812Sjmallett When the recommended 37.4 Ohm resistor is present 906232812Sjmallett on USB_REXT, the recommended TXRISETUNE value is 1 */ 907232812Sjmallett uint64_t txpreemphasistune : 1; /**< HS transmitter pre-emphasis enable. 908232812Sjmallett When the recommended 37.4 Ohm resistor is present 909232812Sjmallett on USB_REXT, the recommended TXPREEMPHASISTUNE 910232812Sjmallett value is 1 */ 911215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedance Adjustment */ 912215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 913215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 914215976Sjmallett uint64_t loop_en : 1; /**< Port Loop back Test Enable 915215976Sjmallett - 1: During data transmission, the receive logic is 916215976Sjmallett enabled 917215976Sjmallett - 0: During data transmission, the receive logic is 918215976Sjmallett disabled */ 919215976Sjmallett uint64_t tclk : 1; /**< PHY port test clock, used to load TDATA_IN to the 920215976Sjmallett UPHY. */ 921215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data out select 922215976Sjmallett - 1: Mode-defined test register contents are output 923215976Sjmallett - 0: internally generated signals are output */ 924215976Sjmallett uint64_t taddr_in : 4; /**< Mode address for test interface. Specifies the 925215976Sjmallett register address for writing to or reading from the 926215976Sjmallett PHY test interface register. */ 927215976Sjmallett uint64_t tdata_in : 8; /**< Internal testing Register input data and select. 928215976Sjmallett This is a test bus. Data presents on [3:0] and the 929215976Sjmallett corresponding select (enable) presents on bits[7:4]. */ 930215976Sjmallett#else 931215976Sjmallett uint64_t tdata_in : 8; 932215976Sjmallett uint64_t taddr_in : 4; 933215976Sjmallett uint64_t tdata_sel : 1; 934215976Sjmallett uint64_t tclk : 1; 935215976Sjmallett uint64_t loop_en : 1; 936215976Sjmallett uint64_t compdistune : 3; 937215976Sjmallett uint64_t sqrxtune : 3; 938215976Sjmallett uint64_t txfslstune : 4; 939215976Sjmallett uint64_t txpreemphasistune : 1; 940215976Sjmallett uint64_t txrisetune : 1; 941215976Sjmallett uint64_t txvreftune : 4; 942215976Sjmallett uint64_t txhsvxtune : 2; 943215976Sjmallett uint64_t portreset : 1; 944215976Sjmallett uint64_t vbusvldext : 1; 945215976Sjmallett uint64_t dppulldown : 1; 946215976Sjmallett uint64_t dmpulldown : 1; 947215976Sjmallett uint64_t txbiststuffen : 1; 948215976Sjmallett uint64_t txbiststuffenh : 1; 949215976Sjmallett uint64_t tdata_out : 4; 950215976Sjmallett uint64_t reserved_43_63 : 21; 951215976Sjmallett#endif 952215976Sjmallett } s; 953232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx; 954215976Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; 955215976Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; 956232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx; 957232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx; 958232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1; 959232812Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx; 960215976Sjmallett}; 961215976Sjmalletttypedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t; 962215976Sjmallett 963215976Sjmallett#endif 964