1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45210284Sjmallett 46215990Sjmallett 47210284Sjmallett/** 48210284Sjmallett * @file 49210284Sjmallett * 50210284Sjmallett * Interface to the Trace buffer hardware. 51210284Sjmallett * 52210284Sjmallett * WRITING THE TRACE BUFFER 53210284Sjmallett * 54210284Sjmallett * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once 55210284Sjmallett * (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled 56210284Sjmallett * by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC 57210284Sjmallett * commands that are traced is determined by the filter and the two triggers, each of which is comprised of 58210284Sjmallett * masks for command, sid, did, and address). If triggers are disabled, then only those commands matching 59210284Sjmallett * the filter are traced. If triggers are enabled, then only those commands matching the filter, the start 60210284Sjmallett * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger. 61210284Sjmallett * 62210284Sjmallett * For a given command, its XMC data is written immediately to the buffer. If the command has XMD data, 63210284Sjmallett * then that data comes in-order at some later time. The XMD data is accumulated across all valid 64210284Sjmallett * XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer 65210284Sjmallett * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC 66210284Sjmallett * data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost. 67210284Sjmallett * 68210284Sjmallett * 69210284Sjmallett * READING THE TRACE BUFFER 70210284Sjmallett * 71210284Sjmallett * Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order, 72210284Sjmallett * as soon as it has access to the (single-ported) trace buffer. 73210284Sjmallett * 74215990Sjmallett * On Octeon2, each entry of the trace buffer is read by two CSR memory read operations. The first read accesses 75215990Sjmallett * bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer 76215990Sjmallett * services each read in order, as soon as it has access to the (single-ported) trace buffer. Buffer's read pointer 77215990Sjmallett * increments after two CSR memory read operations. 78210284Sjmallett * 79215990Sjmallett * 80210284Sjmallett * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS 81210284Sjmallett * 82210284Sjmallett * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow 83210284Sjmallett * conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write 84210284Sjmallett * (traced event) increments the write pointer and each read increments the read pointer. During the overflow 85210284Sjmallett * condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is 86210284Sjmallett * resolved. The first entry that is written immediately following the overflow condition may be marked to 87210284Sjmallett * indicate that a tracing discontinuity has occurred before this entry. During the underflow condition, 88210284Sjmallett * reading does not increment the read pointer and the read data is marked to indicate that no read data is 89210284Sjmallett * available. 90210284Sjmallett * 91210284Sjmallett * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4). 92210284Sjmallett * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the 93210284Sjmallett * absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs 94210284Sjmallett * every time the desired level of "fullness" is achieved. 95210284Sjmallett * 96210284Sjmallett * 97210284Sjmallett * Trace buffer entry format 98210284Sjmallett * @verbatim 99210284Sjmallett * 6 5 4 3 2 1 0 100210284Sjmallett * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 101210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 102210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp| 103210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 104210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp| 105210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 106210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp| 107210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 108210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp| 109210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 110210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp| 111210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 112210284Sjmallett * |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp| 113210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 114210284Sjmallett * |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp| 115210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 116210284Sjmallett * |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp| 117210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 118210284Sjmallett * |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp| 119210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 120210284Sjmallett * |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp| 121210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 122210284Sjmallett * |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp| 123210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 124210284Sjmallett * |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp| 125210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 126210284Sjmallett * |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp| 127210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 128210284Sjmallett * |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp| 129210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 130210284Sjmallett * |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp| 131210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 132210284Sjmallett * |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp| 133210284Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 134210284Sjmallett * 135215990Sjmallett * 136215990Sjmallett * Trace buffer entry format in Octeon2 is different 137215990Sjmallett * 138215990Sjmallett * 6 5 4 3 2 1 0 139215990Sjmallett * 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 140215990Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 141215990Sjmallett * |sta| address[37:0] | 0 | src id | Group 1 | diff timestamp| 142215990Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 143215990Sjmallett * |sta| address[37:0] | 0 | xmd mask | src id | Group 2 | diff timestamp| 144215990Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 145215990Sjmallett * |sta| address[37:0] | 0 |s-did| dest id | src id | Group 3 | diff timestamp| 146215990Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 147215990Sjmallett * |sta| *address[37:3] | *Length | dest id | src id | Group 4 | diff timestamp| 148215990Sjmallett * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 149215990Sjmallett * 150210284Sjmallett * notes: 151215990Sjmallett * - diff timestamp is the difference in time from the previous trace event to this event - 1. the granularity of the timestamp is programmable 152210284Sjmallett * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the 153210284Sjmallett * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'. 154210284Sjmallett * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows: 155232812Sjmallett * 0x0=not valid 156232812Sjmallett * 0x1=valid, no discontinuity 157232812Sjmallett * 0x2=not valid, discontinuity 158232812Sjmallett * 0x3=valid, discontinuity 159210284Sjmallett * - commands are encoded as follows: 160210284Sjmallett * 0x0=DWB 161210284Sjmallett * 0x1=PL2 162210284Sjmallett * 0x2=PSL1 163210284Sjmallett * 0x3=LDD 164210284Sjmallett * 0x4=LDI 165210284Sjmallett * 0x5=LDT 166215990Sjmallett * 0x6=STF 167215990Sjmallett * 0x7=STC 168210284Sjmallett * 0x8=STP 169210284Sjmallett * 0x9=STT 170210284Sjmallett * 0xa=IOBLD8 171210284Sjmallett * 0xb=IOBLD16 172210284Sjmallett * 0xc=IOBLD32 173210284Sjmallett * 0xd=IOBLD64 174210284Sjmallett * 0xe=IOBST 175210284Sjmallett * 0xf=IOBDMA 176215990Sjmallett * - In Octeon2 the commands are grouped as follows: 177215990Sjmallett * Group1: 178215990Sjmallett * XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2, 179215990Sjmallett * XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64, 180215990Sjmallett * XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64, 181215990Sjmallett * XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64, 182215990Sjmallett * XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64 183215990Sjmallett * Group2: 184215990Sjmallett * XMC_STF, XMC_STT, XMC_STP, XMC_STC, 185215990Sjmallett * XMC_LDD, XMC_PSL1 186215990Sjmallett * XMC_SAA32, XMC_SAA64, 187215990Sjmallett * XMC_FAA32, XMC_FAA64, 188215990Sjmallett * XMC_FAS32, XMC_FAS64 189215990Sjmallett * Group3: 190215990Sjmallett * XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64, 191215990Sjmallett * XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64 192215990Sjmallett * Group4: 193215990Sjmallett * XMC_IOBDMA 194210284Sjmallett * - For non IOB* commands 195210284Sjmallett * - source id is encoded as follows: 196210284Sjmallett * 0x00-0x0f=PP[n] 197210284Sjmallett * 0x10=IOB(Packet) 198210284Sjmallett * 0x11=IOB(PKO) 199210284Sjmallett * 0x12=IOB(ReqLoad, ReqStore) 200210284Sjmallett * 0x13=IOB(DWB) 201210284Sjmallett * 0x14-0x1e=illegal 202210284Sjmallett * 0x1f=IOB(generic) 203215990Sjmallett * - dest id is unused (can only be L2c) 204210284Sjmallett * - For IOB* commands 205210284Sjmallett * - source id is encoded as follows: 206210284Sjmallett * 0x00-0x0f = PP[n] 207210284Sjmallett * - dest id is encoded as follows: 208215990Sjmallett * 0 = CIU/GPIO (for CSRs) 209215990Sjmallett * 1-2 = illegal 210215990Sjmallett * 3 = PCIe (access to RSL-type CSRs) 211215990Sjmallett * 4 = KEY (read/write operations) 212215990Sjmallett * 5 = FPA (free pool allocate/free operations) 213215990Sjmallett * 6 = DFA 214215990Sjmallett * 7 = ZIP (doorbell operations) 215215990Sjmallett * 8 = RNG (load/IOBDMA operations) 216215990Sjmallett * 10 = PKO (doorbell operations) 217215990Sjmallett * 11 = illegal 218215990Sjmallett * 12 = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations) 219215990Sjmallett * 13-31 = illegal 220210284Sjmallett * @endverbatim 221210284Sjmallett * 222232812Sjmallett * <hr>$Revision: 70030 $<hr> 223210284Sjmallett */ 224210284Sjmallett 225210284Sjmallett#ifndef __CVMX_TRA_H__ 226210284Sjmallett#define __CVMX_TRA_H__ 227210284Sjmallett 228210284Sjmallett#include "cvmx.h" 229232812Sjmallett#include "cvmx-l2c.h" 230215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 231215990Sjmallett#include "cvmx-tra-defs.h" 232215990Sjmallett#endif 233210284Sjmallett 234210284Sjmallett#ifdef __cplusplus 235210284Sjmallettextern "C" { 236210284Sjmallett#endif 237210284Sjmallett 238210284Sjmallett 239215990Sjmallett/* CSR typedefs have been moved to cvmx-tra-defs.h */ 240210284Sjmallett 241215990Sjmallett/* The 'saa' filter command is renamed as 'saa64' */ 242215990Sjmallett#define CVMX_TRA_FILT_SAA CVMX_TRA_FILT_SAA64 243215990Sjmallett/* The 'iobst' filter command is renamed as 'iobst64' */ 244215990Sjmallett#define CVMX_TRA_FILT_IOBST CVMX_TRA_FILT_IOBST64 245215990Sjmallett 246210284Sjmallett/** 247215990Sjmallett * Enumeration of the bitmask of all the filter commands. The bit positions 248215990Sjmallett * correspond to Octeon2 model. 249210284Sjmallett */ 250210284Sjmalletttypedef enum 251210284Sjmallett{ 252215990Sjmallett CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */ 253215990Sjmallett CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */ 254215990Sjmallett CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */ 255215990Sjmallett CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */ 256215990Sjmallett CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */ 257215990Sjmallett CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */ 258215990Sjmallett CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */ 259215990Sjmallett CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */ 260215990Sjmallett CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */ 261215990Sjmallett CVMX_TRA_FILT_STF = 1ull<<16, /**< full block store to L2, fill 0's */ 262215990Sjmallett CVMX_TRA_FILT_STT = 1ull<<17, /**< full block store bypass-L2, fill 0's */ 263215990Sjmallett CVMX_TRA_FILT_STP = 1ull<<18, /**< partial store to L2 */ 264215990Sjmallett CVMX_TRA_FILT_STC = 1ull<<19, /**< partial store to L2, if duptag valid */ 265215990Sjmallett CVMX_TRA_FILT_STFIL1 = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */ 266215990Sjmallett CVMX_TRA_FILT_STTIL1 = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */ 267215990Sjmallett CVMX_TRA_FILT_FAS32 = 1ull<<22, /**< to load from and write a word of memory atomically */ 268215990Sjmallett CVMX_TRA_FILT_FAS64 = 1ull<<23, /**< to load from and write a doubleword of memory atomically */ 269215990Sjmallett CVMX_TRA_FILT_WBIL2I = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */ 270215990Sjmallett CVMX_TRA_FILT_LTGL2I = 1ull<<25, /**< read tag @ index/way into CSR */ 271215990Sjmallett CVMX_TRA_FILT_STGL2I = 1ull<<26, /**< write tag @ index/way from CSR */ 272215990Sjmallett CVMX_TRA_FILT_INVL2 = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */ 273215990Sjmallett CVMX_TRA_FILT_WBIL2 = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */ 274215990Sjmallett CVMX_TRA_FILT_WBL2 = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */ 275215990Sjmallett CVMX_TRA_FILT_LCKL2 = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */ 276215990Sjmallett CVMX_TRA_FILT_IOBLD8 = 1ull<<32, /**< load reflection 8bit */ 277215990Sjmallett CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */ 278215990Sjmallett CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */ 279215990Sjmallett CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */ 280215990Sjmallett CVMX_TRA_FILT_IOBST8 = 1ull<<36, /**< store reflection 8bit */ 281215990Sjmallett CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */ 282215990Sjmallett CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */ 283215990Sjmallett CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */ 284215990Sjmallett CVMX_TRA_FILT_SET8 = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */ 285215990Sjmallett CVMX_TRA_FILT_SET16 = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */ 286215990Sjmallett CVMX_TRA_FILT_SET32 = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */ 287215990Sjmallett CVMX_TRA_FILT_SET64 = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */ 288215990Sjmallett CVMX_TRA_FILT_CLR8 = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */ 289215990Sjmallett CVMX_TRA_FILT_CLR16 = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */ 290215990Sjmallett CVMX_TRA_FILT_CLR32 = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */ 291215990Sjmallett CVMX_TRA_FILT_CLR64 = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */ 292215990Sjmallett CVMX_TRA_FILT_INCR8 = 1ull<<48, /**< to load and increment 8bit of memory atomically */ 293215990Sjmallett CVMX_TRA_FILT_INCR16 = 1ull<<49, /**< to load and increment 16bit of memory atomically */ 294215990Sjmallett CVMX_TRA_FILT_INCR32 = 1ull<<50, /**< to load and increment 32bit of memory atomically */ 295215990Sjmallett CVMX_TRA_FILT_INCR64 = 1ull<<51, /**< to load and increment 64bit of memory atomically */ 296215990Sjmallett CVMX_TRA_FILT_DECR8 = 1ull<<52, /**< to load and decrement 8bit of memory atomically */ 297215990Sjmallett CVMX_TRA_FILT_DECR16 = 1ull<<53, /**< to load and decrement 16bit of memory atomically */ 298215990Sjmallett CVMX_TRA_FILT_DECR32 = 1ull<<54, /**< to load and decrement 32bit of memory atomically */ 299215990Sjmallett CVMX_TRA_FILT_DECR64 = 1ull<<55, /**< to load and decrement 64bit of memory atomically */ 300215990Sjmallett CVMX_TRA_FILT_FAA32 = 1ull<<58, /**< to load from and add to a word of memory atomically */ 301215990Sjmallett CVMX_TRA_FILT_FAA64 = 1ull<<59, /**< to load from and add to a doubleword of memory atomically */ 302215990Sjmallett CVMX_TRA_FILT_SAA32 = 1ull<<62, /**< to atomically add a word to a memory location */ 303215990Sjmallett CVMX_TRA_FILT_SAA64 = 1ull<<63, /**< to atomically add a doubleword to a memory location */ 304215990Sjmallett CVMX_TRA_FILT_ALL = -1ull /**< all the above filter commands */ 305215990Sjmallett} cvmx_tra_filt_t; 306210284Sjmallett 307215990Sjmallett/* 308215990Sjmallett * Enumeration of the bitmask of all source commands. 309215990Sjmallett */ 310215990Sjmalletttypedef enum 311215990Sjmallett{ 312215990Sjmallett CVMX_TRA_SID_PP0 = 1ull<<0, /**< Enable tracing from PP0 with matching sourceID */ 313215990Sjmallett CVMX_TRA_SID_PP1 = 1ull<<1, /**< Enable tracing from PP1 with matching sourceID */ 314215990Sjmallett CVMX_TRA_SID_PP2 = 1ull<<2, /**< Enable tracing from PP2 with matching sourceID */ 315215990Sjmallett CVMX_TRA_SID_PP3 = 1ull<<3, /**< Enable tracing from PP3 with matching sourceID */ 316215990Sjmallett CVMX_TRA_SID_PP4 = 1ull<<4, /**< Enable tracing from PP4 with matching sourceID */ 317215990Sjmallett CVMX_TRA_SID_PP5 = 1ull<<5, /**< Enable tracing from PP5 with matching sourceID */ 318215990Sjmallett CVMX_TRA_SID_PP6 = 1ull<<6, /**< Enable tracing from PP6 with matching sourceID */ 319215990Sjmallett CVMX_TRA_SID_PP7 = 1ull<<7, /**< Enable tracing from PP7 with matching sourceID */ 320215990Sjmallett CVMX_TRA_SID_PP8 = 1ull<<8, /**< Enable tracing from PP8 with matching sourceID */ 321215990Sjmallett CVMX_TRA_SID_PP9 = 1ull<<9, /**< Enable tracing from PP9 with matching sourceID */ 322215990Sjmallett CVMX_TRA_SID_PP10 = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */ 323215990Sjmallett CVMX_TRA_SID_PP11 = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */ 324215990Sjmallett CVMX_TRA_SID_PP12 = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */ 325215990Sjmallett CVMX_TRA_SID_PP13 = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */ 326215990Sjmallett CVMX_TRA_SID_PP14 = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */ 327215990Sjmallett CVMX_TRA_SID_PP15 = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */ 328215990Sjmallett CVMX_TRA_SID_PKI = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */ 329215990Sjmallett CVMX_TRA_SID_PKO = 1ull<<17, /**< Enable tracing of write requests from PKO */ 330215990Sjmallett CVMX_TRA_SID_IOBREQ = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */ 331215990Sjmallett CVMX_TRA_SID_DWB = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */ 332215990Sjmallett CVMX_TRA_SID_ALL = -1ull /**< Enable tracing all the above source commands */ 333215990Sjmallett} cvmx_tra_sid_t; 334215990Sjmallett 335215990Sjmallett 336215990Sjmallett#define CVMX_TRA_DID_SLI CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */ 337215990Sjmallett/* 338215990Sjmallett * Enumeration of the bitmask of all destination commands. 339215990Sjmallett */ 340215990Sjmalletttypedef enum 341215990Sjmallett{ 342215990Sjmallett CVMX_TRA_DID_MIO = 1ull<<0, /**< Enable tracing of CIU and GPIO CSR's */ 343215990Sjmallett CVMX_TRA_DID_PCI = 1ull<<3, /**< Enable tracing of requests to PCI and RSL type CSR's */ 344215990Sjmallett CVMX_TRA_DID_KEY = 1ull<<4, /**< Enable tracing of requests to KEY memory */ 345215990Sjmallett CVMX_TRA_DID_FPA = 1ull<<5, /**< Enable tracing of requests to FPA */ 346215990Sjmallett CVMX_TRA_DID_DFA = 1ull<<6, /**< Enable tracing of requests to DFA */ 347215990Sjmallett CVMX_TRA_DID_ZIP = 1ull<<7, /**< Enable tracing of requests to ZIP */ 348215990Sjmallett CVMX_TRA_DID_RNG = 1ull<<8, /**< Enable tracing of requests to RNG */ 349215990Sjmallett CVMX_TRA_DID_IPD = 1ull<<9, /**< Enable tracing of IPD CSR accesses */ 350215990Sjmallett CVMX_TRA_DID_PKO = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */ 351215990Sjmallett CVMX_TRA_DID_POW = 1ull<<12, /**< Enable tracing of requests to RNG */ 352215990Sjmallett CVMX_TRA_DID_USB0 = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */ 353215990Sjmallett CVMX_TRA_DID_RAD = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */ 354215990Sjmallett CVMX_TRA_DID_DPI = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */ 355215990Sjmallett CVMX_TRA_DID_FAU = 1ull<<30, /**< Enable tracing FAU accesses */ 356215990Sjmallett CVMX_TRA_DID_ALL = -1ull /**< Enable tracing all the above destination commands */ 357215990Sjmallett} cvmx_tra_did_t; 358215990Sjmallett 359210284Sjmallett/** 360210284Sjmallett * TRA data format definition. Use the type field to 361210284Sjmallett * determine which union element to use. 362215990Sjmallett * 363215990Sjmallett * In Octeon 2, the trace buffer is 69 bits, 364215990Sjmallett * the first read accesses bits 63:0 of the trace buffer entry, and 365215990Sjmallett * the second read accesses bits 68:64 of the trace buffer entry. 366210284Sjmallett */ 367210284Sjmalletttypedef union 368210284Sjmallett{ 369210284Sjmallett struct 370210284Sjmallett { 371232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 372215990Sjmallett uint64_t datahi; 373215990Sjmallett uint64_t data; 374215990Sjmallett#else 375215990Sjmallett uint64_t data; 376215990Sjmallett uint64_t datahi; 377215990Sjmallett#endif 378215990Sjmallett } u128; 379215990Sjmallett 380215990Sjmallett struct 381215990Sjmallett { 382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 383215990Sjmallett uint64_t reserved3 : 64; 384210284Sjmallett uint64_t valid : 1; 385210284Sjmallett uint64_t discontinuity:1; 386210284Sjmallett uint64_t address : 36; 387210284Sjmallett uint64_t reserved : 5; 388210284Sjmallett uint64_t source : 5; 389210284Sjmallett uint64_t reserved2 : 3; 390215990Sjmallett uint64_t type : 5; 391210284Sjmallett uint64_t timestamp : 8; 392210284Sjmallett#else 393210284Sjmallett uint64_t timestamp : 8; 394215990Sjmallett uint64_t type : 5; 395210284Sjmallett uint64_t reserved2 : 3; 396210284Sjmallett uint64_t source : 5; 397210284Sjmallett uint64_t reserved : 5; 398210284Sjmallett uint64_t address : 36; 399210284Sjmallett uint64_t discontinuity:1; 400210284Sjmallett uint64_t valid : 1; 401215990Sjmallett uint64_t reserved3 : 64; 402210284Sjmallett#endif 403210284Sjmallett } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */ 404210284Sjmallett struct 405210284Sjmallett { 406232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 407215990Sjmallett uint64_t reserved3 : 64; 408210284Sjmallett uint64_t valid : 1; 409210284Sjmallett uint64_t discontinuity:1; 410210284Sjmallett uint64_t address : 33; 411210284Sjmallett uint64_t mask : 8; 412210284Sjmallett uint64_t source : 5; 413210284Sjmallett uint64_t reserved2 : 3; 414215990Sjmallett uint64_t type : 5; 415210284Sjmallett uint64_t timestamp : 8; 416210284Sjmallett#else 417210284Sjmallett uint64_t timestamp : 8; 418215990Sjmallett uint64_t type : 5; 419210284Sjmallett uint64_t reserved2 : 3; 420210284Sjmallett uint64_t source : 5; 421210284Sjmallett uint64_t mask : 8; 422210284Sjmallett uint64_t address : 33; 423210284Sjmallett uint64_t discontinuity:1; 424210284Sjmallett uint64_t valid : 1; 425215990Sjmallett uint64_t reserved3 : 64; 426210284Sjmallett#endif 427210284Sjmallett } store; /**< STC, STF, STP, STT */ 428210284Sjmallett struct 429210284Sjmallett { 430232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 431215990Sjmallett uint64_t reserved3 : 64; 432210284Sjmallett uint64_t valid : 1; 433210284Sjmallett uint64_t discontinuity:1; 434210284Sjmallett uint64_t address : 36; 435210284Sjmallett uint64_t reserved : 2; 436210284Sjmallett uint64_t subid : 3; 437210284Sjmallett uint64_t source : 4; 438210284Sjmallett uint64_t dest : 5; 439210284Sjmallett uint64_t type : 4; 440210284Sjmallett uint64_t timestamp : 8; 441210284Sjmallett#else 442210284Sjmallett uint64_t timestamp : 8; 443210284Sjmallett uint64_t type : 4; 444210284Sjmallett uint64_t dest : 5; 445210284Sjmallett uint64_t source : 4; 446210284Sjmallett uint64_t subid : 3; 447210284Sjmallett uint64_t reserved : 2; 448210284Sjmallett uint64_t address : 36; 449210284Sjmallett uint64_t discontinuity:1; 450210284Sjmallett uint64_t valid : 1; 451215990Sjmallett uint64_t reserved3 : 64; 452210284Sjmallett#endif 453210284Sjmallett } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */ 454210284Sjmallett struct 455210284Sjmallett { 456232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 457215990Sjmallett uint64_t reserved3 : 64; 458210284Sjmallett uint64_t valid : 1; 459210284Sjmallett uint64_t discontinuity:1; 460210284Sjmallett uint64_t address : 33; 461210284Sjmallett uint64_t mask : 8; 462210284Sjmallett uint64_t source : 4; 463210284Sjmallett uint64_t dest : 5; 464210284Sjmallett uint64_t type : 4; 465210284Sjmallett uint64_t timestamp : 8; 466210284Sjmallett#else 467210284Sjmallett uint64_t timestamp : 8; 468210284Sjmallett uint64_t type : 4; 469210284Sjmallett uint64_t dest : 5; 470210284Sjmallett uint64_t source : 4; 471210284Sjmallett uint64_t mask : 8; 472210284Sjmallett uint64_t address : 33; 473210284Sjmallett uint64_t discontinuity:1; 474210284Sjmallett uint64_t valid : 1; 475215990Sjmallett uint64_t reserved3 : 64; 476210284Sjmallett#endif 477210284Sjmallett } iob; /**< for IOBDMA */ 478215990Sjmallett 479215990Sjmallett struct 480215990Sjmallett { 481232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 482215990Sjmallett uint64_t reserved1 : 59; 483232812Sjmallett uint64_t discontinuity:1; 484215990Sjmallett uint64_t valid : 1; 485215990Sjmallett uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 486215990Sjmallett uint64_t addresslo : 35; /* and lower 64-bits. */ 487215990Sjmallett uint64_t reserved : 10; 488215990Sjmallett uint64_t source : 5; 489215990Sjmallett uint64_t type : 6; 490215990Sjmallett uint64_t timestamp : 8; 491215990Sjmallett#else 492215990Sjmallett uint64_t timestamp : 8; 493215990Sjmallett uint64_t type : 6; 494215990Sjmallett uint64_t source : 5; 495215990Sjmallett uint64_t reserved : 10; 496215990Sjmallett uint64_t addresslo : 35; 497215990Sjmallett uint64_t addresshi : 3; 498232812Sjmallett uint64_t valid : 1; 499215990Sjmallett uint64_t discontinuity:1; 500215990Sjmallett uint64_t reserved1 : 59; 501215990Sjmallett#endif 502232812Sjmallett } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, WBIL2i, LTGL2i, STGL2i, INVL2, WBIL2, LCKL2, SET*, CLR*, INCR*, DECR* */ 503215990Sjmallett struct 504215990Sjmallett { 505232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 506215990Sjmallett uint64_t reserved1 : 59; 507232812Sjmallett uint64_t discontinuity:1; 508215990Sjmallett uint64_t valid : 1; 509215990Sjmallett uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 510215990Sjmallett uint64_t addresslo : 35; /* and lower 64-bits */ 511215990Sjmallett uint64_t reserved : 2; 512215990Sjmallett uint64_t mask : 8; 513215990Sjmallett uint64_t source : 5; 514215990Sjmallett uint64_t type : 6; 515215990Sjmallett uint64_t timestamp : 8; 516215990Sjmallett#else 517215990Sjmallett uint64_t timestamp : 8; 518215990Sjmallett uint64_t type : 6; 519215990Sjmallett uint64_t source : 5; 520215990Sjmallett uint64_t mask : 8; 521215990Sjmallett uint64_t reserved : 2; 522215990Sjmallett uint64_t addresslo : 35; 523215990Sjmallett uint64_t addresshi : 3; 524232812Sjmallett uint64_t valid : 1; 525215990Sjmallett uint64_t discontinuity:1; 526215990Sjmallett uint64_t reserved1 : 59; 527215990Sjmallett#endif 528232812Sjmallett } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64, STTIL1, STFIL1 */ 529215990Sjmallett struct 530215990Sjmallett { 531232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 532215990Sjmallett uint64_t reserved1 : 59; 533232812Sjmallett uint64_t discontinuity:1; 534215990Sjmallett uint64_t valid : 1; 535215990Sjmallett uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 536215990Sjmallett uint64_t addresslo : 35; /* and lower 64-bits */ 537215990Sjmallett uint64_t reserved : 2; 538215990Sjmallett uint64_t subid : 3; 539215990Sjmallett uint64_t dest : 5; 540215990Sjmallett uint64_t source : 5; 541215990Sjmallett uint64_t type : 6; 542215990Sjmallett uint64_t timestamp : 8; 543215990Sjmallett#else 544215990Sjmallett uint64_t timestamp : 8; 545215990Sjmallett uint64_t type : 6; 546215990Sjmallett uint64_t source : 5; 547215990Sjmallett uint64_t dest : 5; 548215990Sjmallett uint64_t subid : 3; 549215990Sjmallett uint64_t reserved : 2; 550215990Sjmallett uint64_t addresslo : 35; 551215990Sjmallett uint64_t addresshi : 3; 552232812Sjmallett uint64_t valid : 1; 553215990Sjmallett uint64_t discontinuity:1; 554215990Sjmallett uint64_t reserved1 : 59; 555215990Sjmallett#endif 556215990Sjmallett } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */ 557215990Sjmallett struct 558215990Sjmallett { 559232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 560215990Sjmallett uint64_t reserved1 : 59; 561232812Sjmallett uint64_t discontinuity:1; 562215990Sjmallett uint64_t valid : 1; 563215990Sjmallett uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 564215990Sjmallett uint64_t addresslo : 32; /* and lower 64-bits */ 565215990Sjmallett uint64_t mask : 8; 566215990Sjmallett uint64_t dest : 5; 567215990Sjmallett uint64_t source : 5; 568215990Sjmallett uint64_t type : 6; 569215990Sjmallett uint64_t timestamp : 8; 570215990Sjmallett#else 571215990Sjmallett uint64_t timestamp : 8; 572215990Sjmallett uint64_t type : 6; 573215990Sjmallett uint64_t source : 5; 574215990Sjmallett uint64_t dest : 5; 575215990Sjmallett uint64_t mask : 8; 576215990Sjmallett uint64_t addresslo : 32; 577215990Sjmallett uint64_t addresshi : 3; 578232812Sjmallett uint64_t valid : 1; 579215990Sjmallett uint64_t discontinuity:1; 580215990Sjmallett uint64_t reserved1 : 59; 581215990Sjmallett#endif 582215990Sjmallett } iob2; /**< for IOBDMA */ 583210284Sjmallett} cvmx_tra_data_t; 584210284Sjmallett 585232812Sjmallett/* The trace buffer number to use. */ 586232812Sjmallettextern int _cvmx_tra_unit; 587210284Sjmallett 588210284Sjmallett/** 589210284Sjmallett * Setup the TRA buffer for use 590210284Sjmallett * 591210284Sjmallett * @param control TRA control setup 592210284Sjmallett * @param filter Which events to log 593210284Sjmallett * @param source_filter 594210284Sjmallett * Source match 595210284Sjmallett * @param dest_filter 596210284Sjmallett * Destination match 597210284Sjmallett * @param address Address compare 598210284Sjmallett * @param address_mask 599210284Sjmallett * Address mask 600210284Sjmallett */ 601215990Sjmallettextern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter, 602215990Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 603210284Sjmallett uint64_t address, uint64_t address_mask); 604210284Sjmallett 605210284Sjmallett/** 606232812Sjmallett * Setup each TRA buffer for use 607232812Sjmallett * 608232812Sjmallett * @param tra Which TRA buffer to use (0-3) 609232812Sjmallett * @param control TRA control setup 610232812Sjmallett * @param filter Which events to log 611232812Sjmallett * @param source_filter 612232812Sjmallett * Source match 613232812Sjmallett * @param dest_filter 614232812Sjmallett * Destination match 615232812Sjmallett * @param address Address compare 616232812Sjmallett * @param address_mask 617232812Sjmallett * Address mask 618232812Sjmallett */ 619232812Sjmallettextern void cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter, 620232812Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 621232812Sjmallett uint64_t address, uint64_t address_mask); 622232812Sjmallett 623232812Sjmallett/** 624210284Sjmallett * Setup a TRA trigger. How the triggers are used should be 625210284Sjmallett * setup using cvmx_tra_setup. 626210284Sjmallett * 627210284Sjmallett * @param trigger Trigger to setup (0 or 1) 628210284Sjmallett * @param filter Which types of events to trigger on 629210284Sjmallett * @param source_filter 630210284Sjmallett * Source trigger match 631210284Sjmallett * @param dest_filter 632210284Sjmallett * Destination trigger match 633210284Sjmallett * @param address Trigger address compare 634210284Sjmallett * @param address_mask 635210284Sjmallett * Trigger address mask 636210284Sjmallett */ 637215990Sjmallettextern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter, 638215990Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 639210284Sjmallett uint64_t address, uint64_t address_mask); 640210284Sjmallett 641210284Sjmallett/** 642232812Sjmallett * Setup each TRA trigger. How the triggers are used should be 643232812Sjmallett * setup using cvmx_tra_setup. 644232812Sjmallett * 645232812Sjmallett * @param tra Which TRA buffer to use (0-3) 646232812Sjmallett * @param trigger Trigger to setup (0 or 1) 647232812Sjmallett * @param filter Which types of events to trigger on 648232812Sjmallett * @param source_filter 649232812Sjmallett * Source trigger match 650232812Sjmallett * @param dest_filter 651232812Sjmallett * Destination trigger match 652232812Sjmallett * @param address Trigger address compare 653232812Sjmallett * @param address_mask 654232812Sjmallett * Trigger address mask 655232812Sjmallett */ 656232812Sjmallettextern void cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter, 657232812Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 658232812Sjmallett uint64_t address, uint64_t address_mask); 659232812Sjmallett 660232812Sjmallett/** 661215990Sjmallett * Read an entry from the TRA buffer. The trace buffer format is 662215990Sjmallett * different in Octeon2, need to read twice from TRA_READ_DAT. 663210284Sjmallett * 664210284Sjmallett * @return Value return. High bit will be zero if there wasn't any data 665210284Sjmallett */ 666210284Sjmallettextern cvmx_tra_data_t cvmx_tra_read(void); 667210284Sjmallett 668210284Sjmallett/** 669232812Sjmallett * Read an entry from the TRA buffer from a given TRA unit. 670232812Sjmallett * 671232812Sjmallett * @param tra_unit Trace buffer unit to read 672232812Sjmallett * 673232812Sjmallett * @return Value return. High bit will be zero if there wasn't any data 674232812Sjmallett */ 675232812Sjmallettcvmx_tra_data_t cvmx_tra_read_v2(int tra_unit); 676232812Sjmallett 677232812Sjmallett/** 678210284Sjmallett * Decode a TRA entry into human readable output 679210284Sjmallett * 680210284Sjmallett * @param tra_ctl Trace control setup 681210284Sjmallett * @param data Data to decode 682210284Sjmallett */ 683210284Sjmallettextern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data); 684210284Sjmallett 685210284Sjmallett/** 686210284Sjmallett * Display the entire trace buffer. It is advised that you 687210284Sjmallett * disable the trace buffer before calling this routine 688210284Sjmallett * otherwise it could infinitely loop displaying trace data 689210284Sjmallett * that it created. 690210284Sjmallett */ 691210284Sjmallettextern void cvmx_tra_display(void); 692210284Sjmallett 693210284Sjmallett/** 694232812Sjmallett * Display the entire trace buffer. It is advised that you 695232812Sjmallett * disable the trace buffer before calling this routine 696232812Sjmallett * otherwise it could infinitely loop displaying trace data 697232812Sjmallett * that it created. 698210284Sjmallett * 699232812Sjmallett * @param tra_unit Which TRA buffer to use. 700232812Sjmallett */ 701232812Sjmallettextern void cvmx_tra_display_v2(int tra_unit); 702232812Sjmallett 703232812Sjmallett/** 704232812Sjmallett * Enable or disable the TRA hardware, by default enables all TRAs. 705232812Sjmallett * 706210284Sjmallett * @param enable 1=enable, 0=disable 707210284Sjmallett */ 708210284Sjmallettstatic inline void cvmx_tra_enable(int enable) 709210284Sjmallett{ 710210284Sjmallett cvmx_tra_ctl_t control; 711232812Sjmallett int tad; 712232812Sjmallett 713232812Sjmallett for (tad = 0; tad < CVMX_L2C_TADS; tad++) 714232812Sjmallett { 715232812Sjmallett control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad)); 716232812Sjmallett control.s.ena = enable; 717232812Sjmallett cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64); 718232812Sjmallett cvmx_read_csr(CVMX_TRAX_CTL(tad)); 719232812Sjmallett } 720232812Sjmallett} 721232812Sjmallett 722232812Sjmallett/** 723232812Sjmallett * Enable or disable a particular TRA hardware 724232812Sjmallett * 725232812Sjmallett * @param enable 1=enable, 0=disable 726232812Sjmallett * @param tra which TRA to enable, CN68XX has 4. 727232812Sjmallett */ 728232812Sjmallettstatic inline void cvmx_tra_enable_v2(int enable, int tra) 729232812Sjmallett{ 730232812Sjmallett cvmx_tra_ctl_t control; 731232812Sjmallett 732232812Sjmallett if ((tra + 1) > CVMX_L2C_TADS) 733232812Sjmallett { 734232812Sjmallett cvmx_dprintf("cvmx_tra_enable: Invalid TRA(%d), max allowed are %d\n", tra, CVMX_L2C_TADS - 1); 735232812Sjmallett tra = 0; 736232812Sjmallett } 737232812Sjmallett control.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra)); 738210284Sjmallett control.s.ena = enable; 739232812Sjmallett cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64); 740232812Sjmallett cvmx_read_csr(CVMX_TRAX_CTL(tra)); 741210284Sjmallett} 742210284Sjmallett 743210284Sjmallett#ifdef __cplusplus 744210284Sjmallett} 745210284Sjmallett#endif 746210284Sjmallett 747210284Sjmallett#endif 748210284Sjmallett 749