1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-stxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon stxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_STXX_DEFS_H__ 53232812Sjmallett#define __CVMX_STXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61215976Sjmallett cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73215976Sjmallett cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 85215976Sjmallett cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 86215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull; 87215976Sjmallett} 88215976Sjmallett#else 89215976Sjmallett#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97215976Sjmallett cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109215976Sjmallett cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121215976Sjmallett cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) 126215976Sjmallett#endif 127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128215976Sjmallettstatic inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id) 129215976Sjmallett{ 130215976Sjmallett if (!( 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 132215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 133215976Sjmallett cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id); 134215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull; 135215976Sjmallett} 136215976Sjmallett#else 137215976Sjmallett#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) 138215976Sjmallett#endif 139215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140215976Sjmallettstatic inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id) 141215976Sjmallett{ 142215976Sjmallett if (!( 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 145215976Sjmallett cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 157215976Sjmallett cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id); 158215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull; 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 165215976Sjmallett{ 166215976Sjmallett if (!( 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 169215976Sjmallett cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 181215976Sjmallett cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 192215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 193215976Sjmallett cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 194215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull; 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id) 201215976Sjmallett{ 202215976Sjmallett if (!( 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 205215976Sjmallett cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 217215976Sjmallett cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id); 218215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull; 219215976Sjmallett} 220215976Sjmallett#else 221215976Sjmallett#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) 222215976Sjmallett#endif 223215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224215976Sjmallettstatic inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id) 225215976Sjmallett{ 226215976Sjmallett if (!( 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 229215976Sjmallett cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 241215976Sjmallett cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id); 242215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) 246215976Sjmallett#endif 247215976Sjmallett 248215976Sjmallett/** 249215976Sjmallett * cvmx_stx#_arb_ctl 250215976Sjmallett * 251215976Sjmallett * STX_ARB_CTL - Spi transmit arbitration control 252215976Sjmallett * 253215976Sjmallett * 254215976Sjmallett * Notes: 255215976Sjmallett * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 256215976Sjmallett * parameter will have to be adjusted. Please see the 257215976Sjmallett * STX_SPI4_DAT[MAX_T] section for additional information. In 258215976Sjmallett * addition, the min_burst can only be guaranteed on the initial data 259215976Sjmallett * burst of a given packet (i.e. the first data burst which contains 260215976Sjmallett * the SOP tick). All subsequent bursts could be truncated by training 261215976Sjmallett * sequences at any point during transmission and could be arbitrarily 262215976Sjmallett * small. This mode is only for use in Spi4 mode. 263215976Sjmallett */ 264232812Sjmallettunion cvmx_stxx_arb_ctl { 265215976Sjmallett uint64_t u64; 266232812Sjmallett struct cvmx_stxx_arb_ctl_s { 267232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 268215976Sjmallett uint64_t reserved_6_63 : 58; 269215976Sjmallett uint64_t mintrn : 1; /**< Hold off training cycles until STX_MIN_BST[MINB] 270215976Sjmallett is satisfied */ 271215976Sjmallett uint64_t reserved_4_4 : 1; 272215976Sjmallett uint64_t igntpa : 1; /**< User switch to ignore any TPA information from the 273215976Sjmallett Spi interface. This CSR forces all TPA terms to 274215976Sjmallett be masked out. It is only intended as backdoor 275215976Sjmallett or debug feature. */ 276215976Sjmallett uint64_t reserved_0_2 : 3; 277215976Sjmallett#else 278215976Sjmallett uint64_t reserved_0_2 : 3; 279215976Sjmallett uint64_t igntpa : 1; 280215976Sjmallett uint64_t reserved_4_4 : 1; 281215976Sjmallett uint64_t mintrn : 1; 282215976Sjmallett uint64_t reserved_6_63 : 58; 283215976Sjmallett#endif 284215976Sjmallett } s; 285215976Sjmallett struct cvmx_stxx_arb_ctl_s cn38xx; 286215976Sjmallett struct cvmx_stxx_arb_ctl_s cn38xxp2; 287215976Sjmallett struct cvmx_stxx_arb_ctl_s cn58xx; 288215976Sjmallett struct cvmx_stxx_arb_ctl_s cn58xxp1; 289215976Sjmallett}; 290215976Sjmalletttypedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t; 291215976Sjmallett 292215976Sjmallett/** 293215976Sjmallett * cvmx_stx#_bckprs_cnt 294215976Sjmallett * 295215976Sjmallett * Notes: 296215976Sjmallett * This register reports the total number of cycles (STX data clks - 297215976Sjmallett * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA 298215976Sjmallett * or is otherwise receiving backpressure. 299215976Sjmallett * 300215976Sjmallett * In Spi4 mode, this is defined as a loss of TPA which is indicated when 301215976Sjmallett * the receiving device reports SATISFIED for the given port. The calendar 302215976Sjmallett * status is brought into N2 on the spi4_tx*_sclk and synchronized into the 303215976Sjmallett * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk 304215976Sjmallett * clock (internally, this the stx_clk). The counter will update on the 305215976Sjmallett * rising edge in which backpressure is reported. 306215976Sjmallett * 307215976Sjmallett * This register will be cleared when software writes all '1's to 308215976Sjmallett * the STX_BCKPRS_CNT. 309215976Sjmallett */ 310232812Sjmallettunion cvmx_stxx_bckprs_cnt { 311215976Sjmallett uint64_t u64; 312232812Sjmallett struct cvmx_stxx_bckprs_cnt_s { 313232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 314215976Sjmallett uint64_t reserved_32_63 : 32; 315215976Sjmallett uint64_t cnt : 32; /**< Number of cycles when back-pressure is received 316215976Sjmallett for port defined in STX_STAT_CTL[BCKPRS] */ 317215976Sjmallett#else 318215976Sjmallett uint64_t cnt : 32; 319215976Sjmallett uint64_t reserved_32_63 : 32; 320215976Sjmallett#endif 321215976Sjmallett } s; 322215976Sjmallett struct cvmx_stxx_bckprs_cnt_s cn38xx; 323215976Sjmallett struct cvmx_stxx_bckprs_cnt_s cn38xxp2; 324215976Sjmallett struct cvmx_stxx_bckprs_cnt_s cn58xx; 325215976Sjmallett struct cvmx_stxx_bckprs_cnt_s cn58xxp1; 326215976Sjmallett}; 327215976Sjmalletttypedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t; 328215976Sjmallett 329215976Sjmallett/** 330215976Sjmallett * cvmx_stx#_com_ctl 331215976Sjmallett * 332215976Sjmallett * STX_COM_CTL - TX Common Control Register 333215976Sjmallett * 334215976Sjmallett * 335215976Sjmallett * Notes: 336215976Sjmallett * Restrictions: 337215976Sjmallett * Both the calendar table and the LEN and M parameters must be 338215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 339215976Sjmallett * Status channel enabled (ST_EN) asserted. 340215976Sjmallett */ 341232812Sjmallettunion cvmx_stxx_com_ctl { 342215976Sjmallett uint64_t u64; 343232812Sjmallett struct cvmx_stxx_com_ctl_s { 344232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 345215976Sjmallett uint64_t reserved_4_63 : 60; 346215976Sjmallett uint64_t st_en : 1; /**< Status channel enabled */ 347215976Sjmallett uint64_t reserved_1_2 : 2; 348215976Sjmallett uint64_t inf_en : 1; /**< Interface enable */ 349215976Sjmallett#else 350215976Sjmallett uint64_t inf_en : 1; 351215976Sjmallett uint64_t reserved_1_2 : 2; 352215976Sjmallett uint64_t st_en : 1; 353215976Sjmallett uint64_t reserved_4_63 : 60; 354215976Sjmallett#endif 355215976Sjmallett } s; 356215976Sjmallett struct cvmx_stxx_com_ctl_s cn38xx; 357215976Sjmallett struct cvmx_stxx_com_ctl_s cn38xxp2; 358215976Sjmallett struct cvmx_stxx_com_ctl_s cn58xx; 359215976Sjmallett struct cvmx_stxx_com_ctl_s cn58xxp1; 360215976Sjmallett}; 361215976Sjmalletttypedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t; 362215976Sjmallett 363215976Sjmallett/** 364215976Sjmallett * cvmx_stx#_dip_cnt 365215976Sjmallett * 366215976Sjmallett * Notes: 367215976Sjmallett * * DIPMAX 368215976Sjmallett * This counts the number of consecutive DIP2 states in which the the 369215976Sjmallett * received DIP2 is bad. The expected range is 1-15 cycles with the 370215976Sjmallett * value of 0 meaning disabled. 371215976Sjmallett * 372215976Sjmallett * * FRMMAX 373215976Sjmallett * This counts the number of consecutive unexpected framing patterns (11) 374215976Sjmallett * states. The expected range is 1-15 cycles with the value of 0 meaning 375215976Sjmallett * disabled. 376215976Sjmallett */ 377232812Sjmallettunion cvmx_stxx_dip_cnt { 378215976Sjmallett uint64_t u64; 379232812Sjmallett struct cvmx_stxx_dip_cnt_s { 380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 381215976Sjmallett uint64_t reserved_8_63 : 56; 382215976Sjmallett uint64_t frmmax : 4; /**< Number of consecutive unexpected framing patterns 383215976Sjmallett before loss of sync */ 384215976Sjmallett uint64_t dipmax : 4; /**< Number of consecutive DIP2 error before loss 385215976Sjmallett of sync */ 386215976Sjmallett#else 387215976Sjmallett uint64_t dipmax : 4; 388215976Sjmallett uint64_t frmmax : 4; 389215976Sjmallett uint64_t reserved_8_63 : 56; 390215976Sjmallett#endif 391215976Sjmallett } s; 392215976Sjmallett struct cvmx_stxx_dip_cnt_s cn38xx; 393215976Sjmallett struct cvmx_stxx_dip_cnt_s cn38xxp2; 394215976Sjmallett struct cvmx_stxx_dip_cnt_s cn58xx; 395215976Sjmallett struct cvmx_stxx_dip_cnt_s cn58xxp1; 396215976Sjmallett}; 397215976Sjmalletttypedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t; 398215976Sjmallett 399215976Sjmallett/** 400215976Sjmallett * cvmx_stx#_ign_cal 401215976Sjmallett * 402215976Sjmallett * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel 403215976Sjmallett * 404215976Sjmallett */ 405232812Sjmallettunion cvmx_stxx_ign_cal { 406215976Sjmallett uint64_t u64; 407232812Sjmallett struct cvmx_stxx_ign_cal_s { 408232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 409215976Sjmallett uint64_t reserved_16_63 : 48; 410215976Sjmallett uint64_t igntpa : 16; /**< Ignore Calendar Status from Spi4 Status Channel 411215976Sjmallett per Spi4 port 412215976Sjmallett - 0: Use the status channel info 413215976Sjmallett - 1: Grant the given port MAX_BURST1 credits */ 414215976Sjmallett#else 415215976Sjmallett uint64_t igntpa : 16; 416215976Sjmallett uint64_t reserved_16_63 : 48; 417215976Sjmallett#endif 418215976Sjmallett } s; 419215976Sjmallett struct cvmx_stxx_ign_cal_s cn38xx; 420215976Sjmallett struct cvmx_stxx_ign_cal_s cn38xxp2; 421215976Sjmallett struct cvmx_stxx_ign_cal_s cn58xx; 422215976Sjmallett struct cvmx_stxx_ign_cal_s cn58xxp1; 423215976Sjmallett}; 424215976Sjmalletttypedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t; 425215976Sjmallett 426215976Sjmallett/** 427215976Sjmallett * cvmx_stx#_int_msk 428215976Sjmallett * 429215976Sjmallett * Notes: 430215976Sjmallett * If the bit is enabled, then the coresponding exception condition will 431215976Sjmallett * result in an interrupt to the system. 432215976Sjmallett */ 433232812Sjmallettunion cvmx_stxx_int_msk { 434215976Sjmallett uint64_t u64; 435232812Sjmallett struct cvmx_stxx_int_msk_s { 436232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 437215976Sjmallett uint64_t reserved_8_63 : 56; 438215976Sjmallett uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 439215976Sjmallett uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 440215976Sjmallett uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 441215976Sjmallett uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 442215976Sjmallett uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 443215976Sjmallett uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 444215976Sjmallett uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 445215976Sjmallett uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 446215976Sjmallett#else 447215976Sjmallett uint64_t calpar0 : 1; 448215976Sjmallett uint64_t calpar1 : 1; 449215976Sjmallett uint64_t ovrbst : 1; 450215976Sjmallett uint64_t datovr : 1; 451215976Sjmallett uint64_t diperr : 1; 452215976Sjmallett uint64_t nosync : 1; 453215976Sjmallett uint64_t unxfrm : 1; 454215976Sjmallett uint64_t frmerr : 1; 455215976Sjmallett uint64_t reserved_8_63 : 56; 456215976Sjmallett#endif 457215976Sjmallett } s; 458215976Sjmallett struct cvmx_stxx_int_msk_s cn38xx; 459215976Sjmallett struct cvmx_stxx_int_msk_s cn38xxp2; 460215976Sjmallett struct cvmx_stxx_int_msk_s cn58xx; 461215976Sjmallett struct cvmx_stxx_int_msk_s cn58xxp1; 462215976Sjmallett}; 463215976Sjmalletttypedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t; 464215976Sjmallett 465215976Sjmallett/** 466215976Sjmallett * cvmx_stx#_int_reg 467215976Sjmallett * 468215976Sjmallett * Notes: 469215976Sjmallett * * CALPAR0 470215976Sjmallett * This bit indicates that the Spi4 calendar table encountered a parity 471215976Sjmallett * error on bank0 of the calendar table memory. This error bit is 472215976Sjmallett * associated with the calendar table on the TX interface - the interface 473215976Sjmallett * that drives the Spi databus. The calendar table is used in Spi4 mode 474215976Sjmallett * when using the status channel. Parity errors can occur during normal 475215976Sjmallett * operation when the calendar table is constantly being read for the port 476215976Sjmallett * information, or during initialization time, when the user has access. 477215976Sjmallett * This errors will force the the status channel to the reset state and 478215976Sjmallett * begin driving training sequences. The status channel will also reset. 479215976Sjmallett * Software must follow the init sequence to resynch the interface. This 480215976Sjmallett * includes toggling INF_EN which will cancel all outstanding accumulated 481215976Sjmallett * credits. 482215976Sjmallett * 483215976Sjmallett * * CALPAR1 484215976Sjmallett * Identical to CALPAR0 except that it indicates that the error occured 485215976Sjmallett * on bank1 (instead of bank0). 486215976Sjmallett * 487215976Sjmallett * * OVRBST 488215976Sjmallett * STX can track upto a 512KB data burst. Any packet larger than that is 489215976Sjmallett * illegal and will cause confusion in the STX state machine. BMI is 490215976Sjmallett * responsible for throwing away these out of control packets from the 491215976Sjmallett * input and the Execs should never generate them on the output. This is 492215976Sjmallett * a fatal error and should have STX_INT_SYNC[OVRBST] set. 493215976Sjmallett * 494215976Sjmallett * * DATOVR 495215976Sjmallett * FIFO where the Spi4 data ramps upto its transmit frequency has 496215976Sjmallett * overflowed. This is a fatal error and should have 497215976Sjmallett * STX_INT_SYNC[DATOVR] set. 498215976Sjmallett * 499215976Sjmallett * * DIPERR 500215976Sjmallett * This bit will fire if any DIP2 error is caught by the Spi4 status 501215976Sjmallett * channel. 502215976Sjmallett * 503215976Sjmallett * * NOSYNC 504215976Sjmallett * This bit indicates that the number of consecutive DIP2 errors exceeds 505215976Sjmallett * STX_DIP_CNT[MAXDIP] and that the interface should be taken down. The 506215976Sjmallett * datapath will be notified and send continuous training sequences until 507215976Sjmallett * software resynchronizes the interface. This error condition should 508215976Sjmallett * have STX_INT_SYNC[NOSYNC] set. 509215976Sjmallett * 510215976Sjmallett * * UNXFRM 511215976Sjmallett * Unexpected framing data was seen on the status channel. 512215976Sjmallett * 513215976Sjmallett * * FRMERR 514215976Sjmallett * This bit indicates that the number of consecutive unexpected framing 515215976Sjmallett * sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken 516215976Sjmallett * down. The datapath will be notified and send continuous training 517215976Sjmallett * sequences until software resynchronizes the interface. This error 518215976Sjmallett * condition should have STX_INT_SYNC[FRMERR] set. 519215976Sjmallett * 520215976Sjmallett * * SYNCERR 521215976Sjmallett * Indicates that an exception marked in STX_INT_SYNC has occured and the 522215976Sjmallett * TX datapath is disabled. It is recommended that the OVRBST, DATOVR, 523215976Sjmallett * NOSYNC, and FRMERR error conditions all have their bits set in the 524215976Sjmallett * STX_INT_SYNC register. 525215976Sjmallett */ 526232812Sjmallettunion cvmx_stxx_int_reg { 527215976Sjmallett uint64_t u64; 528232812Sjmallett struct cvmx_stxx_int_reg_s { 529232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 530215976Sjmallett uint64_t reserved_9_63 : 55; 531215976Sjmallett uint64_t syncerr : 1; /**< Interface encountered a fatal error */ 532215976Sjmallett uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 533215976Sjmallett uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 534215976Sjmallett uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 535215976Sjmallett uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 536215976Sjmallett uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 537215976Sjmallett uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 538215976Sjmallett uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 539215976Sjmallett uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 540215976Sjmallett#else 541215976Sjmallett uint64_t calpar0 : 1; 542215976Sjmallett uint64_t calpar1 : 1; 543215976Sjmallett uint64_t ovrbst : 1; 544215976Sjmallett uint64_t datovr : 1; 545215976Sjmallett uint64_t diperr : 1; 546215976Sjmallett uint64_t nosync : 1; 547215976Sjmallett uint64_t unxfrm : 1; 548215976Sjmallett uint64_t frmerr : 1; 549215976Sjmallett uint64_t syncerr : 1; 550215976Sjmallett uint64_t reserved_9_63 : 55; 551215976Sjmallett#endif 552215976Sjmallett } s; 553215976Sjmallett struct cvmx_stxx_int_reg_s cn38xx; 554215976Sjmallett struct cvmx_stxx_int_reg_s cn38xxp2; 555215976Sjmallett struct cvmx_stxx_int_reg_s cn58xx; 556215976Sjmallett struct cvmx_stxx_int_reg_s cn58xxp1; 557215976Sjmallett}; 558215976Sjmalletttypedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t; 559215976Sjmallett 560215976Sjmallett/** 561215976Sjmallett * cvmx_stx#_int_sync 562215976Sjmallett * 563215976Sjmallett * Notes: 564215976Sjmallett * If the bit is enabled, then the coresponding exception condition is flagged 565215976Sjmallett * to be fatal. In Spi4 mode, the exception condition will result in a loss 566215976Sjmallett * of sync condition on the Spi4 interface and the datapath will send 567215976Sjmallett * continuous traing sequences. 568215976Sjmallett * 569215976Sjmallett * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and 570215976Sjmallett * FRMERR errors as synchronization events. Software is free to 571215976Sjmallett * synchronize the bus on other conditions, but this is the minimum 572215976Sjmallett * recommended set. 573215976Sjmallett */ 574232812Sjmallettunion cvmx_stxx_int_sync { 575215976Sjmallett uint64_t u64; 576232812Sjmallett struct cvmx_stxx_int_sync_s { 577232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 578215976Sjmallett uint64_t reserved_8_63 : 56; 579215976Sjmallett uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 580215976Sjmallett uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 581215976Sjmallett uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 582215976Sjmallett uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 583215976Sjmallett uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 584215976Sjmallett uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 585215976Sjmallett uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 586215976Sjmallett uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 587215976Sjmallett#else 588215976Sjmallett uint64_t calpar0 : 1; 589215976Sjmallett uint64_t calpar1 : 1; 590215976Sjmallett uint64_t ovrbst : 1; 591215976Sjmallett uint64_t datovr : 1; 592215976Sjmallett uint64_t diperr : 1; 593215976Sjmallett uint64_t nosync : 1; 594215976Sjmallett uint64_t unxfrm : 1; 595215976Sjmallett uint64_t frmerr : 1; 596215976Sjmallett uint64_t reserved_8_63 : 56; 597215976Sjmallett#endif 598215976Sjmallett } s; 599215976Sjmallett struct cvmx_stxx_int_sync_s cn38xx; 600215976Sjmallett struct cvmx_stxx_int_sync_s cn38xxp2; 601215976Sjmallett struct cvmx_stxx_int_sync_s cn58xx; 602215976Sjmallett struct cvmx_stxx_int_sync_s cn58xxp1; 603215976Sjmallett}; 604215976Sjmalletttypedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t; 605215976Sjmallett 606215976Sjmallett/** 607215976Sjmallett * cvmx_stx#_min_bst 608215976Sjmallett * 609215976Sjmallett * STX_MIN_BST - Min Burst to enforce when inserting training sequence 610215976Sjmallett * 611215976Sjmallett */ 612232812Sjmallettunion cvmx_stxx_min_bst { 613215976Sjmallett uint64_t u64; 614232812Sjmallett struct cvmx_stxx_min_bst_s { 615232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 616215976Sjmallett uint64_t reserved_9_63 : 55; 617215976Sjmallett uint64_t minb : 9; /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates 618215976Sjmallett the number of 8B blocks to send before inserting 619215976Sjmallett a training sequence. Normally MINB will be set 620215976Sjmallett to GMX_TX_SPI_THRESH[THRESH]. MINB should always 621215976Sjmallett be set to an even number (ie. multiple of 16B) */ 622215976Sjmallett#else 623215976Sjmallett uint64_t minb : 9; 624215976Sjmallett uint64_t reserved_9_63 : 55; 625215976Sjmallett#endif 626215976Sjmallett } s; 627215976Sjmallett struct cvmx_stxx_min_bst_s cn38xx; 628215976Sjmallett struct cvmx_stxx_min_bst_s cn38xxp2; 629215976Sjmallett struct cvmx_stxx_min_bst_s cn58xx; 630215976Sjmallett struct cvmx_stxx_min_bst_s cn58xxp1; 631215976Sjmallett}; 632215976Sjmalletttypedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t; 633215976Sjmallett 634215976Sjmallett/** 635215976Sjmallett * cvmx_stx#_spi4_cal# 636215976Sjmallett * 637215976Sjmallett * specify the RSL base addresses for the block 638215976Sjmallett * STX_SPI4_CAL - Spi4 Calender table 639215976Sjmallett * direct_calendar_write / direct_calendar_read 640215976Sjmallett * 641215976Sjmallett * Notes: 642215976Sjmallett * There are 32 calendar table CSR's, each containing 4 entries for a 643215976Sjmallett * total of 128 entries. In the above definition... 644215976Sjmallett * 645215976Sjmallett * n = calendar table offset * 4 646215976Sjmallett * 647215976Sjmallett * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 648215976Sjmallett * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 649215976Sjmallett * and would contain entries (16*4) = 64, 65, 66, and 67. 650215976Sjmallett * 651215976Sjmallett * Restrictions: 652215976Sjmallett * Calendar table entry accesses (read or write) can only occur 653215976Sjmallett * if the interface is disabled. All other accesses will be 654215976Sjmallett * unpredictable. 655215976Sjmallett * 656215976Sjmallett * Both the calendar table and the LEN and M parameters must be 657215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 658215976Sjmallett * Status channel enabled (ST_EN) asserted. 659215976Sjmallett */ 660232812Sjmallettunion cvmx_stxx_spi4_calx { 661215976Sjmallett uint64_t u64; 662232812Sjmallett struct cvmx_stxx_spi4_calx_s { 663232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 664215976Sjmallett uint64_t reserved_17_63 : 47; 665215976Sjmallett uint64_t oddpar : 1; /**< Odd parity over STX_SPI4_CAL[15:0] 666215976Sjmallett (^STX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 667215976Sjmallett uint64_t prt3 : 4; /**< Status for port n+3 */ 668215976Sjmallett uint64_t prt2 : 4; /**< Status for port n+2 */ 669215976Sjmallett uint64_t prt1 : 4; /**< Status for port n+1 */ 670215976Sjmallett uint64_t prt0 : 4; /**< Status for port n+0 */ 671215976Sjmallett#else 672215976Sjmallett uint64_t prt0 : 4; 673215976Sjmallett uint64_t prt1 : 4; 674215976Sjmallett uint64_t prt2 : 4; 675215976Sjmallett uint64_t prt3 : 4; 676215976Sjmallett uint64_t oddpar : 1; 677215976Sjmallett uint64_t reserved_17_63 : 47; 678215976Sjmallett#endif 679215976Sjmallett } s; 680215976Sjmallett struct cvmx_stxx_spi4_calx_s cn38xx; 681215976Sjmallett struct cvmx_stxx_spi4_calx_s cn38xxp2; 682215976Sjmallett struct cvmx_stxx_spi4_calx_s cn58xx; 683215976Sjmallett struct cvmx_stxx_spi4_calx_s cn58xxp1; 684215976Sjmallett}; 685215976Sjmalletttypedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t; 686215976Sjmallett 687215976Sjmallett/** 688215976Sjmallett * cvmx_stx#_spi4_dat 689215976Sjmallett * 690215976Sjmallett * STX_SPI4_DAT - Spi4 datapath channel control register 691215976Sjmallett * 692215976Sjmallett * 693215976Sjmallett * Notes: 694215976Sjmallett * Restrictions: 695215976Sjmallett * * DATA_MAX_T must be in MOD 4 cycles 696215976Sjmallett * 697215976Sjmallett * * DATA_MAX_T must at least 0x20 698215976Sjmallett * 699215976Sjmallett * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce 700215976Sjmallett * 701215976Sjmallett * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall 702215976Sjmallett * waiting for min bursts to complete. In the worst case, this will 703215976Sjmallett * add the entire min burst transmission time to the interval between 704215976Sjmallett * trainging sequence. The observed MAX_T on the Spi4 bus will be... 705215976Sjmallett * 706215976Sjmallett * STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4) 707215976Sjmallett * 708215976Sjmallett * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 709215976Sjmallett * parameter will have to be adjusted. Please see the 710215976Sjmallett * STX_SPI4_DAT[MAX_T] section for additional information. In 711215976Sjmallett * addition, the min_burst can only be guaranteed on the initial data 712215976Sjmallett * burst of a given packet (i.e. the first data burst which contains 713215976Sjmallett * the SOP tick). All subsequent bursts could be truncated by training 714215976Sjmallett * sequences at any point during transmission and could be arbitrarily 715215976Sjmallett * small. This mode is only for use in Spi4 mode. 716215976Sjmallett */ 717232812Sjmallettunion cvmx_stxx_spi4_dat { 718215976Sjmallett uint64_t u64; 719232812Sjmallett struct cvmx_stxx_spi4_dat_s { 720232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 721215976Sjmallett uint64_t reserved_32_63 : 32; 722215976Sjmallett uint64_t alpha : 16; /**< alpha (from spi4.2 spec) */ 723215976Sjmallett uint64_t max_t : 16; /**< DATA_MAX_T (from spi4.2 spec) */ 724215976Sjmallett#else 725215976Sjmallett uint64_t max_t : 16; 726215976Sjmallett uint64_t alpha : 16; 727215976Sjmallett uint64_t reserved_32_63 : 32; 728215976Sjmallett#endif 729215976Sjmallett } s; 730215976Sjmallett struct cvmx_stxx_spi4_dat_s cn38xx; 731215976Sjmallett struct cvmx_stxx_spi4_dat_s cn38xxp2; 732215976Sjmallett struct cvmx_stxx_spi4_dat_s cn58xx; 733215976Sjmallett struct cvmx_stxx_spi4_dat_s cn58xxp1; 734215976Sjmallett}; 735215976Sjmalletttypedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t; 736215976Sjmallett 737215976Sjmallett/** 738215976Sjmallett * cvmx_stx#_spi4_stat 739215976Sjmallett * 740215976Sjmallett * STX_SPI4_STAT - Spi4 status channel control register 741215976Sjmallett * 742215976Sjmallett * 743215976Sjmallett * Notes: 744215976Sjmallett * Restrictions: 745215976Sjmallett * Both the calendar table and the LEN and M parameters must be 746215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 747215976Sjmallett * Status channel enabled (ST_EN) asserted. 748215976Sjmallett * 749215976Sjmallett * The calendar table will only be enabled when LEN > 0. 750215976Sjmallett * 751215976Sjmallett * Current rev will only support LVTTL status IO. 752215976Sjmallett */ 753232812Sjmallettunion cvmx_stxx_spi4_stat { 754215976Sjmallett uint64_t u64; 755232812Sjmallett struct cvmx_stxx_spi4_stat_s { 756232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 757215976Sjmallett uint64_t reserved_16_63 : 48; 758215976Sjmallett uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 759215976Sjmallett uint64_t reserved_7_7 : 1; 760215976Sjmallett uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 761215976Sjmallett#else 762215976Sjmallett uint64_t len : 7; 763215976Sjmallett uint64_t reserved_7_7 : 1; 764215976Sjmallett uint64_t m : 8; 765215976Sjmallett uint64_t reserved_16_63 : 48; 766215976Sjmallett#endif 767215976Sjmallett } s; 768215976Sjmallett struct cvmx_stxx_spi4_stat_s cn38xx; 769215976Sjmallett struct cvmx_stxx_spi4_stat_s cn38xxp2; 770215976Sjmallett struct cvmx_stxx_spi4_stat_s cn58xx; 771215976Sjmallett struct cvmx_stxx_spi4_stat_s cn58xxp1; 772215976Sjmallett}; 773215976Sjmalletttypedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t; 774215976Sjmallett 775215976Sjmallett/** 776215976Sjmallett * cvmx_stx#_stat_bytes_hi 777215976Sjmallett */ 778232812Sjmallettunion cvmx_stxx_stat_bytes_hi { 779215976Sjmallett uint64_t u64; 780232812Sjmallett struct cvmx_stxx_stat_bytes_hi_s { 781232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 782215976Sjmallett uint64_t reserved_32_63 : 32; 783215976Sjmallett uint64_t cnt : 32; /**< Number of bytes sent (CNT[63:32]) */ 784215976Sjmallett#else 785215976Sjmallett uint64_t cnt : 32; 786215976Sjmallett uint64_t reserved_32_63 : 32; 787215976Sjmallett#endif 788215976Sjmallett } s; 789215976Sjmallett struct cvmx_stxx_stat_bytes_hi_s cn38xx; 790215976Sjmallett struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; 791215976Sjmallett struct cvmx_stxx_stat_bytes_hi_s cn58xx; 792215976Sjmallett struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; 793215976Sjmallett}; 794215976Sjmalletttypedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t; 795215976Sjmallett 796215976Sjmallett/** 797215976Sjmallett * cvmx_stx#_stat_bytes_lo 798215976Sjmallett */ 799232812Sjmallettunion cvmx_stxx_stat_bytes_lo { 800215976Sjmallett uint64_t u64; 801232812Sjmallett struct cvmx_stxx_stat_bytes_lo_s { 802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 803215976Sjmallett uint64_t reserved_32_63 : 32; 804215976Sjmallett uint64_t cnt : 32; /**< Number of bytes sent (CNT[31:0]) */ 805215976Sjmallett#else 806215976Sjmallett uint64_t cnt : 32; 807215976Sjmallett uint64_t reserved_32_63 : 32; 808215976Sjmallett#endif 809215976Sjmallett } s; 810215976Sjmallett struct cvmx_stxx_stat_bytes_lo_s cn38xx; 811215976Sjmallett struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; 812215976Sjmallett struct cvmx_stxx_stat_bytes_lo_s cn58xx; 813215976Sjmallett struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; 814215976Sjmallett}; 815215976Sjmalletttypedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t; 816215976Sjmallett 817215976Sjmallett/** 818215976Sjmallett * cvmx_stx#_stat_ctl 819215976Sjmallett */ 820232812Sjmallettunion cvmx_stxx_stat_ctl { 821215976Sjmallett uint64_t u64; 822232812Sjmallett struct cvmx_stxx_stat_ctl_s { 823232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 824215976Sjmallett uint64_t reserved_5_63 : 59; 825215976Sjmallett uint64_t clr : 1; /**< Clear all statistics counters 826215976Sjmallett - STX_STAT_PKT_XMT 827215976Sjmallett - STX_STAT_BYTES_HI 828215976Sjmallett - STX_STAT_BYTES_LO */ 829215976Sjmallett uint64_t bckprs : 4; /**< The selected port for STX_BCKPRS_CNT */ 830215976Sjmallett#else 831215976Sjmallett uint64_t bckprs : 4; 832215976Sjmallett uint64_t clr : 1; 833215976Sjmallett uint64_t reserved_5_63 : 59; 834215976Sjmallett#endif 835215976Sjmallett } s; 836215976Sjmallett struct cvmx_stxx_stat_ctl_s cn38xx; 837215976Sjmallett struct cvmx_stxx_stat_ctl_s cn38xxp2; 838215976Sjmallett struct cvmx_stxx_stat_ctl_s cn58xx; 839215976Sjmallett struct cvmx_stxx_stat_ctl_s cn58xxp1; 840215976Sjmallett}; 841215976Sjmalletttypedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t; 842215976Sjmallett 843215976Sjmallett/** 844215976Sjmallett * cvmx_stx#_stat_pkt_xmt 845215976Sjmallett */ 846232812Sjmallettunion cvmx_stxx_stat_pkt_xmt { 847215976Sjmallett uint64_t u64; 848232812Sjmallett struct cvmx_stxx_stat_pkt_xmt_s { 849232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 850215976Sjmallett uint64_t reserved_32_63 : 32; 851215976Sjmallett uint64_t cnt : 32; /**< Number of packets sent */ 852215976Sjmallett#else 853215976Sjmallett uint64_t cnt : 32; 854215976Sjmallett uint64_t reserved_32_63 : 32; 855215976Sjmallett#endif 856215976Sjmallett } s; 857215976Sjmallett struct cvmx_stxx_stat_pkt_xmt_s cn38xx; 858215976Sjmallett struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; 859215976Sjmallett struct cvmx_stxx_stat_pkt_xmt_s cn58xx; 860215976Sjmallett struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; 861215976Sjmallett}; 862215976Sjmalletttypedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t; 863215976Sjmallett 864215976Sjmallett#endif 865