1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-sli-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon sli. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SLI_DEFS_H__ 53232812Sjmallett#define __CVMX_SLI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60215976Sjmallett cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n"); 61215976Sjmallett return 0x0000000000000580ull; 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset) 68215976Sjmallett{ 69215976Sjmallett if (!( 70232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 71232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 72232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 73232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 75215976Sjmallett cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset); 76232812Sjmallett return 0x0000000000000050ull + ((offset) & 3) * 16; 77215976Sjmallett} 78215976Sjmallett#else 79232812Sjmallett#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallett#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC() 83215976Sjmallettstatic inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void) 84215976Sjmallett{ 85232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 86215976Sjmallett cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n"); 87215976Sjmallett return 0x0000000000000570ull; 88215976Sjmallett} 89215976Sjmallett#else 90215976Sjmallett#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) 91215976Sjmallett#endif 92215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93215976Sjmallett#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC() 94215976Sjmallettstatic inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void) 95215976Sjmallett{ 96232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 97215976Sjmallett cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n"); 98215976Sjmallett return 0x00000000000005F0ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallett#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC() 105215976Sjmallettstatic inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void) 106215976Sjmallett{ 107232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 108215976Sjmallett cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n"); 109215976Sjmallett return 0x0000000000000310ull; 110215976Sjmallett} 111215976Sjmallett#else 112215976Sjmallett#define CVMX_SLI_DBG_DATA (0x0000000000000310ull) 113215976Sjmallett#endif 114215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115215976Sjmallett#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC() 116215976Sjmallettstatic inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void) 117215976Sjmallett{ 118232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 119215976Sjmallett cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n"); 120215976Sjmallett return 0x0000000000000300ull; 121215976Sjmallett} 122215976Sjmallett#else 123215976Sjmallett#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) 124215976Sjmallett#endif 125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126215976Sjmallettstatic inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset) 127215976Sjmallett{ 128215976Sjmallett if (!( 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 130232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 134215976Sjmallett cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset); 135215976Sjmallett return 0x0000000000000400ull + ((offset) & 1) * 16; 136215976Sjmallett} 137215976Sjmallett#else 138215976Sjmallett#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) 139215976Sjmallett#endif 140215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141215976Sjmallettstatic inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset) 142215976Sjmallett{ 143215976Sjmallett if (!( 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 145232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 146232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 147232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 149215976Sjmallett cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset); 150215976Sjmallett return 0x00000000000003E0ull + ((offset) & 1) * 16; 151215976Sjmallett} 152215976Sjmallett#else 153215976Sjmallett#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) 154215976Sjmallett#endif 155215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156215976Sjmallettstatic inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset) 157215976Sjmallett{ 158215976Sjmallett if (!( 159232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 160232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 161232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 162232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 163232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 164215976Sjmallett cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset); 165215976Sjmallett return 0x0000000000000420ull + ((offset) & 1) * 16; 166215976Sjmallett} 167215976Sjmallett#else 168215976Sjmallett#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) 169215976Sjmallett#endif 170215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 171215976Sjmallett#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC() 172215976Sjmallettstatic inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void) 173215976Sjmallett{ 174232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 175215976Sjmallett cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n"); 176215976Sjmallett return 0x0000000000003CD0ull; 177215976Sjmallett} 178215976Sjmallett#else 179215976Sjmallett#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) 180215976Sjmallett#endif 181215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 182215976Sjmallettstatic inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset) 183215976Sjmallett{ 184215976Sjmallett if (!( 185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 188232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 189232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 190215976Sjmallett cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset); 191215976Sjmallett return 0x0000000000000340ull + ((offset) & 1) * 16; 192215976Sjmallett} 193215976Sjmallett#else 194215976Sjmallett#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) 195215976Sjmallett#endif 196215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 197215976Sjmallett#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC() 198215976Sjmallettstatic inline uint64_t CVMX_SLI_INT_SUM_FUNC(void) 199215976Sjmallett{ 200232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 201215976Sjmallett cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n"); 202215976Sjmallett return 0x0000000000000330ull; 203215976Sjmallett} 204215976Sjmallett#else 205215976Sjmallett#define CVMX_SLI_INT_SUM (0x0000000000000330ull) 206215976Sjmallett#endif 207215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 208215976Sjmallett#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC() 209215976Sjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void) 210215976Sjmallett{ 211232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 212215976Sjmallett cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n"); 213215976Sjmallett return 0x0000000000000600ull; 214215976Sjmallett} 215215976Sjmallett#else 216215976Sjmallett#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) 217215976Sjmallett#endif 218215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 219215976Sjmallett#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC() 220215976Sjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void) 221215976Sjmallett{ 222232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 223215976Sjmallett cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n"); 224215976Sjmallett return 0x0000000000000610ull; 225215976Sjmallett} 226215976Sjmallett#else 227215976Sjmallett#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) 228215976Sjmallett#endif 229215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 230232812Sjmallett#define CVMX_SLI_LAST_WIN_RDATA2 CVMX_SLI_LAST_WIN_RDATA2_FUNC() 231232812Sjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA2_FUNC(void) 232232812Sjmallett{ 233232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 234232812Sjmallett cvmx_warn("CVMX_SLI_LAST_WIN_RDATA2 not supported on this chip\n"); 235232812Sjmallett return 0x00000000000006C0ull; 236232812Sjmallett} 237232812Sjmallett#else 238232812Sjmallett#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull) 239232812Sjmallett#endif 240232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 241232812Sjmallett#define CVMX_SLI_LAST_WIN_RDATA3 CVMX_SLI_LAST_WIN_RDATA3_FUNC() 242232812Sjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA3_FUNC(void) 243232812Sjmallett{ 244232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 245232812Sjmallett cvmx_warn("CVMX_SLI_LAST_WIN_RDATA3 not supported on this chip\n"); 246232812Sjmallett return 0x00000000000006D0ull; 247232812Sjmallett} 248232812Sjmallett#else 249232812Sjmallett#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull) 250232812Sjmallett#endif 251232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 252215976Sjmallett#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC() 253215976Sjmallettstatic inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void) 254215976Sjmallett{ 255232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 256215976Sjmallett cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n"); 257215976Sjmallett return 0x0000000000003D70ull; 258215976Sjmallett} 259215976Sjmallett#else 260215976Sjmallett#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) 261215976Sjmallett#endif 262215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 263232812Sjmallett#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC() 264232812Sjmallettstatic inline uint64_t CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void) 265232812Sjmallett{ 266232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 267232812Sjmallett cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT2 not supported on this chip\n"); 268232812Sjmallett return 0x0000000000003E10ull; 269232812Sjmallett} 270232812Sjmallett#else 271232812Sjmallett#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull) 272232812Sjmallett#endif 273232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 274215976Sjmallett#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC() 275215976Sjmallettstatic inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void) 276215976Sjmallett{ 277232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 278215976Sjmallett cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n"); 279215976Sjmallett return 0x0000000000003E00ull; 280215976Sjmallett} 281215976Sjmallett#else 282215976Sjmallett#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) 283215976Sjmallett#endif 284215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 285215976Sjmallett#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC() 286215976Sjmallettstatic inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void) 287215976Sjmallett{ 288232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 289215976Sjmallett cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n"); 290215976Sjmallett return 0x00000000000002F0ull; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset) 297215976Sjmallett{ 298215976Sjmallett if (!( 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) || 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) || 303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27)))))) 304215976Sjmallett cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 305232812Sjmallett return 0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12; 306215976Sjmallett} 307215976Sjmallett#else 308232812Sjmallett#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallett#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC() 312215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void) 313215976Sjmallett{ 314232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 315215976Sjmallett cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n"); 316215976Sjmallett return 0x0000000000003C50ull; 317215976Sjmallett} 318215976Sjmallett#else 319215976Sjmallett#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) 320215976Sjmallett#endif 321215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 322215976Sjmallett#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC() 323215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void) 324215976Sjmallett{ 325232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 326215976Sjmallett cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n"); 327215976Sjmallett return 0x0000000000003C60ull; 328215976Sjmallett} 329215976Sjmallett#else 330215976Sjmallett#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull) 331215976Sjmallett#endif 332215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 333215976Sjmallett#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC() 334215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void) 335215976Sjmallett{ 336232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 337215976Sjmallett cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n"); 338215976Sjmallett return 0x0000000000003C70ull; 339215976Sjmallett} 340215976Sjmallett#else 341215976Sjmallett#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull) 342215976Sjmallett#endif 343215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 344215976Sjmallett#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC() 345215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void) 346215976Sjmallett{ 347232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 348215976Sjmallett cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n"); 349215976Sjmallett return 0x0000000000003C80ull; 350215976Sjmallett} 351215976Sjmallett#else 352215976Sjmallett#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull) 353215976Sjmallett#endif 354215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355215976Sjmallett#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC() 356215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void) 357215976Sjmallett{ 358232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 359215976Sjmallett cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n"); 360215976Sjmallett return 0x0000000000003C10ull; 361215976Sjmallett} 362215976Sjmallett#else 363215976Sjmallett#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull) 364215976Sjmallett#endif 365215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 366215976Sjmallett#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC() 367215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void) 368215976Sjmallett{ 369232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 370215976Sjmallett cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n"); 371215976Sjmallett return 0x0000000000003C20ull; 372215976Sjmallett} 373215976Sjmallett#else 374215976Sjmallett#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull) 375215976Sjmallett#endif 376215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 377215976Sjmallett#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC() 378215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void) 379215976Sjmallett{ 380232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 381215976Sjmallett cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n"); 382215976Sjmallett return 0x0000000000003C30ull; 383215976Sjmallett} 384215976Sjmallett#else 385215976Sjmallett#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull) 386215976Sjmallett#endif 387215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 388215976Sjmallett#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC() 389215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void) 390215976Sjmallett{ 391232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 392215976Sjmallett cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n"); 393215976Sjmallett return 0x0000000000003C40ull; 394215976Sjmallett} 395215976Sjmallett#else 396215976Sjmallett#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull) 397215976Sjmallett#endif 398215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 399215976Sjmallett#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC() 400215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void) 401215976Sjmallett{ 402232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 403215976Sjmallett cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n"); 404215976Sjmallett return 0x0000000000003CA0ull; 405215976Sjmallett} 406215976Sjmallett#else 407215976Sjmallett#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull) 408215976Sjmallett#endif 409215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 410215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC() 411215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void) 412215976Sjmallett{ 413232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 414215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n"); 415215976Sjmallett return 0x0000000000003CF0ull; 416215976Sjmallett} 417215976Sjmallett#else 418215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 419215976Sjmallett#endif 420215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 421215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC() 422215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void) 423215976Sjmallett{ 424232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 425215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n"); 426215976Sjmallett return 0x0000000000003D00ull; 427215976Sjmallett} 428215976Sjmallett#else 429215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull) 430215976Sjmallett#endif 431215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 432215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC() 433215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void) 434215976Sjmallett{ 435232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 436215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n"); 437215976Sjmallett return 0x0000000000003D10ull; 438215976Sjmallett} 439215976Sjmallett#else 440215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull) 441215976Sjmallett#endif 442215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 443215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC() 444215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void) 445215976Sjmallett{ 446232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 447215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n"); 448215976Sjmallett return 0x0000000000003D20ull; 449215976Sjmallett} 450215976Sjmallett#else 451215976Sjmallett#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull) 452215976Sjmallett#endif 453215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 454215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC() 455215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void) 456215976Sjmallett{ 457232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 458215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n"); 459215976Sjmallett return 0x0000000000003D30ull; 460215976Sjmallett} 461215976Sjmallett#else 462215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull) 463215976Sjmallett#endif 464215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 465215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC() 466215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void) 467215976Sjmallett{ 468232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 469215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n"); 470215976Sjmallett return 0x0000000000003D40ull; 471215976Sjmallett} 472215976Sjmallett#else 473215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull) 474215976Sjmallett#endif 475215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC() 477215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void) 478215976Sjmallett{ 479232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 480215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n"); 481215976Sjmallett return 0x0000000000003D50ull; 482215976Sjmallett} 483215976Sjmallett#else 484215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull) 485215976Sjmallett#endif 486215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 487215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC() 488215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void) 489215976Sjmallett{ 490232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 491215976Sjmallett cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n"); 492215976Sjmallett return 0x0000000000003D60ull; 493215976Sjmallett} 494215976Sjmallett#else 495215976Sjmallett#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull) 496215976Sjmallett#endif 497215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498215976Sjmallett#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC() 499215976Sjmallettstatic inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void) 500215976Sjmallett{ 501232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 502215976Sjmallett cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n"); 503215976Sjmallett return 0x0000000000003C90ull; 504215976Sjmallett} 505215976Sjmallett#else 506215976Sjmallett#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull) 507215976Sjmallett#endif 508215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 509215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC() 510215976Sjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void) 511215976Sjmallett{ 512232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 513215976Sjmallett cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n"); 514215976Sjmallett return 0x0000000000003CB0ull; 515215976Sjmallett} 516215976Sjmallett#else 517215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull) 518215976Sjmallett#endif 519215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 520215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC() 521215976Sjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void) 522215976Sjmallett{ 523232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 524215976Sjmallett cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 525215976Sjmallett return 0x0000000000000650ull; 526215976Sjmallett} 527215976Sjmallett#else 528215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 529215976Sjmallett#endif 530215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 531215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC() 532215976Sjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void) 533215976Sjmallett{ 534232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 535215976Sjmallett cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 536215976Sjmallett return 0x0000000000000660ull; 537215976Sjmallett} 538215976Sjmallett#else 539215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 540215976Sjmallett#endif 541215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 542215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC() 543215976Sjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void) 544215976Sjmallett{ 545232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 546215976Sjmallett cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 547215976Sjmallett return 0x0000000000000670ull; 548215976Sjmallett} 549215976Sjmallett#else 550215976Sjmallett#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 551215976Sjmallett#endif 552215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 553215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset) 554215976Sjmallett{ 555215976Sjmallett if (!( 556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 558232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 559232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 560232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 561215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 562215976Sjmallett return 0x0000000000002400ull + ((offset) & 31) * 16; 563215976Sjmallett} 564215976Sjmallett#else 565215976Sjmallett#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 566215976Sjmallett#endif 567215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 568215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset) 569215976Sjmallett{ 570215976Sjmallett if (!( 571232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 572232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 573232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 574232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 576215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 577215976Sjmallett return 0x0000000000002800ull + ((offset) & 31) * 16; 578215976Sjmallett} 579215976Sjmallett#else 580215976Sjmallett#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 581215976Sjmallett#endif 582215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 584215976Sjmallett{ 585215976Sjmallett if (!( 586232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 587232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 588232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 589232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 590232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 591215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 592215976Sjmallett return 0x0000000000002C00ull + ((offset) & 31) * 16; 593215976Sjmallett} 594215976Sjmallett#else 595215976Sjmallett#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 596215976Sjmallett#endif 597215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 598215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 599215976Sjmallett{ 600215976Sjmallett if (!( 601232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 602232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 603232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 604232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 605232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 606215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 607215976Sjmallett return 0x0000000000003000ull + ((offset) & 31) * 16; 608215976Sjmallett} 609215976Sjmallett#else 610215976Sjmallett#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 611215976Sjmallett#endif 612215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 613215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset) 614215976Sjmallett{ 615215976Sjmallett if (!( 616232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 617232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 618232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 619232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 620232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 621215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 622215976Sjmallett return 0x0000000000003400ull + ((offset) & 31) * 16; 623215976Sjmallett} 624215976Sjmallett#else 625215976Sjmallett#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 626215976Sjmallett#endif 627215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset) 629215976Sjmallett{ 630215976Sjmallett if (!( 631232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 632232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 633232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 634232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 635215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 636215976Sjmallett return 0x0000000000003800ull + ((offset) & 31) * 16; 637215976Sjmallett} 638215976Sjmallett#else 639215976Sjmallett#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 640215976Sjmallett#endif 641215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 642215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset) 643215976Sjmallett{ 644215976Sjmallett if (!( 645232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 646232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 647232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 648232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 649232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 650215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset); 651215976Sjmallett return 0x0000000000000C00ull + ((offset) & 31) * 16; 652215976Sjmallett} 653215976Sjmallett#else 654215976Sjmallett#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16) 655215976Sjmallett#endif 656215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 657215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset) 658215976Sjmallett{ 659215976Sjmallett if (!( 660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 661232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 662232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 663232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 664232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 665215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 666215976Sjmallett return 0x0000000000001400ull + ((offset) & 31) * 16; 667215976Sjmallett} 668215976Sjmallett#else 669215976Sjmallett#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 670215976Sjmallett#endif 671215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 673215976Sjmallett{ 674215976Sjmallett if (!( 675232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 676232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 677232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 678232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 679232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 680215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 681215976Sjmallett return 0x0000000000001800ull + ((offset) & 31) * 16; 682215976Sjmallett} 683215976Sjmallett#else 684215976Sjmallett#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 685215976Sjmallett#endif 686215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 687215976Sjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 688215976Sjmallett{ 689215976Sjmallett if (!( 690232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 691232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 692232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 693232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 694232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 695215976Sjmallett cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 696215976Sjmallett return 0x0000000000001C00ull + ((offset) & 31) * 16; 697215976Sjmallett} 698215976Sjmallett#else 699215976Sjmallett#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 700215976Sjmallett#endif 701215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 702215976Sjmallett#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC() 703215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void) 704215976Sjmallett{ 705232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 706215976Sjmallett cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n"); 707215976Sjmallett return 0x0000000000001130ull; 708215976Sjmallett} 709215976Sjmallett#else 710215976Sjmallett#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull) 711215976Sjmallett#endif 712215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 713215976Sjmallett#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC() 714215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void) 715215976Sjmallett{ 716232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 717215976Sjmallett cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n"); 718215976Sjmallett return 0x0000000000001150ull; 719215976Sjmallett} 720215976Sjmallett#else 721215976Sjmallett#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull) 722215976Sjmallett#endif 723215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 724215976Sjmallett#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC() 725215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void) 726215976Sjmallett{ 727232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 728215976Sjmallett cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n"); 729215976Sjmallett return 0x0000000000001220ull; 730215976Sjmallett} 731215976Sjmallett#else 732215976Sjmallett#define CVMX_SLI_PKT_CTL (0x0000000000001220ull) 733215976Sjmallett#endif 734215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 735215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC() 736215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void) 737215976Sjmallett{ 738232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 739215976Sjmallett cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n"); 740215976Sjmallett return 0x00000000000010B0ull; 741215976Sjmallett} 742215976Sjmallett#else 743215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 744215976Sjmallett#endif 745215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 746215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC() 747215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void) 748215976Sjmallett{ 749232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 750215976Sjmallett cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n"); 751215976Sjmallett return 0x00000000000010A0ull; 752215976Sjmallett} 753215976Sjmallett#else 754215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 755215976Sjmallett#endif 756215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 757215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC() 758215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void) 759215976Sjmallett{ 760232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 761215976Sjmallett cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n"); 762215976Sjmallett return 0x0000000000001090ull; 763215976Sjmallett} 764215976Sjmallett#else 765215976Sjmallett#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 766215976Sjmallett#endif 767215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 768215976Sjmallett#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC() 769215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void) 770215976Sjmallett{ 771232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 772215976Sjmallett cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n"); 773215976Sjmallett return 0x0000000000001080ull; 774215976Sjmallett} 775215976Sjmallett#else 776215976Sjmallett#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull) 777215976Sjmallett#endif 778215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 779215976Sjmallett#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC() 780215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void) 781215976Sjmallett{ 782232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 783215976Sjmallett cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n"); 784215976Sjmallett return 0x0000000000001170ull; 785215976Sjmallett} 786215976Sjmallett#else 787215976Sjmallett#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull) 788215976Sjmallett#endif 789215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 790215976Sjmallett#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC() 791215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void) 792215976Sjmallett{ 793232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 794215976Sjmallett cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n"); 795215976Sjmallett return 0x0000000000001000ull; 796215976Sjmallett} 797215976Sjmallett#else 798215976Sjmallett#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull) 799215976Sjmallett#endif 800215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 801215976Sjmallett#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC() 802215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void) 803215976Sjmallett{ 804232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 805215976Sjmallett cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 806215976Sjmallett return 0x00000000000011A0ull; 807215976Sjmallett} 808215976Sjmallett#else 809215976Sjmallett#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull) 810215976Sjmallett#endif 811215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 812215976Sjmallett#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC() 813215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void) 814215976Sjmallett{ 815232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 816215976Sjmallett cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n"); 817215976Sjmallett return 0x0000000000001020ull; 818215976Sjmallett} 819215976Sjmallett#else 820215976Sjmallett#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull) 821215976Sjmallett#endif 822215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 823215976Sjmallett#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC() 824215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void) 825215976Sjmallett{ 826232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 827215976Sjmallett cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n"); 828215976Sjmallett return 0x0000000000001120ull; 829215976Sjmallett} 830215976Sjmallett#else 831215976Sjmallett#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull) 832215976Sjmallett#endif 833215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 834215976Sjmallett#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC() 835215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void) 836215976Sjmallett{ 837232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 838215976Sjmallett cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n"); 839215976Sjmallett return 0x0000000000001210ull; 840215976Sjmallett} 841215976Sjmallett#else 842215976Sjmallett#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull) 843215976Sjmallett#endif 844215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 845215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset) 846215976Sjmallett{ 847215976Sjmallett if (!( 848232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 849232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 850232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 851232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 852232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 853215976Sjmallett cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 854215976Sjmallett return 0x0000000000002000ull + ((offset) & 31) * 16; 855215976Sjmallett} 856215976Sjmallett#else 857215976Sjmallett#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 858215976Sjmallett#endif 859215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 860215976Sjmallett#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC() 861215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void) 862215976Sjmallett{ 863232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 864215976Sjmallett cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 865215976Sjmallett return 0x0000000000001200ull; 866215976Sjmallett} 867215976Sjmallett#else 868215976Sjmallett#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull) 869215976Sjmallett#endif 870215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 871215976Sjmallett#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC() 872215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void) 873215976Sjmallett{ 874232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 875215976Sjmallett cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n"); 876215976Sjmallett return 0x00000000000011B0ull; 877215976Sjmallett} 878215976Sjmallett#else 879215976Sjmallett#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull) 880215976Sjmallett#endif 881215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 882215976Sjmallett#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC() 883215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void) 884215976Sjmallett{ 885232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 886215976Sjmallett cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n"); 887215976Sjmallett return 0x0000000000001070ull; 888215976Sjmallett} 889215976Sjmallett#else 890215976Sjmallett#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull) 891215976Sjmallett#endif 892215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 893215976Sjmallett#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC() 894215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void) 895215976Sjmallett{ 896232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 897215976Sjmallett cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n"); 898215976Sjmallett return 0x0000000000001180ull; 899215976Sjmallett} 900215976Sjmallett#else 901215976Sjmallett#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull) 902215976Sjmallett#endif 903215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 904215976Sjmallett#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC() 905215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void) 906215976Sjmallett{ 907232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 908215976Sjmallett cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n"); 909215976Sjmallett return 0x00000000000010D0ull; 910215976Sjmallett} 911215976Sjmallett#else 912215976Sjmallett#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull) 913215976Sjmallett#endif 914215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 915232812Sjmallett#define CVMX_SLI_PKT_OUT_BP_EN CVMX_SLI_PKT_OUT_BP_EN_FUNC() 916232812Sjmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_BP_EN_FUNC(void) 917232812Sjmallett{ 918232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 919232812Sjmallett cvmx_warn("CVMX_SLI_PKT_OUT_BP_EN not supported on this chip\n"); 920232812Sjmallett return 0x0000000000001240ull; 921232812Sjmallett} 922232812Sjmallett#else 923232812Sjmallett#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull) 924232812Sjmallett#endif 925232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 926215976Sjmallett#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC() 927215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void) 928215976Sjmallett{ 929232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 930215976Sjmallett cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n"); 931215976Sjmallett return 0x0000000000001010ull; 932215976Sjmallett} 933215976Sjmallett#else 934215976Sjmallett#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull) 935215976Sjmallett#endif 936215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 937215976Sjmallett#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC() 938215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void) 939215976Sjmallett{ 940232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 941215976Sjmallett cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n"); 942215976Sjmallett return 0x00000000000010E0ull; 943215976Sjmallett} 944215976Sjmallett#else 945215976Sjmallett#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull) 946215976Sjmallett#endif 947215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 948215976Sjmallett#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC() 949215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void) 950215976Sjmallett{ 951232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 952215976Sjmallett cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n"); 953215976Sjmallett return 0x00000000000011F0ull; 954215976Sjmallett} 955215976Sjmallett#else 956215976Sjmallett#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull) 957215976Sjmallett#endif 958215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 959215976Sjmallett#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC() 960215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void) 961215976Sjmallett{ 962232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 963215976Sjmallett cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n"); 964215976Sjmallett return 0x0000000000001050ull; 965215976Sjmallett} 966215976Sjmallett#else 967215976Sjmallett#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull) 968215976Sjmallett#endif 969215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 970215976Sjmallett#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC() 971215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void) 972215976Sjmallett{ 973232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 974215976Sjmallett cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n"); 975215976Sjmallett return 0x0000000000001040ull; 976215976Sjmallett} 977215976Sjmallett#else 978215976Sjmallett#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull) 979215976Sjmallett#endif 980215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 981215976Sjmallett#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC() 982215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void) 983215976Sjmallett{ 984232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 985215976Sjmallett cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n"); 986215976Sjmallett return 0x0000000000001030ull; 987215976Sjmallett} 988215976Sjmallett#else 989215976Sjmallett#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull) 990215976Sjmallett#endif 991215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 992215976Sjmallett#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC() 993215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void) 994215976Sjmallett{ 995232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 996215976Sjmallett cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n"); 997215976Sjmallett return 0x0000000000001140ull; 998215976Sjmallett} 999215976Sjmallett#else 1000215976Sjmallett#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull) 1001215976Sjmallett#endif 1002215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1003215976Sjmallett#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC() 1004215976Sjmallettstatic inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void) 1005215976Sjmallett{ 1006232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1007215976Sjmallett cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n"); 1008215976Sjmallett return 0x0000000000001160ull; 1009215976Sjmallett} 1010215976Sjmallett#else 1011215976Sjmallett#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull) 1012215976Sjmallett#endif 1013215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1014232812Sjmallettstatic inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset) 1015232812Sjmallett{ 1016232812Sjmallett if (!( 1017232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))))) 1018232812Sjmallett cvmx_warn("CVMX_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset); 1019232812Sjmallett return 0x0000000000000800ull + ((offset) & 31) * 16; 1020232812Sjmallett} 1021232812Sjmallett#else 1022232812Sjmallett#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16) 1023232812Sjmallett#endif 1024232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1025215976Sjmallettstatic inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset) 1026215976Sjmallett{ 1027215976Sjmallett if (!( 1028232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1029232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1030232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 1031232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1032232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1033215976Sjmallett cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset); 1034232812Sjmallett return 0x0000000000003D80ull + ((offset) & 3) * 16; 1035215976Sjmallett} 1036215976Sjmallett#else 1037232812Sjmallett#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16) 1038215976Sjmallett#endif 1039215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1040215976Sjmallett#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC() 1041215976Sjmallettstatic inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void) 1042215976Sjmallett{ 1043232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1044215976Sjmallett cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n"); 1045215976Sjmallett return 0x00000000000003C0ull; 1046215976Sjmallett} 1047215976Sjmallett#else 1048215976Sjmallett#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull) 1049215976Sjmallett#endif 1050215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1051215976Sjmallett#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC() 1052215976Sjmallettstatic inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void) 1053215976Sjmallett{ 1054232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1055215976Sjmallett cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n"); 1056215976Sjmallett return 0x00000000000003D0ull; 1057215976Sjmallett} 1058215976Sjmallett#else 1059215976Sjmallett#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull) 1060215976Sjmallett#endif 1061215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1062215976Sjmallett#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC() 1063215976Sjmallettstatic inline uint64_t CVMX_SLI_STATE1_FUNC(void) 1064215976Sjmallett{ 1065232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1066215976Sjmallett cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n"); 1067215976Sjmallett return 0x0000000000000620ull; 1068215976Sjmallett} 1069215976Sjmallett#else 1070215976Sjmallett#define CVMX_SLI_STATE1 (0x0000000000000620ull) 1071215976Sjmallett#endif 1072215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1073215976Sjmallett#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC() 1074215976Sjmallettstatic inline uint64_t CVMX_SLI_STATE2_FUNC(void) 1075215976Sjmallett{ 1076232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1077215976Sjmallett cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n"); 1078215976Sjmallett return 0x0000000000000630ull; 1079215976Sjmallett} 1080215976Sjmallett#else 1081215976Sjmallett#define CVMX_SLI_STATE2 (0x0000000000000630ull) 1082215976Sjmallett#endif 1083215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1084215976Sjmallett#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC() 1085215976Sjmallettstatic inline uint64_t CVMX_SLI_STATE3_FUNC(void) 1086215976Sjmallett{ 1087232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1088215976Sjmallett cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n"); 1089215976Sjmallett return 0x0000000000000640ull; 1090215976Sjmallett} 1091215976Sjmallett#else 1092215976Sjmallett#define CVMX_SLI_STATE3 (0x0000000000000640ull) 1093215976Sjmallett#endif 1094215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1095232812Sjmallett#define CVMX_SLI_TX_PIPE CVMX_SLI_TX_PIPE_FUNC() 1096232812Sjmallettstatic inline uint64_t CVMX_SLI_TX_PIPE_FUNC(void) 1097232812Sjmallett{ 1098232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 1099232812Sjmallett cvmx_warn("CVMX_SLI_TX_PIPE not supported on this chip\n"); 1100232812Sjmallett return 0x0000000000001230ull; 1101232812Sjmallett} 1102232812Sjmallett#else 1103232812Sjmallett#define CVMX_SLI_TX_PIPE (0x0000000000001230ull) 1104232812Sjmallett#endif 1105232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1106215976Sjmallett#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC() 1107215976Sjmallettstatic inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void) 1108215976Sjmallett{ 1109232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1110215976Sjmallett cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n"); 1111215976Sjmallett return 0x00000000000002E0ull; 1112215976Sjmallett} 1113215976Sjmallett#else 1114215976Sjmallett#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull) 1115215976Sjmallett#endif 1116215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1117215976Sjmallett#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC() 1118215976Sjmallettstatic inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void) 1119215976Sjmallett{ 1120232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1121215976Sjmallett cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n"); 1122215976Sjmallett return 0x0000000000000010ull; 1123215976Sjmallett} 1124215976Sjmallett#else 1125215976Sjmallett#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull) 1126215976Sjmallett#endif 1127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1128215976Sjmallett#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC() 1129215976Sjmallettstatic inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void) 1130215976Sjmallett{ 1131232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1132215976Sjmallett cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n"); 1133215976Sjmallett return 0x0000000000000040ull; 1134215976Sjmallett} 1135215976Sjmallett#else 1136215976Sjmallett#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull) 1137215976Sjmallett#endif 1138215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1139215976Sjmallett#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC() 1140215976Sjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void) 1141215976Sjmallett{ 1142232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1143215976Sjmallett cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n"); 1144215976Sjmallett return 0x0000000000000000ull; 1145215976Sjmallett} 1146215976Sjmallett#else 1147215976Sjmallett#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull) 1148215976Sjmallett#endif 1149215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1150215976Sjmallett#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC() 1151215976Sjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void) 1152215976Sjmallett{ 1153232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1154215976Sjmallett cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n"); 1155215976Sjmallett return 0x0000000000000020ull; 1156215976Sjmallett} 1157215976Sjmallett#else 1158215976Sjmallett#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull) 1159215976Sjmallett#endif 1160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1161215976Sjmallett#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC() 1162215976Sjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void) 1163215976Sjmallett{ 1164232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1165215976Sjmallett cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n"); 1166215976Sjmallett return 0x0000000000000030ull; 1167215976Sjmallett} 1168215976Sjmallett#else 1169215976Sjmallett#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull) 1170215976Sjmallett#endif 1171215976Sjmallett 1172215976Sjmallett/** 1173215976Sjmallett * cvmx_sli_bist_status 1174215976Sjmallett * 1175215976Sjmallett * SLI_BIST_STATUS = SLI's BIST Status Register 1176215976Sjmallett * 1177215976Sjmallett * Results from BIST runs of SLI's memories. 1178215976Sjmallett */ 1179232812Sjmallettunion cvmx_sli_bist_status { 1180215976Sjmallett uint64_t u64; 1181232812Sjmallett struct cvmx_sli_bist_status_s { 1182232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1183232812Sjmallett uint64_t reserved_32_63 : 32; 1184232812Sjmallett uint64_t ncb_req : 1; /**< BIST Status for NCB Request FIFO */ 1185232812Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1186232812Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1187232812Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1188232812Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1189232812Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1190232812Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1191232812Sjmallett uint64_t reserved_19_24 : 6; 1192232812Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1193232812Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1194232812Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1195232812Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1196232812Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1197232812Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1198232812Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1199232812Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1200232812Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1201232812Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1202232812Sjmallett uint64_t reserved_6_8 : 3; 1203232812Sjmallett uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */ 1204232812Sjmallett uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */ 1205232812Sjmallett uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */ 1206232812Sjmallett uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */ 1207232812Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1208232812Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1209232812Sjmallett#else 1210232812Sjmallett uint64_t ncb_cmd : 1; 1211232812Sjmallett uint64_t msi : 1; 1212232812Sjmallett uint64_t dsi0_0 : 1; 1213232812Sjmallett uint64_t dsi0_1 : 1; 1214232812Sjmallett uint64_t dsi1_0 : 1; 1215232812Sjmallett uint64_t dsi1_1 : 1; 1216232812Sjmallett uint64_t reserved_6_8 : 3; 1217232812Sjmallett uint64_t p2n1_p1 : 1; 1218232812Sjmallett uint64_t p2n1_p0 : 1; 1219232812Sjmallett uint64_t p2n1_n : 1; 1220232812Sjmallett uint64_t p2n1_c1 : 1; 1221232812Sjmallett uint64_t p2n1_c0 : 1; 1222232812Sjmallett uint64_t p2n0_p1 : 1; 1223232812Sjmallett uint64_t p2n0_p0 : 1; 1224232812Sjmallett uint64_t p2n0_n : 1; 1225232812Sjmallett uint64_t p2n0_c1 : 1; 1226232812Sjmallett uint64_t p2n0_c0 : 1; 1227232812Sjmallett uint64_t reserved_19_24 : 6; 1228232812Sjmallett uint64_t cpl_p1 : 1; 1229232812Sjmallett uint64_t cpl_p0 : 1; 1230232812Sjmallett uint64_t n2p1_o : 1; 1231232812Sjmallett uint64_t n2p1_c : 1; 1232232812Sjmallett uint64_t n2p0_o : 1; 1233232812Sjmallett uint64_t n2p0_c : 1; 1234232812Sjmallett uint64_t ncb_req : 1; 1235232812Sjmallett uint64_t reserved_32_63 : 32; 1236232812Sjmallett#endif 1237232812Sjmallett } s; 1238232812Sjmallett struct cvmx_sli_bist_status_cn61xx { 1239232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1240215976Sjmallett uint64_t reserved_31_63 : 33; 1241215976Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1242215976Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1243232812Sjmallett uint64_t reserved_27_28 : 2; 1244232812Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1245232812Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1246232812Sjmallett uint64_t reserved_19_24 : 6; 1247232812Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1248232812Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1249232812Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1250232812Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1251232812Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1252232812Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1253232812Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1254232812Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1255232812Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1256232812Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1257232812Sjmallett uint64_t reserved_6_8 : 3; 1258232812Sjmallett uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */ 1259232812Sjmallett uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */ 1260232812Sjmallett uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */ 1261232812Sjmallett uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */ 1262232812Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1263232812Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1264232812Sjmallett#else 1265232812Sjmallett uint64_t ncb_cmd : 1; 1266232812Sjmallett uint64_t msi : 1; 1267232812Sjmallett uint64_t dsi0_0 : 1; 1268232812Sjmallett uint64_t dsi0_1 : 1; 1269232812Sjmallett uint64_t dsi1_0 : 1; 1270232812Sjmallett uint64_t dsi1_1 : 1; 1271232812Sjmallett uint64_t reserved_6_8 : 3; 1272232812Sjmallett uint64_t p2n1_p1 : 1; 1273232812Sjmallett uint64_t p2n1_p0 : 1; 1274232812Sjmallett uint64_t p2n1_n : 1; 1275232812Sjmallett uint64_t p2n1_c1 : 1; 1276232812Sjmallett uint64_t p2n1_c0 : 1; 1277232812Sjmallett uint64_t p2n0_p1 : 1; 1278232812Sjmallett uint64_t p2n0_p0 : 1; 1279232812Sjmallett uint64_t p2n0_n : 1; 1280232812Sjmallett uint64_t p2n0_c1 : 1; 1281232812Sjmallett uint64_t p2n0_c0 : 1; 1282232812Sjmallett uint64_t reserved_19_24 : 6; 1283232812Sjmallett uint64_t cpl_p1 : 1; 1284232812Sjmallett uint64_t cpl_p0 : 1; 1285232812Sjmallett uint64_t reserved_27_28 : 2; 1286232812Sjmallett uint64_t n2p0_o : 1; 1287232812Sjmallett uint64_t n2p0_c : 1; 1288232812Sjmallett uint64_t reserved_31_63 : 33; 1289232812Sjmallett#endif 1290232812Sjmallett } cn61xx; 1291232812Sjmallett struct cvmx_sli_bist_status_cn63xx { 1292232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1293232812Sjmallett uint64_t reserved_31_63 : 33; 1294232812Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1295232812Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1296215976Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1297215976Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1298215976Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1299215976Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1300215976Sjmallett uint64_t reserved_19_24 : 6; 1301215976Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1302215976Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1303215976Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1304215976Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1305215976Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1306215976Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1307215976Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1308215976Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1309215976Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1310215976Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1311215976Sjmallett uint64_t reserved_6_8 : 3; 1312215976Sjmallett uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */ 1313215976Sjmallett uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */ 1314215976Sjmallett uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */ 1315215976Sjmallett uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */ 1316215976Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1317215976Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1318215976Sjmallett#else 1319215976Sjmallett uint64_t ncb_cmd : 1; 1320215976Sjmallett uint64_t msi : 1; 1321215976Sjmallett uint64_t dsi0_0 : 1; 1322215976Sjmallett uint64_t dsi0_1 : 1; 1323215976Sjmallett uint64_t dsi1_0 : 1; 1324215976Sjmallett uint64_t dsi1_1 : 1; 1325215976Sjmallett uint64_t reserved_6_8 : 3; 1326215976Sjmallett uint64_t p2n1_p1 : 1; 1327215976Sjmallett uint64_t p2n1_p0 : 1; 1328215976Sjmallett uint64_t p2n1_n : 1; 1329215976Sjmallett uint64_t p2n1_c1 : 1; 1330215976Sjmallett uint64_t p2n1_c0 : 1; 1331215976Sjmallett uint64_t p2n0_p1 : 1; 1332215976Sjmallett uint64_t p2n0_p0 : 1; 1333215976Sjmallett uint64_t p2n0_n : 1; 1334215976Sjmallett uint64_t p2n0_c1 : 1; 1335215976Sjmallett uint64_t p2n0_c0 : 1; 1336215976Sjmallett uint64_t reserved_19_24 : 6; 1337215976Sjmallett uint64_t cpl_p1 : 1; 1338215976Sjmallett uint64_t cpl_p0 : 1; 1339215976Sjmallett uint64_t n2p1_o : 1; 1340215976Sjmallett uint64_t n2p1_c : 1; 1341215976Sjmallett uint64_t n2p0_o : 1; 1342215976Sjmallett uint64_t n2p0_c : 1; 1343215976Sjmallett uint64_t reserved_31_63 : 33; 1344215976Sjmallett#endif 1345232812Sjmallett } cn63xx; 1346232812Sjmallett struct cvmx_sli_bist_status_cn63xx cn63xxp1; 1347232812Sjmallett struct cvmx_sli_bist_status_cn61xx cn66xx; 1348232812Sjmallett struct cvmx_sli_bist_status_s cn68xx; 1349232812Sjmallett struct cvmx_sli_bist_status_s cn68xxp1; 1350232812Sjmallett struct cvmx_sli_bist_status_cn61xx cnf71xx; 1351215976Sjmallett}; 1352215976Sjmalletttypedef union cvmx_sli_bist_status cvmx_sli_bist_status_t; 1353215976Sjmallett 1354215976Sjmallett/** 1355215976Sjmallett * cvmx_sli_ctl_port# 1356215976Sjmallett * 1357215976Sjmallett * SLI_CTL_PORTX = SLI's Control Port X 1358215976Sjmallett * 1359215976Sjmallett * Contains control for access for Port0 1360215976Sjmallett */ 1361232812Sjmallettunion cvmx_sli_ctl_portx { 1362215976Sjmallett uint64_t u64; 1363232812Sjmallett struct cvmx_sli_ctl_portx_s { 1364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1365215976Sjmallett uint64_t reserved_22_63 : 42; 1366215976Sjmallett uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1367215976Sjmallett uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1368215976Sjmallett uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */ 1369215976Sjmallett uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1370215976Sjmallett uint64_t dis_port : 1; /**< When set the output to the MAC is disabled. This 1371215976Sjmallett occurs when the MAC reset line transitions from 1372215976Sjmallett de-asserted to asserted. Writing a '1' to this 1373215976Sjmallett location will clear this condition when the MAC is 1374215976Sjmallett no longer in reset and the output to the MAC is at 1375215976Sjmallett the begining of a transfer. */ 1376215976Sjmallett uint64_t waitl_com : 1; /**< When set '1' casues the SLI to wait for a commit 1377215976Sjmallett from the L2C before sending additional completions 1378215976Sjmallett to the L2C from a MAC. 1379215976Sjmallett Set this for more conservative behavior. Clear 1380215976Sjmallett this for more aggressive, higher-performance 1381215976Sjmallett behavior */ 1382215976Sjmallett uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1383215976Sjmallett INTD (11). */ 1384215976Sjmallett uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1385215976Sjmallett INTD (11). */ 1386215976Sjmallett uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1387215976Sjmallett INTD (11). */ 1388215976Sjmallett uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1389215976Sjmallett INTD (11). */ 1390215976Sjmallett uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1391215976Sjmallett uint64_t reserved_6_6 : 1; 1392215976Sjmallett uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1393215976Sjmallett uint64_t reserved_1_4 : 4; 1394215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the SLI to wait for a commit 1395215976Sjmallett from the L2C before sending additional stores to 1396215976Sjmallett the L2C from a MAC. 1397215976Sjmallett The SLI will request a commit on the last store 1398215976Sjmallett if more than one STORE operation is required on 1399215976Sjmallett the NCB. 1400215976Sjmallett Most applications will not notice a difference, so 1401215976Sjmallett should not set this bit. Setting the bit is more 1402215976Sjmallett conservative on ordering, lower performance */ 1403215976Sjmallett#else 1404215976Sjmallett uint64_t wait_com : 1; 1405215976Sjmallett uint64_t reserved_1_4 : 4; 1406215976Sjmallett uint64_t ptlp_ro : 1; 1407215976Sjmallett uint64_t reserved_6_6 : 1; 1408215976Sjmallett uint64_t ctlp_ro : 1; 1409215976Sjmallett uint64_t inta_map : 2; 1410215976Sjmallett uint64_t intb_map : 2; 1411215976Sjmallett uint64_t intc_map : 2; 1412215976Sjmallett uint64_t intd_map : 2; 1413215976Sjmallett uint64_t waitl_com : 1; 1414215976Sjmallett uint64_t dis_port : 1; 1415215976Sjmallett uint64_t inta : 1; 1416215976Sjmallett uint64_t intb : 1; 1417215976Sjmallett uint64_t intc : 1; 1418215976Sjmallett uint64_t intd : 1; 1419215976Sjmallett uint64_t reserved_22_63 : 42; 1420215976Sjmallett#endif 1421215976Sjmallett } s; 1422232812Sjmallett struct cvmx_sli_ctl_portx_s cn61xx; 1423215976Sjmallett struct cvmx_sli_ctl_portx_s cn63xx; 1424215976Sjmallett struct cvmx_sli_ctl_portx_s cn63xxp1; 1425232812Sjmallett struct cvmx_sli_ctl_portx_s cn66xx; 1426232812Sjmallett struct cvmx_sli_ctl_portx_s cn68xx; 1427232812Sjmallett struct cvmx_sli_ctl_portx_s cn68xxp1; 1428232812Sjmallett struct cvmx_sli_ctl_portx_s cnf71xx; 1429215976Sjmallett}; 1430215976Sjmalletttypedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t; 1431215976Sjmallett 1432215976Sjmallett/** 1433215976Sjmallett * cvmx_sli_ctl_status 1434215976Sjmallett * 1435215976Sjmallett * SLI_CTL_STATUS = SLI Control Status Register 1436215976Sjmallett * 1437215976Sjmallett * Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space. 1438215976Sjmallett * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space) 1439215976Sjmallett * that requires the value of this register to be updated. 1440215976Sjmallett */ 1441232812Sjmallettunion cvmx_sli_ctl_status { 1442215976Sjmallett uint64_t u64; 1443232812Sjmallett struct cvmx_sli_ctl_status_s { 1444232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1445215976Sjmallett uint64_t reserved_20_63 : 44; 1446215976Sjmallett uint64_t p1_ntags : 6; /**< Number of tags available for MAC Port1. 1447215976Sjmallett In RC mode 1 tag is needed for each outbound TLP 1448215976Sjmallett that requires a CPL TLP. In Endpoint mode the 1449215976Sjmallett number of tags required for a TLP request is 1450215976Sjmallett 1 per 64-bytes of CPL data + 1. 1451215976Sjmallett This field should only be written as part of 1452215976Sjmallett reset sequence, before issuing any reads, CFGs, or 1453215976Sjmallett IO transactions from the core(s). */ 1454232812Sjmallett uint64_t p0_ntags : 6; /**< Number of tags available for outbound TLPs to the 1455232812Sjmallett MACS. One tag is needed for each outbound TLP that 1456232812Sjmallett requires a CPL TLP. 1457215976Sjmallett This field should only be written as part of 1458215976Sjmallett reset sequence, before issuing any reads, CFGs, or 1459215976Sjmallett IO transactions from the core(s). */ 1460215976Sjmallett uint64_t chip_rev : 8; /**< The chip revision. */ 1461215976Sjmallett#else 1462215976Sjmallett uint64_t chip_rev : 8; 1463215976Sjmallett uint64_t p0_ntags : 6; 1464215976Sjmallett uint64_t p1_ntags : 6; 1465215976Sjmallett uint64_t reserved_20_63 : 44; 1466215976Sjmallett#endif 1467215976Sjmallett } s; 1468232812Sjmallett struct cvmx_sli_ctl_status_cn61xx { 1469232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1470232812Sjmallett uint64_t reserved_14_63 : 50; 1471232812Sjmallett uint64_t p0_ntags : 6; /**< Number of tags available for outbound TLPs to the 1472232812Sjmallett MACS. One tag is needed for each outbound TLP that 1473232812Sjmallett requires a CPL TLP. 1474232812Sjmallett This field should only be written as part of 1475232812Sjmallett reset sequence, before issuing any reads, CFGs, or 1476232812Sjmallett IO transactions from the core(s). */ 1477232812Sjmallett uint64_t chip_rev : 8; /**< The chip revision. */ 1478232812Sjmallett#else 1479232812Sjmallett uint64_t chip_rev : 8; 1480232812Sjmallett uint64_t p0_ntags : 6; 1481232812Sjmallett uint64_t reserved_14_63 : 50; 1482232812Sjmallett#endif 1483232812Sjmallett } cn61xx; 1484215976Sjmallett struct cvmx_sli_ctl_status_s cn63xx; 1485215976Sjmallett struct cvmx_sli_ctl_status_s cn63xxp1; 1486232812Sjmallett struct cvmx_sli_ctl_status_cn61xx cn66xx; 1487232812Sjmallett struct cvmx_sli_ctl_status_s cn68xx; 1488232812Sjmallett struct cvmx_sli_ctl_status_s cn68xxp1; 1489232812Sjmallett struct cvmx_sli_ctl_status_cn61xx cnf71xx; 1490215976Sjmallett}; 1491215976Sjmalletttypedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t; 1492215976Sjmallett 1493215976Sjmallett/** 1494215976Sjmallett * cvmx_sli_data_out_cnt 1495215976Sjmallett * 1496215976Sjmallett * SLI_DATA_OUT_CNT = SLI DATA OUT COUNT 1497215976Sjmallett * 1498215976Sjmallett * The EXEC data out fifo-count and the data unload counter. 1499215976Sjmallett */ 1500232812Sjmallettunion cvmx_sli_data_out_cnt { 1501215976Sjmallett uint64_t u64; 1502232812Sjmallett struct cvmx_sli_data_out_cnt_s { 1503232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1504215976Sjmallett uint64_t reserved_44_63 : 20; 1505232812Sjmallett uint64_t p1_ucnt : 16; /**< SLI Order-FIFO1 Fifo Unload Count. This counter is 1506215976Sjmallett incremented by '1' every time a word is removed 1507215976Sjmallett from the Data Out FIFO, whose count is shown in 1508232812Sjmallett P1_FCNT. */ 1509232812Sjmallett uint64_t p1_fcnt : 6; /**< SLI Order-FIFO1 Data Out Fifo Count. Number of 1510232812Sjmallett address data words to be sent out the Order-FIFO 1511232812Sjmallett presently buffered in the FIFO. */ 1512232812Sjmallett uint64_t p0_ucnt : 16; /**< SLI Order-FIFO0 Fifo Unload Count. This counter is 1513215976Sjmallett incremented by '1' every time a word is removed 1514215976Sjmallett from the Data Out FIFO, whose count is shown in 1515215976Sjmallett P0_FCNT. */ 1516232812Sjmallett uint64_t p0_fcnt : 6; /**< SLI Order-FIFO0 Data Out Fifo Count. Number of 1517232812Sjmallett address data words to be sent out the Order-FIFO 1518232812Sjmallett presently buffered in the FIFO. */ 1519215976Sjmallett#else 1520215976Sjmallett uint64_t p0_fcnt : 6; 1521215976Sjmallett uint64_t p0_ucnt : 16; 1522215976Sjmallett uint64_t p1_fcnt : 6; 1523215976Sjmallett uint64_t p1_ucnt : 16; 1524215976Sjmallett uint64_t reserved_44_63 : 20; 1525215976Sjmallett#endif 1526215976Sjmallett } s; 1527232812Sjmallett struct cvmx_sli_data_out_cnt_s cn61xx; 1528215976Sjmallett struct cvmx_sli_data_out_cnt_s cn63xx; 1529215976Sjmallett struct cvmx_sli_data_out_cnt_s cn63xxp1; 1530232812Sjmallett struct cvmx_sli_data_out_cnt_s cn66xx; 1531232812Sjmallett struct cvmx_sli_data_out_cnt_s cn68xx; 1532232812Sjmallett struct cvmx_sli_data_out_cnt_s cn68xxp1; 1533232812Sjmallett struct cvmx_sli_data_out_cnt_s cnf71xx; 1534215976Sjmallett}; 1535215976Sjmalletttypedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t; 1536215976Sjmallett 1537215976Sjmallett/** 1538215976Sjmallett * cvmx_sli_dbg_data 1539215976Sjmallett * 1540215976Sjmallett * SLI_DBG_DATA = SLI Debug Data Register 1541215976Sjmallett * 1542215976Sjmallett * Value returned on the debug-data lines from the RSLs 1543215976Sjmallett */ 1544232812Sjmallettunion cvmx_sli_dbg_data { 1545215976Sjmallett uint64_t u64; 1546232812Sjmallett struct cvmx_sli_dbg_data_s { 1547232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1548215976Sjmallett uint64_t reserved_18_63 : 46; 1549215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 1550215976Sjmallett debug select value. */ 1551215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 1552215976Sjmallett#else 1553215976Sjmallett uint64_t data : 17; 1554215976Sjmallett uint64_t dsel_ext : 1; 1555215976Sjmallett uint64_t reserved_18_63 : 46; 1556215976Sjmallett#endif 1557215976Sjmallett } s; 1558232812Sjmallett struct cvmx_sli_dbg_data_s cn61xx; 1559215976Sjmallett struct cvmx_sli_dbg_data_s cn63xx; 1560215976Sjmallett struct cvmx_sli_dbg_data_s cn63xxp1; 1561232812Sjmallett struct cvmx_sli_dbg_data_s cn66xx; 1562232812Sjmallett struct cvmx_sli_dbg_data_s cn68xx; 1563232812Sjmallett struct cvmx_sli_dbg_data_s cn68xxp1; 1564232812Sjmallett struct cvmx_sli_dbg_data_s cnf71xx; 1565215976Sjmallett}; 1566215976Sjmalletttypedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t; 1567215976Sjmallett 1568215976Sjmallett/** 1569215976Sjmallett * cvmx_sli_dbg_select 1570215976Sjmallett * 1571215976Sjmallett * SLI_DBG_SELECT = Debug Select Register 1572215976Sjmallett * 1573215976Sjmallett * Contains the debug select value last written to the RSLs. 1574215976Sjmallett */ 1575232812Sjmallettunion cvmx_sli_dbg_select { 1576215976Sjmallett uint64_t u64; 1577232812Sjmallett struct cvmx_sli_dbg_select_s { 1578232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1579215976Sjmallett uint64_t reserved_33_63 : 31; 1580215976Sjmallett uint64_t adbg_sel : 1; /**< When set '1' the SLI_DBG_DATA[DATA] will only be 1581215976Sjmallett loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'. 1582215976Sjmallett When the debug data comes from an Async-RSL bit 1583215976Sjmallett 16 is used to tell that the data present is valid. */ 1584215976Sjmallett uint64_t dbg_sel : 32; /**< When this register is written the RML will write 1585215976Sjmallett all "F"s to the previous RTL to disable it from 1586215976Sjmallett sending Debug-Data. The RML will then send a write 1587215976Sjmallett to the new RSL with the supplied Debug-Select 1588215976Sjmallett value. Because it takes time for the new Debug 1589215976Sjmallett Select value to take effect and the requested 1590215976Sjmallett Debug-Data to return, time is needed to the new 1591215976Sjmallett Debug-Data to arrive. The inititator of the Debug 1592215976Sjmallett Select should issue a read to a CSR before reading 1593215976Sjmallett the Debug Data (this read could also be to the 1594215976Sjmallett SLI_DBG_DATA but the returned value for the first 1595215976Sjmallett read will return NS data. */ 1596215976Sjmallett#else 1597215976Sjmallett uint64_t dbg_sel : 32; 1598215976Sjmallett uint64_t adbg_sel : 1; 1599215976Sjmallett uint64_t reserved_33_63 : 31; 1600215976Sjmallett#endif 1601215976Sjmallett } s; 1602232812Sjmallett struct cvmx_sli_dbg_select_s cn61xx; 1603215976Sjmallett struct cvmx_sli_dbg_select_s cn63xx; 1604215976Sjmallett struct cvmx_sli_dbg_select_s cn63xxp1; 1605232812Sjmallett struct cvmx_sli_dbg_select_s cn66xx; 1606232812Sjmallett struct cvmx_sli_dbg_select_s cn68xx; 1607232812Sjmallett struct cvmx_sli_dbg_select_s cn68xxp1; 1608232812Sjmallett struct cvmx_sli_dbg_select_s cnf71xx; 1609215976Sjmallett}; 1610215976Sjmalletttypedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t; 1611215976Sjmallett 1612215976Sjmallett/** 1613215976Sjmallett * cvmx_sli_dma#_cnt 1614215976Sjmallett * 1615215976Sjmallett * SLI_DMAx_CNT = SLI DMA Count 1616215976Sjmallett * 1617215976Sjmallett * The DMA Count value. 1618215976Sjmallett */ 1619232812Sjmallettunion cvmx_sli_dmax_cnt { 1620215976Sjmallett uint64_t u64; 1621232812Sjmallett struct cvmx_sli_dmax_cnt_s { 1622232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1623215976Sjmallett uint64_t reserved_32_63 : 32; 1624215976Sjmallett uint64_t cnt : 32; /**< The DMA counter. 1625215976Sjmallett Writing this field will cause the written value 1626215976Sjmallett to be subtracted from DMA. HW will optionally 1627215976Sjmallett increment this field after it completes an 1628215976Sjmallett OUTBOUND or EXTERNAL-ONLY DMA instruction. These 1629215976Sjmallett increments may cause interrupts. Refer to 1630215976Sjmallett SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */ 1631215976Sjmallett#else 1632215976Sjmallett uint64_t cnt : 32; 1633215976Sjmallett uint64_t reserved_32_63 : 32; 1634215976Sjmallett#endif 1635215976Sjmallett } s; 1636232812Sjmallett struct cvmx_sli_dmax_cnt_s cn61xx; 1637215976Sjmallett struct cvmx_sli_dmax_cnt_s cn63xx; 1638215976Sjmallett struct cvmx_sli_dmax_cnt_s cn63xxp1; 1639232812Sjmallett struct cvmx_sli_dmax_cnt_s cn66xx; 1640232812Sjmallett struct cvmx_sli_dmax_cnt_s cn68xx; 1641232812Sjmallett struct cvmx_sli_dmax_cnt_s cn68xxp1; 1642232812Sjmallett struct cvmx_sli_dmax_cnt_s cnf71xx; 1643215976Sjmallett}; 1644215976Sjmalletttypedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t; 1645215976Sjmallett 1646215976Sjmallett/** 1647215976Sjmallett * cvmx_sli_dma#_int_level 1648215976Sjmallett * 1649215976Sjmallett * SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level 1650215976Sjmallett * 1651215976Sjmallett * Thresholds for DMA count and timer interrupts. 1652215976Sjmallett */ 1653232812Sjmallettunion cvmx_sli_dmax_int_level { 1654215976Sjmallett uint64_t u64; 1655232812Sjmallett struct cvmx_sli_dmax_int_level_s { 1656232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1657215976Sjmallett uint64_t time : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds 1658215976Sjmallett this value, SLI_INT_SUM[DTIME<x>] is set. 1659215976Sjmallett The SLI_DMAx_TIM[TIM] timer increments every SLI 1660215976Sjmallett clock whenever SLI_DMAx_CNT[CNT]!=0, and is 1661215976Sjmallett cleared when SLI_INT_SUM[DTIME<x>] is written with 1662215976Sjmallett one. */ 1663215976Sjmallett uint64_t cnt : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value, 1664215976Sjmallett SLI_INT_SUM[DCNT<x>] is set. */ 1665215976Sjmallett#else 1666215976Sjmallett uint64_t cnt : 32; 1667215976Sjmallett uint64_t time : 32; 1668215976Sjmallett#endif 1669215976Sjmallett } s; 1670232812Sjmallett struct cvmx_sli_dmax_int_level_s cn61xx; 1671215976Sjmallett struct cvmx_sli_dmax_int_level_s cn63xx; 1672215976Sjmallett struct cvmx_sli_dmax_int_level_s cn63xxp1; 1673232812Sjmallett struct cvmx_sli_dmax_int_level_s cn66xx; 1674232812Sjmallett struct cvmx_sli_dmax_int_level_s cn68xx; 1675232812Sjmallett struct cvmx_sli_dmax_int_level_s cn68xxp1; 1676232812Sjmallett struct cvmx_sli_dmax_int_level_s cnf71xx; 1677215976Sjmallett}; 1678215976Sjmalletttypedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t; 1679215976Sjmallett 1680215976Sjmallett/** 1681215976Sjmallett * cvmx_sli_dma#_tim 1682215976Sjmallett * 1683215976Sjmallett * SLI_DMAx_TIM = SLI DMA Timer 1684215976Sjmallett * 1685215976Sjmallett * The DMA Timer value. 1686215976Sjmallett */ 1687232812Sjmallettunion cvmx_sli_dmax_tim { 1688215976Sjmallett uint64_t u64; 1689232812Sjmallett struct cvmx_sli_dmax_tim_s { 1690232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1691215976Sjmallett uint64_t reserved_32_63 : 32; 1692215976Sjmallett uint64_t tim : 32; /**< The DMA timer value. 1693215976Sjmallett The timer will increment when SLI_DMAx_CNT[CNT]!=0 1694215976Sjmallett and will clear when SLI_DMAx_CNT[CNT]==0 */ 1695215976Sjmallett#else 1696215976Sjmallett uint64_t tim : 32; 1697215976Sjmallett uint64_t reserved_32_63 : 32; 1698215976Sjmallett#endif 1699215976Sjmallett } s; 1700232812Sjmallett struct cvmx_sli_dmax_tim_s cn61xx; 1701215976Sjmallett struct cvmx_sli_dmax_tim_s cn63xx; 1702215976Sjmallett struct cvmx_sli_dmax_tim_s cn63xxp1; 1703232812Sjmallett struct cvmx_sli_dmax_tim_s cn66xx; 1704232812Sjmallett struct cvmx_sli_dmax_tim_s cn68xx; 1705232812Sjmallett struct cvmx_sli_dmax_tim_s cn68xxp1; 1706232812Sjmallett struct cvmx_sli_dmax_tim_s cnf71xx; 1707215976Sjmallett}; 1708215976Sjmalletttypedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t; 1709215976Sjmallett 1710215976Sjmallett/** 1711215976Sjmallett * cvmx_sli_int_enb_ciu 1712215976Sjmallett * 1713215976Sjmallett * SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register 1714215976Sjmallett * 1715215976Sjmallett * Used to enable the various interrupting conditions of SLI 1716215976Sjmallett */ 1717232812Sjmallettunion cvmx_sli_int_enb_ciu { 1718215976Sjmallett uint64_t u64; 1719232812Sjmallett struct cvmx_sli_int_enb_ciu_s { 1720232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1721232812Sjmallett uint64_t reserved_62_63 : 2; 1722232812Sjmallett uint64_t pipe_err : 1; /**< Illegal packet csr address. */ 1723232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 1724232812Sjmallett uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */ 1725232812Sjmallett uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */ 1726232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 1727232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 1728232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 1729232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 1730232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 1731232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 1732232812Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 1733232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 1734232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 1735232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 1736232812Sjmallett uint64_t reserved_38_47 : 10; 1737232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 1738232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 1739232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 1740232812Sjmallett uint64_t reserved_28_31 : 4; 1741232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 1742232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 1743232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 1744232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 1745232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 1746232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 1747232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 1748232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 1749232812Sjmallett uint64_t reserved_18_19 : 2; 1750232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 1751232812Sjmallett interrupt on the RSL. 1752232812Sjmallett THIS SHOULD NEVER BE SET */ 1753232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 1754232812Sjmallett interrupt on the RSL. 1755232812Sjmallett THIS SHOULD NEVER BE SET */ 1756232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 1757232812Sjmallett interrupt on the RSL. */ 1758232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 1759232812Sjmallett interrupt on the RSL. */ 1760232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 1761232812Sjmallett interrupt on the RSL. */ 1762232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 1763232812Sjmallett interrupt on the RSL. */ 1764232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 1765232812Sjmallett interrupt on the RSL. */ 1766232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 1767232812Sjmallett interrupt on the RSL. */ 1768232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 1769232812Sjmallett interrupt on the RSL. */ 1770232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 1771232812Sjmallett interrupt on the RSL. */ 1772232812Sjmallett uint64_t reserved_6_7 : 2; 1773232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 1774232812Sjmallett interrupt on the RSL. */ 1775232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 1776232812Sjmallett interrupt on the RSL. */ 1777232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 1778232812Sjmallett interrupt on the RSL. */ 1779232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 1780232812Sjmallett interrupt on the RSL. */ 1781232812Sjmallett uint64_t reserved_1_1 : 1; 1782232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 1783232812Sjmallett interrupt on the RSL. */ 1784232812Sjmallett#else 1785232812Sjmallett uint64_t rml_to : 1; 1786232812Sjmallett uint64_t reserved_1_1 : 1; 1787232812Sjmallett uint64_t bar0_to : 1; 1788232812Sjmallett uint64_t iob2big : 1; 1789232812Sjmallett uint64_t pcnt : 1; 1790232812Sjmallett uint64_t ptime : 1; 1791232812Sjmallett uint64_t reserved_6_7 : 2; 1792232812Sjmallett uint64_t m0_up_b0 : 1; 1793232812Sjmallett uint64_t m0_up_wi : 1; 1794232812Sjmallett uint64_t m0_un_b0 : 1; 1795232812Sjmallett uint64_t m0_un_wi : 1; 1796232812Sjmallett uint64_t m1_up_b0 : 1; 1797232812Sjmallett uint64_t m1_up_wi : 1; 1798232812Sjmallett uint64_t m1_un_b0 : 1; 1799232812Sjmallett uint64_t m1_un_wi : 1; 1800232812Sjmallett uint64_t mio_int0 : 1; 1801232812Sjmallett uint64_t mio_int1 : 1; 1802232812Sjmallett uint64_t reserved_18_19 : 2; 1803232812Sjmallett uint64_t m2_up_b0 : 1; 1804232812Sjmallett uint64_t m2_up_wi : 1; 1805232812Sjmallett uint64_t m2_un_b0 : 1; 1806232812Sjmallett uint64_t m2_un_wi : 1; 1807232812Sjmallett uint64_t m3_up_b0 : 1; 1808232812Sjmallett uint64_t m3_up_wi : 1; 1809232812Sjmallett uint64_t m3_un_b0 : 1; 1810232812Sjmallett uint64_t m3_un_wi : 1; 1811232812Sjmallett uint64_t reserved_28_31 : 4; 1812232812Sjmallett uint64_t dmafi : 2; 1813232812Sjmallett uint64_t dcnt : 2; 1814232812Sjmallett uint64_t dtime : 2; 1815232812Sjmallett uint64_t reserved_38_47 : 10; 1816232812Sjmallett uint64_t pidbof : 1; 1817232812Sjmallett uint64_t psldbof : 1; 1818232812Sjmallett uint64_t pout_err : 1; 1819232812Sjmallett uint64_t pin_bp : 1; 1820232812Sjmallett uint64_t pgl_err : 1; 1821232812Sjmallett uint64_t pdi_err : 1; 1822232812Sjmallett uint64_t pop_err : 1; 1823232812Sjmallett uint64_t pins_err : 1; 1824232812Sjmallett uint64_t sprt0_err : 1; 1825232812Sjmallett uint64_t sprt1_err : 1; 1826232812Sjmallett uint64_t sprt2_err : 1; 1827232812Sjmallett uint64_t sprt3_err : 1; 1828232812Sjmallett uint64_t ill_pad : 1; 1829232812Sjmallett uint64_t pipe_err : 1; 1830232812Sjmallett uint64_t reserved_62_63 : 2; 1831232812Sjmallett#endif 1832232812Sjmallett } s; 1833232812Sjmallett struct cvmx_sli_int_enb_ciu_cn61xx { 1834232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1835215976Sjmallett uint64_t reserved_61_63 : 3; 1836215976Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 1837232812Sjmallett uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */ 1838232812Sjmallett uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */ 1839232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 1840232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 1841232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 1842232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 1843232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 1844232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 1845232812Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 1846232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 1847232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 1848232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 1849232812Sjmallett uint64_t reserved_38_47 : 10; 1850232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 1851232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 1852232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 1853232812Sjmallett uint64_t reserved_28_31 : 4; 1854232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 1855232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 1856232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 1857232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 1858232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 1859232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 1860232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 1861232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 1862232812Sjmallett uint64_t reserved_18_19 : 2; 1863232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 1864232812Sjmallett interrupt on the RSL. 1865232812Sjmallett THIS SHOULD NEVER BE SET */ 1866232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 1867232812Sjmallett interrupt on the RSL. 1868232812Sjmallett THIS SHOULD NEVER BE SET */ 1869232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 1870232812Sjmallett interrupt on the RSL. */ 1871232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 1872232812Sjmallett interrupt on the RSL. */ 1873232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 1874232812Sjmallett interrupt on the RSL. */ 1875232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 1876232812Sjmallett interrupt on the RSL. */ 1877232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 1878232812Sjmallett interrupt on the RSL. */ 1879232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 1880232812Sjmallett interrupt on the RSL. */ 1881232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 1882232812Sjmallett interrupt on the RSL. */ 1883232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 1884232812Sjmallett interrupt on the RSL. */ 1885232812Sjmallett uint64_t reserved_6_7 : 2; 1886232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 1887232812Sjmallett interrupt on the RSL. */ 1888232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 1889232812Sjmallett interrupt on the RSL. */ 1890232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 1891232812Sjmallett interrupt on the RSL. */ 1892232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 1893232812Sjmallett interrupt on the RSL. */ 1894232812Sjmallett uint64_t reserved_1_1 : 1; 1895232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 1896232812Sjmallett interrupt on the RSL. */ 1897232812Sjmallett#else 1898232812Sjmallett uint64_t rml_to : 1; 1899232812Sjmallett uint64_t reserved_1_1 : 1; 1900232812Sjmallett uint64_t bar0_to : 1; 1901232812Sjmallett uint64_t iob2big : 1; 1902232812Sjmallett uint64_t pcnt : 1; 1903232812Sjmallett uint64_t ptime : 1; 1904232812Sjmallett uint64_t reserved_6_7 : 2; 1905232812Sjmallett uint64_t m0_up_b0 : 1; 1906232812Sjmallett uint64_t m0_up_wi : 1; 1907232812Sjmallett uint64_t m0_un_b0 : 1; 1908232812Sjmallett uint64_t m0_un_wi : 1; 1909232812Sjmallett uint64_t m1_up_b0 : 1; 1910232812Sjmallett uint64_t m1_up_wi : 1; 1911232812Sjmallett uint64_t m1_un_b0 : 1; 1912232812Sjmallett uint64_t m1_un_wi : 1; 1913232812Sjmallett uint64_t mio_int0 : 1; 1914232812Sjmallett uint64_t mio_int1 : 1; 1915232812Sjmallett uint64_t reserved_18_19 : 2; 1916232812Sjmallett uint64_t m2_up_b0 : 1; 1917232812Sjmallett uint64_t m2_up_wi : 1; 1918232812Sjmallett uint64_t m2_un_b0 : 1; 1919232812Sjmallett uint64_t m2_un_wi : 1; 1920232812Sjmallett uint64_t m3_up_b0 : 1; 1921232812Sjmallett uint64_t m3_up_wi : 1; 1922232812Sjmallett uint64_t m3_un_b0 : 1; 1923232812Sjmallett uint64_t m3_un_wi : 1; 1924232812Sjmallett uint64_t reserved_28_31 : 4; 1925232812Sjmallett uint64_t dmafi : 2; 1926232812Sjmallett uint64_t dcnt : 2; 1927232812Sjmallett uint64_t dtime : 2; 1928232812Sjmallett uint64_t reserved_38_47 : 10; 1929232812Sjmallett uint64_t pidbof : 1; 1930232812Sjmallett uint64_t psldbof : 1; 1931232812Sjmallett uint64_t pout_err : 1; 1932232812Sjmallett uint64_t pin_bp : 1; 1933232812Sjmallett uint64_t pgl_err : 1; 1934232812Sjmallett uint64_t pdi_err : 1; 1935232812Sjmallett uint64_t pop_err : 1; 1936232812Sjmallett uint64_t pins_err : 1; 1937232812Sjmallett uint64_t sprt0_err : 1; 1938232812Sjmallett uint64_t sprt1_err : 1; 1939232812Sjmallett uint64_t sprt2_err : 1; 1940232812Sjmallett uint64_t sprt3_err : 1; 1941232812Sjmallett uint64_t ill_pad : 1; 1942232812Sjmallett uint64_t reserved_61_63 : 3; 1943232812Sjmallett#endif 1944232812Sjmallett } cn61xx; 1945232812Sjmallett struct cvmx_sli_int_enb_ciu_cn63xx { 1946232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1947232812Sjmallett uint64_t reserved_61_63 : 3; 1948232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 1949215976Sjmallett uint64_t reserved_58_59 : 2; 1950215976Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 1951215976Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 1952215976Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 1953215976Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 1954215976Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 1955215976Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 1956215976Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 1957215976Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 1958215976Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 1959215976Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 1960215976Sjmallett uint64_t reserved_38_47 : 10; 1961215976Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 1962215976Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 1963215976Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 1964215976Sjmallett uint64_t reserved_18_31 : 14; 1965215976Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 1966215976Sjmallett interrupt on the RSL. 1967215976Sjmallett THIS SHOULD NEVER BE SET */ 1968215976Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 1969215976Sjmallett interrupt on the RSL. 1970215976Sjmallett THIS SHOULD NEVER BE SET */ 1971215976Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 1972215976Sjmallett interrupt on the RSL. */ 1973215976Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 1974215976Sjmallett interrupt on the RSL. */ 1975215976Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 1976215976Sjmallett interrupt on the RSL. */ 1977215976Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 1978215976Sjmallett interrupt on the RSL. */ 1979215976Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 1980215976Sjmallett interrupt on the RSL. */ 1981215976Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 1982215976Sjmallett interrupt on the RSL. */ 1983215976Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 1984215976Sjmallett interrupt on the RSL. */ 1985215976Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 1986215976Sjmallett interrupt on the RSL. */ 1987215976Sjmallett uint64_t reserved_6_7 : 2; 1988215976Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 1989215976Sjmallett interrupt on the RSL. */ 1990215976Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 1991215976Sjmallett interrupt on the RSL. */ 1992215976Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 1993215976Sjmallett interrupt on the RSL. */ 1994215976Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 1995215976Sjmallett interrupt on the RSL. */ 1996215976Sjmallett uint64_t reserved_1_1 : 1; 1997215976Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 1998215976Sjmallett interrupt on the RSL. */ 1999215976Sjmallett#else 2000215976Sjmallett uint64_t rml_to : 1; 2001215976Sjmallett uint64_t reserved_1_1 : 1; 2002215976Sjmallett uint64_t bar0_to : 1; 2003215976Sjmallett uint64_t iob2big : 1; 2004215976Sjmallett uint64_t pcnt : 1; 2005215976Sjmallett uint64_t ptime : 1; 2006215976Sjmallett uint64_t reserved_6_7 : 2; 2007215976Sjmallett uint64_t m0_up_b0 : 1; 2008215976Sjmallett uint64_t m0_up_wi : 1; 2009215976Sjmallett uint64_t m0_un_b0 : 1; 2010215976Sjmallett uint64_t m0_un_wi : 1; 2011215976Sjmallett uint64_t m1_up_b0 : 1; 2012215976Sjmallett uint64_t m1_up_wi : 1; 2013215976Sjmallett uint64_t m1_un_b0 : 1; 2014215976Sjmallett uint64_t m1_un_wi : 1; 2015215976Sjmallett uint64_t mio_int0 : 1; 2016215976Sjmallett uint64_t mio_int1 : 1; 2017215976Sjmallett uint64_t reserved_18_31 : 14; 2018215976Sjmallett uint64_t dmafi : 2; 2019215976Sjmallett uint64_t dcnt : 2; 2020215976Sjmallett uint64_t dtime : 2; 2021215976Sjmallett uint64_t reserved_38_47 : 10; 2022215976Sjmallett uint64_t pidbof : 1; 2023215976Sjmallett uint64_t psldbof : 1; 2024215976Sjmallett uint64_t pout_err : 1; 2025215976Sjmallett uint64_t pin_bp : 1; 2026215976Sjmallett uint64_t pgl_err : 1; 2027215976Sjmallett uint64_t pdi_err : 1; 2028215976Sjmallett uint64_t pop_err : 1; 2029215976Sjmallett uint64_t pins_err : 1; 2030215976Sjmallett uint64_t sprt0_err : 1; 2031215976Sjmallett uint64_t sprt1_err : 1; 2032215976Sjmallett uint64_t reserved_58_59 : 2; 2033215976Sjmallett uint64_t ill_pad : 1; 2034215976Sjmallett uint64_t reserved_61_63 : 3; 2035215976Sjmallett#endif 2036232812Sjmallett } cn63xx; 2037232812Sjmallett struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; 2038232812Sjmallett struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; 2039232812Sjmallett struct cvmx_sli_int_enb_ciu_cn68xx { 2040232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2041232812Sjmallett uint64_t reserved_62_63 : 2; 2042232812Sjmallett uint64_t pipe_err : 1; /**< Illegal packet csr address. */ 2043232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 2044232812Sjmallett uint64_t reserved_58_59 : 2; 2045232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 2046232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 2047232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 2048232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 2049232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 2050232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 2051232812Sjmallett uint64_t reserved_51_51 : 1; 2052232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 2053232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 2054232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 2055232812Sjmallett uint64_t reserved_38_47 : 10; 2056232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 2057232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 2058232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 2059232812Sjmallett uint64_t reserved_18_31 : 14; 2060232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 2061232812Sjmallett interrupt on the RSL. 2062232812Sjmallett THIS SHOULD NEVER BE SET */ 2063232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 2064232812Sjmallett interrupt on the RSL. 2065232812Sjmallett THIS SHOULD NEVER BE SET */ 2066232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 2067232812Sjmallett interrupt on the RSL. */ 2068232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 2069232812Sjmallett interrupt on the RSL. */ 2070232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 2071232812Sjmallett interrupt on the RSL. */ 2072232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 2073232812Sjmallett interrupt on the RSL. */ 2074232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 2075232812Sjmallett interrupt on the RSL. */ 2076232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 2077232812Sjmallett interrupt on the RSL. */ 2078232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 2079232812Sjmallett interrupt on the RSL. */ 2080232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 2081232812Sjmallett interrupt on the RSL. */ 2082232812Sjmallett uint64_t reserved_6_7 : 2; 2083232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 2084232812Sjmallett interrupt on the RSL. */ 2085232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 2086232812Sjmallett interrupt on the RSL. */ 2087232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 2088232812Sjmallett interrupt on the RSL. */ 2089232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 2090232812Sjmallett interrupt on the RSL. */ 2091232812Sjmallett uint64_t reserved_1_1 : 1; 2092232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 2093232812Sjmallett interrupt on the RSL. */ 2094232812Sjmallett#else 2095232812Sjmallett uint64_t rml_to : 1; 2096232812Sjmallett uint64_t reserved_1_1 : 1; 2097232812Sjmallett uint64_t bar0_to : 1; 2098232812Sjmallett uint64_t iob2big : 1; 2099232812Sjmallett uint64_t pcnt : 1; 2100232812Sjmallett uint64_t ptime : 1; 2101232812Sjmallett uint64_t reserved_6_7 : 2; 2102232812Sjmallett uint64_t m0_up_b0 : 1; 2103232812Sjmallett uint64_t m0_up_wi : 1; 2104232812Sjmallett uint64_t m0_un_b0 : 1; 2105232812Sjmallett uint64_t m0_un_wi : 1; 2106232812Sjmallett uint64_t m1_up_b0 : 1; 2107232812Sjmallett uint64_t m1_up_wi : 1; 2108232812Sjmallett uint64_t m1_un_b0 : 1; 2109232812Sjmallett uint64_t m1_un_wi : 1; 2110232812Sjmallett uint64_t mio_int0 : 1; 2111232812Sjmallett uint64_t mio_int1 : 1; 2112232812Sjmallett uint64_t reserved_18_31 : 14; 2113232812Sjmallett uint64_t dmafi : 2; 2114232812Sjmallett uint64_t dcnt : 2; 2115232812Sjmallett uint64_t dtime : 2; 2116232812Sjmallett uint64_t reserved_38_47 : 10; 2117232812Sjmallett uint64_t pidbof : 1; 2118232812Sjmallett uint64_t psldbof : 1; 2119232812Sjmallett uint64_t pout_err : 1; 2120232812Sjmallett uint64_t reserved_51_51 : 1; 2121232812Sjmallett uint64_t pgl_err : 1; 2122232812Sjmallett uint64_t pdi_err : 1; 2123232812Sjmallett uint64_t pop_err : 1; 2124232812Sjmallett uint64_t pins_err : 1; 2125232812Sjmallett uint64_t sprt0_err : 1; 2126232812Sjmallett uint64_t sprt1_err : 1; 2127232812Sjmallett uint64_t reserved_58_59 : 2; 2128232812Sjmallett uint64_t ill_pad : 1; 2129232812Sjmallett uint64_t pipe_err : 1; 2130232812Sjmallett uint64_t reserved_62_63 : 2; 2131232812Sjmallett#endif 2132232812Sjmallett } cn68xx; 2133232812Sjmallett struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; 2134232812Sjmallett struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; 2135215976Sjmallett}; 2136215976Sjmalletttypedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t; 2137215976Sjmallett 2138215976Sjmallett/** 2139215976Sjmallett * cvmx_sli_int_enb_port# 2140215976Sjmallett * 2141215976Sjmallett * SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port 2142215976Sjmallett * 2143215976Sjmallett * Used to allow the generation of interrupts (MSI/INTA) to the PORT X 2144215976Sjmallett * 2145215976Sjmallett * Notes: 2146215976Sjmallett * This CSR is not used when the corresponding MAC is sRIO. 2147215976Sjmallett * 2148215976Sjmallett */ 2149232812Sjmallettunion cvmx_sli_int_enb_portx { 2150215976Sjmallett uint64_t u64; 2151232812Sjmallett struct cvmx_sli_int_enb_portx_s { 2152232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2153232812Sjmallett uint64_t reserved_62_63 : 2; 2154232812Sjmallett uint64_t pipe_err : 1; /**< Out of range PIPE value. */ 2155232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 2156232812Sjmallett uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */ 2157232812Sjmallett uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */ 2158232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 2159232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 2160232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 2161232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 2162232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 2163232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 2164232812Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 2165232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 2166232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 2167232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 2168232812Sjmallett uint64_t reserved_38_47 : 10; 2169232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 2170232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 2171232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 2172232812Sjmallett uint64_t reserved_28_31 : 4; 2173232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 2174232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 2175232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 2176232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 2177232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 2178232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 2179232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 2180232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 2181232812Sjmallett uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an 2182232812Sjmallett interrupt to the PCIE-Port1 for MSI/inta. 2183232812Sjmallett The valuse of this bit has NO effect on PCIE Port0. 2184232812Sjmallett SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */ 2185232812Sjmallett uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an 2186232812Sjmallett interrupt to the PCIE-Port0 for MSI/inta. 2187232812Sjmallett The valus of this bit has NO effect on PCIE Port1. 2188232812Sjmallett SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */ 2189232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 2190232812Sjmallett interrupt to the PCIE core for MSI/inta. 2191232812Sjmallett SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */ 2192232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 2193232812Sjmallett interrupt to the PCIE core for MSI/inta. 2194232812Sjmallett SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */ 2195232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 2196232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2197232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 2198232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2199232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 2200232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2201232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 2202232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2203232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 2204232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2205232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 2206232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2207232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 2208232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2209232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 2210232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2211232812Sjmallett uint64_t reserved_6_7 : 2; 2212232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 2213232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2214232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 2215232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2216232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 2217232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2218232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 2219232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2220232812Sjmallett uint64_t reserved_1_1 : 1; 2221232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 2222232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2223232812Sjmallett#else 2224232812Sjmallett uint64_t rml_to : 1; 2225232812Sjmallett uint64_t reserved_1_1 : 1; 2226232812Sjmallett uint64_t bar0_to : 1; 2227232812Sjmallett uint64_t iob2big : 1; 2228232812Sjmallett uint64_t pcnt : 1; 2229232812Sjmallett uint64_t ptime : 1; 2230232812Sjmallett uint64_t reserved_6_7 : 2; 2231232812Sjmallett uint64_t m0_up_b0 : 1; 2232232812Sjmallett uint64_t m0_up_wi : 1; 2233232812Sjmallett uint64_t m0_un_b0 : 1; 2234232812Sjmallett uint64_t m0_un_wi : 1; 2235232812Sjmallett uint64_t m1_up_b0 : 1; 2236232812Sjmallett uint64_t m1_up_wi : 1; 2237232812Sjmallett uint64_t m1_un_b0 : 1; 2238232812Sjmallett uint64_t m1_un_wi : 1; 2239232812Sjmallett uint64_t mio_int0 : 1; 2240232812Sjmallett uint64_t mio_int1 : 1; 2241232812Sjmallett uint64_t mac0_int : 1; 2242232812Sjmallett uint64_t mac1_int : 1; 2243232812Sjmallett uint64_t m2_up_b0 : 1; 2244232812Sjmallett uint64_t m2_up_wi : 1; 2245232812Sjmallett uint64_t m2_un_b0 : 1; 2246232812Sjmallett uint64_t m2_un_wi : 1; 2247232812Sjmallett uint64_t m3_up_b0 : 1; 2248232812Sjmallett uint64_t m3_up_wi : 1; 2249232812Sjmallett uint64_t m3_un_b0 : 1; 2250232812Sjmallett uint64_t m3_un_wi : 1; 2251232812Sjmallett uint64_t reserved_28_31 : 4; 2252232812Sjmallett uint64_t dmafi : 2; 2253232812Sjmallett uint64_t dcnt : 2; 2254232812Sjmallett uint64_t dtime : 2; 2255232812Sjmallett uint64_t reserved_38_47 : 10; 2256232812Sjmallett uint64_t pidbof : 1; 2257232812Sjmallett uint64_t psldbof : 1; 2258232812Sjmallett uint64_t pout_err : 1; 2259232812Sjmallett uint64_t pin_bp : 1; 2260232812Sjmallett uint64_t pgl_err : 1; 2261232812Sjmallett uint64_t pdi_err : 1; 2262232812Sjmallett uint64_t pop_err : 1; 2263232812Sjmallett uint64_t pins_err : 1; 2264232812Sjmallett uint64_t sprt0_err : 1; 2265232812Sjmallett uint64_t sprt1_err : 1; 2266232812Sjmallett uint64_t sprt2_err : 1; 2267232812Sjmallett uint64_t sprt3_err : 1; 2268232812Sjmallett uint64_t ill_pad : 1; 2269232812Sjmallett uint64_t pipe_err : 1; 2270232812Sjmallett uint64_t reserved_62_63 : 2; 2271232812Sjmallett#endif 2272232812Sjmallett } s; 2273232812Sjmallett struct cvmx_sli_int_enb_portx_cn61xx { 2274232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2275215976Sjmallett uint64_t reserved_61_63 : 3; 2276215976Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 2277232812Sjmallett uint64_t sprt3_err : 1; /**< Error Response received on SLI port 3. */ 2278232812Sjmallett uint64_t sprt2_err : 1; /**< Error Response received on SLI port 2. */ 2279232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 2280232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 2281232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 2282232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 2283232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 2284232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 2285232812Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 2286232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 2287232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 2288232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 2289232812Sjmallett uint64_t reserved_38_47 : 10; 2290232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 2291232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 2292232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 2293232812Sjmallett uint64_t reserved_28_31 : 4; 2294232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 2295232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 2296232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 2297232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 2298232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 2299232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 2300232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 2301232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 2302232812Sjmallett uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an 2303232812Sjmallett interrupt to the PCIE-Port1 for MSI/inta. 2304232812Sjmallett The valuse of this bit has NO effect on PCIE Port0. 2305232812Sjmallett SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */ 2306232812Sjmallett uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an 2307232812Sjmallett interrupt to the PCIE-Port0 for MSI/inta. 2308232812Sjmallett The valus of this bit has NO effect on PCIE Port1. 2309232812Sjmallett SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */ 2310232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 2311232812Sjmallett interrupt to the PCIE core for MSI/inta. 2312232812Sjmallett SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */ 2313232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 2314232812Sjmallett interrupt to the PCIE core for MSI/inta. 2315232812Sjmallett SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */ 2316232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 2317232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2318232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 2319232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2320232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 2321232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2322232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 2323232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2324232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 2325232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2326232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 2327232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2328232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 2329232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2330232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 2331232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2332232812Sjmallett uint64_t reserved_6_7 : 2; 2333232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 2334232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2335232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 2336232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2337232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 2338232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2339232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 2340232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2341232812Sjmallett uint64_t reserved_1_1 : 1; 2342232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 2343232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2344232812Sjmallett#else 2345232812Sjmallett uint64_t rml_to : 1; 2346232812Sjmallett uint64_t reserved_1_1 : 1; 2347232812Sjmallett uint64_t bar0_to : 1; 2348232812Sjmallett uint64_t iob2big : 1; 2349232812Sjmallett uint64_t pcnt : 1; 2350232812Sjmallett uint64_t ptime : 1; 2351232812Sjmallett uint64_t reserved_6_7 : 2; 2352232812Sjmallett uint64_t m0_up_b0 : 1; 2353232812Sjmallett uint64_t m0_up_wi : 1; 2354232812Sjmallett uint64_t m0_un_b0 : 1; 2355232812Sjmallett uint64_t m0_un_wi : 1; 2356232812Sjmallett uint64_t m1_up_b0 : 1; 2357232812Sjmallett uint64_t m1_up_wi : 1; 2358232812Sjmallett uint64_t m1_un_b0 : 1; 2359232812Sjmallett uint64_t m1_un_wi : 1; 2360232812Sjmallett uint64_t mio_int0 : 1; 2361232812Sjmallett uint64_t mio_int1 : 1; 2362232812Sjmallett uint64_t mac0_int : 1; 2363232812Sjmallett uint64_t mac1_int : 1; 2364232812Sjmallett uint64_t m2_up_b0 : 1; 2365232812Sjmallett uint64_t m2_up_wi : 1; 2366232812Sjmallett uint64_t m2_un_b0 : 1; 2367232812Sjmallett uint64_t m2_un_wi : 1; 2368232812Sjmallett uint64_t m3_up_b0 : 1; 2369232812Sjmallett uint64_t m3_up_wi : 1; 2370232812Sjmallett uint64_t m3_un_b0 : 1; 2371232812Sjmallett uint64_t m3_un_wi : 1; 2372232812Sjmallett uint64_t reserved_28_31 : 4; 2373232812Sjmallett uint64_t dmafi : 2; 2374232812Sjmallett uint64_t dcnt : 2; 2375232812Sjmallett uint64_t dtime : 2; 2376232812Sjmallett uint64_t reserved_38_47 : 10; 2377232812Sjmallett uint64_t pidbof : 1; 2378232812Sjmallett uint64_t psldbof : 1; 2379232812Sjmallett uint64_t pout_err : 1; 2380232812Sjmallett uint64_t pin_bp : 1; 2381232812Sjmallett uint64_t pgl_err : 1; 2382232812Sjmallett uint64_t pdi_err : 1; 2383232812Sjmallett uint64_t pop_err : 1; 2384232812Sjmallett uint64_t pins_err : 1; 2385232812Sjmallett uint64_t sprt0_err : 1; 2386232812Sjmallett uint64_t sprt1_err : 1; 2387232812Sjmallett uint64_t sprt2_err : 1; 2388232812Sjmallett uint64_t sprt3_err : 1; 2389232812Sjmallett uint64_t ill_pad : 1; 2390232812Sjmallett uint64_t reserved_61_63 : 3; 2391232812Sjmallett#endif 2392232812Sjmallett } cn61xx; 2393232812Sjmallett struct cvmx_sli_int_enb_portx_cn63xx { 2394232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2395232812Sjmallett uint64_t reserved_61_63 : 3; 2396232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 2397215976Sjmallett uint64_t reserved_58_59 : 2; 2398215976Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 2399215976Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 2400215976Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 2401215976Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 2402215976Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 2403215976Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 2404215976Sjmallett uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 2405215976Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 2406215976Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 2407215976Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 2408215976Sjmallett uint64_t reserved_38_47 : 10; 2409215976Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 2410215976Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 2411215976Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 2412215976Sjmallett uint64_t reserved_20_31 : 12; 2413215976Sjmallett uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an 2414215976Sjmallett interrupt to the PCIE-Port1 for MSI/inta. 2415215976Sjmallett The valuse of this bit has NO effect on PCIE Port0. 2416215976Sjmallett SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */ 2417215976Sjmallett uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an 2418215976Sjmallett interrupt to the PCIE-Port0 for MSI/inta. 2419215976Sjmallett The valus of this bit has NO effect on PCIE Port1. 2420215976Sjmallett SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */ 2421215976Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 2422215976Sjmallett interrupt to the PCIE core for MSI/inta. 2423215976Sjmallett SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */ 2424215976Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 2425215976Sjmallett interrupt to the PCIE core for MSI/inta. 2426215976Sjmallett SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */ 2427215976Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 2428215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2429215976Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 2430215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2431215976Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 2432215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2433215976Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 2434215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2435215976Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 2436215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2437215976Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 2438215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2439215976Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 2440215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2441215976Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 2442215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2443215976Sjmallett uint64_t reserved_6_7 : 2; 2444215976Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 2445215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2446215976Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 2447215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2448215976Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 2449215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2450215976Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 2451215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2452215976Sjmallett uint64_t reserved_1_1 : 1; 2453215976Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 2454215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 2455215976Sjmallett#else 2456215976Sjmallett uint64_t rml_to : 1; 2457215976Sjmallett uint64_t reserved_1_1 : 1; 2458215976Sjmallett uint64_t bar0_to : 1; 2459215976Sjmallett uint64_t iob2big : 1; 2460215976Sjmallett uint64_t pcnt : 1; 2461215976Sjmallett uint64_t ptime : 1; 2462215976Sjmallett uint64_t reserved_6_7 : 2; 2463215976Sjmallett uint64_t m0_up_b0 : 1; 2464215976Sjmallett uint64_t m0_up_wi : 1; 2465215976Sjmallett uint64_t m0_un_b0 : 1; 2466215976Sjmallett uint64_t m0_un_wi : 1; 2467215976Sjmallett uint64_t m1_up_b0 : 1; 2468215976Sjmallett uint64_t m1_up_wi : 1; 2469215976Sjmallett uint64_t m1_un_b0 : 1; 2470215976Sjmallett uint64_t m1_un_wi : 1; 2471215976Sjmallett uint64_t mio_int0 : 1; 2472215976Sjmallett uint64_t mio_int1 : 1; 2473215976Sjmallett uint64_t mac0_int : 1; 2474215976Sjmallett uint64_t mac1_int : 1; 2475215976Sjmallett uint64_t reserved_20_31 : 12; 2476215976Sjmallett uint64_t dmafi : 2; 2477215976Sjmallett uint64_t dcnt : 2; 2478215976Sjmallett uint64_t dtime : 2; 2479215976Sjmallett uint64_t reserved_38_47 : 10; 2480215976Sjmallett uint64_t pidbof : 1; 2481215976Sjmallett uint64_t psldbof : 1; 2482215976Sjmallett uint64_t pout_err : 1; 2483215976Sjmallett uint64_t pin_bp : 1; 2484215976Sjmallett uint64_t pgl_err : 1; 2485215976Sjmallett uint64_t pdi_err : 1; 2486215976Sjmallett uint64_t pop_err : 1; 2487215976Sjmallett uint64_t pins_err : 1; 2488215976Sjmallett uint64_t sprt0_err : 1; 2489215976Sjmallett uint64_t sprt1_err : 1; 2490215976Sjmallett uint64_t reserved_58_59 : 2; 2491215976Sjmallett uint64_t ill_pad : 1; 2492215976Sjmallett uint64_t reserved_61_63 : 3; 2493215976Sjmallett#endif 2494232812Sjmallett } cn63xx; 2495232812Sjmallett struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; 2496232812Sjmallett struct cvmx_sli_int_enb_portx_cn61xx cn66xx; 2497232812Sjmallett struct cvmx_sli_int_enb_portx_cn68xx { 2498232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2499232812Sjmallett uint64_t reserved_62_63 : 2; 2500232812Sjmallett uint64_t pipe_err : 1; /**< Out of range PIPE value. */ 2501232812Sjmallett uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 2502232812Sjmallett uint64_t reserved_58_59 : 2; 2503232812Sjmallett uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 2504232812Sjmallett uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 2505232812Sjmallett uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 2506232812Sjmallett uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 2507232812Sjmallett uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 2508232812Sjmallett uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 2509232812Sjmallett uint64_t reserved_51_51 : 1; 2510232812Sjmallett uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 2511232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 2512232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 2513232812Sjmallett uint64_t reserved_38_47 : 10; 2514232812Sjmallett uint64_t dtime : 2; /**< DMA Timer Interrupts */ 2515232812Sjmallett uint64_t dcnt : 2; /**< DMA Count Interrupts */ 2516232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 2517232812Sjmallett uint64_t reserved_20_31 : 12; 2518232812Sjmallett uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an 2519232812Sjmallett interrupt to the PCIE-Port1 for MSI/inta. 2520232812Sjmallett The valuse of this bit has NO effect on PCIE Port0. 2521232812Sjmallett SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */ 2522232812Sjmallett uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an 2523232812Sjmallett interrupt to the PCIE-Port0 for MSI/inta. 2524232812Sjmallett The valus of this bit has NO effect on PCIE Port1. 2525232812Sjmallett SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */ 2526232812Sjmallett uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 2527232812Sjmallett interrupt to the PCIE core for MSI/inta. 2528232812Sjmallett SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */ 2529232812Sjmallett uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 2530232812Sjmallett interrupt to the PCIE core for MSI/inta. 2531232812Sjmallett SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */ 2532232812Sjmallett uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 2533232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2534232812Sjmallett uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 2535232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2536232812Sjmallett uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 2537232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2538232812Sjmallett uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 2539232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2540232812Sjmallett uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 2541232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2542232812Sjmallett uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 2543232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2544232812Sjmallett uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 2545232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2546232812Sjmallett uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 2547232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2548232812Sjmallett uint64_t reserved_6_7 : 2; 2549232812Sjmallett uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 2550232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2551232812Sjmallett uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 2552232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2553232812Sjmallett uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 2554232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2555232812Sjmallett uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 2556232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2557232812Sjmallett uint64_t reserved_1_1 : 1; 2558232812Sjmallett uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 2559232812Sjmallett interrupt to the PCIE core for MSI/inta. */ 2560232812Sjmallett#else 2561232812Sjmallett uint64_t rml_to : 1; 2562232812Sjmallett uint64_t reserved_1_1 : 1; 2563232812Sjmallett uint64_t bar0_to : 1; 2564232812Sjmallett uint64_t iob2big : 1; 2565232812Sjmallett uint64_t pcnt : 1; 2566232812Sjmallett uint64_t ptime : 1; 2567232812Sjmallett uint64_t reserved_6_7 : 2; 2568232812Sjmallett uint64_t m0_up_b0 : 1; 2569232812Sjmallett uint64_t m0_up_wi : 1; 2570232812Sjmallett uint64_t m0_un_b0 : 1; 2571232812Sjmallett uint64_t m0_un_wi : 1; 2572232812Sjmallett uint64_t m1_up_b0 : 1; 2573232812Sjmallett uint64_t m1_up_wi : 1; 2574232812Sjmallett uint64_t m1_un_b0 : 1; 2575232812Sjmallett uint64_t m1_un_wi : 1; 2576232812Sjmallett uint64_t mio_int0 : 1; 2577232812Sjmallett uint64_t mio_int1 : 1; 2578232812Sjmallett uint64_t mac0_int : 1; 2579232812Sjmallett uint64_t mac1_int : 1; 2580232812Sjmallett uint64_t reserved_20_31 : 12; 2581232812Sjmallett uint64_t dmafi : 2; 2582232812Sjmallett uint64_t dcnt : 2; 2583232812Sjmallett uint64_t dtime : 2; 2584232812Sjmallett uint64_t reserved_38_47 : 10; 2585232812Sjmallett uint64_t pidbof : 1; 2586232812Sjmallett uint64_t psldbof : 1; 2587232812Sjmallett uint64_t pout_err : 1; 2588232812Sjmallett uint64_t reserved_51_51 : 1; 2589232812Sjmallett uint64_t pgl_err : 1; 2590232812Sjmallett uint64_t pdi_err : 1; 2591232812Sjmallett uint64_t pop_err : 1; 2592232812Sjmallett uint64_t pins_err : 1; 2593232812Sjmallett uint64_t sprt0_err : 1; 2594232812Sjmallett uint64_t sprt1_err : 1; 2595232812Sjmallett uint64_t reserved_58_59 : 2; 2596232812Sjmallett uint64_t ill_pad : 1; 2597232812Sjmallett uint64_t pipe_err : 1; 2598232812Sjmallett uint64_t reserved_62_63 : 2; 2599232812Sjmallett#endif 2600232812Sjmallett } cn68xx; 2601232812Sjmallett struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; 2602232812Sjmallett struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; 2603215976Sjmallett}; 2604215976Sjmalletttypedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t; 2605215976Sjmallett 2606215976Sjmallett/** 2607215976Sjmallett * cvmx_sli_int_sum 2608215976Sjmallett * 2609215976Sjmallett * SLI_INT_SUM = SLI Interrupt Summary Register 2610215976Sjmallett * 2611215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. 2612215976Sjmallett */ 2613232812Sjmallettunion cvmx_sli_int_sum { 2614215976Sjmallett uint64_t u64; 2615232812Sjmallett struct cvmx_sli_int_sum_s { 2616232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2617232812Sjmallett uint64_t reserved_62_63 : 2; 2618232812Sjmallett uint64_t pipe_err : 1; /**< Set when a PIPE value outside range is received. */ 2619232812Sjmallett uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress 2620232812Sjmallett range of the Packet-CSR, but for an unused 2621232812Sjmallett address. */ 2622232812Sjmallett uint64_t sprt3_err : 1; /**< Reserved. */ 2623232812Sjmallett uint64_t sprt2_err : 1; /**< Reserved. */ 2624232812Sjmallett uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1 2625232812Sjmallett this bit is set. */ 2626232812Sjmallett uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0 2627232812Sjmallett this bit is set. */ 2628232812Sjmallett uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 2629232812Sjmallett this bit is set. */ 2630232812Sjmallett uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 2631232812Sjmallett pointer pair this bit is set. */ 2632232812Sjmallett uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 2633232812Sjmallett this bit is set. */ 2634232812Sjmallett uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 2635232812Sjmallett read this bit is set. */ 2636232812Sjmallett uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 2637232812Sjmallett See SLI_PKT_IN_BP */ 2638232812Sjmallett uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 2639232812Sjmallett set. */ 2640232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 2641232812Sjmallett doorbell can be found in DPI_PINT_INFO[PSLDBOF] */ 2642232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 2643232812Sjmallett doorbell can be found in DPI_PINT_INFO[PIDBOF] */ 2644232812Sjmallett uint64_t reserved_38_47 : 10; 2645232812Sjmallett uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the 2646232812Sjmallett SLI_DMAx_TIM[TIM] timer increments every SLI 2647232812Sjmallett clock. 2648232812Sjmallett DTIME[x] is set whenever SLI_DMAx_TIM[TIM] > 2649232812Sjmallett SLI_DMAx_INT_LEVEL[TIME]. 2650232812Sjmallett DTIME[x] is normally cleared by clearing 2651232812Sjmallett SLI_DMAx_CNT[CNT] (which also clears 2652232812Sjmallett SLI_DMAx_TIM[TIM]). */ 2653232812Sjmallett uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] > 2654232812Sjmallett SLI_DMAx_INT_LEVEL[CNT]. 2655232812Sjmallett DCNT[x] is normally cleared by decreasing 2656232812Sjmallett SLI_DMAx_CNT[CNT]. */ 2657232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */ 2658232812Sjmallett uint64_t reserved_28_31 : 4; 2659232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 2660232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 2661232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 2662232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 2663232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 2664232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 2665232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 2666232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 2667232812Sjmallett uint64_t mac1_int : 1; /**< Interrupt from MAC1. 2668232812Sjmallett See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */ 2669232812Sjmallett uint64_t mac0_int : 1; /**< Interrupt from MAC0. 2670232812Sjmallett See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */ 2671232812Sjmallett uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1. 2672232812Sjmallett See CIU_INT33_SUM0, CIU_INT_SUM1 2673232812Sjmallett (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */ 2674232812Sjmallett uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0. 2675232812Sjmallett See CIU_INT32_SUM0, CIU_INT_SUM1 2676232812Sjmallett (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */ 2677232812Sjmallett uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2678232812Sjmallett from MAC 1. This occurs when the window registers 2679232812Sjmallett are disabeld and a window register access occurs. */ 2680232812Sjmallett uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1. 2681232812Sjmallett This occurs when the BAR 0 address space is 2682232812Sjmallett disabeled. */ 2683232812Sjmallett uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2684232812Sjmallett from MAC 1. This occurs when the window registers 2685232812Sjmallett are disabeld and a window register access occurs. */ 2686232812Sjmallett uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1. 2687232812Sjmallett This occurs when the BAR 0 address space is 2688232812Sjmallett disabeled. */ 2689232812Sjmallett uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2690232812Sjmallett from MAC 0. This occurs when the window registers 2691232812Sjmallett are disabeld and a window register access occurs. */ 2692232812Sjmallett uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0. 2693232812Sjmallett This occurs when the BAR 0 address space is 2694232812Sjmallett disabeled. */ 2695232812Sjmallett uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2696232812Sjmallett from MAC 0. This occurs when the window registers 2697232812Sjmallett are disabeld and a window register access occurs. */ 2698232812Sjmallett uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0. 2699232812Sjmallett This occurs when the BAR 0 address space is 2700232812Sjmallett disabeled. */ 2701232812Sjmallett uint64_t reserved_6_7 : 2; 2702232812Sjmallett uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 2703232812Sjmallett be found in SLI_PKT_TIME_INT. */ 2704232812Sjmallett uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 2705232812Sjmallett be found in SLI_PKT_CNT_INT. */ 2706232812Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 2707232812Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 2708232812Sjmallett read-data/commit in 0xffff core clocks. */ 2709232812Sjmallett uint64_t reserved_1_1 : 1; 2710232812Sjmallett uint64_t rml_to : 1; /**< A read or write transfer did not complete 2711232812Sjmallett within 0xffff core clocks. */ 2712232812Sjmallett#else 2713232812Sjmallett uint64_t rml_to : 1; 2714232812Sjmallett uint64_t reserved_1_1 : 1; 2715232812Sjmallett uint64_t bar0_to : 1; 2716232812Sjmallett uint64_t iob2big : 1; 2717232812Sjmallett uint64_t pcnt : 1; 2718232812Sjmallett uint64_t ptime : 1; 2719232812Sjmallett uint64_t reserved_6_7 : 2; 2720232812Sjmallett uint64_t m0_up_b0 : 1; 2721232812Sjmallett uint64_t m0_up_wi : 1; 2722232812Sjmallett uint64_t m0_un_b0 : 1; 2723232812Sjmallett uint64_t m0_un_wi : 1; 2724232812Sjmallett uint64_t m1_up_b0 : 1; 2725232812Sjmallett uint64_t m1_up_wi : 1; 2726232812Sjmallett uint64_t m1_un_b0 : 1; 2727232812Sjmallett uint64_t m1_un_wi : 1; 2728232812Sjmallett uint64_t mio_int0 : 1; 2729232812Sjmallett uint64_t mio_int1 : 1; 2730232812Sjmallett uint64_t mac0_int : 1; 2731232812Sjmallett uint64_t mac1_int : 1; 2732232812Sjmallett uint64_t m2_up_b0 : 1; 2733232812Sjmallett uint64_t m2_up_wi : 1; 2734232812Sjmallett uint64_t m2_un_b0 : 1; 2735232812Sjmallett uint64_t m2_un_wi : 1; 2736232812Sjmallett uint64_t m3_up_b0 : 1; 2737232812Sjmallett uint64_t m3_up_wi : 1; 2738232812Sjmallett uint64_t m3_un_b0 : 1; 2739232812Sjmallett uint64_t m3_un_wi : 1; 2740232812Sjmallett uint64_t reserved_28_31 : 4; 2741232812Sjmallett uint64_t dmafi : 2; 2742232812Sjmallett uint64_t dcnt : 2; 2743232812Sjmallett uint64_t dtime : 2; 2744232812Sjmallett uint64_t reserved_38_47 : 10; 2745232812Sjmallett uint64_t pidbof : 1; 2746232812Sjmallett uint64_t psldbof : 1; 2747232812Sjmallett uint64_t pout_err : 1; 2748232812Sjmallett uint64_t pin_bp : 1; 2749232812Sjmallett uint64_t pgl_err : 1; 2750232812Sjmallett uint64_t pdi_err : 1; 2751232812Sjmallett uint64_t pop_err : 1; 2752232812Sjmallett uint64_t pins_err : 1; 2753232812Sjmallett uint64_t sprt0_err : 1; 2754232812Sjmallett uint64_t sprt1_err : 1; 2755232812Sjmallett uint64_t sprt2_err : 1; 2756232812Sjmallett uint64_t sprt3_err : 1; 2757232812Sjmallett uint64_t ill_pad : 1; 2758232812Sjmallett uint64_t pipe_err : 1; 2759232812Sjmallett uint64_t reserved_62_63 : 2; 2760232812Sjmallett#endif 2761232812Sjmallett } s; 2762232812Sjmallett struct cvmx_sli_int_sum_cn61xx { 2763232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2764215976Sjmallett uint64_t reserved_61_63 : 3; 2765215976Sjmallett uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress 2766215976Sjmallett range of the Packet-CSR, but for an unused 2767215976Sjmallett address. */ 2768232812Sjmallett uint64_t sprt3_err : 1; /**< Reserved. */ 2769232812Sjmallett uint64_t sprt2_err : 1; /**< Reserved. */ 2770232812Sjmallett uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1 2771232812Sjmallett this bit is set. */ 2772232812Sjmallett uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0 2773232812Sjmallett this bit is set. */ 2774232812Sjmallett uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 2775232812Sjmallett this bit is set. */ 2776232812Sjmallett uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 2777232812Sjmallett pointer pair this bit is set. */ 2778232812Sjmallett uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 2779232812Sjmallett this bit is set. */ 2780232812Sjmallett uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 2781232812Sjmallett read this bit is set. */ 2782232812Sjmallett uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 2783232812Sjmallett See SLI_PKT_IN_BP */ 2784232812Sjmallett uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 2785232812Sjmallett set. */ 2786232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 2787232812Sjmallett doorbell can be found in DPI_PINT_INFO[PSLDBOF] */ 2788232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 2789232812Sjmallett doorbell can be found in DPI_PINT_INFO[PIDBOF] */ 2790232812Sjmallett uint64_t reserved_38_47 : 10; 2791232812Sjmallett uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the 2792232812Sjmallett SLI_DMAx_TIM[TIM] timer increments every SLI 2793232812Sjmallett clock. 2794232812Sjmallett DTIME[x] is set whenever SLI_DMAx_TIM[TIM] > 2795232812Sjmallett SLI_DMAx_INT_LEVEL[TIME]. 2796232812Sjmallett DTIME[x] is normally cleared by clearing 2797232812Sjmallett SLI_DMAx_CNT[CNT] (which also clears 2798232812Sjmallett SLI_DMAx_TIM[TIM]). */ 2799232812Sjmallett uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] > 2800232812Sjmallett SLI_DMAx_INT_LEVEL[CNT]. 2801232812Sjmallett DCNT[x] is normally cleared by decreasing 2802232812Sjmallett SLI_DMAx_CNT[CNT]. */ 2803232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */ 2804232812Sjmallett uint64_t reserved_28_31 : 4; 2805232812Sjmallett uint64_t m3_un_wi : 1; /**< Reserved. */ 2806232812Sjmallett uint64_t m3_un_b0 : 1; /**< Reserved. */ 2807232812Sjmallett uint64_t m3_up_wi : 1; /**< Reserved. */ 2808232812Sjmallett uint64_t m3_up_b0 : 1; /**< Reserved. */ 2809232812Sjmallett uint64_t m2_un_wi : 1; /**< Reserved. */ 2810232812Sjmallett uint64_t m2_un_b0 : 1; /**< Reserved. */ 2811232812Sjmallett uint64_t m2_up_wi : 1; /**< Reserved. */ 2812232812Sjmallett uint64_t m2_up_b0 : 1; /**< Reserved. */ 2813232812Sjmallett uint64_t mac1_int : 1; /**< Interrupt from MAC1. 2814232812Sjmallett See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */ 2815232812Sjmallett uint64_t mac0_int : 1; /**< Interrupt from MAC0. 2816232812Sjmallett See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */ 2817232812Sjmallett uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1. 2818232812Sjmallett See CIU_INT33_SUM0, CIU_INT_SUM1 2819232812Sjmallett (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */ 2820232812Sjmallett uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0. 2821232812Sjmallett See CIU_INT32_SUM0, CIU_INT_SUM1 2822232812Sjmallett (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */ 2823232812Sjmallett uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2824232812Sjmallett from MAC 1. This occurs when the window registers 2825232812Sjmallett are disabeld and a window register access occurs. */ 2826232812Sjmallett uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1. 2827232812Sjmallett This occurs when the BAR 0 address space is 2828232812Sjmallett disabeled. */ 2829232812Sjmallett uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2830232812Sjmallett from MAC 1. This occurs when the window registers 2831232812Sjmallett are disabeld and a window register access occurs. */ 2832232812Sjmallett uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1. 2833232812Sjmallett This occurs when the BAR 0 address space is 2834232812Sjmallett disabeled. */ 2835232812Sjmallett uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2836232812Sjmallett from MAC 0. This occurs when the window registers 2837232812Sjmallett are disabeld and a window register access occurs. */ 2838232812Sjmallett uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0. 2839232812Sjmallett This occurs when the BAR 0 address space is 2840232812Sjmallett disabeled. */ 2841232812Sjmallett uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2842232812Sjmallett from MAC 0. This occurs when the window registers 2843232812Sjmallett are disabeld and a window register access occurs. */ 2844232812Sjmallett uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0. 2845232812Sjmallett This occurs when the BAR 0 address space is 2846232812Sjmallett disabeled. */ 2847232812Sjmallett uint64_t reserved_6_7 : 2; 2848232812Sjmallett uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 2849232812Sjmallett be found in SLI_PKT_TIME_INT. */ 2850232812Sjmallett uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 2851232812Sjmallett be found in SLI_PKT_CNT_INT. */ 2852232812Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 2853232812Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 2854232812Sjmallett read-data/commit in 0xffff core clocks. */ 2855232812Sjmallett uint64_t reserved_1_1 : 1; 2856232812Sjmallett uint64_t rml_to : 1; /**< A read or write transfer did not complete 2857232812Sjmallett within 0xffff core clocks. */ 2858232812Sjmallett#else 2859232812Sjmallett uint64_t rml_to : 1; 2860232812Sjmallett uint64_t reserved_1_1 : 1; 2861232812Sjmallett uint64_t bar0_to : 1; 2862232812Sjmallett uint64_t iob2big : 1; 2863232812Sjmallett uint64_t pcnt : 1; 2864232812Sjmallett uint64_t ptime : 1; 2865232812Sjmallett uint64_t reserved_6_7 : 2; 2866232812Sjmallett uint64_t m0_up_b0 : 1; 2867232812Sjmallett uint64_t m0_up_wi : 1; 2868232812Sjmallett uint64_t m0_un_b0 : 1; 2869232812Sjmallett uint64_t m0_un_wi : 1; 2870232812Sjmallett uint64_t m1_up_b0 : 1; 2871232812Sjmallett uint64_t m1_up_wi : 1; 2872232812Sjmallett uint64_t m1_un_b0 : 1; 2873232812Sjmallett uint64_t m1_un_wi : 1; 2874232812Sjmallett uint64_t mio_int0 : 1; 2875232812Sjmallett uint64_t mio_int1 : 1; 2876232812Sjmallett uint64_t mac0_int : 1; 2877232812Sjmallett uint64_t mac1_int : 1; 2878232812Sjmallett uint64_t m2_up_b0 : 1; 2879232812Sjmallett uint64_t m2_up_wi : 1; 2880232812Sjmallett uint64_t m2_un_b0 : 1; 2881232812Sjmallett uint64_t m2_un_wi : 1; 2882232812Sjmallett uint64_t m3_up_b0 : 1; 2883232812Sjmallett uint64_t m3_up_wi : 1; 2884232812Sjmallett uint64_t m3_un_b0 : 1; 2885232812Sjmallett uint64_t m3_un_wi : 1; 2886232812Sjmallett uint64_t reserved_28_31 : 4; 2887232812Sjmallett uint64_t dmafi : 2; 2888232812Sjmallett uint64_t dcnt : 2; 2889232812Sjmallett uint64_t dtime : 2; 2890232812Sjmallett uint64_t reserved_38_47 : 10; 2891232812Sjmallett uint64_t pidbof : 1; 2892232812Sjmallett uint64_t psldbof : 1; 2893232812Sjmallett uint64_t pout_err : 1; 2894232812Sjmallett uint64_t pin_bp : 1; 2895232812Sjmallett uint64_t pgl_err : 1; 2896232812Sjmallett uint64_t pdi_err : 1; 2897232812Sjmallett uint64_t pop_err : 1; 2898232812Sjmallett uint64_t pins_err : 1; 2899232812Sjmallett uint64_t sprt0_err : 1; 2900232812Sjmallett uint64_t sprt1_err : 1; 2901232812Sjmallett uint64_t sprt2_err : 1; 2902232812Sjmallett uint64_t sprt3_err : 1; 2903232812Sjmallett uint64_t ill_pad : 1; 2904232812Sjmallett uint64_t reserved_61_63 : 3; 2905232812Sjmallett#endif 2906232812Sjmallett } cn61xx; 2907232812Sjmallett struct cvmx_sli_int_sum_cn63xx { 2908232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2909232812Sjmallett uint64_t reserved_61_63 : 3; 2910232812Sjmallett uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress 2911232812Sjmallett range of the Packet-CSR, but for an unused 2912232812Sjmallett address. */ 2913215976Sjmallett uint64_t reserved_58_59 : 2; 2914215976Sjmallett uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1 2915215976Sjmallett this bit is set. */ 2916215976Sjmallett uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0 2917215976Sjmallett this bit is set. */ 2918215976Sjmallett uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 2919215976Sjmallett this bit is set. */ 2920215976Sjmallett uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 2921215976Sjmallett pointer pair this bit is set. */ 2922215976Sjmallett uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 2923215976Sjmallett this bit is set. */ 2924215976Sjmallett uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 2925215976Sjmallett read this bit is set. */ 2926215976Sjmallett uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 2927215976Sjmallett See SLI_PKT_IN_BP */ 2928215976Sjmallett uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 2929215976Sjmallett set. */ 2930215976Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 2931215976Sjmallett doorbell can be found in DPI_PINT_INFO[PSLDBOF] */ 2932215976Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 2933215976Sjmallett doorbell can be found in DPI_PINT_INFO[PIDBOF] */ 2934215976Sjmallett uint64_t reserved_38_47 : 10; 2935215976Sjmallett uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the 2936215976Sjmallett SLI_DMAx_TIM[TIM] timer increments every SLI 2937215976Sjmallett clock. 2938215976Sjmallett DTIME[x] is set whenever SLI_DMAx_TIM[TIM] > 2939215976Sjmallett SLI_DMAx_INT_LEVEL[TIME]. 2940215976Sjmallett DTIME[x] is normally cleared by clearing 2941215976Sjmallett SLI_DMAx_CNT[CNT] (which also clears 2942215976Sjmallett SLI_DMAx_TIM[TIM]). */ 2943215976Sjmallett uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] > 2944215976Sjmallett SLI_DMAx_INT_LEVEL[CNT]. 2945215976Sjmallett DCNT[x] is normally cleared by decreasing 2946215976Sjmallett SLI_DMAx_CNT[CNT]. */ 2947215976Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */ 2948215976Sjmallett uint64_t reserved_20_31 : 12; 2949215976Sjmallett uint64_t mac1_int : 1; /**< Interrupt from MAC1. 2950215976Sjmallett See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */ 2951215976Sjmallett uint64_t mac0_int : 1; /**< Interrupt from MAC0. 2952215976Sjmallett See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */ 2953215976Sjmallett uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1. 2954215976Sjmallett See CIU_INT33_SUM0, CIU_INT_SUM1 2955215976Sjmallett (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */ 2956215976Sjmallett uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0. 2957215976Sjmallett See CIU_INT32_SUM0, CIU_INT_SUM1 2958215976Sjmallett (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */ 2959215976Sjmallett uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2960215976Sjmallett from MAC 1. This occurs when the window registers 2961215976Sjmallett are disabeld and a window register access occurs. */ 2962215976Sjmallett uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1. 2963215976Sjmallett This occurs when the BAR 0 address space is 2964215976Sjmallett disabeled. */ 2965215976Sjmallett uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2966215976Sjmallett from MAC 1. This occurs when the window registers 2967215976Sjmallett are disabeld and a window register access occurs. */ 2968215976Sjmallett uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1. 2969215976Sjmallett This occurs when the BAR 0 address space is 2970215976Sjmallett disabeled. */ 2971215976Sjmallett uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 2972215976Sjmallett from MAC 0. This occurs when the window registers 2973215976Sjmallett are disabeld and a window register access occurs. */ 2974215976Sjmallett uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0. 2975215976Sjmallett This occurs when the BAR 0 address space is 2976215976Sjmallett disabeled. */ 2977215976Sjmallett uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 2978215976Sjmallett from MAC 0. This occurs when the window registers 2979215976Sjmallett are disabeld and a window register access occurs. */ 2980215976Sjmallett uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0. 2981215976Sjmallett This occurs when the BAR 0 address space is 2982215976Sjmallett disabeled. */ 2983215976Sjmallett uint64_t reserved_6_7 : 2; 2984215976Sjmallett uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 2985215976Sjmallett be found in SLI_PKT_TIME_INT. */ 2986215976Sjmallett uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 2987215976Sjmallett be found in SLI_PKT_CNT_INT. */ 2988215976Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 2989215976Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 2990215976Sjmallett read-data/commit in 0xffff core clocks. */ 2991215976Sjmallett uint64_t reserved_1_1 : 1; 2992215976Sjmallett uint64_t rml_to : 1; /**< A read or write transfer did not complete 2993215976Sjmallett within 0xffff core clocks. */ 2994215976Sjmallett#else 2995215976Sjmallett uint64_t rml_to : 1; 2996215976Sjmallett uint64_t reserved_1_1 : 1; 2997215976Sjmallett uint64_t bar0_to : 1; 2998215976Sjmallett uint64_t iob2big : 1; 2999215976Sjmallett uint64_t pcnt : 1; 3000215976Sjmallett uint64_t ptime : 1; 3001215976Sjmallett uint64_t reserved_6_7 : 2; 3002215976Sjmallett uint64_t m0_up_b0 : 1; 3003215976Sjmallett uint64_t m0_up_wi : 1; 3004215976Sjmallett uint64_t m0_un_b0 : 1; 3005215976Sjmallett uint64_t m0_un_wi : 1; 3006215976Sjmallett uint64_t m1_up_b0 : 1; 3007215976Sjmallett uint64_t m1_up_wi : 1; 3008215976Sjmallett uint64_t m1_un_b0 : 1; 3009215976Sjmallett uint64_t m1_un_wi : 1; 3010215976Sjmallett uint64_t mio_int0 : 1; 3011215976Sjmallett uint64_t mio_int1 : 1; 3012215976Sjmallett uint64_t mac0_int : 1; 3013215976Sjmallett uint64_t mac1_int : 1; 3014215976Sjmallett uint64_t reserved_20_31 : 12; 3015215976Sjmallett uint64_t dmafi : 2; 3016215976Sjmallett uint64_t dcnt : 2; 3017215976Sjmallett uint64_t dtime : 2; 3018215976Sjmallett uint64_t reserved_38_47 : 10; 3019215976Sjmallett uint64_t pidbof : 1; 3020215976Sjmallett uint64_t psldbof : 1; 3021215976Sjmallett uint64_t pout_err : 1; 3022215976Sjmallett uint64_t pin_bp : 1; 3023215976Sjmallett uint64_t pgl_err : 1; 3024215976Sjmallett uint64_t pdi_err : 1; 3025215976Sjmallett uint64_t pop_err : 1; 3026215976Sjmallett uint64_t pins_err : 1; 3027215976Sjmallett uint64_t sprt0_err : 1; 3028215976Sjmallett uint64_t sprt1_err : 1; 3029215976Sjmallett uint64_t reserved_58_59 : 2; 3030215976Sjmallett uint64_t ill_pad : 1; 3031215976Sjmallett uint64_t reserved_61_63 : 3; 3032215976Sjmallett#endif 3033232812Sjmallett } cn63xx; 3034232812Sjmallett struct cvmx_sli_int_sum_cn63xx cn63xxp1; 3035232812Sjmallett struct cvmx_sli_int_sum_cn61xx cn66xx; 3036232812Sjmallett struct cvmx_sli_int_sum_cn68xx { 3037232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3038232812Sjmallett uint64_t reserved_62_63 : 2; 3039232812Sjmallett uint64_t pipe_err : 1; /**< Set when a PIPE value outside range is received. */ 3040232812Sjmallett uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress 3041232812Sjmallett range of the Packet-CSR, but for an unused 3042232812Sjmallett address. */ 3043232812Sjmallett uint64_t reserved_58_59 : 2; 3044232812Sjmallett uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1 3045232812Sjmallett this bit is set. */ 3046232812Sjmallett uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0 3047232812Sjmallett this bit is set. */ 3048232812Sjmallett uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 3049232812Sjmallett this bit is set. */ 3050232812Sjmallett uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 3051232812Sjmallett pointer pair this bit is set. */ 3052232812Sjmallett uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 3053232812Sjmallett this bit is set. */ 3054232812Sjmallett uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 3055232812Sjmallett read this bit is set. */ 3056232812Sjmallett uint64_t reserved_51_51 : 1; 3057232812Sjmallett uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 3058232812Sjmallett set. */ 3059232812Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 3060232812Sjmallett doorbell can be found in DPI_PINT_INFO[PSLDBOF] */ 3061232812Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 3062232812Sjmallett doorbell can be found in DPI_PINT_INFO[PIDBOF] */ 3063232812Sjmallett uint64_t reserved_38_47 : 10; 3064232812Sjmallett uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the 3065232812Sjmallett SLI_DMAx_TIM[TIM] timer increments every SLI 3066232812Sjmallett clock. 3067232812Sjmallett DTIME[x] is set whenever SLI_DMAx_TIM[TIM] > 3068232812Sjmallett SLI_DMAx_INT_LEVEL[TIME]. 3069232812Sjmallett DTIME[x] is normally cleared by clearing 3070232812Sjmallett SLI_DMAx_CNT[CNT] (which also clears 3071232812Sjmallett SLI_DMAx_TIM[TIM]). */ 3072232812Sjmallett uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] > 3073232812Sjmallett SLI_DMAx_INT_LEVEL[CNT]. 3074232812Sjmallett DCNT[x] is normally cleared by decreasing 3075232812Sjmallett SLI_DMAx_CNT[CNT]. */ 3076232812Sjmallett uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */ 3077232812Sjmallett uint64_t reserved_20_31 : 12; 3078232812Sjmallett uint64_t mac1_int : 1; /**< Interrupt from MAC1. 3079232812Sjmallett See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */ 3080232812Sjmallett uint64_t mac0_int : 1; /**< Interrupt from MAC0. 3081232812Sjmallett See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */ 3082232812Sjmallett uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1. 3083232812Sjmallett See CIU_INT33_SUM0, CIU_INT_SUM1 3084232812Sjmallett (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */ 3085232812Sjmallett uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0. 3086232812Sjmallett See CIU_INT32_SUM0, CIU_INT_SUM1 3087232812Sjmallett (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */ 3088232812Sjmallett uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 3089232812Sjmallett from MAC 1. This occurs when the window registers 3090232812Sjmallett are disabeld and a window register access occurs. */ 3091232812Sjmallett uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1. 3092232812Sjmallett This occurs when the BAR 0 address space is 3093232812Sjmallett disabeled. */ 3094232812Sjmallett uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 3095232812Sjmallett from MAC 1. This occurs when the window registers 3096232812Sjmallett are disabeld and a window register access occurs. */ 3097232812Sjmallett uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1. 3098232812Sjmallett This occurs when the BAR 0 address space is 3099232812Sjmallett disabeled. */ 3100232812Sjmallett uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 3101232812Sjmallett from MAC 0. This occurs when the window registers 3102232812Sjmallett are disabeld and a window register access occurs. */ 3103232812Sjmallett uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0. 3104232812Sjmallett This occurs when the BAR 0 address space is 3105232812Sjmallett disabeled. */ 3106232812Sjmallett uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 3107232812Sjmallett from MAC 0. This occurs when the window registers 3108232812Sjmallett are disabeld and a window register access occurs. */ 3109232812Sjmallett uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0. 3110232812Sjmallett This occurs when the BAR 0 address space is 3111232812Sjmallett disabeled. */ 3112232812Sjmallett uint64_t reserved_6_7 : 2; 3113232812Sjmallett uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 3114232812Sjmallett be found in SLI_PKT_TIME_INT. */ 3115232812Sjmallett uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 3116232812Sjmallett be found in SLI_PKT_CNT_INT. */ 3117232812Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 3118232812Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 3119232812Sjmallett read-data/commit in 0xffff core clocks. */ 3120232812Sjmallett uint64_t reserved_1_1 : 1; 3121232812Sjmallett uint64_t rml_to : 1; /**< A read or write transfer did not complete 3122232812Sjmallett within 0xffff core clocks. */ 3123232812Sjmallett#else 3124232812Sjmallett uint64_t rml_to : 1; 3125232812Sjmallett uint64_t reserved_1_1 : 1; 3126232812Sjmallett uint64_t bar0_to : 1; 3127232812Sjmallett uint64_t iob2big : 1; 3128232812Sjmallett uint64_t pcnt : 1; 3129232812Sjmallett uint64_t ptime : 1; 3130232812Sjmallett uint64_t reserved_6_7 : 2; 3131232812Sjmallett uint64_t m0_up_b0 : 1; 3132232812Sjmallett uint64_t m0_up_wi : 1; 3133232812Sjmallett uint64_t m0_un_b0 : 1; 3134232812Sjmallett uint64_t m0_un_wi : 1; 3135232812Sjmallett uint64_t m1_up_b0 : 1; 3136232812Sjmallett uint64_t m1_up_wi : 1; 3137232812Sjmallett uint64_t m1_un_b0 : 1; 3138232812Sjmallett uint64_t m1_un_wi : 1; 3139232812Sjmallett uint64_t mio_int0 : 1; 3140232812Sjmallett uint64_t mio_int1 : 1; 3141232812Sjmallett uint64_t mac0_int : 1; 3142232812Sjmallett uint64_t mac1_int : 1; 3143232812Sjmallett uint64_t reserved_20_31 : 12; 3144232812Sjmallett uint64_t dmafi : 2; 3145232812Sjmallett uint64_t dcnt : 2; 3146232812Sjmallett uint64_t dtime : 2; 3147232812Sjmallett uint64_t reserved_38_47 : 10; 3148232812Sjmallett uint64_t pidbof : 1; 3149232812Sjmallett uint64_t psldbof : 1; 3150232812Sjmallett uint64_t pout_err : 1; 3151232812Sjmallett uint64_t reserved_51_51 : 1; 3152232812Sjmallett uint64_t pgl_err : 1; 3153232812Sjmallett uint64_t pdi_err : 1; 3154232812Sjmallett uint64_t pop_err : 1; 3155232812Sjmallett uint64_t pins_err : 1; 3156232812Sjmallett uint64_t sprt0_err : 1; 3157232812Sjmallett uint64_t sprt1_err : 1; 3158232812Sjmallett uint64_t reserved_58_59 : 2; 3159232812Sjmallett uint64_t ill_pad : 1; 3160232812Sjmallett uint64_t pipe_err : 1; 3161232812Sjmallett uint64_t reserved_62_63 : 2; 3162232812Sjmallett#endif 3163232812Sjmallett } cn68xx; 3164232812Sjmallett struct cvmx_sli_int_sum_cn68xx cn68xxp1; 3165232812Sjmallett struct cvmx_sli_int_sum_cn61xx cnf71xx; 3166215976Sjmallett}; 3167215976Sjmalletttypedef union cvmx_sli_int_sum cvmx_sli_int_sum_t; 3168215976Sjmallett 3169215976Sjmallett/** 3170215976Sjmallett * cvmx_sli_last_win_rdata0 3171215976Sjmallett * 3172232812Sjmallett * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data 3173215976Sjmallett * 3174232812Sjmallett * The data from the last initiated window read by MAC 0. 3175215976Sjmallett */ 3176232812Sjmallettunion cvmx_sli_last_win_rdata0 { 3177215976Sjmallett uint64_t u64; 3178232812Sjmallett struct cvmx_sli_last_win_rdata0_s { 3179232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3180215976Sjmallett uint64_t data : 64; /**< Last window read data. */ 3181215976Sjmallett#else 3182215976Sjmallett uint64_t data : 64; 3183215976Sjmallett#endif 3184215976Sjmallett } s; 3185232812Sjmallett struct cvmx_sli_last_win_rdata0_s cn61xx; 3186215976Sjmallett struct cvmx_sli_last_win_rdata0_s cn63xx; 3187215976Sjmallett struct cvmx_sli_last_win_rdata0_s cn63xxp1; 3188232812Sjmallett struct cvmx_sli_last_win_rdata0_s cn66xx; 3189232812Sjmallett struct cvmx_sli_last_win_rdata0_s cn68xx; 3190232812Sjmallett struct cvmx_sli_last_win_rdata0_s cn68xxp1; 3191232812Sjmallett struct cvmx_sli_last_win_rdata0_s cnf71xx; 3192215976Sjmallett}; 3193215976Sjmalletttypedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t; 3194215976Sjmallett 3195215976Sjmallett/** 3196215976Sjmallett * cvmx_sli_last_win_rdata1 3197215976Sjmallett * 3198232812Sjmallett * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data 3199215976Sjmallett * 3200232812Sjmallett * The data from the last initiated window read by MAC 1. 3201215976Sjmallett */ 3202232812Sjmallettunion cvmx_sli_last_win_rdata1 { 3203215976Sjmallett uint64_t u64; 3204232812Sjmallett struct cvmx_sli_last_win_rdata1_s { 3205232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3206215976Sjmallett uint64_t data : 64; /**< Last window read data. */ 3207215976Sjmallett#else 3208215976Sjmallett uint64_t data : 64; 3209215976Sjmallett#endif 3210215976Sjmallett } s; 3211232812Sjmallett struct cvmx_sli_last_win_rdata1_s cn61xx; 3212215976Sjmallett struct cvmx_sli_last_win_rdata1_s cn63xx; 3213215976Sjmallett struct cvmx_sli_last_win_rdata1_s cn63xxp1; 3214232812Sjmallett struct cvmx_sli_last_win_rdata1_s cn66xx; 3215232812Sjmallett struct cvmx_sli_last_win_rdata1_s cn68xx; 3216232812Sjmallett struct cvmx_sli_last_win_rdata1_s cn68xxp1; 3217232812Sjmallett struct cvmx_sli_last_win_rdata1_s cnf71xx; 3218215976Sjmallett}; 3219215976Sjmalletttypedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t; 3220215976Sjmallett 3221215976Sjmallett/** 3222232812Sjmallett * cvmx_sli_last_win_rdata2 3223232812Sjmallett * 3224232812Sjmallett * SLI_LAST_WIN_RDATA2 = SLI Last Window Read Data 3225232812Sjmallett * 3226232812Sjmallett * The data from the last initiated window read by MAC 2. 3227232812Sjmallett */ 3228232812Sjmallettunion cvmx_sli_last_win_rdata2 { 3229232812Sjmallett uint64_t u64; 3230232812Sjmallett struct cvmx_sli_last_win_rdata2_s { 3231232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3232232812Sjmallett uint64_t data : 64; /**< Last window read data. */ 3233232812Sjmallett#else 3234232812Sjmallett uint64_t data : 64; 3235232812Sjmallett#endif 3236232812Sjmallett } s; 3237232812Sjmallett struct cvmx_sli_last_win_rdata2_s cn61xx; 3238232812Sjmallett struct cvmx_sli_last_win_rdata2_s cn66xx; 3239232812Sjmallett struct cvmx_sli_last_win_rdata2_s cnf71xx; 3240232812Sjmallett}; 3241232812Sjmalletttypedef union cvmx_sli_last_win_rdata2 cvmx_sli_last_win_rdata2_t; 3242232812Sjmallett 3243232812Sjmallett/** 3244232812Sjmallett * cvmx_sli_last_win_rdata3 3245232812Sjmallett * 3246232812Sjmallett * SLI_LAST_WIN_RDATA3 = SLI Last Window Read Data 3247232812Sjmallett * 3248232812Sjmallett * The data from the last initiated window read by MAC 3. 3249232812Sjmallett */ 3250232812Sjmallettunion cvmx_sli_last_win_rdata3 { 3251232812Sjmallett uint64_t u64; 3252232812Sjmallett struct cvmx_sli_last_win_rdata3_s { 3253232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3254232812Sjmallett uint64_t data : 64; /**< Last window read data. */ 3255232812Sjmallett#else 3256232812Sjmallett uint64_t data : 64; 3257232812Sjmallett#endif 3258232812Sjmallett } s; 3259232812Sjmallett struct cvmx_sli_last_win_rdata3_s cn61xx; 3260232812Sjmallett struct cvmx_sli_last_win_rdata3_s cn66xx; 3261232812Sjmallett struct cvmx_sli_last_win_rdata3_s cnf71xx; 3262232812Sjmallett}; 3263232812Sjmalletttypedef union cvmx_sli_last_win_rdata3 cvmx_sli_last_win_rdata3_t; 3264232812Sjmallett 3265232812Sjmallett/** 3266215976Sjmallett * cvmx_sli_mac_credit_cnt 3267215976Sjmallett * 3268215976Sjmallett * SLI_MAC_CREDIT_CNT = SLI MAC Credit Count 3269215976Sjmallett * 3270215976Sjmallett * Contains the number of credits for the MAC port FIFOs used by the SLI. This value needs to be set BEFORE S2M traffic 3271215976Sjmallett * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value 3272215976Sjmallett * in this register. 3273215976Sjmallett */ 3274232812Sjmallettunion cvmx_sli_mac_credit_cnt { 3275215976Sjmallett uint64_t u64; 3276232812Sjmallett struct cvmx_sli_mac_credit_cnt_s { 3277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3278215976Sjmallett uint64_t reserved_54_63 : 10; 3279215976Sjmallett uint64_t p1_c_d : 1; /**< When set does not allow writing of P1_CCNT. */ 3280215976Sjmallett uint64_t p1_n_d : 1; /**< When set does not allow writing of P1_NCNT. */ 3281215976Sjmallett uint64_t p1_p_d : 1; /**< When set does not allow writing of P1_PCNT. */ 3282215976Sjmallett uint64_t p0_c_d : 1; /**< When set does not allow writing of P0_CCNT. */ 3283215976Sjmallett uint64_t p0_n_d : 1; /**< When set does not allow writing of P0_NCNT. */ 3284215976Sjmallett uint64_t p0_p_d : 1; /**< When set does not allow writing of P0_PCNT. */ 3285215976Sjmallett uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 3286215976Sjmallett Legal values are 0x25 to 0x80. */ 3287215976Sjmallett uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 3288215976Sjmallett Legal values are 0x5 to 0x10. */ 3289215976Sjmallett uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 3290215976Sjmallett Legal values are 0x25 to 0x80. */ 3291215976Sjmallett uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 3292215976Sjmallett Legal values are 0x25 to 0x80. */ 3293215976Sjmallett uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 3294215976Sjmallett Legal values are 0x5 to 0x10. */ 3295215976Sjmallett uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 3296215976Sjmallett Legal values are 0x25 to 0x80. */ 3297215976Sjmallett#else 3298215976Sjmallett uint64_t p0_pcnt : 8; 3299215976Sjmallett uint64_t p0_ncnt : 8; 3300215976Sjmallett uint64_t p0_ccnt : 8; 3301215976Sjmallett uint64_t p1_pcnt : 8; 3302215976Sjmallett uint64_t p1_ncnt : 8; 3303215976Sjmallett uint64_t p1_ccnt : 8; 3304215976Sjmallett uint64_t p0_p_d : 1; 3305215976Sjmallett uint64_t p0_n_d : 1; 3306215976Sjmallett uint64_t p0_c_d : 1; 3307215976Sjmallett uint64_t p1_p_d : 1; 3308215976Sjmallett uint64_t p1_n_d : 1; 3309215976Sjmallett uint64_t p1_c_d : 1; 3310215976Sjmallett uint64_t reserved_54_63 : 10; 3311215976Sjmallett#endif 3312215976Sjmallett } s; 3313232812Sjmallett struct cvmx_sli_mac_credit_cnt_s cn61xx; 3314215976Sjmallett struct cvmx_sli_mac_credit_cnt_s cn63xx; 3315232812Sjmallett struct cvmx_sli_mac_credit_cnt_cn63xxp1 { 3316232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3317215976Sjmallett uint64_t reserved_48_63 : 16; 3318215976Sjmallett uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 3319215976Sjmallett Legal values are 0x25 to 0x80. */ 3320215976Sjmallett uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 3321215976Sjmallett Legal values are 0x5 to 0x10. */ 3322215976Sjmallett uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 3323215976Sjmallett Legal values are 0x25 to 0x80. */ 3324215976Sjmallett uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 3325215976Sjmallett Legal values are 0x25 to 0x80. */ 3326215976Sjmallett uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 3327215976Sjmallett Legal values are 0x5 to 0x10. */ 3328215976Sjmallett uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 3329215976Sjmallett Legal values are 0x25 to 0x80. */ 3330215976Sjmallett#else 3331215976Sjmallett uint64_t p0_pcnt : 8; 3332215976Sjmallett uint64_t p0_ncnt : 8; 3333215976Sjmallett uint64_t p0_ccnt : 8; 3334215976Sjmallett uint64_t p1_pcnt : 8; 3335215976Sjmallett uint64_t p1_ncnt : 8; 3336215976Sjmallett uint64_t p1_ccnt : 8; 3337215976Sjmallett uint64_t reserved_48_63 : 16; 3338215976Sjmallett#endif 3339215976Sjmallett } cn63xxp1; 3340232812Sjmallett struct cvmx_sli_mac_credit_cnt_s cn66xx; 3341232812Sjmallett struct cvmx_sli_mac_credit_cnt_s cn68xx; 3342232812Sjmallett struct cvmx_sli_mac_credit_cnt_s cn68xxp1; 3343232812Sjmallett struct cvmx_sli_mac_credit_cnt_s cnf71xx; 3344215976Sjmallett}; 3345215976Sjmalletttypedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t; 3346215976Sjmallett 3347215976Sjmallett/** 3348232812Sjmallett * cvmx_sli_mac_credit_cnt2 3349232812Sjmallett * 3350232812Sjmallett * SLI_MAC_CREDIT_CNT2 = SLI MAC Credit Count2 3351232812Sjmallett * 3352232812Sjmallett * Contains the number of credits for the MAC port FIFOs (for MACs 2 and 3) used by the SLI. This value needs to be set BEFORE S2M traffic 3353232812Sjmallett * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value 3354232812Sjmallett * in this register. 3355232812Sjmallett */ 3356232812Sjmallettunion cvmx_sli_mac_credit_cnt2 { 3357232812Sjmallett uint64_t u64; 3358232812Sjmallett struct cvmx_sli_mac_credit_cnt2_s { 3359232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3360232812Sjmallett uint64_t reserved_54_63 : 10; 3361232812Sjmallett uint64_t p3_c_d : 1; /**< When set does not allow writing of P3_CCNT. */ 3362232812Sjmallett uint64_t p3_n_d : 1; /**< When set does not allow writing of P3_NCNT. */ 3363232812Sjmallett uint64_t p3_p_d : 1; /**< When set does not allow writing of P3_PCNT. */ 3364232812Sjmallett uint64_t p2_c_d : 1; /**< When set does not allow writing of P2_CCNT. */ 3365232812Sjmallett uint64_t p2_n_d : 1; /**< When set does not allow writing of P2_NCNT. */ 3366232812Sjmallett uint64_t p2_p_d : 1; /**< When set does not allow writing of P2_PCNT. */ 3367232812Sjmallett uint64_t p3_ccnt : 8; /**< Port3 C-TLP FIFO Credits. 3368232812Sjmallett Legal values are 0x25 to 0x80. */ 3369232812Sjmallett uint64_t p3_ncnt : 8; /**< Port3 N-TLP FIFO Credits. 3370232812Sjmallett Legal values are 0x5 to 0x10. */ 3371232812Sjmallett uint64_t p3_pcnt : 8; /**< Port3 P-TLP FIFO Credits. 3372232812Sjmallett Legal values are 0x25 to 0x80. */ 3373232812Sjmallett uint64_t p2_ccnt : 8; /**< Port2 C-TLP FIFO Credits. 3374232812Sjmallett Legal values are 0x25 to 0x80. */ 3375232812Sjmallett uint64_t p2_ncnt : 8; /**< Port2 N-TLP FIFO Credits. 3376232812Sjmallett Legal values are 0x5 to 0x10. */ 3377232812Sjmallett uint64_t p2_pcnt : 8; /**< Port2 P-TLP FIFO Credits. 3378232812Sjmallett Legal values are 0x25 to 0x80. */ 3379232812Sjmallett#else 3380232812Sjmallett uint64_t p2_pcnt : 8; 3381232812Sjmallett uint64_t p2_ncnt : 8; 3382232812Sjmallett uint64_t p2_ccnt : 8; 3383232812Sjmallett uint64_t p3_pcnt : 8; 3384232812Sjmallett uint64_t p3_ncnt : 8; 3385232812Sjmallett uint64_t p3_ccnt : 8; 3386232812Sjmallett uint64_t p2_p_d : 1; 3387232812Sjmallett uint64_t p2_n_d : 1; 3388232812Sjmallett uint64_t p2_c_d : 1; 3389232812Sjmallett uint64_t p3_p_d : 1; 3390232812Sjmallett uint64_t p3_n_d : 1; 3391232812Sjmallett uint64_t p3_c_d : 1; 3392232812Sjmallett uint64_t reserved_54_63 : 10; 3393232812Sjmallett#endif 3394232812Sjmallett } s; 3395232812Sjmallett struct cvmx_sli_mac_credit_cnt2_s cn61xx; 3396232812Sjmallett struct cvmx_sli_mac_credit_cnt2_s cn66xx; 3397232812Sjmallett struct cvmx_sli_mac_credit_cnt2_s cnf71xx; 3398232812Sjmallett}; 3399232812Sjmalletttypedef union cvmx_sli_mac_credit_cnt2 cvmx_sli_mac_credit_cnt2_t; 3400232812Sjmallett 3401232812Sjmallett/** 3402215976Sjmallett * cvmx_sli_mac_number 3403215976Sjmallett * 3404215976Sjmallett * 0x13DA0 - 0x13DF0 reserved for ports 2 - 7 3405215976Sjmallett * 3406215976Sjmallett * SLI_MAC_NUMBER = SLI MAC Number 3407215976Sjmallett * 3408215976Sjmallett * When read from a MAC port it returns the MAC's port number. 3409215976Sjmallett */ 3410232812Sjmallettunion cvmx_sli_mac_number { 3411215976Sjmallett uint64_t u64; 3412232812Sjmallett struct cvmx_sli_mac_number_s { 3413232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3414232812Sjmallett uint64_t reserved_9_63 : 55; 3415232812Sjmallett uint64_t a_mode : 1; /**< SLI in Authenticate Mode. */ 3416232812Sjmallett uint64_t num : 8; /**< The mac number. */ 3417232812Sjmallett#else 3418232812Sjmallett uint64_t num : 8; 3419232812Sjmallett uint64_t a_mode : 1; 3420232812Sjmallett uint64_t reserved_9_63 : 55; 3421232812Sjmallett#endif 3422232812Sjmallett } s; 3423232812Sjmallett struct cvmx_sli_mac_number_s cn61xx; 3424232812Sjmallett struct cvmx_sli_mac_number_cn63xx { 3425232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3426215976Sjmallett uint64_t reserved_8_63 : 56; 3427215976Sjmallett uint64_t num : 8; /**< The mac number. */ 3428215976Sjmallett#else 3429215976Sjmallett uint64_t num : 8; 3430215976Sjmallett uint64_t reserved_8_63 : 56; 3431215976Sjmallett#endif 3432232812Sjmallett } cn63xx; 3433232812Sjmallett struct cvmx_sli_mac_number_s cn66xx; 3434232812Sjmallett struct cvmx_sli_mac_number_cn63xx cn68xx; 3435232812Sjmallett struct cvmx_sli_mac_number_cn63xx cn68xxp1; 3436232812Sjmallett struct cvmx_sli_mac_number_s cnf71xx; 3437215976Sjmallett}; 3438215976Sjmalletttypedef union cvmx_sli_mac_number cvmx_sli_mac_number_t; 3439215976Sjmallett 3440215976Sjmallett/** 3441215976Sjmallett * cvmx_sli_mem_access_ctl 3442215976Sjmallett * 3443215976Sjmallett * SLI_MEM_ACCESS_CTL = SLI's Memory Access Control 3444215976Sjmallett * 3445215976Sjmallett * Contains control for access to the MAC address space. 3446215976Sjmallett */ 3447232812Sjmallettunion cvmx_sli_mem_access_ctl { 3448215976Sjmallett uint64_t u64; 3449232812Sjmallett struct cvmx_sli_mem_access_ctl_s { 3450232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3451215976Sjmallett uint64_t reserved_14_63 : 50; 3452215976Sjmallett uint64_t max_word : 4; /**< The maximum number of words to merge into a single 3453215976Sjmallett write operation from the PPs to the MAC. Legal 3454215976Sjmallett values are 1 to 16, where a '0' is treated as 16. */ 3455215976Sjmallett uint64_t timer : 10; /**< When the SLI starts a PP to MAC write it waits 3456215976Sjmallett no longer than the value of TIMER in eclks to 3457215976Sjmallett merge additional writes from the PPs into 1 3458215976Sjmallett large write. The values for this field is 1 to 3459215976Sjmallett 1024 where a value of '0' is treated as 1024. */ 3460215976Sjmallett#else 3461215976Sjmallett uint64_t timer : 10; 3462215976Sjmallett uint64_t max_word : 4; 3463215976Sjmallett uint64_t reserved_14_63 : 50; 3464215976Sjmallett#endif 3465215976Sjmallett } s; 3466232812Sjmallett struct cvmx_sli_mem_access_ctl_s cn61xx; 3467215976Sjmallett struct cvmx_sli_mem_access_ctl_s cn63xx; 3468215976Sjmallett struct cvmx_sli_mem_access_ctl_s cn63xxp1; 3469232812Sjmallett struct cvmx_sli_mem_access_ctl_s cn66xx; 3470232812Sjmallett struct cvmx_sli_mem_access_ctl_s cn68xx; 3471232812Sjmallett struct cvmx_sli_mem_access_ctl_s cn68xxp1; 3472232812Sjmallett struct cvmx_sli_mem_access_ctl_s cnf71xx; 3473215976Sjmallett}; 3474215976Sjmalletttypedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t; 3475215976Sjmallett 3476215976Sjmallett/** 3477215976Sjmallett * cvmx_sli_mem_access_subid# 3478215976Sjmallett * 3479215976Sjmallett * // * 3480215976Sjmallett * // * 8070 - 80C0 saved for ports 2 through 7 3481215976Sjmallett * // * 3482215976Sjmallett * // * 3483215976Sjmallett * // * 0x80d0 free 3484215976Sjmallett * // * 3485215976Sjmallett * 3486215976Sjmallett * SLI_MEM_ACCESS_SUBIDX = SLI Memory Access SubidX Register 3487215976Sjmallett * 3488215976Sjmallett * Contains address index and control bits for access to memory from Core PPs. 3489215976Sjmallett */ 3490232812Sjmallettunion cvmx_sli_mem_access_subidx { 3491215976Sjmallett uint64_t u64; 3492232812Sjmallett struct cvmx_sli_mem_access_subidx_s { 3493232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3494215976Sjmallett uint64_t reserved_43_63 : 21; 3495215976Sjmallett uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 3496215976Sjmallett Returns to the EXEC a zero for all read data. 3497215976Sjmallett This must be zero for sRIO ports. */ 3498215976Sjmallett uint64_t port : 3; /**< Physical MAC Port that reads/writes to 3499215976Sjmallett this subid are sent to. Must be <= 1, as there are 3500215976Sjmallett only two ports present. */ 3501215976Sjmallett uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */ 3502215976Sjmallett uint64_t esr : 2; /**< ES<1:0> for reads to this subid. 3503215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3504215976Sjmallett memory space reads. */ 3505215976Sjmallett uint64_t esw : 2; /**< ES<1:0> for writes to this subid. 3506215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3507215976Sjmallett memory space writes. */ 3508215976Sjmallett uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid 3509215976Sjmallett For PCIe: 3510215976Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3511215976Sjmallett - ADDRTYPE<1> is the no-snoop attribute 3512215976Sjmallett For sRIO: 3513215976Sjmallett - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 3514215976Sjmallett entry */ 3515215976Sjmallett uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid 3516215976Sjmallett For PCIe: 3517215976Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3518215976Sjmallett - ADDRTYPE<1> is the no-snoop attribute 3519215976Sjmallett For sRIO: 3520215976Sjmallett - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 3521215976Sjmallett entry */ 3522232812Sjmallett uint64_t reserved_0_29 : 30; 3523232812Sjmallett#else 3524232812Sjmallett uint64_t reserved_0_29 : 30; 3525232812Sjmallett uint64_t rtype : 2; 3526232812Sjmallett uint64_t wtype : 2; 3527232812Sjmallett uint64_t esw : 2; 3528232812Sjmallett uint64_t esr : 2; 3529232812Sjmallett uint64_t nmerge : 1; 3530232812Sjmallett uint64_t port : 3; 3531232812Sjmallett uint64_t zero : 1; 3532232812Sjmallett uint64_t reserved_43_63 : 21; 3533232812Sjmallett#endif 3534232812Sjmallett } s; 3535232812Sjmallett struct cvmx_sli_mem_access_subidx_cn61xx { 3536232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3537232812Sjmallett uint64_t reserved_43_63 : 21; 3538232812Sjmallett uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 3539232812Sjmallett Returns to the EXEC a zero for all read data. 3540232812Sjmallett This must be zero for sRIO ports. */ 3541232812Sjmallett uint64_t port : 3; /**< Physical MAC Port that reads/writes to 3542232812Sjmallett this subid are sent to. Must be <= 1, as there are 3543232812Sjmallett only two ports present. */ 3544232812Sjmallett uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */ 3545232812Sjmallett uint64_t esr : 2; /**< ES<1:0> for reads to this subid. 3546232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3547232812Sjmallett memory space reads. */ 3548232812Sjmallett uint64_t esw : 2; /**< ES<1:0> for writes to this subid. 3549232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3550232812Sjmallett memory space writes. */ 3551232812Sjmallett uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid 3552232812Sjmallett For PCIe: 3553232812Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3554232812Sjmallett - ADDRTYPE<1> is the no-snoop attribute 3555232812Sjmallett For sRIO: 3556232812Sjmallett - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 3557232812Sjmallett entry */ 3558232812Sjmallett uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid 3559232812Sjmallett For PCIe: 3560232812Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3561232812Sjmallett - ADDRTYPE<1> is the no-snoop attribute 3562232812Sjmallett For sRIO: 3563232812Sjmallett - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 3564232812Sjmallett entry */ 3565215976Sjmallett uint64_t ba : 30; /**< Address Bits <63:34> for reads/writes that use 3566215976Sjmallett this subid. */ 3567215976Sjmallett#else 3568215976Sjmallett uint64_t ba : 30; 3569215976Sjmallett uint64_t rtype : 2; 3570215976Sjmallett uint64_t wtype : 2; 3571215976Sjmallett uint64_t esw : 2; 3572215976Sjmallett uint64_t esr : 2; 3573215976Sjmallett uint64_t nmerge : 1; 3574215976Sjmallett uint64_t port : 3; 3575215976Sjmallett uint64_t zero : 1; 3576215976Sjmallett uint64_t reserved_43_63 : 21; 3577215976Sjmallett#endif 3578232812Sjmallett } cn61xx; 3579232812Sjmallett struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; 3580232812Sjmallett struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; 3581232812Sjmallett struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; 3582232812Sjmallett struct cvmx_sli_mem_access_subidx_cn68xx { 3583232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3584232812Sjmallett uint64_t reserved_43_63 : 21; 3585232812Sjmallett uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 3586232812Sjmallett Returns to the EXEC a zero for all read data. 3587232812Sjmallett This must be zero for sRIO ports. */ 3588232812Sjmallett uint64_t port : 3; /**< Physical MAC Port that reads/writes to 3589232812Sjmallett this subid are sent to. Must be <= 1, as there are 3590232812Sjmallett only two ports present. */ 3591232812Sjmallett uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */ 3592232812Sjmallett uint64_t esr : 2; /**< ES<1:0> for reads to this subid. 3593232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3594232812Sjmallett memory space reads. */ 3595232812Sjmallett uint64_t esw : 2; /**< ES<1:0> for writes to this subid. 3596232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 3597232812Sjmallett memory space writes. */ 3598232812Sjmallett uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid 3599232812Sjmallett For PCIe: 3600232812Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3601232812Sjmallett - ADDRTYPE<1> is the no-snoop attribute */ 3602232812Sjmallett uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid 3603232812Sjmallett For PCIe: 3604232812Sjmallett - ADDRTYPE<0> is the relaxed-order attribute 3605232812Sjmallett - ADDRTYPE<1> is the no-snoop attribute */ 3606232812Sjmallett uint64_t ba : 28; /**< Address Bits <63:36> for reads/writes that use 3607232812Sjmallett this subid. */ 3608232812Sjmallett uint64_t reserved_0_1 : 2; 3609232812Sjmallett#else 3610232812Sjmallett uint64_t reserved_0_1 : 2; 3611232812Sjmallett uint64_t ba : 28; 3612232812Sjmallett uint64_t rtype : 2; 3613232812Sjmallett uint64_t wtype : 2; 3614232812Sjmallett uint64_t esw : 2; 3615232812Sjmallett uint64_t esr : 2; 3616232812Sjmallett uint64_t nmerge : 1; 3617232812Sjmallett uint64_t port : 3; 3618232812Sjmallett uint64_t zero : 1; 3619232812Sjmallett uint64_t reserved_43_63 : 21; 3620232812Sjmallett#endif 3621232812Sjmallett } cn68xx; 3622232812Sjmallett struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; 3623232812Sjmallett struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; 3624215976Sjmallett}; 3625215976Sjmalletttypedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t; 3626215976Sjmallett 3627215976Sjmallett/** 3628215976Sjmallett * cvmx_sli_msi_enb0 3629215976Sjmallett * 3630215976Sjmallett * SLI_MSI_ENB0 = SLI MSI Enable0 3631215976Sjmallett * 3632215976Sjmallett * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0. 3633215976Sjmallett */ 3634232812Sjmallettunion cvmx_sli_msi_enb0 { 3635215976Sjmallett uint64_t u64; 3636232812Sjmallett struct cvmx_sli_msi_enb0_s { 3637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3638215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */ 3639215976Sjmallett#else 3640215976Sjmallett uint64_t enb : 64; 3641215976Sjmallett#endif 3642215976Sjmallett } s; 3643232812Sjmallett struct cvmx_sli_msi_enb0_s cn61xx; 3644215976Sjmallett struct cvmx_sli_msi_enb0_s cn63xx; 3645215976Sjmallett struct cvmx_sli_msi_enb0_s cn63xxp1; 3646232812Sjmallett struct cvmx_sli_msi_enb0_s cn66xx; 3647232812Sjmallett struct cvmx_sli_msi_enb0_s cn68xx; 3648232812Sjmallett struct cvmx_sli_msi_enb0_s cn68xxp1; 3649232812Sjmallett struct cvmx_sli_msi_enb0_s cnf71xx; 3650215976Sjmallett}; 3651215976Sjmalletttypedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t; 3652215976Sjmallett 3653215976Sjmallett/** 3654215976Sjmallett * cvmx_sli_msi_enb1 3655215976Sjmallett * 3656215976Sjmallett * SLI_MSI_ENB1 = SLI MSI Enable1 3657215976Sjmallett * 3658215976Sjmallett * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1. 3659215976Sjmallett */ 3660232812Sjmallettunion cvmx_sli_msi_enb1 { 3661215976Sjmallett uint64_t u64; 3662232812Sjmallett struct cvmx_sli_msi_enb1_s { 3663232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3664215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */ 3665215976Sjmallett#else 3666215976Sjmallett uint64_t enb : 64; 3667215976Sjmallett#endif 3668215976Sjmallett } s; 3669232812Sjmallett struct cvmx_sli_msi_enb1_s cn61xx; 3670215976Sjmallett struct cvmx_sli_msi_enb1_s cn63xx; 3671215976Sjmallett struct cvmx_sli_msi_enb1_s cn63xxp1; 3672232812Sjmallett struct cvmx_sli_msi_enb1_s cn66xx; 3673232812Sjmallett struct cvmx_sli_msi_enb1_s cn68xx; 3674232812Sjmallett struct cvmx_sli_msi_enb1_s cn68xxp1; 3675232812Sjmallett struct cvmx_sli_msi_enb1_s cnf71xx; 3676215976Sjmallett}; 3677215976Sjmalletttypedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t; 3678215976Sjmallett 3679215976Sjmallett/** 3680215976Sjmallett * cvmx_sli_msi_enb2 3681215976Sjmallett * 3682215976Sjmallett * SLI_MSI_ENB2 = SLI MSI Enable2 3683215976Sjmallett * 3684215976Sjmallett * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2. 3685215976Sjmallett */ 3686232812Sjmallettunion cvmx_sli_msi_enb2 { 3687215976Sjmallett uint64_t u64; 3688232812Sjmallett struct cvmx_sli_msi_enb2_s { 3689232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3690215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */ 3691215976Sjmallett#else 3692215976Sjmallett uint64_t enb : 64; 3693215976Sjmallett#endif 3694215976Sjmallett } s; 3695232812Sjmallett struct cvmx_sli_msi_enb2_s cn61xx; 3696215976Sjmallett struct cvmx_sli_msi_enb2_s cn63xx; 3697215976Sjmallett struct cvmx_sli_msi_enb2_s cn63xxp1; 3698232812Sjmallett struct cvmx_sli_msi_enb2_s cn66xx; 3699232812Sjmallett struct cvmx_sli_msi_enb2_s cn68xx; 3700232812Sjmallett struct cvmx_sli_msi_enb2_s cn68xxp1; 3701232812Sjmallett struct cvmx_sli_msi_enb2_s cnf71xx; 3702215976Sjmallett}; 3703215976Sjmalletttypedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t; 3704215976Sjmallett 3705215976Sjmallett/** 3706215976Sjmallett * cvmx_sli_msi_enb3 3707215976Sjmallett * 3708215976Sjmallett * SLI_MSI_ENB3 = SLI MSI Enable3 3709215976Sjmallett * 3710215976Sjmallett * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3. 3711215976Sjmallett */ 3712232812Sjmallettunion cvmx_sli_msi_enb3 { 3713215976Sjmallett uint64_t u64; 3714232812Sjmallett struct cvmx_sli_msi_enb3_s { 3715232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3716215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */ 3717215976Sjmallett#else 3718215976Sjmallett uint64_t enb : 64; 3719215976Sjmallett#endif 3720215976Sjmallett } s; 3721232812Sjmallett struct cvmx_sli_msi_enb3_s cn61xx; 3722215976Sjmallett struct cvmx_sli_msi_enb3_s cn63xx; 3723215976Sjmallett struct cvmx_sli_msi_enb3_s cn63xxp1; 3724232812Sjmallett struct cvmx_sli_msi_enb3_s cn66xx; 3725232812Sjmallett struct cvmx_sli_msi_enb3_s cn68xx; 3726232812Sjmallett struct cvmx_sli_msi_enb3_s cn68xxp1; 3727232812Sjmallett struct cvmx_sli_msi_enb3_s cnf71xx; 3728215976Sjmallett}; 3729215976Sjmalletttypedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t; 3730215976Sjmallett 3731215976Sjmallett/** 3732215976Sjmallett * cvmx_sli_msi_rcv0 3733215976Sjmallett * 3734215976Sjmallett * SLI_MSI_RCV0 = SLI MSI Receive0 3735215976Sjmallett * 3736215976Sjmallett * Contains bits [63:0] of the 256 bits of MSI interrupts. 3737215976Sjmallett */ 3738232812Sjmallettunion cvmx_sli_msi_rcv0 { 3739215976Sjmallett uint64_t u64; 3740232812Sjmallett struct cvmx_sli_msi_rcv0_s { 3741232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3742215976Sjmallett uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */ 3743215976Sjmallett#else 3744215976Sjmallett uint64_t intr : 64; 3745215976Sjmallett#endif 3746215976Sjmallett } s; 3747232812Sjmallett struct cvmx_sli_msi_rcv0_s cn61xx; 3748215976Sjmallett struct cvmx_sli_msi_rcv0_s cn63xx; 3749215976Sjmallett struct cvmx_sli_msi_rcv0_s cn63xxp1; 3750232812Sjmallett struct cvmx_sli_msi_rcv0_s cn66xx; 3751232812Sjmallett struct cvmx_sli_msi_rcv0_s cn68xx; 3752232812Sjmallett struct cvmx_sli_msi_rcv0_s cn68xxp1; 3753232812Sjmallett struct cvmx_sli_msi_rcv0_s cnf71xx; 3754215976Sjmallett}; 3755215976Sjmalletttypedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t; 3756215976Sjmallett 3757215976Sjmallett/** 3758215976Sjmallett * cvmx_sli_msi_rcv1 3759215976Sjmallett * 3760215976Sjmallett * SLI_MSI_RCV1 = SLI MSI Receive1 3761215976Sjmallett * 3762215976Sjmallett * Contains bits [127:64] of the 256 bits of MSI interrupts. 3763215976Sjmallett */ 3764232812Sjmallettunion cvmx_sli_msi_rcv1 { 3765215976Sjmallett uint64_t u64; 3766232812Sjmallett struct cvmx_sli_msi_rcv1_s { 3767232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3768215976Sjmallett uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */ 3769215976Sjmallett#else 3770215976Sjmallett uint64_t intr : 64; 3771215976Sjmallett#endif 3772215976Sjmallett } s; 3773232812Sjmallett struct cvmx_sli_msi_rcv1_s cn61xx; 3774215976Sjmallett struct cvmx_sli_msi_rcv1_s cn63xx; 3775215976Sjmallett struct cvmx_sli_msi_rcv1_s cn63xxp1; 3776232812Sjmallett struct cvmx_sli_msi_rcv1_s cn66xx; 3777232812Sjmallett struct cvmx_sli_msi_rcv1_s cn68xx; 3778232812Sjmallett struct cvmx_sli_msi_rcv1_s cn68xxp1; 3779232812Sjmallett struct cvmx_sli_msi_rcv1_s cnf71xx; 3780215976Sjmallett}; 3781215976Sjmalletttypedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t; 3782215976Sjmallett 3783215976Sjmallett/** 3784215976Sjmallett * cvmx_sli_msi_rcv2 3785215976Sjmallett * 3786215976Sjmallett * SLI_MSI_RCV2 = SLI MSI Receive2 3787215976Sjmallett * 3788215976Sjmallett * Contains bits [191:128] of the 256 bits of MSI interrupts. 3789215976Sjmallett */ 3790232812Sjmallettunion cvmx_sli_msi_rcv2 { 3791215976Sjmallett uint64_t u64; 3792232812Sjmallett struct cvmx_sli_msi_rcv2_s { 3793232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3794215976Sjmallett uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */ 3795215976Sjmallett#else 3796215976Sjmallett uint64_t intr : 64; 3797215976Sjmallett#endif 3798215976Sjmallett } s; 3799232812Sjmallett struct cvmx_sli_msi_rcv2_s cn61xx; 3800215976Sjmallett struct cvmx_sli_msi_rcv2_s cn63xx; 3801215976Sjmallett struct cvmx_sli_msi_rcv2_s cn63xxp1; 3802232812Sjmallett struct cvmx_sli_msi_rcv2_s cn66xx; 3803232812Sjmallett struct cvmx_sli_msi_rcv2_s cn68xx; 3804232812Sjmallett struct cvmx_sli_msi_rcv2_s cn68xxp1; 3805232812Sjmallett struct cvmx_sli_msi_rcv2_s cnf71xx; 3806215976Sjmallett}; 3807215976Sjmalletttypedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t; 3808215976Sjmallett 3809215976Sjmallett/** 3810215976Sjmallett * cvmx_sli_msi_rcv3 3811215976Sjmallett * 3812215976Sjmallett * SLI_MSI_RCV3 = SLI MSI Receive3 3813215976Sjmallett * 3814215976Sjmallett * Contains bits [255:192] of the 256 bits of MSI interrupts. 3815215976Sjmallett */ 3816232812Sjmallettunion cvmx_sli_msi_rcv3 { 3817215976Sjmallett uint64_t u64; 3818232812Sjmallett struct cvmx_sli_msi_rcv3_s { 3819232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3820215976Sjmallett uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */ 3821215976Sjmallett#else 3822215976Sjmallett uint64_t intr : 64; 3823215976Sjmallett#endif 3824215976Sjmallett } s; 3825232812Sjmallett struct cvmx_sli_msi_rcv3_s cn61xx; 3826215976Sjmallett struct cvmx_sli_msi_rcv3_s cn63xx; 3827215976Sjmallett struct cvmx_sli_msi_rcv3_s cn63xxp1; 3828232812Sjmallett struct cvmx_sli_msi_rcv3_s cn66xx; 3829232812Sjmallett struct cvmx_sli_msi_rcv3_s cn68xx; 3830232812Sjmallett struct cvmx_sli_msi_rcv3_s cn68xxp1; 3831232812Sjmallett struct cvmx_sli_msi_rcv3_s cnf71xx; 3832215976Sjmallett}; 3833215976Sjmalletttypedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t; 3834215976Sjmallett 3835215976Sjmallett/** 3836215976Sjmallett * cvmx_sli_msi_rd_map 3837215976Sjmallett * 3838215976Sjmallett * SLI_MSI_RD_MAP = SLI MSI Read MAP 3839215976Sjmallett * 3840215976Sjmallett * Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers. 3841215976Sjmallett */ 3842232812Sjmallettunion cvmx_sli_msi_rd_map { 3843215976Sjmallett uint64_t u64; 3844232812Sjmallett struct cvmx_sli_msi_rd_map_s { 3845232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3846215976Sjmallett uint64_t reserved_16_63 : 48; 3847215976Sjmallett uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY 3848215976Sjmallett written to the MSI_INT field of this register. */ 3849215976Sjmallett uint64_t msi_int : 8; /**< Selects the value that would be received when the 3850215976Sjmallett SLI_PCIE_MSI_RCV register is written. */ 3851215976Sjmallett#else 3852215976Sjmallett uint64_t msi_int : 8; 3853215976Sjmallett uint64_t rd_int : 8; 3854215976Sjmallett uint64_t reserved_16_63 : 48; 3855215976Sjmallett#endif 3856215976Sjmallett } s; 3857232812Sjmallett struct cvmx_sli_msi_rd_map_s cn61xx; 3858215976Sjmallett struct cvmx_sli_msi_rd_map_s cn63xx; 3859215976Sjmallett struct cvmx_sli_msi_rd_map_s cn63xxp1; 3860232812Sjmallett struct cvmx_sli_msi_rd_map_s cn66xx; 3861232812Sjmallett struct cvmx_sli_msi_rd_map_s cn68xx; 3862232812Sjmallett struct cvmx_sli_msi_rd_map_s cn68xxp1; 3863232812Sjmallett struct cvmx_sli_msi_rd_map_s cnf71xx; 3864215976Sjmallett}; 3865215976Sjmalletttypedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t; 3866215976Sjmallett 3867215976Sjmallett/** 3868215976Sjmallett * cvmx_sli_msi_w1c_enb0 3869215976Sjmallett * 3870215976Sjmallett * SLI_MSI_W1C_ENB0 = SLI MSI Write 1 To Clear Enable0 3871215976Sjmallett * 3872215976Sjmallett * Used to clear bits in SLI_MSI_ENB0. 3873215976Sjmallett */ 3874232812Sjmallettunion cvmx_sli_msi_w1c_enb0 { 3875215976Sjmallett uint64_t u64; 3876232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s { 3877232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3878215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 3879215976Sjmallett cooresponding bit in SLI_MSI_ENB0. 3880215976Sjmallett A read to this address will return 0. */ 3881215976Sjmallett#else 3882215976Sjmallett uint64_t clr : 64; 3883215976Sjmallett#endif 3884215976Sjmallett } s; 3885232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn61xx; 3886215976Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn63xx; 3887215976Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn63xxp1; 3888232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn66xx; 3889232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn68xx; 3890232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; 3891232812Sjmallett struct cvmx_sli_msi_w1c_enb0_s cnf71xx; 3892215976Sjmallett}; 3893215976Sjmalletttypedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t; 3894215976Sjmallett 3895215976Sjmallett/** 3896215976Sjmallett * cvmx_sli_msi_w1c_enb1 3897215976Sjmallett * 3898215976Sjmallett * SLI_MSI_W1C_ENB1 = SLI MSI Write 1 To Clear Enable1 3899215976Sjmallett * 3900215976Sjmallett * Used to clear bits in SLI_MSI_ENB1. 3901215976Sjmallett */ 3902232812Sjmallettunion cvmx_sli_msi_w1c_enb1 { 3903215976Sjmallett uint64_t u64; 3904232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s { 3905232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3906215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 3907215976Sjmallett cooresponding bit in SLI_MSI_ENB1. 3908215976Sjmallett A read to this address will return 0. */ 3909215976Sjmallett#else 3910215976Sjmallett uint64_t clr : 64; 3911215976Sjmallett#endif 3912215976Sjmallett } s; 3913232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn61xx; 3914215976Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn63xx; 3915215976Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn63xxp1; 3916232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn66xx; 3917232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn68xx; 3918232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; 3919232812Sjmallett struct cvmx_sli_msi_w1c_enb1_s cnf71xx; 3920215976Sjmallett}; 3921215976Sjmalletttypedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t; 3922215976Sjmallett 3923215976Sjmallett/** 3924215976Sjmallett * cvmx_sli_msi_w1c_enb2 3925215976Sjmallett * 3926215976Sjmallett * SLI_MSI_W1C_ENB2 = SLI MSI Write 1 To Clear Enable2 3927215976Sjmallett * 3928215976Sjmallett * Used to clear bits in SLI_MSI_ENB2. 3929215976Sjmallett */ 3930232812Sjmallettunion cvmx_sli_msi_w1c_enb2 { 3931215976Sjmallett uint64_t u64; 3932232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s { 3933232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3934215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 3935215976Sjmallett cooresponding bit in SLI_MSI_ENB2. 3936215976Sjmallett A read to this address will return 0. */ 3937215976Sjmallett#else 3938215976Sjmallett uint64_t clr : 64; 3939215976Sjmallett#endif 3940215976Sjmallett } s; 3941232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn61xx; 3942215976Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn63xx; 3943215976Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn63xxp1; 3944232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn66xx; 3945232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn68xx; 3946232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; 3947232812Sjmallett struct cvmx_sli_msi_w1c_enb2_s cnf71xx; 3948215976Sjmallett}; 3949215976Sjmalletttypedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t; 3950215976Sjmallett 3951215976Sjmallett/** 3952215976Sjmallett * cvmx_sli_msi_w1c_enb3 3953215976Sjmallett * 3954215976Sjmallett * SLI_MSI_W1C_ENB3 = SLI MSI Write 1 To Clear Enable3 3955215976Sjmallett * 3956215976Sjmallett * Used to clear bits in SLI_MSI_ENB3. 3957215976Sjmallett */ 3958232812Sjmallettunion cvmx_sli_msi_w1c_enb3 { 3959215976Sjmallett uint64_t u64; 3960232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s { 3961232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3962215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 3963215976Sjmallett cooresponding bit in SLI_MSI_ENB3. 3964215976Sjmallett A read to this address will return 0. */ 3965215976Sjmallett#else 3966215976Sjmallett uint64_t clr : 64; 3967215976Sjmallett#endif 3968215976Sjmallett } s; 3969232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn61xx; 3970215976Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn63xx; 3971215976Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn63xxp1; 3972232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn66xx; 3973232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn68xx; 3974232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; 3975232812Sjmallett struct cvmx_sli_msi_w1c_enb3_s cnf71xx; 3976215976Sjmallett}; 3977215976Sjmalletttypedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t; 3978215976Sjmallett 3979215976Sjmallett/** 3980215976Sjmallett * cvmx_sli_msi_w1s_enb0 3981215976Sjmallett * 3982215976Sjmallett * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable0 3983215976Sjmallett * 3984215976Sjmallett * Used to set bits in SLI_MSI_ENB0. 3985215976Sjmallett */ 3986232812Sjmallettunion cvmx_sli_msi_w1s_enb0 { 3987215976Sjmallett uint64_t u64; 3988232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s { 3989232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3990215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 3991215976Sjmallett cooresponding bit in SLI_MSI_ENB0. 3992215976Sjmallett A read to this address will return 0. */ 3993215976Sjmallett#else 3994215976Sjmallett uint64_t set : 64; 3995215976Sjmallett#endif 3996215976Sjmallett } s; 3997232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn61xx; 3998215976Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn63xx; 3999215976Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn63xxp1; 4000232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn66xx; 4001232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn68xx; 4002232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; 4003232812Sjmallett struct cvmx_sli_msi_w1s_enb0_s cnf71xx; 4004215976Sjmallett}; 4005215976Sjmalletttypedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t; 4006215976Sjmallett 4007215976Sjmallett/** 4008215976Sjmallett * cvmx_sli_msi_w1s_enb1 4009215976Sjmallett * 4010215976Sjmallett * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1 4011215976Sjmallett * 4012215976Sjmallett * Used to set bits in SLI_MSI_ENB1. 4013215976Sjmallett */ 4014232812Sjmallettunion cvmx_sli_msi_w1s_enb1 { 4015215976Sjmallett uint64_t u64; 4016232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s { 4017232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4018215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 4019215976Sjmallett cooresponding bit in SLI_MSI_ENB1. 4020215976Sjmallett A read to this address will return 0. */ 4021215976Sjmallett#else 4022215976Sjmallett uint64_t set : 64; 4023215976Sjmallett#endif 4024215976Sjmallett } s; 4025232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn61xx; 4026215976Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn63xx; 4027215976Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn63xxp1; 4028232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn66xx; 4029232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn68xx; 4030232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; 4031232812Sjmallett struct cvmx_sli_msi_w1s_enb1_s cnf71xx; 4032215976Sjmallett}; 4033215976Sjmalletttypedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t; 4034215976Sjmallett 4035215976Sjmallett/** 4036215976Sjmallett * cvmx_sli_msi_w1s_enb2 4037215976Sjmallett * 4038215976Sjmallett * SLI_MSI_W1S_ENB2 = SLI MSI Write 1 To Set Enable2 4039215976Sjmallett * 4040215976Sjmallett * Used to set bits in SLI_MSI_ENB2. 4041215976Sjmallett */ 4042232812Sjmallettunion cvmx_sli_msi_w1s_enb2 { 4043215976Sjmallett uint64_t u64; 4044232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s { 4045232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4046215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 4047215976Sjmallett cooresponding bit in SLI_MSI_ENB2. 4048215976Sjmallett A read to this address will return 0. */ 4049215976Sjmallett#else 4050215976Sjmallett uint64_t set : 64; 4051215976Sjmallett#endif 4052215976Sjmallett } s; 4053232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn61xx; 4054215976Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn63xx; 4055215976Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn63xxp1; 4056232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn66xx; 4057232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn68xx; 4058232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; 4059232812Sjmallett struct cvmx_sli_msi_w1s_enb2_s cnf71xx; 4060215976Sjmallett}; 4061215976Sjmalletttypedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t; 4062215976Sjmallett 4063215976Sjmallett/** 4064215976Sjmallett * cvmx_sli_msi_w1s_enb3 4065215976Sjmallett * 4066215976Sjmallett * SLI_MSI_W1S_ENB3 = SLI MSI Write 1 To Set Enable3 4067215976Sjmallett * 4068215976Sjmallett * Used to set bits in SLI_MSI_ENB3. 4069215976Sjmallett */ 4070232812Sjmallettunion cvmx_sli_msi_w1s_enb3 { 4071215976Sjmallett uint64_t u64; 4072232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s { 4073232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4074215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 4075215976Sjmallett cooresponding bit in SLI_MSI_ENB3. 4076215976Sjmallett A read to this address will return 0. */ 4077215976Sjmallett#else 4078215976Sjmallett uint64_t set : 64; 4079215976Sjmallett#endif 4080215976Sjmallett } s; 4081232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn61xx; 4082215976Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn63xx; 4083215976Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn63xxp1; 4084232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn66xx; 4085232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn68xx; 4086232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; 4087232812Sjmallett struct cvmx_sli_msi_w1s_enb3_s cnf71xx; 4088215976Sjmallett}; 4089215976Sjmalletttypedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t; 4090215976Sjmallett 4091215976Sjmallett/** 4092215976Sjmallett * cvmx_sli_msi_wr_map 4093215976Sjmallett * 4094215976Sjmallett * SLI_MSI_WR_MAP = SLI MSI Write MAP 4095215976Sjmallett * 4096215976Sjmallett * Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers. 4097215976Sjmallett */ 4098232812Sjmallettunion cvmx_sli_msi_wr_map { 4099215976Sjmallett uint64_t u64; 4100232812Sjmallett struct cvmx_sli_msi_wr_map_s { 4101232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4102215976Sjmallett uint64_t reserved_16_63 : 48; 4103215976Sjmallett uint64_t ciu_int : 8; /**< Selects which bit in the SLI_MSI_RCV# (0-255) 4104215976Sjmallett will be set when the value specified in the 4105215976Sjmallett MSI_INT of this register is recevied during a 4106215976Sjmallett write to the SLI_PCIE_MSI_RCV register. */ 4107215976Sjmallett uint64_t msi_int : 8; /**< Selects the value that would be received when the 4108215976Sjmallett SLI_PCIE_MSI_RCV register is written. */ 4109215976Sjmallett#else 4110215976Sjmallett uint64_t msi_int : 8; 4111215976Sjmallett uint64_t ciu_int : 8; 4112215976Sjmallett uint64_t reserved_16_63 : 48; 4113215976Sjmallett#endif 4114215976Sjmallett } s; 4115232812Sjmallett struct cvmx_sli_msi_wr_map_s cn61xx; 4116215976Sjmallett struct cvmx_sli_msi_wr_map_s cn63xx; 4117215976Sjmallett struct cvmx_sli_msi_wr_map_s cn63xxp1; 4118232812Sjmallett struct cvmx_sli_msi_wr_map_s cn66xx; 4119232812Sjmallett struct cvmx_sli_msi_wr_map_s cn68xx; 4120232812Sjmallett struct cvmx_sli_msi_wr_map_s cn68xxp1; 4121232812Sjmallett struct cvmx_sli_msi_wr_map_s cnf71xx; 4122215976Sjmallett}; 4123215976Sjmalletttypedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t; 4124215976Sjmallett 4125215976Sjmallett/** 4126215976Sjmallett * cvmx_sli_pcie_msi_rcv 4127215976Sjmallett * 4128215976Sjmallett * SLI_PCIE_MSI_RCV = SLI MAC MSI Receive 4129215976Sjmallett * 4130215976Sjmallett * Register where MSI writes are directed from the MAC. 4131215976Sjmallett */ 4132232812Sjmallettunion cvmx_sli_pcie_msi_rcv { 4133215976Sjmallett uint64_t u64; 4134232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s { 4135232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4136215976Sjmallett uint64_t reserved_8_63 : 56; 4137215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 4138215976Sjmallett one of the SLI_MSI_RCV# registers being set. 4139215976Sjmallett Which bit is set is dependent on the previously 4140215976Sjmallett written using the SLI_MSI_WR_MAP register or if 4141215976Sjmallett not previously written the reset value of the MAP. */ 4142215976Sjmallett#else 4143215976Sjmallett uint64_t intr : 8; 4144215976Sjmallett uint64_t reserved_8_63 : 56; 4145215976Sjmallett#endif 4146215976Sjmallett } s; 4147232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn61xx; 4148215976Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn63xx; 4149215976Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn63xxp1; 4150232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn66xx; 4151232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn68xx; 4152232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; 4153232812Sjmallett struct cvmx_sli_pcie_msi_rcv_s cnf71xx; 4154215976Sjmallett}; 4155215976Sjmalletttypedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t; 4156215976Sjmallett 4157215976Sjmallett/** 4158215976Sjmallett * cvmx_sli_pcie_msi_rcv_b1 4159215976Sjmallett * 4160215976Sjmallett * SLI_PCIE_MSI_RCV_B1 = SLI MAC MSI Receive Byte 1 4161215976Sjmallett * 4162215976Sjmallett * Register where MSI writes are directed from the MAC. 4163215976Sjmallett * 4164215976Sjmallett * Notes: 4165215976Sjmallett * This CSR can be used by PCIe and sRIO MACs. 4166215976Sjmallett * 4167215976Sjmallett */ 4168232812Sjmallettunion cvmx_sli_pcie_msi_rcv_b1 { 4169215976Sjmallett uint64_t u64; 4170232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s { 4171232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4172215976Sjmallett uint64_t reserved_16_63 : 48; 4173215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 4174215976Sjmallett one of the SLI_MSI_RCV# registers being set. 4175215976Sjmallett Which bit is set is dependent on the previously 4176215976Sjmallett written using the SLI_MSI_WR_MAP register or if 4177215976Sjmallett not previously written the reset value of the MAP. */ 4178215976Sjmallett uint64_t reserved_0_7 : 8; 4179215976Sjmallett#else 4180215976Sjmallett uint64_t reserved_0_7 : 8; 4181215976Sjmallett uint64_t intr : 8; 4182215976Sjmallett uint64_t reserved_16_63 : 48; 4183215976Sjmallett#endif 4184215976Sjmallett } s; 4185232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; 4186215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; 4187215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1; 4188232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; 4189232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; 4190232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; 4191232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; 4192215976Sjmallett}; 4193215976Sjmalletttypedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t; 4194215976Sjmallett 4195215976Sjmallett/** 4196215976Sjmallett * cvmx_sli_pcie_msi_rcv_b2 4197215976Sjmallett * 4198215976Sjmallett * SLI_PCIE_MSI_RCV_B2 = SLI MAC MSI Receive Byte 2 4199215976Sjmallett * 4200215976Sjmallett * Register where MSI writes are directed from the MAC. 4201215976Sjmallett * 4202215976Sjmallett * Notes: 4203215976Sjmallett * This CSR can be used by PCIe and sRIO MACs. 4204215976Sjmallett * 4205215976Sjmallett */ 4206232812Sjmallettunion cvmx_sli_pcie_msi_rcv_b2 { 4207215976Sjmallett uint64_t u64; 4208232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s { 4209232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4210215976Sjmallett uint64_t reserved_24_63 : 40; 4211215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 4212215976Sjmallett one of the SLI_MSI_RCV# registers being set. 4213215976Sjmallett Which bit is set is dependent on the previously 4214215976Sjmallett written using the SLI_MSI_WR_MAP register or if 4215215976Sjmallett not previously written the reset value of the MAP. */ 4216215976Sjmallett uint64_t reserved_0_15 : 16; 4217215976Sjmallett#else 4218215976Sjmallett uint64_t reserved_0_15 : 16; 4219215976Sjmallett uint64_t intr : 8; 4220215976Sjmallett uint64_t reserved_24_63 : 40; 4221215976Sjmallett#endif 4222215976Sjmallett } s; 4223232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; 4224215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; 4225215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1; 4226232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; 4227232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; 4228232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; 4229232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; 4230215976Sjmallett}; 4231215976Sjmalletttypedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t; 4232215976Sjmallett 4233215976Sjmallett/** 4234215976Sjmallett * cvmx_sli_pcie_msi_rcv_b3 4235215976Sjmallett * 4236215976Sjmallett * SLI_PCIE_MSI_RCV_B3 = SLI MAC MSI Receive Byte 3 4237215976Sjmallett * 4238215976Sjmallett * Register where MSI writes are directed from the MAC. 4239215976Sjmallett * 4240215976Sjmallett * Notes: 4241215976Sjmallett * This CSR can be used by PCIe and sRIO MACs. 4242215976Sjmallett * 4243215976Sjmallett */ 4244232812Sjmallettunion cvmx_sli_pcie_msi_rcv_b3 { 4245215976Sjmallett uint64_t u64; 4246232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s { 4247232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4248215976Sjmallett uint64_t reserved_32_63 : 32; 4249215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 4250215976Sjmallett one of the SLI_MSI_RCV# registers being set. 4251215976Sjmallett Which bit is set is dependent on the previously 4252215976Sjmallett written using the SLI_MSI_WR_MAP register or if 4253215976Sjmallett not previously written the reset value of the MAP. */ 4254215976Sjmallett uint64_t reserved_0_23 : 24; 4255215976Sjmallett#else 4256215976Sjmallett uint64_t reserved_0_23 : 24; 4257215976Sjmallett uint64_t intr : 8; 4258215976Sjmallett uint64_t reserved_32_63 : 32; 4259215976Sjmallett#endif 4260215976Sjmallett } s; 4261232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; 4262215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; 4263215976Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1; 4264232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; 4265232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; 4266232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; 4267232812Sjmallett struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; 4268215976Sjmallett}; 4269215976Sjmalletttypedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t; 4270215976Sjmallett 4271215976Sjmallett/** 4272215976Sjmallett * cvmx_sli_pkt#_cnts 4273215976Sjmallett * 4274215976Sjmallett * SLI_PKT[0..31]_CNTS = SLI Packet ring# Counts 4275215976Sjmallett * 4276215976Sjmallett * The counters for output rings. 4277215976Sjmallett */ 4278232812Sjmallettunion cvmx_sli_pktx_cnts { 4279215976Sjmallett uint64_t u64; 4280232812Sjmallett struct cvmx_sli_pktx_cnts_s { 4281232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4282215976Sjmallett uint64_t reserved_54_63 : 10; 4283215976Sjmallett uint64_t timer : 22; /**< Timer incremented every 1024 core clocks 4284215976Sjmallett when SLI_PKTS#_CNTS[CNT] is non zero. Field 4285215976Sjmallett cleared when SLI_PKTS#_CNTS[CNT] goes to 0. 4286215976Sjmallett Field is also cleared when SLI_PKT_TIME_INT is 4287215976Sjmallett cleared. 4288215976Sjmallett The first increment of this count can occur 4289215976Sjmallett between 0 to 1023 core clocks. */ 4290215976Sjmallett uint64_t cnt : 32; /**< ring counter. This field is incremented as 4291215976Sjmallett packets are sent out and decremented in response to 4292215976Sjmallett writes to this field. 4293215976Sjmallett When SLI_PKT_OUT_BMODE is '0' a value of 1 is 4294215976Sjmallett added to the register for each packet, when '1' 4295215976Sjmallett and the info-pointer is NOT used the length of the 4296215976Sjmallett packet plus 8 is added, when '1' and info-pointer 4297215976Sjmallett mode IS used the packet length is added to this 4298215976Sjmallett field. */ 4299215976Sjmallett#else 4300215976Sjmallett uint64_t cnt : 32; 4301215976Sjmallett uint64_t timer : 22; 4302215976Sjmallett uint64_t reserved_54_63 : 10; 4303215976Sjmallett#endif 4304215976Sjmallett } s; 4305232812Sjmallett struct cvmx_sli_pktx_cnts_s cn61xx; 4306215976Sjmallett struct cvmx_sli_pktx_cnts_s cn63xx; 4307215976Sjmallett struct cvmx_sli_pktx_cnts_s cn63xxp1; 4308232812Sjmallett struct cvmx_sli_pktx_cnts_s cn66xx; 4309232812Sjmallett struct cvmx_sli_pktx_cnts_s cn68xx; 4310232812Sjmallett struct cvmx_sli_pktx_cnts_s cn68xxp1; 4311232812Sjmallett struct cvmx_sli_pktx_cnts_s cnf71xx; 4312215976Sjmallett}; 4313215976Sjmalletttypedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t; 4314215976Sjmallett 4315215976Sjmallett/** 4316215976Sjmallett * cvmx_sli_pkt#_in_bp 4317215976Sjmallett * 4318215976Sjmallett * SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure 4319215976Sjmallett * 4320215976Sjmallett * The counters and thresholds for input packets to apply backpressure to processing of the packets. 4321215976Sjmallett */ 4322232812Sjmallettunion cvmx_sli_pktx_in_bp { 4323215976Sjmallett uint64_t u64; 4324232812Sjmallett struct cvmx_sli_pktx_in_bp_s { 4325232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4326215976Sjmallett uint64_t wmark : 32; /**< When CNT is greater than this threshold no more 4327215976Sjmallett packets will be processed for this ring. 4328215976Sjmallett When writing this field of the SLI_PKT#_IN_BP 4329215976Sjmallett register, use a 4-byte write so as to not write 4330215976Sjmallett any other field of this register. */ 4331215976Sjmallett uint64_t cnt : 32; /**< ring counter. This field is incremented by one 4332215976Sjmallett whenever OCTEON receives, buffers, and creates a 4333215976Sjmallett work queue entry for a packet that arrives by the 4334215976Sjmallett cooresponding input ring. A write to this field 4335215976Sjmallett will be subtracted from the field value. 4336215976Sjmallett When writing this field of the SLI_PKT#_IN_BP 4337215976Sjmallett register, use a 4-byte write so as to not write 4338215976Sjmallett any other field of this register. */ 4339215976Sjmallett#else 4340215976Sjmallett uint64_t cnt : 32; 4341215976Sjmallett uint64_t wmark : 32; 4342215976Sjmallett#endif 4343215976Sjmallett } s; 4344232812Sjmallett struct cvmx_sli_pktx_in_bp_s cn61xx; 4345215976Sjmallett struct cvmx_sli_pktx_in_bp_s cn63xx; 4346215976Sjmallett struct cvmx_sli_pktx_in_bp_s cn63xxp1; 4347232812Sjmallett struct cvmx_sli_pktx_in_bp_s cn66xx; 4348232812Sjmallett struct cvmx_sli_pktx_in_bp_s cnf71xx; 4349215976Sjmallett}; 4350215976Sjmalletttypedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t; 4351215976Sjmallett 4352215976Sjmallett/** 4353215976Sjmallett * cvmx_sli_pkt#_instr_baddr 4354215976Sjmallett * 4355215976Sjmallett * SLI_PKT[0..31]_INSTR_BADDR = SLI Packet ring# Instruction Base Address 4356215976Sjmallett * 4357215976Sjmallett * Start of Instruction for input packets. 4358215976Sjmallett */ 4359232812Sjmallettunion cvmx_sli_pktx_instr_baddr { 4360215976Sjmallett uint64_t u64; 4361232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s { 4362232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4363215976Sjmallett uint64_t addr : 61; /**< Base address for Instructions. */ 4364215976Sjmallett uint64_t reserved_0_2 : 3; 4365215976Sjmallett#else 4366215976Sjmallett uint64_t reserved_0_2 : 3; 4367215976Sjmallett uint64_t addr : 61; 4368215976Sjmallett#endif 4369215976Sjmallett } s; 4370232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn61xx; 4371215976Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn63xx; 4372215976Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn63xxp1; 4373232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn66xx; 4374232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn68xx; 4375232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; 4376232812Sjmallett struct cvmx_sli_pktx_instr_baddr_s cnf71xx; 4377215976Sjmallett}; 4378215976Sjmalletttypedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t; 4379215976Sjmallett 4380215976Sjmallett/** 4381215976Sjmallett * cvmx_sli_pkt#_instr_baoff_dbell 4382215976Sjmallett * 4383215976Sjmallett * SLI_PKT[0..31]_INSTR_BAOFF_DBELL = SLI Packet ring# Instruction Base Address Offset and Doorbell 4384215976Sjmallett * 4385215976Sjmallett * The doorbell and base address offset for next read. 4386215976Sjmallett */ 4387232812Sjmallettunion cvmx_sli_pktx_instr_baoff_dbell { 4388215976Sjmallett uint64_t u64; 4389232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s { 4390232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4391215976Sjmallett uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR 4392215976Sjmallett where the next instruction will be read. */ 4393215976Sjmallett uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field 4394215976Sjmallett will increment the value here. Reads will return 4395215976Sjmallett present value. A write of 0xffffffff will set the 4396215976Sjmallett DBELL and AOFF fields to '0'. */ 4397215976Sjmallett#else 4398215976Sjmallett uint64_t dbell : 32; 4399215976Sjmallett uint64_t aoff : 32; 4400215976Sjmallett#endif 4401215976Sjmallett } s; 4402232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; 4403215976Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; 4404215976Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1; 4405232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; 4406232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; 4407232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; 4408232812Sjmallett struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; 4409215976Sjmallett}; 4410215976Sjmalletttypedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t; 4411215976Sjmallett 4412215976Sjmallett/** 4413215976Sjmallett * cvmx_sli_pkt#_instr_fifo_rsize 4414215976Sjmallett * 4415215976Sjmallett * SLI_PKT[0..31]_INSTR_FIFO_RSIZE = SLI Packet ring# Instruction FIFO and Ring Size. 4416215976Sjmallett * 4417215976Sjmallett * Fifo field and ring size for Instructions. 4418215976Sjmallett */ 4419232812Sjmallettunion cvmx_sli_pktx_instr_fifo_rsize { 4420215976Sjmallett uint64_t u64; 4421232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s { 4422232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4423215976Sjmallett uint64_t max : 9; /**< Max Fifo Size. */ 4424215976Sjmallett uint64_t rrp : 9; /**< Fifo read pointer. */ 4425215976Sjmallett uint64_t wrp : 9; /**< Fifo write pointer. */ 4426215976Sjmallett uint64_t fcnt : 5; /**< Fifo count. */ 4427215976Sjmallett uint64_t rsize : 32; /**< Instruction ring size. */ 4428215976Sjmallett#else 4429215976Sjmallett uint64_t rsize : 32; 4430215976Sjmallett uint64_t fcnt : 5; 4431215976Sjmallett uint64_t wrp : 9; 4432215976Sjmallett uint64_t rrp : 9; 4433215976Sjmallett uint64_t max : 9; 4434215976Sjmallett#endif 4435215976Sjmallett } s; 4436232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; 4437215976Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; 4438215976Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1; 4439232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; 4440232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; 4441232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; 4442232812Sjmallett struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; 4443215976Sjmallett}; 4444215976Sjmalletttypedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t; 4445215976Sjmallett 4446215976Sjmallett/** 4447215976Sjmallett * cvmx_sli_pkt#_instr_header 4448215976Sjmallett * 4449215976Sjmallett * SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header. 4450215976Sjmallett * 4451215976Sjmallett * VAlues used to build input packet header. 4452215976Sjmallett */ 4453232812Sjmallettunion cvmx_sli_pktx_instr_header { 4454215976Sjmallett uint64_t u64; 4455232812Sjmallett struct cvmx_sli_pktx_instr_header_s { 4456232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4457215976Sjmallett uint64_t reserved_44_63 : 20; 4458232812Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. 4459232812Sjmallett Allows DPI to generate PKT_INST_HDR[PM,SL] 4460232812Sjmallett differently per DPI instruction. 4461232812Sjmallett USE_IHDR must be set whenever PBP is set. */ 4462215976Sjmallett uint64_t reserved_38_42 : 5; 4463232812Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM] 4464232812Sjmallett when DPI_INST_HDR[R]==1 and PBP==0 */ 4465215976Sjmallett uint64_t reserved_35_35 : 1; 4466232812Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL] 4467232812Sjmallett when DPI_INST_HDR[R]==1 and PBP==0 */ 4468232812Sjmallett uint64_t rngrpext : 2; /**< Becomes PKT_INST_HDR[GRPEXT] 4469232812Sjmallett when DPI_INST_HDR[R]==1 */ 4470232812Sjmallett uint64_t rnqos : 1; /**< Becomes PKT_INST_HDR[NQOS] 4471232812Sjmallett when DPI_INST_HDR[R]==1 */ 4472232812Sjmallett uint64_t rngrp : 1; /**< Becomes PKT_INST_HDR[NGRP] 4473232812Sjmallett when DPI_INST_HDR[R]==1 */ 4474232812Sjmallett uint64_t rntt : 1; /**< Becomes PKT_INST_HDR[NTT] 4475232812Sjmallett when DPI_INST_HDR[R]==1 */ 4476232812Sjmallett uint64_t rntag : 1; /**< Becomes PKT_INST_HDR[NTAG] 4477232812Sjmallett when DPI_INST_HDR[R]==1 */ 4478232812Sjmallett uint64_t use_ihdr : 1; /**< When set '1' DPI always prepends a PKT_INST_HDR 4479232812Sjmallett as part of the packet data sent to PIP/IPD, 4480232812Sjmallett regardless of DPI_INST_HDR[R]. (DPI also always 4481232812Sjmallett prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.) 4482232812Sjmallett USE_IHDR must be set whenever PBP is set. */ 4483232812Sjmallett uint64_t reserved_16_20 : 5; 4484232812Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM] 4485232812Sjmallett when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */ 4486232812Sjmallett uint64_t reserved_13_13 : 1; 4487232812Sjmallett uint64_t skp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL] 4488232812Sjmallett when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */ 4489232812Sjmallett uint64_t ngrpext : 2; /**< Becomes PKT_INST_HDR[GRPEXT] 4490232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4491232812Sjmallett uint64_t nqos : 1; /**< Becomes PKT_INST_HDR[NQOS] 4492232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4493232812Sjmallett uint64_t ngrp : 1; /**< Becomes PKT_INST_HDR[NGRP] 4494232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4495232812Sjmallett uint64_t ntt : 1; /**< Becomes PKT_INST_HDR[NTT] 4496232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4497232812Sjmallett uint64_t ntag : 1; /**< Becomes PKT_INST_HDR[NTAG] 4498232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4499232812Sjmallett#else 4500232812Sjmallett uint64_t ntag : 1; 4501232812Sjmallett uint64_t ntt : 1; 4502232812Sjmallett uint64_t ngrp : 1; 4503232812Sjmallett uint64_t nqos : 1; 4504232812Sjmallett uint64_t ngrpext : 2; 4505232812Sjmallett uint64_t skp_len : 7; 4506232812Sjmallett uint64_t reserved_13_13 : 1; 4507232812Sjmallett uint64_t par_mode : 2; 4508232812Sjmallett uint64_t reserved_16_20 : 5; 4509232812Sjmallett uint64_t use_ihdr : 1; 4510232812Sjmallett uint64_t rntag : 1; 4511232812Sjmallett uint64_t rntt : 1; 4512232812Sjmallett uint64_t rngrp : 1; 4513232812Sjmallett uint64_t rnqos : 1; 4514232812Sjmallett uint64_t rngrpext : 2; 4515232812Sjmallett uint64_t rskp_len : 7; 4516232812Sjmallett uint64_t reserved_35_35 : 1; 4517232812Sjmallett uint64_t rparmode : 2; 4518232812Sjmallett uint64_t reserved_38_42 : 5; 4519232812Sjmallett uint64_t pbp : 1; 4520232812Sjmallett uint64_t reserved_44_63 : 20; 4521232812Sjmallett#endif 4522232812Sjmallett } s; 4523232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx { 4524232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4525232812Sjmallett uint64_t reserved_44_63 : 20; 4526232812Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. 4527232812Sjmallett Allows DPI to generate PKT_INST_HDR[PM,SL] 4528232812Sjmallett differently per DPI instruction. 4529232812Sjmallett USE_IHDR must be set whenever PBP is set. */ 4530232812Sjmallett uint64_t reserved_38_42 : 5; 4531232812Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM] 4532232812Sjmallett when DPI_INST_HDR[R]==1 and PBP==0 */ 4533232812Sjmallett uint64_t reserved_35_35 : 1; 4534232812Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL] 4535232812Sjmallett when DPI_INST_HDR[R]==1 and PBP==0 */ 4536215976Sjmallett uint64_t reserved_26_27 : 2; 4537232812Sjmallett uint64_t rnqos : 1; /**< Becomes PKT_INST_HDR[NQOS] 4538232812Sjmallett when DPI_INST_HDR[R]==1 */ 4539232812Sjmallett uint64_t rngrp : 1; /**< Becomes PKT_INST_HDR[NGRP] 4540232812Sjmallett when DPI_INST_HDR[R]==1 */ 4541232812Sjmallett uint64_t rntt : 1; /**< Becomes PKT_INST_HDR[NTT] 4542232812Sjmallett when DPI_INST_HDR[R]==1 */ 4543232812Sjmallett uint64_t rntag : 1; /**< Becomes PKT_INST_HDR[NTAG] 4544232812Sjmallett when DPI_INST_HDR[R]==1 */ 4545232812Sjmallett uint64_t use_ihdr : 1; /**< When set '1' DPI always prepends a PKT_INST_HDR 4546232812Sjmallett as part of the packet data sent to PIP/IPD, 4547232812Sjmallett regardless of DPI_INST_HDR[R]. (DPI also always 4548232812Sjmallett prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.) 4549215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 4550215976Sjmallett uint64_t reserved_16_20 : 5; 4551232812Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Becomes PKT_INST_HDR[PM] 4552232812Sjmallett when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */ 4553215976Sjmallett uint64_t reserved_13_13 : 1; 4554232812Sjmallett uint64_t skp_len : 7; /**< Skip Length. Becomes PKT_INST_HDR[SL] 4555232812Sjmallett when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */ 4556215976Sjmallett uint64_t reserved_4_5 : 2; 4557232812Sjmallett uint64_t nqos : 1; /**< Becomes PKT_INST_HDR[NQOS] 4558232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4559232812Sjmallett uint64_t ngrp : 1; /**< Becomes PKT_INST_HDR[NGRP] 4560232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4561232812Sjmallett uint64_t ntt : 1; /**< Becomes PKT_INST_HDR[NTT] 4562232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4563232812Sjmallett uint64_t ntag : 1; /**< Becomes PKT_INST_HDR[NTAG] 4564232812Sjmallett when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */ 4565215976Sjmallett#else 4566215976Sjmallett uint64_t ntag : 1; 4567215976Sjmallett uint64_t ntt : 1; 4568215976Sjmallett uint64_t ngrp : 1; 4569215976Sjmallett uint64_t nqos : 1; 4570215976Sjmallett uint64_t reserved_4_5 : 2; 4571215976Sjmallett uint64_t skp_len : 7; 4572215976Sjmallett uint64_t reserved_13_13 : 1; 4573215976Sjmallett uint64_t par_mode : 2; 4574215976Sjmallett uint64_t reserved_16_20 : 5; 4575215976Sjmallett uint64_t use_ihdr : 1; 4576215976Sjmallett uint64_t rntag : 1; 4577215976Sjmallett uint64_t rntt : 1; 4578215976Sjmallett uint64_t rngrp : 1; 4579215976Sjmallett uint64_t rnqos : 1; 4580215976Sjmallett uint64_t reserved_26_27 : 2; 4581215976Sjmallett uint64_t rskp_len : 7; 4582215976Sjmallett uint64_t reserved_35_35 : 1; 4583215976Sjmallett uint64_t rparmode : 2; 4584215976Sjmallett uint64_t reserved_38_42 : 5; 4585215976Sjmallett uint64_t pbp : 1; 4586215976Sjmallett uint64_t reserved_44_63 : 20; 4587215976Sjmallett#endif 4588232812Sjmallett } cn61xx; 4589232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; 4590232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; 4591232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; 4592232812Sjmallett struct cvmx_sli_pktx_instr_header_s cn68xx; 4593232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; 4594232812Sjmallett struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; 4595215976Sjmallett}; 4596215976Sjmalletttypedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t; 4597215976Sjmallett 4598215976Sjmallett/** 4599215976Sjmallett * cvmx_sli_pkt#_out_size 4600215976Sjmallett * 4601215976Sjmallett * SLI_PKT[0..31]_OUT_SIZE = SLI Packet Out Size 4602215976Sjmallett * 4603215976Sjmallett * Contains the BSIZE and ISIZE for output packet ports. 4604215976Sjmallett */ 4605232812Sjmallettunion cvmx_sli_pktx_out_size { 4606215976Sjmallett uint64_t u64; 4607232812Sjmallett struct cvmx_sli_pktx_out_size_s { 4608232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4609215976Sjmallett uint64_t reserved_23_63 : 41; 4610215976Sjmallett uint64_t isize : 7; /**< INFO BYTES size (bytes) for ring X. Legal sizes 4611215976Sjmallett are 0 to 120. Not used in buffer-pointer-only mode. */ 4612215976Sjmallett uint64_t bsize : 16; /**< BUFFER SIZE (bytes) for ring X. */ 4613215976Sjmallett#else 4614215976Sjmallett uint64_t bsize : 16; 4615215976Sjmallett uint64_t isize : 7; 4616215976Sjmallett uint64_t reserved_23_63 : 41; 4617215976Sjmallett#endif 4618215976Sjmallett } s; 4619232812Sjmallett struct cvmx_sli_pktx_out_size_s cn61xx; 4620215976Sjmallett struct cvmx_sli_pktx_out_size_s cn63xx; 4621215976Sjmallett struct cvmx_sli_pktx_out_size_s cn63xxp1; 4622232812Sjmallett struct cvmx_sli_pktx_out_size_s cn66xx; 4623232812Sjmallett struct cvmx_sli_pktx_out_size_s cn68xx; 4624232812Sjmallett struct cvmx_sli_pktx_out_size_s cn68xxp1; 4625232812Sjmallett struct cvmx_sli_pktx_out_size_s cnf71xx; 4626215976Sjmallett}; 4627215976Sjmalletttypedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t; 4628215976Sjmallett 4629215976Sjmallett/** 4630215976Sjmallett * cvmx_sli_pkt#_slist_baddr 4631215976Sjmallett * 4632215976Sjmallett * SLI_PKT[0..31]_SLIST_BADDR = SLI Packet ring# Scatter List Base Address 4633215976Sjmallett * 4634215976Sjmallett * Start of Scatter List for output packet pointers - MUST be 16 byte alligned 4635215976Sjmallett */ 4636232812Sjmallettunion cvmx_sli_pktx_slist_baddr { 4637215976Sjmallett uint64_t u64; 4638232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s { 4639232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4640215976Sjmallett uint64_t addr : 60; /**< Base address for scatter list pointers. */ 4641215976Sjmallett uint64_t reserved_0_3 : 4; 4642215976Sjmallett#else 4643215976Sjmallett uint64_t reserved_0_3 : 4; 4644215976Sjmallett uint64_t addr : 60; 4645215976Sjmallett#endif 4646215976Sjmallett } s; 4647232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn61xx; 4648215976Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn63xx; 4649215976Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn63xxp1; 4650232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn66xx; 4651232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn68xx; 4652232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; 4653232812Sjmallett struct cvmx_sli_pktx_slist_baddr_s cnf71xx; 4654215976Sjmallett}; 4655215976Sjmalletttypedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t; 4656215976Sjmallett 4657215976Sjmallett/** 4658215976Sjmallett * cvmx_sli_pkt#_slist_baoff_dbell 4659215976Sjmallett * 4660215976Sjmallett * SLI_PKT[0..31]_SLIST_BAOFF_DBELL = SLI Packet ring# Scatter List Base Address Offset and Doorbell 4661215976Sjmallett * 4662215976Sjmallett * The doorbell and base address offset for next read. 4663215976Sjmallett */ 4664232812Sjmallettunion cvmx_sli_pktx_slist_baoff_dbell { 4665215976Sjmallett uint64_t u64; 4666232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s { 4667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4668215976Sjmallett uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR 4669215976Sjmallett where the next SList pointer will be read. 4670215976Sjmallett A write of 0xFFFFFFFF to the DBELL field will 4671215976Sjmallett clear DBELL and AOFF */ 4672215976Sjmallett uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field 4673215976Sjmallett will increment the value here. Reads will return 4674215976Sjmallett present value. The value of this field is 4675215976Sjmallett decremented as read operations are ISSUED for 4676215976Sjmallett scatter pointers. 4677215976Sjmallett A write of 0xFFFFFFFF will clear DBELL and AOFF */ 4678215976Sjmallett#else 4679215976Sjmallett uint64_t dbell : 32; 4680215976Sjmallett uint64_t aoff : 32; 4681215976Sjmallett#endif 4682215976Sjmallett } s; 4683232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; 4684215976Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; 4685215976Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1; 4686232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; 4687232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; 4688232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; 4689232812Sjmallett struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; 4690215976Sjmallett}; 4691215976Sjmalletttypedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t; 4692215976Sjmallett 4693215976Sjmallett/** 4694215976Sjmallett * cvmx_sli_pkt#_slist_fifo_rsize 4695215976Sjmallett * 4696215976Sjmallett * SLI_PKT[0..31]_SLIST_FIFO_RSIZE = SLI Packet ring# Scatter List FIFO and Ring Size. 4697215976Sjmallett * 4698215976Sjmallett * The number of scatter pointer pairs in the scatter list. 4699215976Sjmallett */ 4700232812Sjmallettunion cvmx_sli_pktx_slist_fifo_rsize { 4701215976Sjmallett uint64_t u64; 4702232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s { 4703232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4704215976Sjmallett uint64_t reserved_32_63 : 32; 4705215976Sjmallett uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in 4706215976Sjmallett the scatter list ring. */ 4707215976Sjmallett#else 4708215976Sjmallett uint64_t rsize : 32; 4709215976Sjmallett uint64_t reserved_32_63 : 32; 4710215976Sjmallett#endif 4711215976Sjmallett } s; 4712232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; 4713215976Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; 4714215976Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1; 4715232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; 4716232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; 4717232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; 4718232812Sjmallett struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; 4719215976Sjmallett}; 4720215976Sjmalletttypedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t; 4721215976Sjmallett 4722215976Sjmallett/** 4723215976Sjmallett * cvmx_sli_pkt_cnt_int 4724215976Sjmallett * 4725215976Sjmallett * SLI_PKT_CNT_INT = SLI Packet Counter Interrupt 4726215976Sjmallett * 4727215976Sjmallett * The packets rings that are interrupting because of Packet Counters. 4728215976Sjmallett */ 4729232812Sjmallettunion cvmx_sli_pkt_cnt_int { 4730215976Sjmallett uint64_t u64; 4731232812Sjmallett struct cvmx_sli_pkt_cnt_int_s { 4732232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4733215976Sjmallett uint64_t reserved_32_63 : 32; 4734215976Sjmallett uint64_t port : 32; /**< Output ring packet counter interrupt bits 4735215976Sjmallett SLI sets PORT<i> whenever 4736215976Sjmallett SLI_PKTi_CNTS[CNT] > SLI_PKT_INT_LEVELS[CNT]. 4737215976Sjmallett SLI_PKT_CNT_INT_ENB[PORT<i>] is the corresponding 4738215976Sjmallett enable. */ 4739215976Sjmallett#else 4740215976Sjmallett uint64_t port : 32; 4741215976Sjmallett uint64_t reserved_32_63 : 32; 4742215976Sjmallett#endif 4743215976Sjmallett } s; 4744232812Sjmallett struct cvmx_sli_pkt_cnt_int_s cn61xx; 4745215976Sjmallett struct cvmx_sli_pkt_cnt_int_s cn63xx; 4746215976Sjmallett struct cvmx_sli_pkt_cnt_int_s cn63xxp1; 4747232812Sjmallett struct cvmx_sli_pkt_cnt_int_s cn66xx; 4748232812Sjmallett struct cvmx_sli_pkt_cnt_int_s cn68xx; 4749232812Sjmallett struct cvmx_sli_pkt_cnt_int_s cn68xxp1; 4750232812Sjmallett struct cvmx_sli_pkt_cnt_int_s cnf71xx; 4751215976Sjmallett}; 4752215976Sjmalletttypedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t; 4753215976Sjmallett 4754215976Sjmallett/** 4755215976Sjmallett * cvmx_sli_pkt_cnt_int_enb 4756215976Sjmallett * 4757215976Sjmallett * SLI_PKT_CNT_INT_ENB = SLI Packet Counter Interrupt Enable 4758215976Sjmallett * 4759215976Sjmallett * Enable for the packets rings that are interrupting because of Packet Counters. 4760215976Sjmallett */ 4761232812Sjmallettunion cvmx_sli_pkt_cnt_int_enb { 4762215976Sjmallett uint64_t u64; 4763232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s { 4764232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4765215976Sjmallett uint64_t reserved_32_63 : 32; 4766215976Sjmallett uint64_t port : 32; /**< Output ring packet counter interrupt enables 4767215976Sjmallett When both PORT<i> and corresponding 4768215976Sjmallett SLI_PKT_CNT_INT[PORT<i>] are set, for any i, 4769215976Sjmallett then SLI_INT_SUM[PCNT] is set, which can cause 4770215976Sjmallett an interrupt. */ 4771215976Sjmallett#else 4772215976Sjmallett uint64_t port : 32; 4773215976Sjmallett uint64_t reserved_32_63 : 32; 4774215976Sjmallett#endif 4775215976Sjmallett } s; 4776232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; 4777215976Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; 4778215976Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1; 4779232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; 4780232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; 4781232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; 4782232812Sjmallett struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; 4783215976Sjmallett}; 4784215976Sjmalletttypedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t; 4785215976Sjmallett 4786215976Sjmallett/** 4787215976Sjmallett * cvmx_sli_pkt_ctl 4788215976Sjmallett * 4789215976Sjmallett * SLI_PKT_CTL = SLI Packet Control 4790215976Sjmallett * 4791215976Sjmallett * Control for packets. 4792215976Sjmallett */ 4793232812Sjmallettunion cvmx_sli_pkt_ctl { 4794215976Sjmallett uint64_t u64; 4795232812Sjmallett struct cvmx_sli_pkt_ctl_s { 4796232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4797215976Sjmallett uint64_t reserved_5_63 : 59; 4798215976Sjmallett uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received 4799215976Sjmallett from PKO to be zero, and replicates the back- 4800215976Sjmallett pressure indication for the first ring attached 4801215976Sjmallett to a PKO port across all the rings attached to a 4802215976Sjmallett PKO port. When '1' backpressure is on a per 4803215976Sjmallett port/ring. */ 4804215976Sjmallett uint64_t pkt_bp : 4; /**< When set '1' enable the port level backpressure for 4805215976Sjmallett PKO ports associated with the bit. */ 4806215976Sjmallett#else 4807215976Sjmallett uint64_t pkt_bp : 4; 4808215976Sjmallett uint64_t ring_en : 1; 4809215976Sjmallett uint64_t reserved_5_63 : 59; 4810215976Sjmallett#endif 4811215976Sjmallett } s; 4812232812Sjmallett struct cvmx_sli_pkt_ctl_s cn61xx; 4813215976Sjmallett struct cvmx_sli_pkt_ctl_s cn63xx; 4814215976Sjmallett struct cvmx_sli_pkt_ctl_s cn63xxp1; 4815232812Sjmallett struct cvmx_sli_pkt_ctl_s cn66xx; 4816232812Sjmallett struct cvmx_sli_pkt_ctl_s cn68xx; 4817232812Sjmallett struct cvmx_sli_pkt_ctl_s cn68xxp1; 4818232812Sjmallett struct cvmx_sli_pkt_ctl_s cnf71xx; 4819215976Sjmallett}; 4820215976Sjmalletttypedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t; 4821215976Sjmallett 4822215976Sjmallett/** 4823215976Sjmallett * cvmx_sli_pkt_data_out_es 4824215976Sjmallett * 4825215976Sjmallett * SLI_PKT_DATA_OUT_ES = SLI's Packet Data Out Endian Swap 4826215976Sjmallett * 4827215976Sjmallett * The Endian Swap for writing Data Out. 4828215976Sjmallett */ 4829232812Sjmallettunion cvmx_sli_pkt_data_out_es { 4830215976Sjmallett uint64_t u64; 4831232812Sjmallett struct cvmx_sli_pkt_data_out_es_s { 4832232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4833215976Sjmallett uint64_t es : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes. 4834215976Sjmallett ES<2i+1:2i> becomes either ES<1:0> or 4835215976Sjmallett MACADD<63:62> for writes to buffer/info pair 4836215976Sjmallett MAC memory space addresses fetched from packet 4837215976Sjmallett output ring i. ES<1:0> if SLI_PKT_DPADDR[DPTR<i>]=1 4838215976Sjmallett , else MACADD<63:62>. 4839215976Sjmallett In the latter case, ES<1:0> comes from DPTR<63:62>. 4840215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 4841215976Sjmallett memory space writes. */ 4842215976Sjmallett#else 4843215976Sjmallett uint64_t es : 64; 4844215976Sjmallett#endif 4845215976Sjmallett } s; 4846232812Sjmallett struct cvmx_sli_pkt_data_out_es_s cn61xx; 4847215976Sjmallett struct cvmx_sli_pkt_data_out_es_s cn63xx; 4848215976Sjmallett struct cvmx_sli_pkt_data_out_es_s cn63xxp1; 4849232812Sjmallett struct cvmx_sli_pkt_data_out_es_s cn66xx; 4850232812Sjmallett struct cvmx_sli_pkt_data_out_es_s cn68xx; 4851232812Sjmallett struct cvmx_sli_pkt_data_out_es_s cn68xxp1; 4852232812Sjmallett struct cvmx_sli_pkt_data_out_es_s cnf71xx; 4853215976Sjmallett}; 4854215976Sjmalletttypedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t; 4855215976Sjmallett 4856215976Sjmallett/** 4857215976Sjmallett * cvmx_sli_pkt_data_out_ns 4858215976Sjmallett * 4859215976Sjmallett * SLI_PKT_DATA_OUT_NS = SLI's Packet Data Out No Snoop 4860215976Sjmallett * 4861215976Sjmallett * The NS field for the TLP when writing packet data. 4862215976Sjmallett */ 4863232812Sjmallettunion cvmx_sli_pkt_data_out_ns { 4864215976Sjmallett uint64_t u64; 4865232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s { 4866232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4867215976Sjmallett uint64_t reserved_32_63 : 32; 4868215976Sjmallett uint64_t nsr : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes. 4869215976Sjmallett NSR<i> becomes either ADDRTYPE<1> or MACADD<61> 4870215976Sjmallett for writes to buffer/info pair MAC memory space 4871215976Sjmallett addresses fetched from packet output ring i. 4872215976Sjmallett ADDRTYPE<1> if SLI_PKT_DPADDR[DPTR<i>]=1, else 4873215976Sjmallett MACADD<61>. 4874215976Sjmallett In the latter case,ADDRTYPE<1> comes from DPTR<61>. 4875215976Sjmallett ADDRTYPE<1> is the no-snoop attribute for PCIe 4876215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 4877215976Sjmallett#else 4878215976Sjmallett uint64_t nsr : 32; 4879215976Sjmallett uint64_t reserved_32_63 : 32; 4880215976Sjmallett#endif 4881215976Sjmallett } s; 4882232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn61xx; 4883215976Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn63xx; 4884215976Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn63xxp1; 4885232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn66xx; 4886232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn68xx; 4887232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; 4888232812Sjmallett struct cvmx_sli_pkt_data_out_ns_s cnf71xx; 4889215976Sjmallett}; 4890215976Sjmalletttypedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t; 4891215976Sjmallett 4892215976Sjmallett/** 4893215976Sjmallett * cvmx_sli_pkt_data_out_ror 4894215976Sjmallett * 4895215976Sjmallett * SLI_PKT_DATA_OUT_ROR = SLI's Packet Data Out Relaxed Ordering 4896215976Sjmallett * 4897215976Sjmallett * The ROR field for the TLP when writing Packet Data. 4898215976Sjmallett */ 4899232812Sjmallettunion cvmx_sli_pkt_data_out_ror { 4900215976Sjmallett uint64_t u64; 4901232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s { 4902232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4903215976Sjmallett uint64_t reserved_32_63 : 32; 4904215976Sjmallett uint64_t ror : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes. 4905215976Sjmallett ROR<i> becomes either ADDRTYPE<0> or MACADD<60> 4906215976Sjmallett for writes to buffer/info pair MAC memory space 4907215976Sjmallett addresses fetched from packet output ring i. 4908215976Sjmallett ADDRTYPE<0> if SLI_PKT_DPADDR[DPTR<i>]=1, else 4909215976Sjmallett MACADD<60>. 4910215976Sjmallett In the latter case,ADDRTYPE<0> comes from DPTR<60>. 4911215976Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 4912215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 4913215976Sjmallett#else 4914215976Sjmallett uint64_t ror : 32; 4915215976Sjmallett uint64_t reserved_32_63 : 32; 4916215976Sjmallett#endif 4917215976Sjmallett } s; 4918232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn61xx; 4919215976Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn63xx; 4920215976Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn63xxp1; 4921232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn66xx; 4922232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn68xx; 4923232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; 4924232812Sjmallett struct cvmx_sli_pkt_data_out_ror_s cnf71xx; 4925215976Sjmallett}; 4926215976Sjmalletttypedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t; 4927215976Sjmallett 4928215976Sjmallett/** 4929215976Sjmallett * cvmx_sli_pkt_dpaddr 4930215976Sjmallett * 4931215976Sjmallett * SLI_PKT_DPADDR = SLI's Packet Data Pointer Addr 4932215976Sjmallett * 4933215976Sjmallett * Used to detemine address and attributes for packet data writes. 4934215976Sjmallett */ 4935232812Sjmallettunion cvmx_sli_pkt_dpaddr { 4936215976Sjmallett uint64_t u64; 4937232812Sjmallett struct cvmx_sli_pkt_dpaddr_s { 4938232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4939215976Sjmallett uint64_t reserved_32_63 : 32; 4940215976Sjmallett uint64_t dptr : 32; /**< Determines whether buffer/info pointers are 4941215976Sjmallett DPTR format 0 or DPTR format 1. 4942215976Sjmallett When DPTR<i>=1, the buffer/info pointers fetched 4943215976Sjmallett from packet output ring i are DPTR format 0. 4944215976Sjmallett When DPTR<i>=0, the buffer/info pointers fetched 4945215976Sjmallett from packet output ring i are DPTR format 1. 4946215976Sjmallett (Replace SLI_PKT_INPUT_CONTROL[D_ESR,D_NSR,D_ROR] 4947215976Sjmallett in the HRM descriptions of DPTR format 0/1 with 4948215976Sjmallett SLI_PKT_DATA_OUT_ES[ES<2i+1:2i>], 4949215976Sjmallett SLI_PKT_DATA_OUT_NS[NSR<i>], and 4950215976Sjmallett SLI_PKT_DATA_OUT_ROR[ROR<i>], respectively, 4951215976Sjmallett though.) */ 4952215976Sjmallett#else 4953215976Sjmallett uint64_t dptr : 32; 4954215976Sjmallett uint64_t reserved_32_63 : 32; 4955215976Sjmallett#endif 4956215976Sjmallett } s; 4957232812Sjmallett struct cvmx_sli_pkt_dpaddr_s cn61xx; 4958215976Sjmallett struct cvmx_sli_pkt_dpaddr_s cn63xx; 4959215976Sjmallett struct cvmx_sli_pkt_dpaddr_s cn63xxp1; 4960232812Sjmallett struct cvmx_sli_pkt_dpaddr_s cn66xx; 4961232812Sjmallett struct cvmx_sli_pkt_dpaddr_s cn68xx; 4962232812Sjmallett struct cvmx_sli_pkt_dpaddr_s cn68xxp1; 4963232812Sjmallett struct cvmx_sli_pkt_dpaddr_s cnf71xx; 4964215976Sjmallett}; 4965215976Sjmalletttypedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t; 4966215976Sjmallett 4967215976Sjmallett/** 4968215976Sjmallett * cvmx_sli_pkt_in_bp 4969215976Sjmallett * 4970215976Sjmallett * SLI_PKT_IN_BP = SLI Packet Input Backpressure 4971215976Sjmallett * 4972215976Sjmallett * Which input rings have backpressure applied. 4973215976Sjmallett */ 4974232812Sjmallettunion cvmx_sli_pkt_in_bp { 4975215976Sjmallett uint64_t u64; 4976232812Sjmallett struct cvmx_sli_pkt_in_bp_s { 4977232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4978215976Sjmallett uint64_t reserved_32_63 : 32; 4979215976Sjmallett uint64_t bp : 32; /**< A packet input ring that has its count greater 4980215976Sjmallett than its WMARK will have backpressure applied. 4981215976Sjmallett Each of the 32 bits coorespond to an input ring. 4982215976Sjmallett When '1' that ring has backpressure applied an 4983215976Sjmallett will fetch no more instructions, but will process 4984215976Sjmallett any previously fetched instructions. */ 4985215976Sjmallett#else 4986215976Sjmallett uint64_t bp : 32; 4987215976Sjmallett uint64_t reserved_32_63 : 32; 4988215976Sjmallett#endif 4989215976Sjmallett } s; 4990232812Sjmallett struct cvmx_sli_pkt_in_bp_s cn61xx; 4991215976Sjmallett struct cvmx_sli_pkt_in_bp_s cn63xx; 4992215976Sjmallett struct cvmx_sli_pkt_in_bp_s cn63xxp1; 4993232812Sjmallett struct cvmx_sli_pkt_in_bp_s cn66xx; 4994232812Sjmallett struct cvmx_sli_pkt_in_bp_s cnf71xx; 4995215976Sjmallett}; 4996215976Sjmalletttypedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t; 4997215976Sjmallett 4998215976Sjmallett/** 4999215976Sjmallett * cvmx_sli_pkt_in_done#_cnts 5000215976Sjmallett * 5001215976Sjmallett * SLI_PKT_IN_DONE[0..31]_CNTS = SLI Instruction Done ring# Counts 5002215976Sjmallett * 5003215976Sjmallett * Counters for instructions completed on Input rings. 5004215976Sjmallett */ 5005232812Sjmallettunion cvmx_sli_pkt_in_donex_cnts { 5006215976Sjmallett uint64_t u64; 5007232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s { 5008232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5009215976Sjmallett uint64_t reserved_32_63 : 32; 5010215976Sjmallett uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction 5011215976Sjmallett is completed. This field is incremented as the 5012215976Sjmallett last of the data is read from the MAC. */ 5013215976Sjmallett#else 5014215976Sjmallett uint64_t cnt : 32; 5015215976Sjmallett uint64_t reserved_32_63 : 32; 5016215976Sjmallett#endif 5017215976Sjmallett } s; 5018232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; 5019215976Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; 5020215976Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1; 5021232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; 5022232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; 5023232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; 5024232812Sjmallett struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; 5025215976Sjmallett}; 5026215976Sjmalletttypedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t; 5027215976Sjmallett 5028215976Sjmallett/** 5029215976Sjmallett * cvmx_sli_pkt_in_instr_counts 5030215976Sjmallett * 5031215976Sjmallett * SLI_PKT_IN_INSTR_COUNTS = SLI Packet Input Instrutction Counts 5032215976Sjmallett * 5033215976Sjmallett * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD. 5034215976Sjmallett */ 5035232812Sjmallettunion cvmx_sli_pkt_in_instr_counts { 5036215976Sjmallett uint64_t u64; 5037232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s { 5038232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5039215976Sjmallett uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */ 5040215976Sjmallett uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads 5041215976Sjmallett issued for them. 5042215976Sjmallett to the Packet-ring is in reset. */ 5043215976Sjmallett#else 5044215976Sjmallett uint64_t rd_cnt : 32; 5045215976Sjmallett uint64_t wr_cnt : 32; 5046215976Sjmallett#endif 5047215976Sjmallett } s; 5048232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn61xx; 5049215976Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn63xx; 5050215976Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1; 5051232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn66xx; 5052232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn68xx; 5053232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; 5054232812Sjmallett struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; 5055215976Sjmallett}; 5056215976Sjmalletttypedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t; 5057215976Sjmallett 5058215976Sjmallett/** 5059215976Sjmallett * cvmx_sli_pkt_in_pcie_port 5060215976Sjmallett * 5061215976Sjmallett * SLI_PKT_IN_PCIE_PORT = SLI's Packet In To MAC Port Assignment 5062215976Sjmallett * 5063215976Sjmallett * Assigns Packet Input rings to MAC ports. 5064215976Sjmallett */ 5065232812Sjmallettunion cvmx_sli_pkt_in_pcie_port { 5066215976Sjmallett uint64_t u64; 5067232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s { 5068232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5069215976Sjmallett uint64_t pp : 64; /**< The MAC port that the Packet ring number is 5070215976Sjmallett assigned. Two bits are used per ring (i.e. ring 0 5071215976Sjmallett [1:0], ring 1 [3:2], ....). A value of '0 means 5072215976Sjmallett that the Packetring is assign to MAC Port 0, a '1' 5073232812Sjmallett MAC Port 1, a '2' MAC Port 2, and a '3' MAC Port 3. */ 5074215976Sjmallett#else 5075215976Sjmallett uint64_t pp : 64; 5076215976Sjmallett#endif 5077215976Sjmallett } s; 5078232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn61xx; 5079215976Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn63xx; 5080215976Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1; 5081232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn66xx; 5082232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn68xx; 5083232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; 5084232812Sjmallett struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; 5085215976Sjmallett}; 5086215976Sjmalletttypedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t; 5087215976Sjmallett 5088215976Sjmallett/** 5089215976Sjmallett * cvmx_sli_pkt_input_control 5090215976Sjmallett * 5091215976Sjmallett * SLI_PKT_INPUT_CONTROL = SLI's Packet Input Control 5092215976Sjmallett * 5093215976Sjmallett * Control for reads for gather list and instructions. 5094215976Sjmallett */ 5095232812Sjmallettunion cvmx_sli_pkt_input_control { 5096215976Sjmallett uint64_t u64; 5097232812Sjmallett struct cvmx_sli_pkt_input_control_s { 5098232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5099232812Sjmallett uint64_t prd_erst : 1; /**< PRD Error Reset */ 5100232812Sjmallett uint64_t prd_rds : 7; /**< PRD Reads Out */ 5101232812Sjmallett uint64_t gii_erst : 1; /**< GII Error Reset */ 5102232812Sjmallett uint64_t gii_rds : 7; /**< GII Reads Out */ 5103232812Sjmallett uint64_t reserved_41_47 : 7; 5104232812Sjmallett uint64_t prc_idle : 1; /**< PRC In IDLE */ 5105232812Sjmallett uint64_t reserved_24_39 : 16; 5106232812Sjmallett uint64_t pin_rst : 1; /**< Packet In Reset. When a gather-list read receives 5107232812Sjmallett an error this bit (along with SLI_INT_SUM[PGL_ERR]) 5108232812Sjmallett is set. When receiveing a PGL_ERR interrupt the SW 5109232812Sjmallett should: 5110232812Sjmallett 1. Wait 2ms to allow any outstanding reads to return 5111232812Sjmallett or be timed out. 5112232812Sjmallett 2. Write a '0' to this bit. 5113232812Sjmallett 3. Startup the packet input again (all previous 5114232812Sjmallett CSR setting of the packet-input will be lost). */ 5115232812Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 5116232812Sjmallett made with a Round Robin arbitration. When '0' 5117232812Sjmallett the input packet ring is fixed in priority, 5118232812Sjmallett where the lower ring number has higher priority. */ 5119232812Sjmallett uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used 5120232812Sjmallett for parse mode and skip-length when 5121232812Sjmallett SLI_PKTi_INSTR_HEADER[PBP]=1. 5122232812Sjmallett PBP_DHI becomes either MACADD<63:55> or MACADD<59:51> 5123232812Sjmallett for the instruction DPTR reads in this case. 5124232812Sjmallett The instruction DPTR reads are called 5125232812Sjmallett "First Direct" or "First Indirect" in the HRM. 5126232812Sjmallett When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI 5127232812Sjmallett becomes MACADD<59:51>, else MACADD<63:55>. */ 5128232812Sjmallett uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data 5129232812Sjmallett reads. 5130232812Sjmallett D_NSR becomes either ADDRTYPE<1> or MACADD<61> 5131232812Sjmallett for MAC memory space reads of packet input data 5132232812Sjmallett fetched for any packet input ring. 5133232812Sjmallett ADDRTYPE<1> if USE_CSR=1, else MACADD<61>. 5134232812Sjmallett In the latter case, ADDRTYPE<1> comes from DPTR<61>. 5135232812Sjmallett ADDRTYPE<1> is the no-snoop attribute for PCIe 5136232812Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5137232812Sjmallett uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data 5138232812Sjmallett reads. 5139232812Sjmallett D_ESR becomes either ES<1:0> or MACADD<63:62> 5140232812Sjmallett for MAC memory space reads of packet input data 5141232812Sjmallett fetched for any packet input ring. 5142232812Sjmallett ES<1:0> if USE_CSR=1, else MACADD<63:62>. 5143232812Sjmallett In the latter case, ES<1:0> comes from DPTR<63:62>. 5144232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 5145232812Sjmallett memory space reads. */ 5146232812Sjmallett uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data 5147232812Sjmallett reads. 5148232812Sjmallett D_ROR becomes either ADDRTYPE<0> or MACADD<60> 5149232812Sjmallett for MAC memory space reads of packet input data 5150232812Sjmallett fetched for any packet input ring. 5151232812Sjmallett ADDRTYPE<0> if USE_CSR=1, else MACADD<60>. 5152232812Sjmallett In the latter case, ADDRTYPE<0> comes from DPTR<60>. 5153232812Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 5154232812Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5155232812Sjmallett uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 5156232812Sjmallett ROR, ESR, and NSR. When clear '0' the value in 5157232812Sjmallett DPTR will be used. In turn the bits not used for 5158232812Sjmallett ROR, ESR, and NSR, will be used for bits [63:60] 5159232812Sjmallett of the address used to fetch packet data. */ 5160232812Sjmallett uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and 5161232812Sjmallett gather list (i.e. DPI component) reads from MAC 5162232812Sjmallett memory space. 5163232812Sjmallett ADDRTYPE<1> is the no-snoop attribute for PCIe 5164232812Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5165232812Sjmallett uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and 5166232812Sjmallett gather list (i.e. DPI component) reads from MAC 5167232812Sjmallett memory space. 5168232812Sjmallett ES<1:0> is the endian-swap attribute for these MAC 5169232812Sjmallett memory space reads. */ 5170232812Sjmallett uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and 5171232812Sjmallett gather list (i.e. DPI component) reads from MAC 5172232812Sjmallett memory space. 5173232812Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 5174232812Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5175232812Sjmallett#else 5176232812Sjmallett uint64_t ror : 1; 5177232812Sjmallett uint64_t esr : 2; 5178232812Sjmallett uint64_t nsr : 1; 5179232812Sjmallett uint64_t use_csr : 1; 5180232812Sjmallett uint64_t d_ror : 1; 5181232812Sjmallett uint64_t d_esr : 2; 5182232812Sjmallett uint64_t d_nsr : 1; 5183232812Sjmallett uint64_t pbp_dhi : 13; 5184232812Sjmallett uint64_t pkt_rr : 1; 5185232812Sjmallett uint64_t pin_rst : 1; 5186232812Sjmallett uint64_t reserved_24_39 : 16; 5187232812Sjmallett uint64_t prc_idle : 1; 5188232812Sjmallett uint64_t reserved_41_47 : 7; 5189232812Sjmallett uint64_t gii_rds : 7; 5190232812Sjmallett uint64_t gii_erst : 1; 5191232812Sjmallett uint64_t prd_rds : 7; 5192232812Sjmallett uint64_t prd_erst : 1; 5193232812Sjmallett#endif 5194232812Sjmallett } s; 5195232812Sjmallett struct cvmx_sli_pkt_input_control_s cn61xx; 5196232812Sjmallett struct cvmx_sli_pkt_input_control_cn63xx { 5197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5198215976Sjmallett uint64_t reserved_23_63 : 41; 5199215976Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 5200215976Sjmallett made with a Round Robin arbitration. When '0' 5201215976Sjmallett the input packet ring is fixed in priority, 5202215976Sjmallett where the lower ring number has higher priority. */ 5203215976Sjmallett uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used 5204215976Sjmallett for parse mode and skip-length when 5205215976Sjmallett SLI_PKTi_INSTR_HEADER[PBP]=1. 5206215976Sjmallett PBP_DHI becomes either MACADD<63:55> or MACADD<59:51> 5207215976Sjmallett for the instruction DPTR reads in this case. 5208215976Sjmallett The instruction DPTR reads are called 5209215976Sjmallett "First Direct" or "First Indirect" in the HRM. 5210215976Sjmallett When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI 5211215976Sjmallett becomes MACADD<59:51>, else MACADD<63:55>. */ 5212215976Sjmallett uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data 5213215976Sjmallett reads. 5214215976Sjmallett D_NSR becomes either ADDRTYPE<1> or MACADD<61> 5215215976Sjmallett for MAC memory space reads of packet input data 5216215976Sjmallett fetched for any packet input ring. 5217215976Sjmallett ADDRTYPE<1> if USE_CSR=1, else MACADD<61>. 5218215976Sjmallett In the latter case, ADDRTYPE<1> comes from DPTR<61>. 5219215976Sjmallett ADDRTYPE<1> is the no-snoop attribute for PCIe 5220215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5221215976Sjmallett uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data 5222215976Sjmallett reads. 5223215976Sjmallett D_ESR becomes either ES<1:0> or MACADD<63:62> 5224215976Sjmallett for MAC memory space reads of packet input data 5225215976Sjmallett fetched for any packet input ring. 5226215976Sjmallett ES<1:0> if USE_CSR=1, else MACADD<63:62>. 5227215976Sjmallett In the latter case, ES<1:0> comes from DPTR<63:62>. 5228215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 5229215976Sjmallett memory space reads. */ 5230215976Sjmallett uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data 5231215976Sjmallett reads. 5232215976Sjmallett D_ROR becomes either ADDRTYPE<0> or MACADD<60> 5233215976Sjmallett for MAC memory space reads of packet input data 5234215976Sjmallett fetched for any packet input ring. 5235215976Sjmallett ADDRTYPE<0> if USE_CSR=1, else MACADD<60>. 5236215976Sjmallett In the latter case, ADDRTYPE<0> comes from DPTR<60>. 5237215976Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 5238215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5239215976Sjmallett uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 5240215976Sjmallett ROR, ESR, and NSR. When clear '0' the value in 5241215976Sjmallett DPTR will be used. In turn the bits not used for 5242215976Sjmallett ROR, ESR, and NSR, will be used for bits [63:60] 5243215976Sjmallett of the address used to fetch packet data. */ 5244215976Sjmallett uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and 5245215976Sjmallett gather list (i.e. DPI component) reads from MAC 5246215976Sjmallett memory space. 5247215976Sjmallett ADDRTYPE<1> is the no-snoop attribute for PCIe 5248215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5249215976Sjmallett uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and 5250215976Sjmallett gather list (i.e. DPI component) reads from MAC 5251215976Sjmallett memory space. 5252215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 5253215976Sjmallett memory space reads. */ 5254215976Sjmallett uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and 5255215976Sjmallett gather list (i.e. DPI component) reads from MAC 5256215976Sjmallett memory space. 5257215976Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 5258215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5259215976Sjmallett#else 5260215976Sjmallett uint64_t ror : 1; 5261215976Sjmallett uint64_t esr : 2; 5262215976Sjmallett uint64_t nsr : 1; 5263215976Sjmallett uint64_t use_csr : 1; 5264215976Sjmallett uint64_t d_ror : 1; 5265215976Sjmallett uint64_t d_esr : 2; 5266215976Sjmallett uint64_t d_nsr : 1; 5267215976Sjmallett uint64_t pbp_dhi : 13; 5268215976Sjmallett uint64_t pkt_rr : 1; 5269215976Sjmallett uint64_t reserved_23_63 : 41; 5270215976Sjmallett#endif 5271232812Sjmallett } cn63xx; 5272232812Sjmallett struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; 5273232812Sjmallett struct cvmx_sli_pkt_input_control_s cn66xx; 5274232812Sjmallett struct cvmx_sli_pkt_input_control_s cn68xx; 5275232812Sjmallett struct cvmx_sli_pkt_input_control_s cn68xxp1; 5276232812Sjmallett struct cvmx_sli_pkt_input_control_s cnf71xx; 5277215976Sjmallett}; 5278215976Sjmalletttypedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t; 5279215976Sjmallett 5280215976Sjmallett/** 5281215976Sjmallett * cvmx_sli_pkt_instr_enb 5282215976Sjmallett * 5283215976Sjmallett * SLI_PKT_INSTR_ENB = SLI's Packet Instruction Enable 5284215976Sjmallett * 5285215976Sjmallett * Enables the instruction fetch for a Packet-ring. 5286215976Sjmallett */ 5287232812Sjmallettunion cvmx_sli_pkt_instr_enb { 5288215976Sjmallett uint64_t u64; 5289232812Sjmallett struct cvmx_sli_pkt_instr_enb_s { 5290232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5291215976Sjmallett uint64_t reserved_32_63 : 32; 5292215976Sjmallett uint64_t enb : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */ 5293215976Sjmallett#else 5294215976Sjmallett uint64_t enb : 32; 5295215976Sjmallett uint64_t reserved_32_63 : 32; 5296215976Sjmallett#endif 5297215976Sjmallett } s; 5298232812Sjmallett struct cvmx_sli_pkt_instr_enb_s cn61xx; 5299215976Sjmallett struct cvmx_sli_pkt_instr_enb_s cn63xx; 5300215976Sjmallett struct cvmx_sli_pkt_instr_enb_s cn63xxp1; 5301232812Sjmallett struct cvmx_sli_pkt_instr_enb_s cn66xx; 5302232812Sjmallett struct cvmx_sli_pkt_instr_enb_s cn68xx; 5303232812Sjmallett struct cvmx_sli_pkt_instr_enb_s cn68xxp1; 5304232812Sjmallett struct cvmx_sli_pkt_instr_enb_s cnf71xx; 5305215976Sjmallett}; 5306215976Sjmalletttypedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t; 5307215976Sjmallett 5308215976Sjmallett/** 5309215976Sjmallett * cvmx_sli_pkt_instr_rd_size 5310215976Sjmallett * 5311215976Sjmallett * SLI_PKT_INSTR_RD_SIZE = SLI Instruction Read Size 5312215976Sjmallett * 5313215976Sjmallett * The number of instruction allowed to be read at one time. 5314215976Sjmallett */ 5315232812Sjmallettunion cvmx_sli_pkt_instr_rd_size { 5316215976Sjmallett uint64_t u64; 5317232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s { 5318232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5319215976Sjmallett uint64_t rdsize : 64; /**< Number of instructions to be read in one MAC read 5320215976Sjmallett request for the 4 ports - 8 rings. Every two bits 5321215976Sjmallett (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring 5322215976Sjmallett combinations. 5323215976Sjmallett - 15:0 PKIPort0,Ring 7..0 31:16 PKIPort1,Ring 7..0 5324215976Sjmallett - 47:32 PKIPort2,Ring 7..0 63:48 PKIPort3,Ring 7..0 5325215976Sjmallett Two bit value are: 5326215976Sjmallett 0 - 1 Instruction 5327215976Sjmallett 1 - 2 Instructions 5328215976Sjmallett 2 - 3 Instructions 5329215976Sjmallett 3 - 4 Instructions */ 5330215976Sjmallett#else 5331215976Sjmallett uint64_t rdsize : 64; 5332215976Sjmallett#endif 5333215976Sjmallett } s; 5334232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn61xx; 5335215976Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn63xx; 5336215976Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1; 5337232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn66xx; 5338232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn68xx; 5339232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; 5340232812Sjmallett struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; 5341215976Sjmallett}; 5342215976Sjmalletttypedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t; 5343215976Sjmallett 5344215976Sjmallett/** 5345215976Sjmallett * cvmx_sli_pkt_instr_size 5346215976Sjmallett * 5347215976Sjmallett * SLI_PKT_INSTR_SIZE = SLI's Packet Instruction Size 5348215976Sjmallett * 5349215976Sjmallett * Determines if instructions are 64 or 32 byte in size for a Packet-ring. 5350215976Sjmallett */ 5351232812Sjmallettunion cvmx_sli_pkt_instr_size { 5352215976Sjmallett uint64_t u64; 5353232812Sjmallett struct cvmx_sli_pkt_instr_size_s { 5354232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5355215976Sjmallett uint64_t reserved_32_63 : 32; 5356215976Sjmallett uint64_t is_64b : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B 5357215976Sjmallett instructions, else 32B instructions. */ 5358215976Sjmallett#else 5359215976Sjmallett uint64_t is_64b : 32; 5360215976Sjmallett uint64_t reserved_32_63 : 32; 5361215976Sjmallett#endif 5362215976Sjmallett } s; 5363232812Sjmallett struct cvmx_sli_pkt_instr_size_s cn61xx; 5364215976Sjmallett struct cvmx_sli_pkt_instr_size_s cn63xx; 5365215976Sjmallett struct cvmx_sli_pkt_instr_size_s cn63xxp1; 5366232812Sjmallett struct cvmx_sli_pkt_instr_size_s cn66xx; 5367232812Sjmallett struct cvmx_sli_pkt_instr_size_s cn68xx; 5368232812Sjmallett struct cvmx_sli_pkt_instr_size_s cn68xxp1; 5369232812Sjmallett struct cvmx_sli_pkt_instr_size_s cnf71xx; 5370215976Sjmallett}; 5371215976Sjmalletttypedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t; 5372215976Sjmallett 5373215976Sjmallett/** 5374215976Sjmallett * cvmx_sli_pkt_int_levels 5375215976Sjmallett * 5376215976Sjmallett * 0x90F0 reserved SLI_PKT_PCIE_PORT2 5377215976Sjmallett * 5378215976Sjmallett * 5379215976Sjmallett * SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels 5380215976Sjmallett * 5381215976Sjmallett * Output packet interrupt levels. 5382215976Sjmallett */ 5383232812Sjmallettunion cvmx_sli_pkt_int_levels { 5384215976Sjmallett uint64_t u64; 5385232812Sjmallett struct cvmx_sli_pkt_int_levels_s { 5386232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5387215976Sjmallett uint64_t reserved_54_63 : 10; 5388215976Sjmallett uint64_t time : 22; /**< Output ring counter time interrupt threshold 5389215976Sjmallett SLI sets SLI_PKT_TIME_INT[PORT<i>] whenever 5390215976Sjmallett SLI_PKTi_CNTS[TIMER] > TIME */ 5391215976Sjmallett uint64_t cnt : 32; /**< Output ring counter interrupt threshold 5392215976Sjmallett SLI sets SLI_PKT_CNT_INT[PORT<i>] whenever 5393215976Sjmallett SLI_PKTi_CNTS[CNT] > CNT */ 5394215976Sjmallett#else 5395215976Sjmallett uint64_t cnt : 32; 5396215976Sjmallett uint64_t time : 22; 5397215976Sjmallett uint64_t reserved_54_63 : 10; 5398215976Sjmallett#endif 5399215976Sjmallett } s; 5400232812Sjmallett struct cvmx_sli_pkt_int_levels_s cn61xx; 5401215976Sjmallett struct cvmx_sli_pkt_int_levels_s cn63xx; 5402215976Sjmallett struct cvmx_sli_pkt_int_levels_s cn63xxp1; 5403232812Sjmallett struct cvmx_sli_pkt_int_levels_s cn66xx; 5404232812Sjmallett struct cvmx_sli_pkt_int_levels_s cn68xx; 5405232812Sjmallett struct cvmx_sli_pkt_int_levels_s cn68xxp1; 5406232812Sjmallett struct cvmx_sli_pkt_int_levels_s cnf71xx; 5407215976Sjmallett}; 5408215976Sjmalletttypedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t; 5409215976Sjmallett 5410215976Sjmallett/** 5411215976Sjmallett * cvmx_sli_pkt_iptr 5412215976Sjmallett * 5413215976Sjmallett * SLI_PKT_IPTR = SLI's Packet Info Poitner 5414215976Sjmallett * 5415215976Sjmallett * Controls using the Info-Pointer to store length and data. 5416215976Sjmallett */ 5417232812Sjmallettunion cvmx_sli_pkt_iptr { 5418215976Sjmallett uint64_t u64; 5419232812Sjmallett struct cvmx_sli_pkt_iptr_s { 5420232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5421215976Sjmallett uint64_t reserved_32_63 : 32; 5422215976Sjmallett uint64_t iptr : 32; /**< When IPTR<i>=1, packet output ring i is in info- 5423215976Sjmallett pointer mode, else buffer-pointer-only mode. */ 5424215976Sjmallett#else 5425215976Sjmallett uint64_t iptr : 32; 5426215976Sjmallett uint64_t reserved_32_63 : 32; 5427215976Sjmallett#endif 5428215976Sjmallett } s; 5429232812Sjmallett struct cvmx_sli_pkt_iptr_s cn61xx; 5430215976Sjmallett struct cvmx_sli_pkt_iptr_s cn63xx; 5431215976Sjmallett struct cvmx_sli_pkt_iptr_s cn63xxp1; 5432232812Sjmallett struct cvmx_sli_pkt_iptr_s cn66xx; 5433232812Sjmallett struct cvmx_sli_pkt_iptr_s cn68xx; 5434232812Sjmallett struct cvmx_sli_pkt_iptr_s cn68xxp1; 5435232812Sjmallett struct cvmx_sli_pkt_iptr_s cnf71xx; 5436215976Sjmallett}; 5437215976Sjmalletttypedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t; 5438215976Sjmallett 5439215976Sjmallett/** 5440215976Sjmallett * cvmx_sli_pkt_out_bmode 5441215976Sjmallett * 5442215976Sjmallett * SLI_PKT_OUT_BMODE = SLI's Packet Out Byte Mode 5443215976Sjmallett * 5444215976Sjmallett * Control the updating of the SLI_PKT#_CNT register. 5445215976Sjmallett */ 5446232812Sjmallettunion cvmx_sli_pkt_out_bmode { 5447215976Sjmallett uint64_t u64; 5448232812Sjmallett struct cvmx_sli_pkt_out_bmode_s { 5449232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5450215976Sjmallett uint64_t reserved_32_63 : 32; 5451215976Sjmallett uint64_t bmode : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or 5452215976Sjmallett packet counter. 5453215976Sjmallett When BMODE<i>=1, SLI_PKTi_CNTS[CNT] is a byte 5454215976Sjmallett counter, else SLI_PKTi_CNTS[CNT] is a packet 5455215976Sjmallett counter. */ 5456215976Sjmallett#else 5457215976Sjmallett uint64_t bmode : 32; 5458215976Sjmallett uint64_t reserved_32_63 : 32; 5459215976Sjmallett#endif 5460215976Sjmallett } s; 5461232812Sjmallett struct cvmx_sli_pkt_out_bmode_s cn61xx; 5462215976Sjmallett struct cvmx_sli_pkt_out_bmode_s cn63xx; 5463215976Sjmallett struct cvmx_sli_pkt_out_bmode_s cn63xxp1; 5464232812Sjmallett struct cvmx_sli_pkt_out_bmode_s cn66xx; 5465232812Sjmallett struct cvmx_sli_pkt_out_bmode_s cn68xx; 5466232812Sjmallett struct cvmx_sli_pkt_out_bmode_s cn68xxp1; 5467232812Sjmallett struct cvmx_sli_pkt_out_bmode_s cnf71xx; 5468215976Sjmallett}; 5469215976Sjmalletttypedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t; 5470215976Sjmallett 5471215976Sjmallett/** 5472232812Sjmallett * cvmx_sli_pkt_out_bp_en 5473232812Sjmallett * 5474232812Sjmallett * SLI_PKT_OUT_BP_EN = SLI Packet Output Backpressure Enable 5475232812Sjmallett * 5476232812Sjmallett * Enables sending backpressure to the PKO. 5477232812Sjmallett */ 5478232812Sjmallettunion cvmx_sli_pkt_out_bp_en { 5479232812Sjmallett uint64_t u64; 5480232812Sjmallett struct cvmx_sli_pkt_out_bp_en_s { 5481232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5482232812Sjmallett uint64_t reserved_32_63 : 32; 5483232812Sjmallett uint64_t bp_en : 32; /**< When set '1' enable the ring level backpressure 5484232812Sjmallett to be sent to PKO. Backpressure is sent to the 5485232812Sjmallett PKO on the PIPE number associated with the ring. 5486232812Sjmallett (See SLI_TX_PIPE for ring to pipe associations). */ 5487232812Sjmallett#else 5488232812Sjmallett uint64_t bp_en : 32; 5489232812Sjmallett uint64_t reserved_32_63 : 32; 5490232812Sjmallett#endif 5491232812Sjmallett } s; 5492232812Sjmallett struct cvmx_sli_pkt_out_bp_en_s cn68xx; 5493232812Sjmallett struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; 5494232812Sjmallett}; 5495232812Sjmalletttypedef union cvmx_sli_pkt_out_bp_en cvmx_sli_pkt_out_bp_en_t; 5496232812Sjmallett 5497232812Sjmallett/** 5498215976Sjmallett * cvmx_sli_pkt_out_enb 5499215976Sjmallett * 5500215976Sjmallett * SLI_PKT_OUT_ENB = SLI's Packet Output Enable 5501215976Sjmallett * 5502215976Sjmallett * Enables the output packet engines. 5503215976Sjmallett */ 5504232812Sjmallettunion cvmx_sli_pkt_out_enb { 5505215976Sjmallett uint64_t u64; 5506232812Sjmallett struct cvmx_sli_pkt_out_enb_s { 5507232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5508215976Sjmallett uint64_t reserved_32_63 : 32; 5509215976Sjmallett uint64_t enb : 32; /**< When ENB<i>=1, packet output ring i is enabled. 5510215976Sjmallett If an error occurs on reading pointers for an 5511215976Sjmallett output ring, the ring will be disabled by clearing 5512215976Sjmallett the bit associated with the ring to '0'. */ 5513215976Sjmallett#else 5514215976Sjmallett uint64_t enb : 32; 5515215976Sjmallett uint64_t reserved_32_63 : 32; 5516215976Sjmallett#endif 5517215976Sjmallett } s; 5518232812Sjmallett struct cvmx_sli_pkt_out_enb_s cn61xx; 5519215976Sjmallett struct cvmx_sli_pkt_out_enb_s cn63xx; 5520215976Sjmallett struct cvmx_sli_pkt_out_enb_s cn63xxp1; 5521232812Sjmallett struct cvmx_sli_pkt_out_enb_s cn66xx; 5522232812Sjmallett struct cvmx_sli_pkt_out_enb_s cn68xx; 5523232812Sjmallett struct cvmx_sli_pkt_out_enb_s cn68xxp1; 5524232812Sjmallett struct cvmx_sli_pkt_out_enb_s cnf71xx; 5525215976Sjmallett}; 5526215976Sjmalletttypedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t; 5527215976Sjmallett 5528215976Sjmallett/** 5529215976Sjmallett * cvmx_sli_pkt_output_wmark 5530215976Sjmallett * 5531215976Sjmallett * SLI_PKT_OUTPUT_WMARK = SLI's Packet Output Water Mark 5532215976Sjmallett * 5533215976Sjmallett * Value that when the SLI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied. 5534215976Sjmallett */ 5535232812Sjmallettunion cvmx_sli_pkt_output_wmark { 5536215976Sjmallett uint64_t u64; 5537232812Sjmallett struct cvmx_sli_pkt_output_wmark_s { 5538232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5539215976Sjmallett uint64_t reserved_32_63 : 32; 5540215976Sjmallett uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure 5541215976Sjmallett for the ring will be applied to the PKO. */ 5542215976Sjmallett#else 5543215976Sjmallett uint64_t wmark : 32; 5544215976Sjmallett uint64_t reserved_32_63 : 32; 5545215976Sjmallett#endif 5546215976Sjmallett } s; 5547232812Sjmallett struct cvmx_sli_pkt_output_wmark_s cn61xx; 5548215976Sjmallett struct cvmx_sli_pkt_output_wmark_s cn63xx; 5549215976Sjmallett struct cvmx_sli_pkt_output_wmark_s cn63xxp1; 5550232812Sjmallett struct cvmx_sli_pkt_output_wmark_s cn66xx; 5551232812Sjmallett struct cvmx_sli_pkt_output_wmark_s cn68xx; 5552232812Sjmallett struct cvmx_sli_pkt_output_wmark_s cn68xxp1; 5553232812Sjmallett struct cvmx_sli_pkt_output_wmark_s cnf71xx; 5554215976Sjmallett}; 5555215976Sjmalletttypedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t; 5556215976Sjmallett 5557215976Sjmallett/** 5558215976Sjmallett * cvmx_sli_pkt_pcie_port 5559215976Sjmallett * 5560215976Sjmallett * SLI_PKT_PCIE_PORT = SLI's Packet To MAC Port Assignment 5561215976Sjmallett * 5562215976Sjmallett * Assigns Packet Ports to MAC ports. 5563215976Sjmallett */ 5564232812Sjmallettunion cvmx_sli_pkt_pcie_port { 5565215976Sjmallett uint64_t u64; 5566232812Sjmallett struct cvmx_sli_pkt_pcie_port_s { 5567232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5568215976Sjmallett uint64_t pp : 64; /**< The physical MAC port that the output ring uses. 5569215976Sjmallett Two bits are used per ring (i.e. ring 0 [1:0], 5570215976Sjmallett ring 1 [3:2], ....). A value of '0 means 5571215976Sjmallett that the Packetring is assign to MAC Port 0, a '1' 5572215976Sjmallett MAC Port 1, '2' and '3' are reserved. */ 5573215976Sjmallett#else 5574215976Sjmallett uint64_t pp : 64; 5575215976Sjmallett#endif 5576215976Sjmallett } s; 5577232812Sjmallett struct cvmx_sli_pkt_pcie_port_s cn61xx; 5578215976Sjmallett struct cvmx_sli_pkt_pcie_port_s cn63xx; 5579215976Sjmallett struct cvmx_sli_pkt_pcie_port_s cn63xxp1; 5580232812Sjmallett struct cvmx_sli_pkt_pcie_port_s cn66xx; 5581232812Sjmallett struct cvmx_sli_pkt_pcie_port_s cn68xx; 5582232812Sjmallett struct cvmx_sli_pkt_pcie_port_s cn68xxp1; 5583232812Sjmallett struct cvmx_sli_pkt_pcie_port_s cnf71xx; 5584215976Sjmallett}; 5585215976Sjmalletttypedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t; 5586215976Sjmallett 5587215976Sjmallett/** 5588215976Sjmallett * cvmx_sli_pkt_port_in_rst 5589215976Sjmallett * 5590215976Sjmallett * 91c0 reserved 5591215976Sjmallett * 91d0 reserved 5592215976Sjmallett * 91e0 reserved 5593215976Sjmallett * 5594215976Sjmallett * 5595215976Sjmallett * SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset 5596215976Sjmallett * 5597215976Sjmallett * Vector bits related to ring-port for ones that are reset. 5598215976Sjmallett */ 5599232812Sjmallettunion cvmx_sli_pkt_port_in_rst { 5600215976Sjmallett uint64_t u64; 5601232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s { 5602232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5603215976Sjmallett uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding 5604215976Sjmallett to the inbound Packet-ring is in reset. */ 5605215976Sjmallett uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding 5606215976Sjmallett to the outbound Packet-ring is in reset. */ 5607215976Sjmallett#else 5608215976Sjmallett uint64_t out_rst : 32; 5609215976Sjmallett uint64_t in_rst : 32; 5610215976Sjmallett#endif 5611215976Sjmallett } s; 5612232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn61xx; 5613215976Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn63xx; 5614215976Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn63xxp1; 5615232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn66xx; 5616232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn68xx; 5617232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; 5618232812Sjmallett struct cvmx_sli_pkt_port_in_rst_s cnf71xx; 5619215976Sjmallett}; 5620215976Sjmalletttypedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t; 5621215976Sjmallett 5622215976Sjmallett/** 5623215976Sjmallett * cvmx_sli_pkt_slist_es 5624215976Sjmallett * 5625215976Sjmallett * SLI_PKT_SLIST_ES = SLI's Packet Scatter List Endian Swap 5626215976Sjmallett * 5627215976Sjmallett * The Endian Swap for Scatter List Read. 5628215976Sjmallett */ 5629232812Sjmallettunion cvmx_sli_pkt_slist_es { 5630215976Sjmallett uint64_t u64; 5631232812Sjmallett struct cvmx_sli_pkt_slist_es_s { 5632232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5633215976Sjmallett uint64_t es : 64; /**< ES<1:0> for the packet output ring reads that 5634215976Sjmallett fetch buffer/info pointer pairs. 5635215976Sjmallett ES<2i+1:2i> becomes ES<1:0> in DPI/SLI reads that 5636215976Sjmallett fetch buffer/info pairs from packet output ring i 5637215976Sjmallett (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 5638215976Sjmallett space.) 5639215976Sjmallett ES<1:0> is the endian-swap attribute for these MAC 5640215976Sjmallett memory space reads. */ 5641215976Sjmallett#else 5642215976Sjmallett uint64_t es : 64; 5643215976Sjmallett#endif 5644215976Sjmallett } s; 5645232812Sjmallett struct cvmx_sli_pkt_slist_es_s cn61xx; 5646215976Sjmallett struct cvmx_sli_pkt_slist_es_s cn63xx; 5647215976Sjmallett struct cvmx_sli_pkt_slist_es_s cn63xxp1; 5648232812Sjmallett struct cvmx_sli_pkt_slist_es_s cn66xx; 5649232812Sjmallett struct cvmx_sli_pkt_slist_es_s cn68xx; 5650232812Sjmallett struct cvmx_sli_pkt_slist_es_s cn68xxp1; 5651232812Sjmallett struct cvmx_sli_pkt_slist_es_s cnf71xx; 5652215976Sjmallett}; 5653215976Sjmalletttypedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t; 5654215976Sjmallett 5655215976Sjmallett/** 5656215976Sjmallett * cvmx_sli_pkt_slist_ns 5657215976Sjmallett * 5658215976Sjmallett * SLI_PKT_SLIST_NS = SLI's Packet Scatter List No Snoop 5659215976Sjmallett * 5660215976Sjmallett * The NS field for the TLP when fetching Scatter List. 5661215976Sjmallett */ 5662232812Sjmallettunion cvmx_sli_pkt_slist_ns { 5663215976Sjmallett uint64_t u64; 5664232812Sjmallett struct cvmx_sli_pkt_slist_ns_s { 5665232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5666215976Sjmallett uint64_t reserved_32_63 : 32; 5667215976Sjmallett uint64_t nsr : 32; /**< ADDRTYPE<1> for the packet output ring reads that 5668215976Sjmallett fetch buffer/info pointer pairs. 5669215976Sjmallett NSR<i> becomes ADDRTYPE<1> in DPI/SLI reads that 5670215976Sjmallett fetch buffer/info pairs from packet output ring i 5671215976Sjmallett (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 5672215976Sjmallett space.) 5673215976Sjmallett ADDRTYPE<1> is the relaxed-order attribute for PCIe 5674215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5675215976Sjmallett#else 5676215976Sjmallett uint64_t nsr : 32; 5677215976Sjmallett uint64_t reserved_32_63 : 32; 5678215976Sjmallett#endif 5679215976Sjmallett } s; 5680232812Sjmallett struct cvmx_sli_pkt_slist_ns_s cn61xx; 5681215976Sjmallett struct cvmx_sli_pkt_slist_ns_s cn63xx; 5682215976Sjmallett struct cvmx_sli_pkt_slist_ns_s cn63xxp1; 5683232812Sjmallett struct cvmx_sli_pkt_slist_ns_s cn66xx; 5684232812Sjmallett struct cvmx_sli_pkt_slist_ns_s cn68xx; 5685232812Sjmallett struct cvmx_sli_pkt_slist_ns_s cn68xxp1; 5686232812Sjmallett struct cvmx_sli_pkt_slist_ns_s cnf71xx; 5687215976Sjmallett}; 5688215976Sjmalletttypedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t; 5689215976Sjmallett 5690215976Sjmallett/** 5691215976Sjmallett * cvmx_sli_pkt_slist_ror 5692215976Sjmallett * 5693215976Sjmallett * SLI_PKT_SLIST_ROR = SLI's Packet Scatter List Relaxed Ordering 5694215976Sjmallett * 5695215976Sjmallett * The ROR field for the TLP when fetching Scatter List. 5696215976Sjmallett */ 5697232812Sjmallettunion cvmx_sli_pkt_slist_ror { 5698215976Sjmallett uint64_t u64; 5699232812Sjmallett struct cvmx_sli_pkt_slist_ror_s { 5700232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5701215976Sjmallett uint64_t reserved_32_63 : 32; 5702215976Sjmallett uint64_t ror : 32; /**< ADDRTYPE<0> for the packet output ring reads that 5703215976Sjmallett fetch buffer/info pointer pairs. 5704215976Sjmallett ROR<i> becomes ADDRTYPE<0> in DPI/SLI reads that 5705215976Sjmallett fetch buffer/info pairs from packet output ring i 5706215976Sjmallett (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 5707215976Sjmallett space.) 5708215976Sjmallett ADDRTYPE<0> is the relaxed-order attribute for PCIe 5709215976Sjmallett , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 5710215976Sjmallett#else 5711215976Sjmallett uint64_t ror : 32; 5712215976Sjmallett uint64_t reserved_32_63 : 32; 5713215976Sjmallett#endif 5714215976Sjmallett } s; 5715232812Sjmallett struct cvmx_sli_pkt_slist_ror_s cn61xx; 5716215976Sjmallett struct cvmx_sli_pkt_slist_ror_s cn63xx; 5717215976Sjmallett struct cvmx_sli_pkt_slist_ror_s cn63xxp1; 5718232812Sjmallett struct cvmx_sli_pkt_slist_ror_s cn66xx; 5719232812Sjmallett struct cvmx_sli_pkt_slist_ror_s cn68xx; 5720232812Sjmallett struct cvmx_sli_pkt_slist_ror_s cn68xxp1; 5721232812Sjmallett struct cvmx_sli_pkt_slist_ror_s cnf71xx; 5722215976Sjmallett}; 5723215976Sjmalletttypedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t; 5724215976Sjmallett 5725215976Sjmallett/** 5726215976Sjmallett * cvmx_sli_pkt_time_int 5727215976Sjmallett * 5728215976Sjmallett * SLI_PKT_TIME_INT = SLI Packet Timer Interrupt 5729215976Sjmallett * 5730215976Sjmallett * The packets rings that are interrupting because of Packet Timers. 5731215976Sjmallett */ 5732232812Sjmallettunion cvmx_sli_pkt_time_int { 5733215976Sjmallett uint64_t u64; 5734232812Sjmallett struct cvmx_sli_pkt_time_int_s { 5735232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5736215976Sjmallett uint64_t reserved_32_63 : 32; 5737215976Sjmallett uint64_t port : 32; /**< Output ring packet timer interrupt bits 5738215976Sjmallett SLI sets PORT<i> whenever 5739215976Sjmallett SLI_PKTi_CNTS[TIMER] > SLI_PKT_INT_LEVELS[TIME]. 5740215976Sjmallett SLI_PKT_TIME_INT_ENB[PORT<i>] is the corresponding 5741215976Sjmallett enable. */ 5742215976Sjmallett#else 5743215976Sjmallett uint64_t port : 32; 5744215976Sjmallett uint64_t reserved_32_63 : 32; 5745215976Sjmallett#endif 5746215976Sjmallett } s; 5747232812Sjmallett struct cvmx_sli_pkt_time_int_s cn61xx; 5748215976Sjmallett struct cvmx_sli_pkt_time_int_s cn63xx; 5749215976Sjmallett struct cvmx_sli_pkt_time_int_s cn63xxp1; 5750232812Sjmallett struct cvmx_sli_pkt_time_int_s cn66xx; 5751232812Sjmallett struct cvmx_sli_pkt_time_int_s cn68xx; 5752232812Sjmallett struct cvmx_sli_pkt_time_int_s cn68xxp1; 5753232812Sjmallett struct cvmx_sli_pkt_time_int_s cnf71xx; 5754215976Sjmallett}; 5755215976Sjmalletttypedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t; 5756215976Sjmallett 5757215976Sjmallett/** 5758215976Sjmallett * cvmx_sli_pkt_time_int_enb 5759215976Sjmallett * 5760215976Sjmallett * SLI_PKT_TIME_INT_ENB = SLI Packet Timer Interrupt Enable 5761215976Sjmallett * 5762215976Sjmallett * The packets rings that are interrupting because of Packet Timers. 5763215976Sjmallett */ 5764232812Sjmallettunion cvmx_sli_pkt_time_int_enb { 5765215976Sjmallett uint64_t u64; 5766232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s { 5767232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5768215976Sjmallett uint64_t reserved_32_63 : 32; 5769215976Sjmallett uint64_t port : 32; /**< Output ring packet timer interrupt enables 5770215976Sjmallett When both PORT<i> and corresponding 5771215976Sjmallett SLI_PKT_TIME_INT[PORT<i>] are set, for any i, 5772215976Sjmallett then SLI_INT_SUM[PTIME] is set, which can cause 5773215976Sjmallett an interrupt. */ 5774215976Sjmallett#else 5775215976Sjmallett uint64_t port : 32; 5776215976Sjmallett uint64_t reserved_32_63 : 32; 5777215976Sjmallett#endif 5778215976Sjmallett } s; 5779232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn61xx; 5780215976Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn63xx; 5781215976Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn63xxp1; 5782232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn66xx; 5783232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn68xx; 5784232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; 5785232812Sjmallett struct cvmx_sli_pkt_time_int_enb_s cnf71xx; 5786215976Sjmallett}; 5787215976Sjmalletttypedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t; 5788215976Sjmallett 5789215976Sjmallett/** 5790232812Sjmallett * cvmx_sli_port#_pkind 5791232812Sjmallett * 5792232812Sjmallett * SLI_PORT[0..31]_PKIND = SLI Port Pkind 5793232812Sjmallett * 5794232812Sjmallett * The SLI/DPI supports 32 input rings for fetching input packets. This register maps the input-rings (0-31) to a PKIND. 5795232812Sjmallett */ 5796232812Sjmallettunion cvmx_sli_portx_pkind { 5797232812Sjmallett uint64_t u64; 5798232812Sjmallett struct cvmx_sli_portx_pkind_s { 5799232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5800232812Sjmallett uint64_t reserved_25_63 : 39; 5801232812Sjmallett uint64_t rpk_enb : 1; /**< Alternate PKT_INST_HDR PKind Enable for this ring. 5802232812Sjmallett When RPK_ENB==1 and DPI prepends 5803232812Sjmallett a PKT_INST_HDR to a packet, the pkind for the 5804232812Sjmallett packet is PKINDR (rather than PKIND), and any 5805232812Sjmallett special PIP/IPD processing of the DPI packet is 5806232812Sjmallett disabled (see PIP_PRT_CFG*[INST_HDR,HIGIG_EN]). 5807232812Sjmallett (DPI prepends a PKT_INST_HDR when either 5808232812Sjmallett DPI_INST_HDR[R]==1 for the packet or 5809232812Sjmallett SLI_PKT*_INSTR_HEADER[USE_IHDR]==1 for the ring.) 5810232812Sjmallett When RPK_ENB==0, PKIND is the pkind for all 5811232812Sjmallett packets through the input ring, and 5812232812Sjmallett PIP/IPD will process a DPI packet that has a 5813232812Sjmallett PKT_INST_HDR specially. */ 5814232812Sjmallett uint64_t reserved_22_23 : 2; 5815232812Sjmallett uint64_t pkindr : 6; /**< Port Kind For this Ring used with packets 5816232812Sjmallett that include a DPI-prepended PKT_INST_HDR 5817232812Sjmallett when RPK_ENB is set. */ 5818232812Sjmallett uint64_t reserved_14_15 : 2; 5819232812Sjmallett uint64_t bpkind : 6; /**< Back-pressure pkind for this Ring. */ 5820232812Sjmallett uint64_t reserved_6_7 : 2; 5821232812Sjmallett uint64_t pkind : 6; /**< Port Kind For this Ring. */ 5822232812Sjmallett#else 5823232812Sjmallett uint64_t pkind : 6; 5824232812Sjmallett uint64_t reserved_6_7 : 2; 5825232812Sjmallett uint64_t bpkind : 6; 5826232812Sjmallett uint64_t reserved_14_15 : 2; 5827232812Sjmallett uint64_t pkindr : 6; 5828232812Sjmallett uint64_t reserved_22_23 : 2; 5829232812Sjmallett uint64_t rpk_enb : 1; 5830232812Sjmallett uint64_t reserved_25_63 : 39; 5831232812Sjmallett#endif 5832232812Sjmallett } s; 5833232812Sjmallett struct cvmx_sli_portx_pkind_s cn68xx; 5834232812Sjmallett struct cvmx_sli_portx_pkind_cn68xxp1 { 5835232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5836232812Sjmallett uint64_t reserved_14_63 : 50; 5837232812Sjmallett uint64_t bpkind : 6; /**< Back-pressure pkind for this Ring. */ 5838232812Sjmallett uint64_t reserved_6_7 : 2; 5839232812Sjmallett uint64_t pkind : 6; /**< Port Kind For this Ring. */ 5840232812Sjmallett#else 5841232812Sjmallett uint64_t pkind : 6; 5842232812Sjmallett uint64_t reserved_6_7 : 2; 5843232812Sjmallett uint64_t bpkind : 6; 5844232812Sjmallett uint64_t reserved_14_63 : 50; 5845232812Sjmallett#endif 5846232812Sjmallett } cn68xxp1; 5847232812Sjmallett}; 5848232812Sjmalletttypedef union cvmx_sli_portx_pkind cvmx_sli_portx_pkind_t; 5849232812Sjmallett 5850232812Sjmallett/** 5851215976Sjmallett * cvmx_sli_s2m_port#_ctl 5852215976Sjmallett * 5853215976Sjmallett * SLI_S2M_PORTX_CTL = SLI's S2M Port 0 Control 5854215976Sjmallett * 5855215976Sjmallett * Contains control for access from SLI to a MAC port. 5856215976Sjmallett * Writes to this register are not ordered with writes/reads to the MAC Memory space. 5857215976Sjmallett * To ensure that a write has completed the user must read the register before 5858215976Sjmallett * making an access(i.e. MAC memory space) that requires the value of this register to be updated. 5859215976Sjmallett */ 5860232812Sjmallettunion cvmx_sli_s2m_portx_ctl { 5861215976Sjmallett uint64_t u64; 5862232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s { 5863232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5864215976Sjmallett uint64_t reserved_5_63 : 59; 5865215976Sjmallett uint64_t wind_d : 1; /**< When set '1' disables access to the Window 5866232812Sjmallett Registers from the MAC-Port. 5867232812Sjmallett When Authenticate-Mode is set the reset value of 5868232812Sjmallett this field is "1" else "0'. */ 5869215976Sjmallett uint64_t bar0_d : 1; /**< When set '1' disables access from MAC to 5870215976Sjmallett BAR-0 address offsets: Less Than 0x330, 5871232812Sjmallett 0x3CD0, and greater than 0x3D70 excluding 5872232812Sjmallett 0x3e00. 5873232812Sjmallett When Authenticate-Mode is set the reset value of 5874232812Sjmallett this field is "1" else "0'. */ 5875215976Sjmallett uint64_t mrrs : 3; /**< Max Read Request Size 5876215976Sjmallett 0 = 128B 5877215976Sjmallett 1 = 256B 5878215976Sjmallett 2 = 512B 5879215976Sjmallett 3 = 1024B 5880215976Sjmallett 4 = 2048B 5881215976Sjmallett 5-7 = Reserved 5882215976Sjmallett This field should not exceed the desired 5883215976Sjmallett max read request size. This field is used to 5884215976Sjmallett determine if an IOBDMA is too large. 5885215976Sjmallett For a PCIe MAC, this field should not exceed 5886215976Sjmallett PCIE*_CFG030[MRRS]. 5887215976Sjmallett For a sRIO MAC, this field should indicate a size 5888215976Sjmallett of 256B or smaller. */ 5889215976Sjmallett#else 5890215976Sjmallett uint64_t mrrs : 3; 5891215976Sjmallett uint64_t bar0_d : 1; 5892215976Sjmallett uint64_t wind_d : 1; 5893215976Sjmallett uint64_t reserved_5_63 : 59; 5894215976Sjmallett#endif 5895215976Sjmallett } s; 5896232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn61xx; 5897215976Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn63xx; 5898215976Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn63xxp1; 5899232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn66xx; 5900232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn68xx; 5901232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; 5902232812Sjmallett struct cvmx_sli_s2m_portx_ctl_s cnf71xx; 5903215976Sjmallett}; 5904215976Sjmalletttypedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t; 5905215976Sjmallett 5906215976Sjmallett/** 5907215976Sjmallett * cvmx_sli_scratch_1 5908215976Sjmallett * 5909215976Sjmallett * SLI_SCRATCH_1 = SLI's Scratch 1 5910215976Sjmallett * 5911215976Sjmallett * A general purpose 64 bit register for SW use. 5912215976Sjmallett */ 5913232812Sjmallettunion cvmx_sli_scratch_1 { 5914215976Sjmallett uint64_t u64; 5915232812Sjmallett struct cvmx_sli_scratch_1_s { 5916232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5917215976Sjmallett uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 5918215976Sjmallett#else 5919215976Sjmallett uint64_t data : 64; 5920215976Sjmallett#endif 5921215976Sjmallett } s; 5922232812Sjmallett struct cvmx_sli_scratch_1_s cn61xx; 5923215976Sjmallett struct cvmx_sli_scratch_1_s cn63xx; 5924215976Sjmallett struct cvmx_sli_scratch_1_s cn63xxp1; 5925232812Sjmallett struct cvmx_sli_scratch_1_s cn66xx; 5926232812Sjmallett struct cvmx_sli_scratch_1_s cn68xx; 5927232812Sjmallett struct cvmx_sli_scratch_1_s cn68xxp1; 5928232812Sjmallett struct cvmx_sli_scratch_1_s cnf71xx; 5929215976Sjmallett}; 5930215976Sjmalletttypedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t; 5931215976Sjmallett 5932215976Sjmallett/** 5933215976Sjmallett * cvmx_sli_scratch_2 5934215976Sjmallett * 5935215976Sjmallett * SLI_SCRATCH_2 = SLI's Scratch 2 5936215976Sjmallett * 5937215976Sjmallett * A general purpose 64 bit register for SW use. 5938215976Sjmallett */ 5939232812Sjmallettunion cvmx_sli_scratch_2 { 5940215976Sjmallett uint64_t u64; 5941232812Sjmallett struct cvmx_sli_scratch_2_s { 5942232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5943215976Sjmallett uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 5944215976Sjmallett#else 5945215976Sjmallett uint64_t data : 64; 5946215976Sjmallett#endif 5947215976Sjmallett } s; 5948232812Sjmallett struct cvmx_sli_scratch_2_s cn61xx; 5949215976Sjmallett struct cvmx_sli_scratch_2_s cn63xx; 5950215976Sjmallett struct cvmx_sli_scratch_2_s cn63xxp1; 5951232812Sjmallett struct cvmx_sli_scratch_2_s cn66xx; 5952232812Sjmallett struct cvmx_sli_scratch_2_s cn68xx; 5953232812Sjmallett struct cvmx_sli_scratch_2_s cn68xxp1; 5954232812Sjmallett struct cvmx_sli_scratch_2_s cnf71xx; 5955215976Sjmallett}; 5956215976Sjmalletttypedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t; 5957215976Sjmallett 5958215976Sjmallett/** 5959215976Sjmallett * cvmx_sli_state1 5960215976Sjmallett * 5961215976Sjmallett * SLI_STATE1 = SLI State 1 5962215976Sjmallett * 5963215976Sjmallett * State machines in SLI. For debug. 5964215976Sjmallett */ 5965232812Sjmallettunion cvmx_sli_state1 { 5966215976Sjmallett uint64_t u64; 5967232812Sjmallett struct cvmx_sli_state1_s { 5968232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5969215976Sjmallett uint64_t cpl1 : 12; /**< CPL1 State */ 5970215976Sjmallett uint64_t cpl0 : 12; /**< CPL0 State */ 5971215976Sjmallett uint64_t arb : 1; /**< ARB State */ 5972215976Sjmallett uint64_t csr : 39; /**< CSR State */ 5973215976Sjmallett#else 5974215976Sjmallett uint64_t csr : 39; 5975215976Sjmallett uint64_t arb : 1; 5976215976Sjmallett uint64_t cpl0 : 12; 5977215976Sjmallett uint64_t cpl1 : 12; 5978215976Sjmallett#endif 5979215976Sjmallett } s; 5980232812Sjmallett struct cvmx_sli_state1_s cn61xx; 5981215976Sjmallett struct cvmx_sli_state1_s cn63xx; 5982215976Sjmallett struct cvmx_sli_state1_s cn63xxp1; 5983232812Sjmallett struct cvmx_sli_state1_s cn66xx; 5984232812Sjmallett struct cvmx_sli_state1_s cn68xx; 5985232812Sjmallett struct cvmx_sli_state1_s cn68xxp1; 5986232812Sjmallett struct cvmx_sli_state1_s cnf71xx; 5987215976Sjmallett}; 5988215976Sjmalletttypedef union cvmx_sli_state1 cvmx_sli_state1_t; 5989215976Sjmallett 5990215976Sjmallett/** 5991215976Sjmallett * cvmx_sli_state2 5992215976Sjmallett * 5993215976Sjmallett * SLI_STATE2 = SLI State 2 5994215976Sjmallett * 5995215976Sjmallett * State machines in SLI. For debug. 5996215976Sjmallett */ 5997232812Sjmallettunion cvmx_sli_state2 { 5998215976Sjmallett uint64_t u64; 5999232812Sjmallett struct cvmx_sli_state2_s { 6000232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6001215976Sjmallett uint64_t reserved_56_63 : 8; 6002215976Sjmallett uint64_t nnp1 : 8; /**< NNP1 State */ 6003215976Sjmallett uint64_t reserved_47_47 : 1; 6004215976Sjmallett uint64_t rac : 1; /**< RAC State */ 6005215976Sjmallett uint64_t csm1 : 15; /**< CSM1 State */ 6006215976Sjmallett uint64_t csm0 : 15; /**< CSM0 State */ 6007215976Sjmallett uint64_t nnp0 : 8; /**< NNP0 State */ 6008215976Sjmallett uint64_t nnd : 8; /**< NND State */ 6009215976Sjmallett#else 6010215976Sjmallett uint64_t nnd : 8; 6011215976Sjmallett uint64_t nnp0 : 8; 6012215976Sjmallett uint64_t csm0 : 15; 6013215976Sjmallett uint64_t csm1 : 15; 6014215976Sjmallett uint64_t rac : 1; 6015215976Sjmallett uint64_t reserved_47_47 : 1; 6016215976Sjmallett uint64_t nnp1 : 8; 6017215976Sjmallett uint64_t reserved_56_63 : 8; 6018215976Sjmallett#endif 6019215976Sjmallett } s; 6020232812Sjmallett struct cvmx_sli_state2_s cn61xx; 6021215976Sjmallett struct cvmx_sli_state2_s cn63xx; 6022215976Sjmallett struct cvmx_sli_state2_s cn63xxp1; 6023232812Sjmallett struct cvmx_sli_state2_s cn66xx; 6024232812Sjmallett struct cvmx_sli_state2_s cn68xx; 6025232812Sjmallett struct cvmx_sli_state2_s cn68xxp1; 6026232812Sjmallett struct cvmx_sli_state2_s cnf71xx; 6027215976Sjmallett}; 6028215976Sjmalletttypedef union cvmx_sli_state2 cvmx_sli_state2_t; 6029215976Sjmallett 6030215976Sjmallett/** 6031215976Sjmallett * cvmx_sli_state3 6032215976Sjmallett * 6033215976Sjmallett * SLI_STATE3 = SLI State 3 6034215976Sjmallett * 6035215976Sjmallett * State machines in SLI. For debug. 6036215976Sjmallett */ 6037232812Sjmallettunion cvmx_sli_state3 { 6038215976Sjmallett uint64_t u64; 6039232812Sjmallett struct cvmx_sli_state3_s { 6040232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6041215976Sjmallett uint64_t reserved_56_63 : 8; 6042215976Sjmallett uint64_t psm1 : 15; /**< PSM1 State */ 6043215976Sjmallett uint64_t psm0 : 15; /**< PSM0 State */ 6044215976Sjmallett uint64_t nsm1 : 13; /**< NSM1 State */ 6045215976Sjmallett uint64_t nsm0 : 13; /**< NSM0 State */ 6046215976Sjmallett#else 6047215976Sjmallett uint64_t nsm0 : 13; 6048215976Sjmallett uint64_t nsm1 : 13; 6049215976Sjmallett uint64_t psm0 : 15; 6050215976Sjmallett uint64_t psm1 : 15; 6051215976Sjmallett uint64_t reserved_56_63 : 8; 6052215976Sjmallett#endif 6053215976Sjmallett } s; 6054232812Sjmallett struct cvmx_sli_state3_s cn61xx; 6055215976Sjmallett struct cvmx_sli_state3_s cn63xx; 6056215976Sjmallett struct cvmx_sli_state3_s cn63xxp1; 6057232812Sjmallett struct cvmx_sli_state3_s cn66xx; 6058232812Sjmallett struct cvmx_sli_state3_s cn68xx; 6059232812Sjmallett struct cvmx_sli_state3_s cn68xxp1; 6060232812Sjmallett struct cvmx_sli_state3_s cnf71xx; 6061215976Sjmallett}; 6062215976Sjmalletttypedef union cvmx_sli_state3 cvmx_sli_state3_t; 6063215976Sjmallett 6064215976Sjmallett/** 6065232812Sjmallett * cvmx_sli_tx_pipe 6066232812Sjmallett * 6067232812Sjmallett * SLI_TX_PIPE = SLI Packet TX Pipe 6068232812Sjmallett * 6069232812Sjmallett * Contains the starting pipe number and number of pipes used by the SLI packet Output. 6070232812Sjmallett * If a packet is recevied from PKO with an out of range PIPE number, the following occurs: 6071232812Sjmallett * - SLI_INT_SUM[PIPE_ERR] is set. 6072232812Sjmallett * - the out of range pipe value is used for returning credits to the PKO. 6073232812Sjmallett * - the PCIe packet engine will treat the PIPE value to be equal to [BASE]. 6074232812Sjmallett */ 6075232812Sjmallettunion cvmx_sli_tx_pipe { 6076232812Sjmallett uint64_t u64; 6077232812Sjmallett struct cvmx_sli_tx_pipe_s { 6078232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6079232812Sjmallett uint64_t reserved_24_63 : 40; 6080232812Sjmallett uint64_t nump : 8; /**< Number of pipes the the SLI/DPI supports. 6081232812Sjmallett When this value is 4 or less there is a performance 6082232812Sjmallett advantage for output packets. 6083232812Sjmallett The SLI/DPI can support up to 32 pipes assigned to 6084232812Sjmallett packet-rings 0 - 31. */ 6085232812Sjmallett uint64_t reserved_7_15 : 9; 6086232812Sjmallett uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe 6087232812Sjmallett number the SLI/DPI will accept. 6088232812Sjmallett The SLI/DPI will accept pko packets from pipes in 6089232812Sjmallett the range of: 6090232812Sjmallett BASE .. (BASE+(NUMP-1)) 6091232812Sjmallett BASE and NUMP must be constrained such that 6092232812Sjmallett 1) BASE+(NUMP-1) < 127 6093232812Sjmallett 2) Each used PKO pipe must map to exactly 6094232812Sjmallett one ring. Where BASE == ring 0, BASE+1 == to 6095232812Sjmallett ring 1, etc 6096232812Sjmallett 3) The pipe ranges must be consistent with 6097232812Sjmallett the PKO configuration. */ 6098232812Sjmallett#else 6099232812Sjmallett uint64_t base : 7; 6100232812Sjmallett uint64_t reserved_7_15 : 9; 6101232812Sjmallett uint64_t nump : 8; 6102232812Sjmallett uint64_t reserved_24_63 : 40; 6103232812Sjmallett#endif 6104232812Sjmallett } s; 6105232812Sjmallett struct cvmx_sli_tx_pipe_s cn68xx; 6106232812Sjmallett struct cvmx_sli_tx_pipe_s cn68xxp1; 6107232812Sjmallett}; 6108232812Sjmalletttypedef union cvmx_sli_tx_pipe cvmx_sli_tx_pipe_t; 6109232812Sjmallett 6110232812Sjmallett/** 6111215976Sjmallett * cvmx_sli_win_rd_addr 6112215976Sjmallett * 6113215976Sjmallett * SLI_WIN_RD_ADDR = SLI Window Read Address Register 6114215976Sjmallett * 6115215976Sjmallett * The address to be read when the SLI_WIN_RD_DATA register is read. 6116215976Sjmallett * This register should NOT be used to read SLI_* registers. 6117215976Sjmallett */ 6118232812Sjmallettunion cvmx_sli_win_rd_addr { 6119215976Sjmallett uint64_t u64; 6120232812Sjmallett struct cvmx_sli_win_rd_addr_s { 6121232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6122215976Sjmallett uint64_t reserved_51_63 : 13; 6123215976Sjmallett uint64_t ld_cmd : 2; /**< The load command sent wit hthe read. 6124215976Sjmallett 0x3 == Load 8-bytes, 0x2 == Load 4-bytes, 6125215976Sjmallett 0x1 == Load 2-bytes, 0x0 == Load 1-bytes, */ 6126215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but will not be used 6127215976Sjmallett in address generation. */ 6128215976Sjmallett uint64_t rd_addr : 48; /**< The address to be read from. 6129215976Sjmallett [47:40] = NCB_ID 6130215976Sjmallett [39:0] = Address 6131215976Sjmallett When [47:43] == SLI & [42:40] == 0 bits [39:0] are: 6132215976Sjmallett [39:32] == x, Not Used 6133215976Sjmallett [31:24] == RSL_ID 6134215976Sjmallett [23:0] == RSL Register Offset */ 6135215976Sjmallett#else 6136215976Sjmallett uint64_t rd_addr : 48; 6137215976Sjmallett uint64_t iobit : 1; 6138215976Sjmallett uint64_t ld_cmd : 2; 6139215976Sjmallett uint64_t reserved_51_63 : 13; 6140215976Sjmallett#endif 6141215976Sjmallett } s; 6142232812Sjmallett struct cvmx_sli_win_rd_addr_s cn61xx; 6143215976Sjmallett struct cvmx_sli_win_rd_addr_s cn63xx; 6144215976Sjmallett struct cvmx_sli_win_rd_addr_s cn63xxp1; 6145232812Sjmallett struct cvmx_sli_win_rd_addr_s cn66xx; 6146232812Sjmallett struct cvmx_sli_win_rd_addr_s cn68xx; 6147232812Sjmallett struct cvmx_sli_win_rd_addr_s cn68xxp1; 6148232812Sjmallett struct cvmx_sli_win_rd_addr_s cnf71xx; 6149215976Sjmallett}; 6150215976Sjmalletttypedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t; 6151215976Sjmallett 6152215976Sjmallett/** 6153215976Sjmallett * cvmx_sli_win_rd_data 6154215976Sjmallett * 6155215976Sjmallett * SLI_WIN_RD_DATA = SLI Window Read Data Register 6156215976Sjmallett * 6157215976Sjmallett * Reading this register causes a window read operation to take place. Address read is that contained in the SLI_WIN_RD_ADDR 6158215976Sjmallett * register. 6159215976Sjmallett */ 6160232812Sjmallettunion cvmx_sli_win_rd_data { 6161215976Sjmallett uint64_t u64; 6162232812Sjmallett struct cvmx_sli_win_rd_data_s { 6163232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6164215976Sjmallett uint64_t rd_data : 64; /**< The read data. */ 6165215976Sjmallett#else 6166215976Sjmallett uint64_t rd_data : 64; 6167215976Sjmallett#endif 6168215976Sjmallett } s; 6169232812Sjmallett struct cvmx_sli_win_rd_data_s cn61xx; 6170215976Sjmallett struct cvmx_sli_win_rd_data_s cn63xx; 6171215976Sjmallett struct cvmx_sli_win_rd_data_s cn63xxp1; 6172232812Sjmallett struct cvmx_sli_win_rd_data_s cn66xx; 6173232812Sjmallett struct cvmx_sli_win_rd_data_s cn68xx; 6174232812Sjmallett struct cvmx_sli_win_rd_data_s cn68xxp1; 6175232812Sjmallett struct cvmx_sli_win_rd_data_s cnf71xx; 6176215976Sjmallett}; 6177215976Sjmalletttypedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t; 6178215976Sjmallett 6179215976Sjmallett/** 6180215976Sjmallett * cvmx_sli_win_wr_addr 6181215976Sjmallett * 6182215976Sjmallett * Add Lock Register (Set on Read, Clear on write), SW uses to control access to BAR0 space. 6183215976Sjmallett * 6184215976Sjmallett * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B) 6185215976Sjmallett * 6186215976Sjmallett * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General) 6187215976Sjmallett * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet) 6188215976Sjmallett * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode) 6189215976Sjmallett * 6190215976Sjmallett * SLI_WIN_WR_ADDR = SLI Window Write Address Register 6191215976Sjmallett * 6192215976Sjmallett * Contains the address to be writen to when a write operation is started by writing the 6193215976Sjmallett * SLI_WIN_WR_DATA register (see below). 6194215976Sjmallett * 6195215976Sjmallett * This register should NOT be used to write SLI_* registers. 6196215976Sjmallett */ 6197232812Sjmallettunion cvmx_sli_win_wr_addr { 6198215976Sjmallett uint64_t u64; 6199232812Sjmallett struct cvmx_sli_win_wr_addr_s { 6200232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6201215976Sjmallett uint64_t reserved_49_63 : 15; 6202215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 6203215976Sjmallett read as '0'. */ 6204215976Sjmallett uint64_t wr_addr : 45; /**< The address that will be written to when the 6205215976Sjmallett SLI_WIN_WR_DATA register is written. 6206215976Sjmallett [47:40] = NCB_ID 6207215976Sjmallett [39:3] = Address 6208215976Sjmallett When [47:43] == SLI & [42:40] == 0 bits [39:0] are: 6209215976Sjmallett [39:32] == x, Not Used 6210215976Sjmallett [31:24] == RSL_ID 6211215976Sjmallett [23:3] == RSL Register Offset */ 6212215976Sjmallett uint64_t reserved_0_2 : 3; 6213215976Sjmallett#else 6214215976Sjmallett uint64_t reserved_0_2 : 3; 6215215976Sjmallett uint64_t wr_addr : 45; 6216215976Sjmallett uint64_t iobit : 1; 6217215976Sjmallett uint64_t reserved_49_63 : 15; 6218215976Sjmallett#endif 6219215976Sjmallett } s; 6220232812Sjmallett struct cvmx_sli_win_wr_addr_s cn61xx; 6221215976Sjmallett struct cvmx_sli_win_wr_addr_s cn63xx; 6222215976Sjmallett struct cvmx_sli_win_wr_addr_s cn63xxp1; 6223232812Sjmallett struct cvmx_sli_win_wr_addr_s cn66xx; 6224232812Sjmallett struct cvmx_sli_win_wr_addr_s cn68xx; 6225232812Sjmallett struct cvmx_sli_win_wr_addr_s cn68xxp1; 6226232812Sjmallett struct cvmx_sli_win_wr_addr_s cnf71xx; 6227215976Sjmallett}; 6228215976Sjmalletttypedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t; 6229215976Sjmallett 6230215976Sjmallett/** 6231215976Sjmallett * cvmx_sli_win_wr_data 6232215976Sjmallett * 6233215976Sjmallett * SLI_WIN_WR_DATA = SLI Window Write Data Register 6234215976Sjmallett * 6235215976Sjmallett * Contains the data to write to the address located in the SLI_WIN_WR_ADDR Register. 6236215976Sjmallett * Writing the least-significant-byte of this register will cause a write operation to take place. 6237215976Sjmallett */ 6238232812Sjmallettunion cvmx_sli_win_wr_data { 6239215976Sjmallett uint64_t u64; 6240232812Sjmallett struct cvmx_sli_win_wr_data_s { 6241232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6242215976Sjmallett uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 6243215976Sjmallett register is written, the Window Write will take 6244215976Sjmallett place. */ 6245215976Sjmallett#else 6246215976Sjmallett uint64_t wr_data : 64; 6247215976Sjmallett#endif 6248215976Sjmallett } s; 6249232812Sjmallett struct cvmx_sli_win_wr_data_s cn61xx; 6250215976Sjmallett struct cvmx_sli_win_wr_data_s cn63xx; 6251215976Sjmallett struct cvmx_sli_win_wr_data_s cn63xxp1; 6252232812Sjmallett struct cvmx_sli_win_wr_data_s cn66xx; 6253232812Sjmallett struct cvmx_sli_win_wr_data_s cn68xx; 6254232812Sjmallett struct cvmx_sli_win_wr_data_s cn68xxp1; 6255232812Sjmallett struct cvmx_sli_win_wr_data_s cnf71xx; 6256215976Sjmallett}; 6257215976Sjmalletttypedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t; 6258215976Sjmallett 6259215976Sjmallett/** 6260215976Sjmallett * cvmx_sli_win_wr_mask 6261215976Sjmallett * 6262215976Sjmallett * SLI_WIN_WR_MASK = SLI Window Write Mask Register 6263215976Sjmallett * 6264215976Sjmallett * Contains the mask for the data in the SLI_WIN_WR_DATA Register. 6265215976Sjmallett */ 6266232812Sjmallettunion cvmx_sli_win_wr_mask { 6267215976Sjmallett uint64_t u64; 6268232812Sjmallett struct cvmx_sli_win_wr_mask_s { 6269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6270215976Sjmallett uint64_t reserved_8_63 : 56; 6271215976Sjmallett uint64_t wr_mask : 8; /**< The data to be written. When a bit is '1' 6272215976Sjmallett the corresponding byte will be written. The values 6273215976Sjmallett of this field must be contiguos and for 1, 2, 4, or 6274215976Sjmallett 8 byte operations and aligned to operation size. 6275215976Sjmallett A Value of 0 will produce unpredictable results */ 6276215976Sjmallett#else 6277215976Sjmallett uint64_t wr_mask : 8; 6278215976Sjmallett uint64_t reserved_8_63 : 56; 6279215976Sjmallett#endif 6280215976Sjmallett } s; 6281232812Sjmallett struct cvmx_sli_win_wr_mask_s cn61xx; 6282215976Sjmallett struct cvmx_sli_win_wr_mask_s cn63xx; 6283215976Sjmallett struct cvmx_sli_win_wr_mask_s cn63xxp1; 6284232812Sjmallett struct cvmx_sli_win_wr_mask_s cn66xx; 6285232812Sjmallett struct cvmx_sli_win_wr_mask_s cn68xx; 6286232812Sjmallett struct cvmx_sli_win_wr_mask_s cn68xxp1; 6287232812Sjmallett struct cvmx_sli_win_wr_mask_s cnf71xx; 6288215976Sjmallett}; 6289215976Sjmalletttypedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t; 6290215976Sjmallett 6291215976Sjmallett/** 6292215976Sjmallett * cvmx_sli_window_ctl 6293215976Sjmallett * 6294215976Sjmallett * // * 6295215976Sjmallett * // * 81e0 - 82d0 Reserved for future subids 6296215976Sjmallett * // * 6297215976Sjmallett * 6298215976Sjmallett * SLI_WINDOW_CTL = SLI's Window Control 6299215976Sjmallett * 6300215976Sjmallett * Access to register space on the NCB (caused by Window Reads/Writes) will wait for a period of time specified 6301215976Sjmallett * by this register before timeing out. Because a Window Access can access the RML, which has a fixed timeout of 0xFFFF 6302215976Sjmallett * core clocks, the value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register 6303215976Sjmallett * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the MAC. 6304215976Sjmallett */ 6305232812Sjmallettunion cvmx_sli_window_ctl { 6306215976Sjmallett uint64_t u64; 6307232812Sjmallett struct cvmx_sli_window_ctl_s { 6308232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6309215976Sjmallett uint64_t reserved_32_63 : 32; 6310215976Sjmallett uint64_t time : 32; /**< Time to wait in core clocks for a 6311215976Sjmallett BAR0 access to completeon the NCB 6312215976Sjmallett before timing out. A value of 0 will cause no 6313215976Sjmallett timeouts. A minimum value of 0x200000 should be 6314215976Sjmallett used when this register is not set to 0x0. */ 6315215976Sjmallett#else 6316215976Sjmallett uint64_t time : 32; 6317215976Sjmallett uint64_t reserved_32_63 : 32; 6318215976Sjmallett#endif 6319215976Sjmallett } s; 6320232812Sjmallett struct cvmx_sli_window_ctl_s cn61xx; 6321215976Sjmallett struct cvmx_sli_window_ctl_s cn63xx; 6322215976Sjmallett struct cvmx_sli_window_ctl_s cn63xxp1; 6323232812Sjmallett struct cvmx_sli_window_ctl_s cn66xx; 6324232812Sjmallett struct cvmx_sli_window_ctl_s cn68xx; 6325232812Sjmallett struct cvmx_sli_window_ctl_s cn68xxp1; 6326232812Sjmallett struct cvmx_sli_window_ctl_s cnf71xx; 6327215976Sjmallett}; 6328215976Sjmalletttypedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t; 6329215976Sjmallett 6330215976Sjmallett#endif 6331