1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-rad-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon rad. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_RAD_DEFS_H__ 53232812Sjmallett#define __CVMX_RAD_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001000ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001008ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void) 80215976Sjmallett{ 81232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001010ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void) 91215976Sjmallett{ 92232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93215976Sjmallett cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000080ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void) 102215976Sjmallett{ 103232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 104215976Sjmallett cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000008ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_CTL_FUNC(void) 113215976Sjmallett{ 114232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 115215976Sjmallett cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000000ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void) 124215976Sjmallett{ 125232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 126215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000100ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void) 135215976Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 137215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000108ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void) 146215976Sjmallett{ 147232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 148215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000150ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void) 157215976Sjmallett{ 158232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 159215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000158ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void) 168215976Sjmallett{ 169232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 170215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000160ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void) 179215976Sjmallett{ 180232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 181215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000110ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallett#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC() 189215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void) 190215976Sjmallett{ 191232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 192215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n"); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000118ull); 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull)) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallett#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC() 200215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void) 201215976Sjmallett{ 202232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n"); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000120ull); 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull)) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallett#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC() 211215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void) 212215976Sjmallett{ 213232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 214215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n"); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000128ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallett#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC() 222215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void) 223215976Sjmallett{ 224232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 225215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n"); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000130ull); 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull)) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallett#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC() 233215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void) 234215976Sjmallett{ 235232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 236215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n"); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000138ull); 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull)) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallett#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC() 244215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void) 245215976Sjmallett{ 246232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 247215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n"); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000140ull); 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull)) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallett#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC() 255215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void) 256215976Sjmallett{ 257232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 258215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n"); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000148ull); 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull)) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallett#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC() 266215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void) 267215976Sjmallett{ 268232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 269215976Sjmallett cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n"); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000088ull); 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull)) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallett#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC() 277215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void) 278215976Sjmallett{ 279232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 280215976Sjmallett cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n"); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000090ull); 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull)) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallett#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC() 288215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void) 289215976Sjmallett{ 290232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 291215976Sjmallett cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n"); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000010ull); 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull)) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallett#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC() 299215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void) 300215976Sjmallett{ 301232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 302215976Sjmallett cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n"); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000018ull); 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull)) 307215976Sjmallett#endif 308215976Sjmallett 309215976Sjmallett/** 310215976Sjmallett * cvmx_rad_mem_debug0 311215976Sjmallett * 312215976Sjmallett * Notes: 313215976Sjmallett * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 314215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 315215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 316215976Sjmallett */ 317232812Sjmallettunion cvmx_rad_mem_debug0 { 318215976Sjmallett uint64_t u64; 319232812Sjmallett struct cvmx_rad_mem_debug0_s { 320232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 321215976Sjmallett uint64_t iword : 64; /**< IWord */ 322215976Sjmallett#else 323215976Sjmallett uint64_t iword : 64; 324215976Sjmallett#endif 325215976Sjmallett } s; 326215976Sjmallett struct cvmx_rad_mem_debug0_s cn52xx; 327215976Sjmallett struct cvmx_rad_mem_debug0_s cn52xxp1; 328215976Sjmallett struct cvmx_rad_mem_debug0_s cn56xx; 329215976Sjmallett struct cvmx_rad_mem_debug0_s cn56xxp1; 330232812Sjmallett struct cvmx_rad_mem_debug0_s cn61xx; 331215976Sjmallett struct cvmx_rad_mem_debug0_s cn63xx; 332215976Sjmallett struct cvmx_rad_mem_debug0_s cn63xxp1; 333232812Sjmallett struct cvmx_rad_mem_debug0_s cn66xx; 334232812Sjmallett struct cvmx_rad_mem_debug0_s cn68xx; 335232812Sjmallett struct cvmx_rad_mem_debug0_s cn68xxp1; 336232812Sjmallett struct cvmx_rad_mem_debug0_s cnf71xx; 337215976Sjmallett}; 338215976Sjmalletttypedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t; 339215976Sjmallett 340215976Sjmallett/** 341215976Sjmallett * cvmx_rad_mem_debug1 342215976Sjmallett * 343215976Sjmallett * Notes: 344215976Sjmallett * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 345215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 346215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 347215976Sjmallett */ 348232812Sjmallettunion cvmx_rad_mem_debug1 { 349215976Sjmallett uint64_t u64; 350232812Sjmallett struct cvmx_rad_mem_debug1_s { 351232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 352215976Sjmallett uint64_t p_dat : 64; /**< P data */ 353215976Sjmallett#else 354215976Sjmallett uint64_t p_dat : 64; 355215976Sjmallett#endif 356215976Sjmallett } s; 357215976Sjmallett struct cvmx_rad_mem_debug1_s cn52xx; 358215976Sjmallett struct cvmx_rad_mem_debug1_s cn52xxp1; 359215976Sjmallett struct cvmx_rad_mem_debug1_s cn56xx; 360215976Sjmallett struct cvmx_rad_mem_debug1_s cn56xxp1; 361232812Sjmallett struct cvmx_rad_mem_debug1_s cn61xx; 362215976Sjmallett struct cvmx_rad_mem_debug1_s cn63xx; 363215976Sjmallett struct cvmx_rad_mem_debug1_s cn63xxp1; 364232812Sjmallett struct cvmx_rad_mem_debug1_s cn66xx; 365232812Sjmallett struct cvmx_rad_mem_debug1_s cn68xx; 366232812Sjmallett struct cvmx_rad_mem_debug1_s cn68xxp1; 367232812Sjmallett struct cvmx_rad_mem_debug1_s cnf71xx; 368215976Sjmallett}; 369215976Sjmalletttypedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t; 370215976Sjmallett 371215976Sjmallett/** 372215976Sjmallett * cvmx_rad_mem_debug2 373215976Sjmallett * 374215976Sjmallett * Notes: 375215976Sjmallett * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 376215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 377215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 378215976Sjmallett */ 379232812Sjmallettunion cvmx_rad_mem_debug2 { 380215976Sjmallett uint64_t u64; 381232812Sjmallett struct cvmx_rad_mem_debug2_s { 382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 383215976Sjmallett uint64_t q_dat : 64; /**< Q data */ 384215976Sjmallett#else 385215976Sjmallett uint64_t q_dat : 64; 386215976Sjmallett#endif 387215976Sjmallett } s; 388215976Sjmallett struct cvmx_rad_mem_debug2_s cn52xx; 389215976Sjmallett struct cvmx_rad_mem_debug2_s cn52xxp1; 390215976Sjmallett struct cvmx_rad_mem_debug2_s cn56xx; 391215976Sjmallett struct cvmx_rad_mem_debug2_s cn56xxp1; 392232812Sjmallett struct cvmx_rad_mem_debug2_s cn61xx; 393215976Sjmallett struct cvmx_rad_mem_debug2_s cn63xx; 394215976Sjmallett struct cvmx_rad_mem_debug2_s cn63xxp1; 395232812Sjmallett struct cvmx_rad_mem_debug2_s cn66xx; 396232812Sjmallett struct cvmx_rad_mem_debug2_s cn68xx; 397232812Sjmallett struct cvmx_rad_mem_debug2_s cn68xxp1; 398232812Sjmallett struct cvmx_rad_mem_debug2_s cnf71xx; 399215976Sjmallett}; 400215976Sjmalletttypedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t; 401215976Sjmallett 402215976Sjmallett/** 403215976Sjmallett * cvmx_rad_reg_bist_result 404215976Sjmallett * 405215976Sjmallett * Notes: 406215976Sjmallett * Access to the internal BiST results 407215976Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 408215976Sjmallett */ 409232812Sjmallettunion cvmx_rad_reg_bist_result { 410215976Sjmallett uint64_t u64; 411232812Sjmallett struct cvmx_rad_reg_bist_result_s { 412232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 413215976Sjmallett uint64_t reserved_6_63 : 58; 414215976Sjmallett uint64_t sta : 1; /**< BiST result of the STA memories */ 415215976Sjmallett uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */ 416215976Sjmallett uint64_t ncb_inb : 2; /**< BiST result of the NCB_INB memories */ 417215976Sjmallett uint64_t dat : 2; /**< BiST result of the DAT memories */ 418215976Sjmallett#else 419215976Sjmallett uint64_t dat : 2; 420215976Sjmallett uint64_t ncb_inb : 2; 421215976Sjmallett uint64_t ncb_oub : 1; 422215976Sjmallett uint64_t sta : 1; 423215976Sjmallett uint64_t reserved_6_63 : 58; 424215976Sjmallett#endif 425215976Sjmallett } s; 426215976Sjmallett struct cvmx_rad_reg_bist_result_s cn52xx; 427215976Sjmallett struct cvmx_rad_reg_bist_result_s cn52xxp1; 428215976Sjmallett struct cvmx_rad_reg_bist_result_s cn56xx; 429215976Sjmallett struct cvmx_rad_reg_bist_result_s cn56xxp1; 430232812Sjmallett struct cvmx_rad_reg_bist_result_s cn61xx; 431215976Sjmallett struct cvmx_rad_reg_bist_result_s cn63xx; 432215976Sjmallett struct cvmx_rad_reg_bist_result_s cn63xxp1; 433232812Sjmallett struct cvmx_rad_reg_bist_result_s cn66xx; 434232812Sjmallett struct cvmx_rad_reg_bist_result_s cn68xx; 435232812Sjmallett struct cvmx_rad_reg_bist_result_s cn68xxp1; 436232812Sjmallett struct cvmx_rad_reg_bist_result_s cnf71xx; 437215976Sjmallett}; 438215976Sjmalletttypedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t; 439215976Sjmallett 440215976Sjmallett/** 441215976Sjmallett * cvmx_rad_reg_cmd_buf 442215976Sjmallett * 443215976Sjmallett * Notes: 444215976Sjmallett * Sets the command buffer parameters 445215976Sjmallett * The size of the command buffer segments is measured in uint64s. The pool specifies 1 of 8 free 446215976Sjmallett * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 447215976Sjmallett * pointer each time that the command buffer segment is exhausted. 448215976Sjmallett */ 449232812Sjmallettunion cvmx_rad_reg_cmd_buf { 450215976Sjmallett uint64_t u64; 451232812Sjmallett struct cvmx_rad_reg_cmd_buf_s { 452232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 453215976Sjmallett uint64_t reserved_58_63 : 6; 454215976Sjmallett uint64_t dwb : 9; /**< Number of DontWriteBacks */ 455215976Sjmallett uint64_t pool : 3; /**< Free list used to free command buffer segments */ 456215976Sjmallett uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 457215976Sjmallett uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 458215976Sjmallett#else 459215976Sjmallett uint64_t ptr : 33; 460215976Sjmallett uint64_t size : 13; 461215976Sjmallett uint64_t pool : 3; 462215976Sjmallett uint64_t dwb : 9; 463215976Sjmallett uint64_t reserved_58_63 : 6; 464215976Sjmallett#endif 465215976Sjmallett } s; 466215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn52xx; 467215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn52xxp1; 468215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn56xx; 469215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn56xxp1; 470232812Sjmallett struct cvmx_rad_reg_cmd_buf_s cn61xx; 471215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn63xx; 472215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn63xxp1; 473232812Sjmallett struct cvmx_rad_reg_cmd_buf_s cn66xx; 474232812Sjmallett struct cvmx_rad_reg_cmd_buf_s cn68xx; 475232812Sjmallett struct cvmx_rad_reg_cmd_buf_s cn68xxp1; 476232812Sjmallett struct cvmx_rad_reg_cmd_buf_s cnf71xx; 477215976Sjmallett}; 478215976Sjmalletttypedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t; 479215976Sjmallett 480215976Sjmallett/** 481215976Sjmallett * cvmx_rad_reg_ctl 482215976Sjmallett * 483215976Sjmallett * Notes: 484215976Sjmallett * MAX_READ is a throttle to control NCB usage. Values >8 are illegal. 485215976Sjmallett * 486215976Sjmallett */ 487232812Sjmallettunion cvmx_rad_reg_ctl { 488215976Sjmallett uint64_t u64; 489232812Sjmallett struct cvmx_rad_reg_ctl_s { 490232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 491215976Sjmallett uint64_t reserved_6_63 : 58; 492215976Sjmallett uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */ 493215976Sjmallett uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */ 494215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse (lasts for 4 cycles) */ 495215976Sjmallett#else 496215976Sjmallett uint64_t reset : 1; 497215976Sjmallett uint64_t store_le : 1; 498215976Sjmallett uint64_t max_read : 4; 499215976Sjmallett uint64_t reserved_6_63 : 58; 500215976Sjmallett#endif 501215976Sjmallett } s; 502215976Sjmallett struct cvmx_rad_reg_ctl_s cn52xx; 503215976Sjmallett struct cvmx_rad_reg_ctl_s cn52xxp1; 504215976Sjmallett struct cvmx_rad_reg_ctl_s cn56xx; 505215976Sjmallett struct cvmx_rad_reg_ctl_s cn56xxp1; 506232812Sjmallett struct cvmx_rad_reg_ctl_s cn61xx; 507215976Sjmallett struct cvmx_rad_reg_ctl_s cn63xx; 508215976Sjmallett struct cvmx_rad_reg_ctl_s cn63xxp1; 509232812Sjmallett struct cvmx_rad_reg_ctl_s cn66xx; 510232812Sjmallett struct cvmx_rad_reg_ctl_s cn68xx; 511232812Sjmallett struct cvmx_rad_reg_ctl_s cn68xxp1; 512232812Sjmallett struct cvmx_rad_reg_ctl_s cnf71xx; 513215976Sjmallett}; 514215976Sjmalletttypedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t; 515215976Sjmallett 516215976Sjmallett/** 517215976Sjmallett * cvmx_rad_reg_debug0 518215976Sjmallett */ 519232812Sjmallettunion cvmx_rad_reg_debug0 { 520215976Sjmallett uint64_t u64; 521232812Sjmallett struct cvmx_rad_reg_debug0_s { 522232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 523215976Sjmallett uint64_t reserved_57_63 : 7; 524215976Sjmallett uint64_t loop : 25; /**< Loop offset */ 525215976Sjmallett uint64_t reserved_22_31 : 10; 526215976Sjmallett uint64_t iridx : 6; /**< IWords read index */ 527215976Sjmallett uint64_t reserved_14_15 : 2; 528215976Sjmallett uint64_t iwidx : 6; /**< IWords write index */ 529215976Sjmallett uint64_t owordqv : 1; /**< Valid for OWORDQ */ 530215976Sjmallett uint64_t owordpv : 1; /**< Valid for OWORDP */ 531215976Sjmallett uint64_t commit : 1; /**< Waiting for write commit */ 532215976Sjmallett uint64_t state : 5; /**< Main state */ 533215976Sjmallett#else 534215976Sjmallett uint64_t state : 5; 535215976Sjmallett uint64_t commit : 1; 536215976Sjmallett uint64_t owordpv : 1; 537215976Sjmallett uint64_t owordqv : 1; 538215976Sjmallett uint64_t iwidx : 6; 539215976Sjmallett uint64_t reserved_14_15 : 2; 540215976Sjmallett uint64_t iridx : 6; 541215976Sjmallett uint64_t reserved_22_31 : 10; 542215976Sjmallett uint64_t loop : 25; 543215976Sjmallett uint64_t reserved_57_63 : 7; 544215976Sjmallett#endif 545215976Sjmallett } s; 546215976Sjmallett struct cvmx_rad_reg_debug0_s cn52xx; 547215976Sjmallett struct cvmx_rad_reg_debug0_s cn52xxp1; 548215976Sjmallett struct cvmx_rad_reg_debug0_s cn56xx; 549215976Sjmallett struct cvmx_rad_reg_debug0_s cn56xxp1; 550232812Sjmallett struct cvmx_rad_reg_debug0_s cn61xx; 551215976Sjmallett struct cvmx_rad_reg_debug0_s cn63xx; 552215976Sjmallett struct cvmx_rad_reg_debug0_s cn63xxp1; 553232812Sjmallett struct cvmx_rad_reg_debug0_s cn66xx; 554232812Sjmallett struct cvmx_rad_reg_debug0_s cn68xx; 555232812Sjmallett struct cvmx_rad_reg_debug0_s cn68xxp1; 556232812Sjmallett struct cvmx_rad_reg_debug0_s cnf71xx; 557215976Sjmallett}; 558215976Sjmalletttypedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t; 559215976Sjmallett 560215976Sjmallett/** 561215976Sjmallett * cvmx_rad_reg_debug1 562215976Sjmallett */ 563232812Sjmallettunion cvmx_rad_reg_debug1 { 564215976Sjmallett uint64_t u64; 565232812Sjmallett struct cvmx_rad_reg_debug1_s { 566232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 567215976Sjmallett uint64_t cword : 64; /**< CWord */ 568215976Sjmallett#else 569215976Sjmallett uint64_t cword : 64; 570215976Sjmallett#endif 571215976Sjmallett } s; 572215976Sjmallett struct cvmx_rad_reg_debug1_s cn52xx; 573215976Sjmallett struct cvmx_rad_reg_debug1_s cn52xxp1; 574215976Sjmallett struct cvmx_rad_reg_debug1_s cn56xx; 575215976Sjmallett struct cvmx_rad_reg_debug1_s cn56xxp1; 576232812Sjmallett struct cvmx_rad_reg_debug1_s cn61xx; 577215976Sjmallett struct cvmx_rad_reg_debug1_s cn63xx; 578215976Sjmallett struct cvmx_rad_reg_debug1_s cn63xxp1; 579232812Sjmallett struct cvmx_rad_reg_debug1_s cn66xx; 580232812Sjmallett struct cvmx_rad_reg_debug1_s cn68xx; 581232812Sjmallett struct cvmx_rad_reg_debug1_s cn68xxp1; 582232812Sjmallett struct cvmx_rad_reg_debug1_s cnf71xx; 583215976Sjmallett}; 584215976Sjmalletttypedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t; 585215976Sjmallett 586215976Sjmallett/** 587215976Sjmallett * cvmx_rad_reg_debug10 588215976Sjmallett */ 589232812Sjmallettunion cvmx_rad_reg_debug10 { 590215976Sjmallett uint64_t u64; 591232812Sjmallett struct cvmx_rad_reg_debug10_s { 592232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 593215976Sjmallett uint64_t flags : 8; /**< OCTL flags */ 594215976Sjmallett uint64_t size : 16; /**< OCTL size (bytes) */ 595215976Sjmallett uint64_t ptr : 40; /**< OCTL pointer */ 596215976Sjmallett#else 597215976Sjmallett uint64_t ptr : 40; 598215976Sjmallett uint64_t size : 16; 599215976Sjmallett uint64_t flags : 8; 600215976Sjmallett#endif 601215976Sjmallett } s; 602215976Sjmallett struct cvmx_rad_reg_debug10_s cn52xx; 603215976Sjmallett struct cvmx_rad_reg_debug10_s cn52xxp1; 604215976Sjmallett struct cvmx_rad_reg_debug10_s cn56xx; 605215976Sjmallett struct cvmx_rad_reg_debug10_s cn56xxp1; 606232812Sjmallett struct cvmx_rad_reg_debug10_s cn61xx; 607215976Sjmallett struct cvmx_rad_reg_debug10_s cn63xx; 608215976Sjmallett struct cvmx_rad_reg_debug10_s cn63xxp1; 609232812Sjmallett struct cvmx_rad_reg_debug10_s cn66xx; 610232812Sjmallett struct cvmx_rad_reg_debug10_s cn68xx; 611232812Sjmallett struct cvmx_rad_reg_debug10_s cn68xxp1; 612232812Sjmallett struct cvmx_rad_reg_debug10_s cnf71xx; 613215976Sjmallett}; 614215976Sjmalletttypedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t; 615215976Sjmallett 616215976Sjmallett/** 617215976Sjmallett * cvmx_rad_reg_debug11 618215976Sjmallett */ 619232812Sjmallettunion cvmx_rad_reg_debug11 { 620215976Sjmallett uint64_t u64; 621232812Sjmallett struct cvmx_rad_reg_debug11_s { 622232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 623215976Sjmallett uint64_t reserved_13_63 : 51; 624215976Sjmallett uint64_t q : 1; /**< OCTL q flag */ 625215976Sjmallett uint64_t p : 1; /**< OCTL p flag */ 626215976Sjmallett uint64_t wc : 1; /**< OCTL write commit flag */ 627215976Sjmallett uint64_t eod : 1; /**< OCTL eod flag */ 628215976Sjmallett uint64_t sod : 1; /**< OCTL sod flag */ 629215976Sjmallett uint64_t index : 8; /**< OCTL index */ 630215976Sjmallett#else 631215976Sjmallett uint64_t index : 8; 632215976Sjmallett uint64_t sod : 1; 633215976Sjmallett uint64_t eod : 1; 634215976Sjmallett uint64_t wc : 1; 635215976Sjmallett uint64_t p : 1; 636215976Sjmallett uint64_t q : 1; 637215976Sjmallett uint64_t reserved_13_63 : 51; 638215976Sjmallett#endif 639215976Sjmallett } s; 640215976Sjmallett struct cvmx_rad_reg_debug11_s cn52xx; 641215976Sjmallett struct cvmx_rad_reg_debug11_s cn52xxp1; 642215976Sjmallett struct cvmx_rad_reg_debug11_s cn56xx; 643215976Sjmallett struct cvmx_rad_reg_debug11_s cn56xxp1; 644232812Sjmallett struct cvmx_rad_reg_debug11_s cn61xx; 645215976Sjmallett struct cvmx_rad_reg_debug11_s cn63xx; 646215976Sjmallett struct cvmx_rad_reg_debug11_s cn63xxp1; 647232812Sjmallett struct cvmx_rad_reg_debug11_s cn66xx; 648232812Sjmallett struct cvmx_rad_reg_debug11_s cn68xx; 649232812Sjmallett struct cvmx_rad_reg_debug11_s cn68xxp1; 650232812Sjmallett struct cvmx_rad_reg_debug11_s cnf71xx; 651215976Sjmallett}; 652215976Sjmalletttypedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t; 653215976Sjmallett 654215976Sjmallett/** 655215976Sjmallett * cvmx_rad_reg_debug12 656215976Sjmallett */ 657232812Sjmallettunion cvmx_rad_reg_debug12 { 658215976Sjmallett uint64_t u64; 659232812Sjmallett struct cvmx_rad_reg_debug12_s { 660232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 661215976Sjmallett uint64_t reserved_15_63 : 49; 662215976Sjmallett uint64_t asserts : 15; /**< Various assertion checks */ 663215976Sjmallett#else 664215976Sjmallett uint64_t asserts : 15; 665215976Sjmallett uint64_t reserved_15_63 : 49; 666215976Sjmallett#endif 667215976Sjmallett } s; 668215976Sjmallett struct cvmx_rad_reg_debug12_s cn52xx; 669215976Sjmallett struct cvmx_rad_reg_debug12_s cn52xxp1; 670215976Sjmallett struct cvmx_rad_reg_debug12_s cn56xx; 671215976Sjmallett struct cvmx_rad_reg_debug12_s cn56xxp1; 672232812Sjmallett struct cvmx_rad_reg_debug12_s cn61xx; 673215976Sjmallett struct cvmx_rad_reg_debug12_s cn63xx; 674215976Sjmallett struct cvmx_rad_reg_debug12_s cn63xxp1; 675232812Sjmallett struct cvmx_rad_reg_debug12_s cn66xx; 676232812Sjmallett struct cvmx_rad_reg_debug12_s cn68xx; 677232812Sjmallett struct cvmx_rad_reg_debug12_s cn68xxp1; 678232812Sjmallett struct cvmx_rad_reg_debug12_s cnf71xx; 679215976Sjmallett}; 680215976Sjmalletttypedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t; 681215976Sjmallett 682215976Sjmallett/** 683215976Sjmallett * cvmx_rad_reg_debug2 684215976Sjmallett */ 685232812Sjmallettunion cvmx_rad_reg_debug2 { 686215976Sjmallett uint64_t u64; 687232812Sjmallett struct cvmx_rad_reg_debug2_s { 688232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 689215976Sjmallett uint64_t owordp : 64; /**< OWordP */ 690215976Sjmallett#else 691215976Sjmallett uint64_t owordp : 64; 692215976Sjmallett#endif 693215976Sjmallett } s; 694215976Sjmallett struct cvmx_rad_reg_debug2_s cn52xx; 695215976Sjmallett struct cvmx_rad_reg_debug2_s cn52xxp1; 696215976Sjmallett struct cvmx_rad_reg_debug2_s cn56xx; 697215976Sjmallett struct cvmx_rad_reg_debug2_s cn56xxp1; 698232812Sjmallett struct cvmx_rad_reg_debug2_s cn61xx; 699215976Sjmallett struct cvmx_rad_reg_debug2_s cn63xx; 700215976Sjmallett struct cvmx_rad_reg_debug2_s cn63xxp1; 701232812Sjmallett struct cvmx_rad_reg_debug2_s cn66xx; 702232812Sjmallett struct cvmx_rad_reg_debug2_s cn68xx; 703232812Sjmallett struct cvmx_rad_reg_debug2_s cn68xxp1; 704232812Sjmallett struct cvmx_rad_reg_debug2_s cnf71xx; 705215976Sjmallett}; 706215976Sjmalletttypedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t; 707215976Sjmallett 708215976Sjmallett/** 709215976Sjmallett * cvmx_rad_reg_debug3 710215976Sjmallett */ 711232812Sjmallettunion cvmx_rad_reg_debug3 { 712215976Sjmallett uint64_t u64; 713232812Sjmallett struct cvmx_rad_reg_debug3_s { 714232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 715215976Sjmallett uint64_t owordq : 64; /**< OWordQ */ 716215976Sjmallett#else 717215976Sjmallett uint64_t owordq : 64; 718215976Sjmallett#endif 719215976Sjmallett } s; 720215976Sjmallett struct cvmx_rad_reg_debug3_s cn52xx; 721215976Sjmallett struct cvmx_rad_reg_debug3_s cn52xxp1; 722215976Sjmallett struct cvmx_rad_reg_debug3_s cn56xx; 723215976Sjmallett struct cvmx_rad_reg_debug3_s cn56xxp1; 724232812Sjmallett struct cvmx_rad_reg_debug3_s cn61xx; 725215976Sjmallett struct cvmx_rad_reg_debug3_s cn63xx; 726215976Sjmallett struct cvmx_rad_reg_debug3_s cn63xxp1; 727232812Sjmallett struct cvmx_rad_reg_debug3_s cn66xx; 728232812Sjmallett struct cvmx_rad_reg_debug3_s cn68xx; 729232812Sjmallett struct cvmx_rad_reg_debug3_s cn68xxp1; 730232812Sjmallett struct cvmx_rad_reg_debug3_s cnf71xx; 731215976Sjmallett}; 732215976Sjmalletttypedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t; 733215976Sjmallett 734215976Sjmallett/** 735215976Sjmallett * cvmx_rad_reg_debug4 736215976Sjmallett */ 737232812Sjmallettunion cvmx_rad_reg_debug4 { 738215976Sjmallett uint64_t u64; 739232812Sjmallett struct cvmx_rad_reg_debug4_s { 740232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 741215976Sjmallett uint64_t rword : 64; /**< RWord */ 742215976Sjmallett#else 743215976Sjmallett uint64_t rword : 64; 744215976Sjmallett#endif 745215976Sjmallett } s; 746215976Sjmallett struct cvmx_rad_reg_debug4_s cn52xx; 747215976Sjmallett struct cvmx_rad_reg_debug4_s cn52xxp1; 748215976Sjmallett struct cvmx_rad_reg_debug4_s cn56xx; 749215976Sjmallett struct cvmx_rad_reg_debug4_s cn56xxp1; 750232812Sjmallett struct cvmx_rad_reg_debug4_s cn61xx; 751215976Sjmallett struct cvmx_rad_reg_debug4_s cn63xx; 752215976Sjmallett struct cvmx_rad_reg_debug4_s cn63xxp1; 753232812Sjmallett struct cvmx_rad_reg_debug4_s cn66xx; 754232812Sjmallett struct cvmx_rad_reg_debug4_s cn68xx; 755232812Sjmallett struct cvmx_rad_reg_debug4_s cn68xxp1; 756232812Sjmallett struct cvmx_rad_reg_debug4_s cnf71xx; 757215976Sjmallett}; 758215976Sjmalletttypedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t; 759215976Sjmallett 760215976Sjmallett/** 761215976Sjmallett * cvmx_rad_reg_debug5 762215976Sjmallett */ 763232812Sjmallettunion cvmx_rad_reg_debug5 { 764215976Sjmallett uint64_t u64; 765232812Sjmallett struct cvmx_rad_reg_debug5_s { 766232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 767215976Sjmallett uint64_t reserved_53_63 : 11; 768215976Sjmallett uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */ 769215976Sjmallett uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */ 770215976Sjmallett uint64_t nirval7 : 5; /**< NCBI rval (stage7 grant) */ 771215976Sjmallett uint64_t niropc6 : 3; /**< NCBI ropc (stage6 arb) */ 772215976Sjmallett uint64_t nirque6 : 2; /**< NCBI rque (stage6 arb) */ 773215976Sjmallett uint64_t nirarb6 : 1; /**< NCBI rarb (stage6 arb) */ 774215976Sjmallett uint64_t nirval6 : 5; /**< NCBI rval (stage6 arb) */ 775215976Sjmallett uint64_t niridx1 : 4; /**< NCBI ridx1 */ 776215976Sjmallett uint64_t niwidx1 : 4; /**< NCBI widx1 */ 777215976Sjmallett uint64_t niridx0 : 4; /**< NCBI ridx0 */ 778215976Sjmallett uint64_t niwidx0 : 4; /**< NCBI widx0 */ 779215976Sjmallett uint64_t wccreds : 2; /**< WC credits */ 780215976Sjmallett uint64_t fpacreds : 2; /**< POW credits */ 781215976Sjmallett uint64_t reserved_10_11 : 2; 782215976Sjmallett uint64_t powcreds : 2; /**< POW credits */ 783215976Sjmallett uint64_t n1creds : 4; /**< NCBI1 credits */ 784215976Sjmallett uint64_t n0creds : 4; /**< NCBI0 credits */ 785215976Sjmallett#else 786215976Sjmallett uint64_t n0creds : 4; 787215976Sjmallett uint64_t n1creds : 4; 788215976Sjmallett uint64_t powcreds : 2; 789215976Sjmallett uint64_t reserved_10_11 : 2; 790215976Sjmallett uint64_t fpacreds : 2; 791215976Sjmallett uint64_t wccreds : 2; 792215976Sjmallett uint64_t niwidx0 : 4; 793215976Sjmallett uint64_t niridx0 : 4; 794215976Sjmallett uint64_t niwidx1 : 4; 795215976Sjmallett uint64_t niridx1 : 4; 796215976Sjmallett uint64_t nirval6 : 5; 797215976Sjmallett uint64_t nirarb6 : 1; 798215976Sjmallett uint64_t nirque6 : 2; 799215976Sjmallett uint64_t niropc6 : 3; 800215976Sjmallett uint64_t nirval7 : 5; 801215976Sjmallett uint64_t nirque7 : 2; 802215976Sjmallett uint64_t niropc7 : 3; 803215976Sjmallett uint64_t reserved_53_63 : 11; 804215976Sjmallett#endif 805215976Sjmallett } s; 806215976Sjmallett struct cvmx_rad_reg_debug5_s cn52xx; 807215976Sjmallett struct cvmx_rad_reg_debug5_s cn52xxp1; 808215976Sjmallett struct cvmx_rad_reg_debug5_s cn56xx; 809215976Sjmallett struct cvmx_rad_reg_debug5_s cn56xxp1; 810232812Sjmallett struct cvmx_rad_reg_debug5_s cn61xx; 811215976Sjmallett struct cvmx_rad_reg_debug5_s cn63xx; 812215976Sjmallett struct cvmx_rad_reg_debug5_s cn63xxp1; 813232812Sjmallett struct cvmx_rad_reg_debug5_s cn66xx; 814232812Sjmallett struct cvmx_rad_reg_debug5_s cn68xx; 815232812Sjmallett struct cvmx_rad_reg_debug5_s cn68xxp1; 816232812Sjmallett struct cvmx_rad_reg_debug5_s cnf71xx; 817215976Sjmallett}; 818215976Sjmalletttypedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t; 819215976Sjmallett 820215976Sjmallett/** 821215976Sjmallett * cvmx_rad_reg_debug6 822215976Sjmallett */ 823232812Sjmallettunion cvmx_rad_reg_debug6 { 824215976Sjmallett uint64_t u64; 825232812Sjmallett struct cvmx_rad_reg_debug6_s { 826232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 827215976Sjmallett uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */ 828215976Sjmallett uint64_t size : 16; /**< CCTL size (bytes) */ 829215976Sjmallett uint64_t ptr : 40; /**< CCTL pointer */ 830215976Sjmallett#else 831215976Sjmallett uint64_t ptr : 40; 832215976Sjmallett uint64_t size : 16; 833215976Sjmallett uint64_t cnt : 8; 834215976Sjmallett#endif 835215976Sjmallett } s; 836215976Sjmallett struct cvmx_rad_reg_debug6_s cn52xx; 837215976Sjmallett struct cvmx_rad_reg_debug6_s cn52xxp1; 838215976Sjmallett struct cvmx_rad_reg_debug6_s cn56xx; 839215976Sjmallett struct cvmx_rad_reg_debug6_s cn56xxp1; 840232812Sjmallett struct cvmx_rad_reg_debug6_s cn61xx; 841215976Sjmallett struct cvmx_rad_reg_debug6_s cn63xx; 842215976Sjmallett struct cvmx_rad_reg_debug6_s cn63xxp1; 843232812Sjmallett struct cvmx_rad_reg_debug6_s cn66xx; 844232812Sjmallett struct cvmx_rad_reg_debug6_s cn68xx; 845232812Sjmallett struct cvmx_rad_reg_debug6_s cn68xxp1; 846232812Sjmallett struct cvmx_rad_reg_debug6_s cnf71xx; 847215976Sjmallett}; 848215976Sjmalletttypedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t; 849215976Sjmallett 850215976Sjmallett/** 851215976Sjmallett * cvmx_rad_reg_debug7 852215976Sjmallett */ 853232812Sjmallettunion cvmx_rad_reg_debug7 { 854215976Sjmallett uint64_t u64; 855232812Sjmallett struct cvmx_rad_reg_debug7_s { 856232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 857215976Sjmallett uint64_t reserved_15_63 : 49; 858215976Sjmallett uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */ 859215976Sjmallett#else 860215976Sjmallett uint64_t cnt : 15; 861215976Sjmallett uint64_t reserved_15_63 : 49; 862215976Sjmallett#endif 863215976Sjmallett } s; 864215976Sjmallett struct cvmx_rad_reg_debug7_s cn52xx; 865215976Sjmallett struct cvmx_rad_reg_debug7_s cn52xxp1; 866215976Sjmallett struct cvmx_rad_reg_debug7_s cn56xx; 867215976Sjmallett struct cvmx_rad_reg_debug7_s cn56xxp1; 868232812Sjmallett struct cvmx_rad_reg_debug7_s cn61xx; 869215976Sjmallett struct cvmx_rad_reg_debug7_s cn63xx; 870215976Sjmallett struct cvmx_rad_reg_debug7_s cn63xxp1; 871232812Sjmallett struct cvmx_rad_reg_debug7_s cn66xx; 872232812Sjmallett struct cvmx_rad_reg_debug7_s cn68xx; 873232812Sjmallett struct cvmx_rad_reg_debug7_s cn68xxp1; 874232812Sjmallett struct cvmx_rad_reg_debug7_s cnf71xx; 875215976Sjmallett}; 876215976Sjmalletttypedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t; 877215976Sjmallett 878215976Sjmallett/** 879215976Sjmallett * cvmx_rad_reg_debug8 880215976Sjmallett */ 881232812Sjmallettunion cvmx_rad_reg_debug8 { 882215976Sjmallett uint64_t u64; 883232812Sjmallett struct cvmx_rad_reg_debug8_s { 884232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 885215976Sjmallett uint64_t flags : 8; /**< ICTL flags */ 886215976Sjmallett uint64_t size : 16; /**< ICTL size (bytes) */ 887215976Sjmallett uint64_t ptr : 40; /**< ICTL pointer */ 888215976Sjmallett#else 889215976Sjmallett uint64_t ptr : 40; 890215976Sjmallett uint64_t size : 16; 891215976Sjmallett uint64_t flags : 8; 892215976Sjmallett#endif 893215976Sjmallett } s; 894215976Sjmallett struct cvmx_rad_reg_debug8_s cn52xx; 895215976Sjmallett struct cvmx_rad_reg_debug8_s cn52xxp1; 896215976Sjmallett struct cvmx_rad_reg_debug8_s cn56xx; 897215976Sjmallett struct cvmx_rad_reg_debug8_s cn56xxp1; 898232812Sjmallett struct cvmx_rad_reg_debug8_s cn61xx; 899215976Sjmallett struct cvmx_rad_reg_debug8_s cn63xx; 900215976Sjmallett struct cvmx_rad_reg_debug8_s cn63xxp1; 901232812Sjmallett struct cvmx_rad_reg_debug8_s cn66xx; 902232812Sjmallett struct cvmx_rad_reg_debug8_s cn68xx; 903232812Sjmallett struct cvmx_rad_reg_debug8_s cn68xxp1; 904232812Sjmallett struct cvmx_rad_reg_debug8_s cnf71xx; 905215976Sjmallett}; 906215976Sjmalletttypedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t; 907215976Sjmallett 908215976Sjmallett/** 909215976Sjmallett * cvmx_rad_reg_debug9 910215976Sjmallett */ 911232812Sjmallettunion cvmx_rad_reg_debug9 { 912215976Sjmallett uint64_t u64; 913232812Sjmallett struct cvmx_rad_reg_debug9_s { 914232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 915215976Sjmallett uint64_t reserved_20_63 : 44; 916215976Sjmallett uint64_t eod : 1; /**< ICTL eod flag */ 917215976Sjmallett uint64_t ini : 1; /**< ICTL init flag */ 918215976Sjmallett uint64_t q : 1; /**< ICTL q enable */ 919215976Sjmallett uint64_t p : 1; /**< ICTL p enable */ 920215976Sjmallett uint64_t mul : 8; /**< ICTL multiplier */ 921215976Sjmallett uint64_t index : 8; /**< ICTL index */ 922215976Sjmallett#else 923215976Sjmallett uint64_t index : 8; 924215976Sjmallett uint64_t mul : 8; 925215976Sjmallett uint64_t p : 1; 926215976Sjmallett uint64_t q : 1; 927215976Sjmallett uint64_t ini : 1; 928215976Sjmallett uint64_t eod : 1; 929215976Sjmallett uint64_t reserved_20_63 : 44; 930215976Sjmallett#endif 931215976Sjmallett } s; 932215976Sjmallett struct cvmx_rad_reg_debug9_s cn52xx; 933215976Sjmallett struct cvmx_rad_reg_debug9_s cn52xxp1; 934215976Sjmallett struct cvmx_rad_reg_debug9_s cn56xx; 935215976Sjmallett struct cvmx_rad_reg_debug9_s cn56xxp1; 936232812Sjmallett struct cvmx_rad_reg_debug9_s cn61xx; 937215976Sjmallett struct cvmx_rad_reg_debug9_s cn63xx; 938215976Sjmallett struct cvmx_rad_reg_debug9_s cn63xxp1; 939232812Sjmallett struct cvmx_rad_reg_debug9_s cn66xx; 940232812Sjmallett struct cvmx_rad_reg_debug9_s cn68xx; 941232812Sjmallett struct cvmx_rad_reg_debug9_s cn68xxp1; 942232812Sjmallett struct cvmx_rad_reg_debug9_s cnf71xx; 943215976Sjmallett}; 944215976Sjmalletttypedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t; 945215976Sjmallett 946215976Sjmallett/** 947215976Sjmallett * cvmx_rad_reg_error 948215976Sjmallett */ 949232812Sjmallettunion cvmx_rad_reg_error { 950215976Sjmallett uint64_t u64; 951232812Sjmallett struct cvmx_rad_reg_error_s { 952232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 953215976Sjmallett uint64_t reserved_1_63 : 63; 954215976Sjmallett uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 955215976Sjmallett#else 956215976Sjmallett uint64_t doorbell : 1; 957215976Sjmallett uint64_t reserved_1_63 : 63; 958215976Sjmallett#endif 959215976Sjmallett } s; 960215976Sjmallett struct cvmx_rad_reg_error_s cn52xx; 961215976Sjmallett struct cvmx_rad_reg_error_s cn52xxp1; 962215976Sjmallett struct cvmx_rad_reg_error_s cn56xx; 963215976Sjmallett struct cvmx_rad_reg_error_s cn56xxp1; 964232812Sjmallett struct cvmx_rad_reg_error_s cn61xx; 965215976Sjmallett struct cvmx_rad_reg_error_s cn63xx; 966215976Sjmallett struct cvmx_rad_reg_error_s cn63xxp1; 967232812Sjmallett struct cvmx_rad_reg_error_s cn66xx; 968232812Sjmallett struct cvmx_rad_reg_error_s cn68xx; 969232812Sjmallett struct cvmx_rad_reg_error_s cn68xxp1; 970232812Sjmallett struct cvmx_rad_reg_error_s cnf71xx; 971215976Sjmallett}; 972215976Sjmalletttypedef union cvmx_rad_reg_error cvmx_rad_reg_error_t; 973215976Sjmallett 974215976Sjmallett/** 975215976Sjmallett * cvmx_rad_reg_int_mask 976215976Sjmallett * 977215976Sjmallett * Notes: 978215976Sjmallett * When a mask bit is set, the corresponding interrupt is enabled. 979215976Sjmallett * 980215976Sjmallett */ 981232812Sjmallettunion cvmx_rad_reg_int_mask { 982215976Sjmallett uint64_t u64; 983232812Sjmallett struct cvmx_rad_reg_int_mask_s { 984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 985215976Sjmallett uint64_t reserved_1_63 : 63; 986215976Sjmallett uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */ 987215976Sjmallett#else 988215976Sjmallett uint64_t doorbell : 1; 989215976Sjmallett uint64_t reserved_1_63 : 63; 990215976Sjmallett#endif 991215976Sjmallett } s; 992215976Sjmallett struct cvmx_rad_reg_int_mask_s cn52xx; 993215976Sjmallett struct cvmx_rad_reg_int_mask_s cn52xxp1; 994215976Sjmallett struct cvmx_rad_reg_int_mask_s cn56xx; 995215976Sjmallett struct cvmx_rad_reg_int_mask_s cn56xxp1; 996232812Sjmallett struct cvmx_rad_reg_int_mask_s cn61xx; 997215976Sjmallett struct cvmx_rad_reg_int_mask_s cn63xx; 998215976Sjmallett struct cvmx_rad_reg_int_mask_s cn63xxp1; 999232812Sjmallett struct cvmx_rad_reg_int_mask_s cn66xx; 1000232812Sjmallett struct cvmx_rad_reg_int_mask_s cn68xx; 1001232812Sjmallett struct cvmx_rad_reg_int_mask_s cn68xxp1; 1002232812Sjmallett struct cvmx_rad_reg_int_mask_s cnf71xx; 1003215976Sjmallett}; 1004215976Sjmalletttypedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t; 1005215976Sjmallett 1006215976Sjmallett/** 1007215976Sjmallett * cvmx_rad_reg_polynomial 1008215976Sjmallett * 1009215976Sjmallett * Notes: 1010215976Sjmallett * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0. 1011215976Sjmallett * 1012215976Sjmallett */ 1013232812Sjmallettunion cvmx_rad_reg_polynomial { 1014215976Sjmallett uint64_t u64; 1015232812Sjmallett struct cvmx_rad_reg_polynomial_s { 1016232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1017215976Sjmallett uint64_t reserved_8_63 : 56; 1018215976Sjmallett uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */ 1019215976Sjmallett#else 1020215976Sjmallett uint64_t coeffs : 8; 1021215976Sjmallett uint64_t reserved_8_63 : 56; 1022215976Sjmallett#endif 1023215976Sjmallett } s; 1024215976Sjmallett struct cvmx_rad_reg_polynomial_s cn52xx; 1025215976Sjmallett struct cvmx_rad_reg_polynomial_s cn52xxp1; 1026215976Sjmallett struct cvmx_rad_reg_polynomial_s cn56xx; 1027215976Sjmallett struct cvmx_rad_reg_polynomial_s cn56xxp1; 1028232812Sjmallett struct cvmx_rad_reg_polynomial_s cn61xx; 1029215976Sjmallett struct cvmx_rad_reg_polynomial_s cn63xx; 1030215976Sjmallett struct cvmx_rad_reg_polynomial_s cn63xxp1; 1031232812Sjmallett struct cvmx_rad_reg_polynomial_s cn66xx; 1032232812Sjmallett struct cvmx_rad_reg_polynomial_s cn68xx; 1033232812Sjmallett struct cvmx_rad_reg_polynomial_s cn68xxp1; 1034232812Sjmallett struct cvmx_rad_reg_polynomial_s cnf71xx; 1035215976Sjmallett}; 1036215976Sjmalletttypedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t; 1037215976Sjmallett 1038215976Sjmallett/** 1039215976Sjmallett * cvmx_rad_reg_read_idx 1040215976Sjmallett * 1041215976Sjmallett * Notes: 1042215976Sjmallett * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 1043215976Sjmallett * as memories. The names of these CSRs begin with the prefix "RAD_MEM_". 1044215976Sjmallett * IDX[15:0] is the read index. INC[15:0] is an increment that is added to IDX[15:0] after any CSR read. 1045215976Sjmallett * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 1046215976Sjmallett * contents of a CSR memory can be read with consecutive CSR read commands. 1047215976Sjmallett */ 1048232812Sjmallettunion cvmx_rad_reg_read_idx { 1049215976Sjmallett uint64_t u64; 1050232812Sjmallett struct cvmx_rad_reg_read_idx_s { 1051232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1052215976Sjmallett uint64_t reserved_32_63 : 32; 1053215976Sjmallett uint64_t inc : 16; /**< Increment to add to current index for next index */ 1054215976Sjmallett uint64_t index : 16; /**< Index to use for next memory CSR read */ 1055215976Sjmallett#else 1056215976Sjmallett uint64_t index : 16; 1057215976Sjmallett uint64_t inc : 16; 1058215976Sjmallett uint64_t reserved_32_63 : 32; 1059215976Sjmallett#endif 1060215976Sjmallett } s; 1061215976Sjmallett struct cvmx_rad_reg_read_idx_s cn52xx; 1062215976Sjmallett struct cvmx_rad_reg_read_idx_s cn52xxp1; 1063215976Sjmallett struct cvmx_rad_reg_read_idx_s cn56xx; 1064215976Sjmallett struct cvmx_rad_reg_read_idx_s cn56xxp1; 1065232812Sjmallett struct cvmx_rad_reg_read_idx_s cn61xx; 1066215976Sjmallett struct cvmx_rad_reg_read_idx_s cn63xx; 1067215976Sjmallett struct cvmx_rad_reg_read_idx_s cn63xxp1; 1068232812Sjmallett struct cvmx_rad_reg_read_idx_s cn66xx; 1069232812Sjmallett struct cvmx_rad_reg_read_idx_s cn68xx; 1070232812Sjmallett struct cvmx_rad_reg_read_idx_s cn68xxp1; 1071232812Sjmallett struct cvmx_rad_reg_read_idx_s cnf71xx; 1072215976Sjmallett}; 1073215976Sjmalletttypedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t; 1074215976Sjmallett 1075215976Sjmallett#endif 1076