1232809Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 2232809Sjmallett#include <asm/octeon/cvmx.h> 3232809Sjmallett#include <asm/octeon/cvmx-qlm.h> 4232809Sjmallett#else 5232812Sjmallett#if !defined(__FreeBSD__) || !defined(_KERNEL) 6232809Sjmallett#include <cvmx.h> 7232809Sjmallett#include <cvmx-qlm.h> 8232812Sjmallett#else 9232812Sjmallett#include "cvmx.h" 10232812Sjmallett#include "cvmx-qlm.h" 11232809Sjmallett#endif 12232812Sjmallett#endif 13232809Sjmallett 14232809Sjmallettconst __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn56xx[] = 15232809Sjmallett{ 16232809Sjmallett {"prbs_error_count", 267, 220}, // BIST/PRBS error count (only valid if pbrs_lock asserted) 17232809Sjmallett {"prbs_unlock_count", 219, 212}, // BIST/PRBS unlock count (only valid if pbrs_lock asserted) 18232809Sjmallett {"prbs_locked", 211, 211}, // BIST/PRBS lock (asserted after QLM achieves lock) 19232809Sjmallett {"reset_prbs", 210, 210}, // BIST/PRBS reset (write 0 to reset) 20232809Sjmallett {"run_prbs", 209, 209}, // run PRBS test pattern 21232809Sjmallett {"run_bist", 208, 208}, // run bist (May only work for PCIe ?) 22232809Sjmallett {"unknown", 207, 202}, // 23232809Sjmallett {"biasdrvsel", 201, 199}, // assign biasdrvsel = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2); 24232809Sjmallett {"biasbuffsel", 198, 196}, // assign biasbuffsel = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4; 25232809Sjmallett {"tcoeff", 195, 192}, // assign tcoeff = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc); 26232809Sjmallett {"mb5000", 181, 181}, // assign mb5000 = fus_cfg_reg[181] ^ jtg_cfg_reg[181] ^ 1'h0; 27232809Sjmallett {"interpbw", 180, 176}, // assign interpbw = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0); 28232809Sjmallett {"mb", 175, 172}, // assign mb = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0; 29232809Sjmallett {"bwoff", 171, 160}, // assign bwoff = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0; 30232809Sjmallett {"bg_ref_sel", 153, 153}, // assign bg_ref_sel = fus_cfg_reg[153] ^ jtg_cfg_reg[153] ^ 1'h0; 31232809Sjmallett {"div2en", 152, 152}, // assign div2en = fus_cfg_reg[152] ^ jtg_cfg_reg[152] ^ 1'h0; 32232809Sjmallett {"trimen", 151, 150}, // assign trimen = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0; 33232809Sjmallett {"clkr", 149, 144}, // assign clkr = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0; 34232809Sjmallett {"clkf", 143, 132}, // assign clkf = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18; 35232809Sjmallett {"bwadj", 131, 120}, // assign bwadj = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30; 36232809Sjmallett {"shlpbck", 119, 118}, // assign shlpbck = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0; 37232809Sjmallett {"serdes_pll_byp", 117, 117}, // assign serdes_pll_byp = fus_cfg_reg[117] ^ jtg_cfg_reg[117] ^ 1'h0; 38232809Sjmallett {"ic50dac", 116, 112}, // assign ic50dac = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11; 39232809Sjmallett {"sl_posedge_sample", 111, 111}, // assign sl_posedge_sample = fus_cfg_reg[111] ^ jtg_cfg_reg[111] ^ 1'h0; 40232809Sjmallett {"sl_enable", 110, 110}, // assign sl_enable = fus_cfg_reg[110] ^ jtg_cfg_reg[110] ^ 1'h0; 41232809Sjmallett {"rx_rout_comp_bypass", 109, 109}, // assign rx_rout_comp_bypass = fus_cfg_reg[109] ^ jtg_cfg_reg[109] ^ 1'h0; 42232809Sjmallett {"ir50dac", 108, 104}, // assign ir50dac = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11; 43232809Sjmallett {"rx_res_offset", 103, 100}, // assign rx_res_offset = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2; 44232809Sjmallett {"rx_rout_comp_value", 99, 96}, // assign rx_rout_comp_value = fus_cfg_reg[99:96] ^ jtg_cfg_reg[99:96] ^ 4'h7; 45232809Sjmallett {"tx_rout_comp_value", 95, 92}, // assign tx_rout_comp_value = fus_cfg_reg[95:92] ^ jtg_cfg_reg[95:92] ^ 4'h7; 46232809Sjmallett {"tx_res_offset", 91, 88}, // assign tx_res_offset = fus_cfg_reg[91:88] ^ jtg_cfg_reg[91:88] ^ 4'h1; 47232809Sjmallett {"tx_rout_comp_bypass", 87, 87}, // assign tx_rout_comp_bypass = fus_cfg_reg[87] ^ jtg_cfg_reg[87] ^ 1'h0; 48232809Sjmallett {"idle_dac", 86, 84}, // assign idle_dac = fus_cfg_reg[86:84] ^ jtg_cfg_reg[86:84] ^ 3'h4; 49232809Sjmallett {"hyst_en", 83, 83}, // assign hyst_en = fus_cfg_reg[83] ^ jtg_cfg_reg[83] ^ 1'h1; 50232809Sjmallett {"rndt", 82, 82}, // assign rndt = fus_cfg_reg[82] ^ jtg_cfg_reg[82] ^ 1'h0; 51232809Sjmallett {"cfg_tx_com", 79, 79}, // CN52XX cfg_tx_com = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0; 52232809Sjmallett {"cfg_cdr_errcor", 78, 78}, // CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0; 53232809Sjmallett {"cfg_cdr_secord", 77, 77}, // CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1; 54232809Sjmallett {"cfg_cdr_rotate", 76, 76}, // assign cfg_cdr_rotate = fus_cfg_reg[76] ^ jtg_cfg_reg[76] ^ 1'h0; 55232809Sjmallett {"cfg_cdr_rqoffs", 75, 68}, // assign cfg_cdr_rqoffs = fus_cfg_reg[75:68] ^ jtg_cfg_reg[75:68] ^ 8'h40; 56232809Sjmallett {"cfg_cdr_incx", 67, 64}, // assign cfg_cdr_incx = fus_cfg_reg[67:64] ^ jtg_cfg_reg[67:64] ^ 4'h2; 57232809Sjmallett {"cfg_cdr_state", 63, 56}, // assign cfg_cdr_state = fus_cfg_reg[63:56] ^ jtg_cfg_reg[63:56] ^ 8'h0; 58232809Sjmallett {"cfg_cdr_bypass", 55, 55}, // assign cfg_cdr_bypass = fus_cfg_reg[55] ^ jtg_cfg_reg[55] ^ 1'h0; 59232809Sjmallett {"cfg_tx_byp", 54, 54}, // assign cfg_tx_byp = fus_cfg_reg[54] ^ jtg_cfg_reg[54] ^ 1'h0; 60232809Sjmallett {"cfg_tx_val", 53, 44}, // assign cfg_tx_val = fus_cfg_reg[53:44] ^ jtg_cfg_reg[53:44] ^ 10'h0; 61232809Sjmallett {"cfg_rx_pol_set", 43, 43}, // assign cfg_rx_pol_set = fus_cfg_reg[43] ^ jtg_cfg_reg[43] ^ 1'h0; 62232809Sjmallett {"cfg_rx_pol_clr", 42, 42}, // assign cfg_rx_pol_clr = fus_cfg_reg[42] ^ jtg_cfg_reg[42] ^ 1'h0; 63232809Sjmallett {"cfg_cdr_bw_ctl", 41, 40}, // assign cfg_cdr_bw_ctl = fus_cfg_reg[41:40] ^ jtg_cfg_reg[41:40] ^ 2'h0; 64232809Sjmallett {"cfg_rst_n_set", 39, 39}, // assign cfg_rst_n_set = fus_cfg_reg[39] ^ jtg_cfg_reg[39] ^ 1'h0; 65232809Sjmallett {"cfg_rst_n_clr", 38, 38}, // assign cfg_rst_n_clr = fus_cfg_reg[38] ^ jtg_cfg_reg[38] ^ 1'h0; 66232809Sjmallett {"cfg_tx_clk2", 37, 37}, // assign cfg_tx_clk2 = fus_cfg_reg[37] ^ jtg_cfg_reg[37] ^ 1'h0; 67232809Sjmallett {"cfg_tx_clk1", 36, 36}, // assign cfg_tx_clk1 = fus_cfg_reg[36] ^ jtg_cfg_reg[36] ^ 1'h0; 68232809Sjmallett {"cfg_tx_pol_set", 35, 35}, // assign cfg_tx_pol_set = fus_cfg_reg[35] ^ jtg_cfg_reg[35] ^ 1'h0; 69232809Sjmallett {"cfg_tx_pol_clr", 34, 34}, // assign cfg_tx_pol_clr = fus_cfg_reg[34] ^ jtg_cfg_reg[34] ^ 1'h0; 70232809Sjmallett {"cfg_tx_one", 33, 33}, // assign cfg_tx_one = fus_cfg_reg[33] ^ jtg_cfg_reg[33] ^ 1'h0; 71232809Sjmallett {"cfg_tx_zero", 32, 32}, // assign cfg_tx_zero = fus_cfg_reg[32] ^ jtg_cfg_reg[32] ^ 1'h0; 72232809Sjmallett {"cfg_rxd_wait", 31, 28}, // assign cfg_rxd_wait = fus_cfg_reg[31:28] ^ jtg_cfg_reg[31:28] ^ 4'h3; 73232809Sjmallett {"cfg_rxd_short", 27, 27}, // assign cfg_rxd_short = fus_cfg_reg[27] ^ jtg_cfg_reg[27] ^ 1'h0; 74232809Sjmallett {"cfg_rxd_set", 26, 26}, // assign cfg_rxd_set = fus_cfg_reg[26] ^ jtg_cfg_reg[26] ^ 1'h0; 75232809Sjmallett {"cfg_rxd_clr", 25, 25}, // assign cfg_rxd_clr = fus_cfg_reg[25] ^ jtg_cfg_reg[25] ^ 1'h0; 76232809Sjmallett {"cfg_loopback", 24, 24}, // assign cfg_loopback = fus_cfg_reg[24] ^ jtg_cfg_reg[24] ^ 1'h0; 77232809Sjmallett {"cfg_tx_idle_set", 23, 23}, // assign cfg_tx_idle_set = fus_cfg_reg[23] ^ jtg_cfg_reg[23] ^ 1'h0; 78232809Sjmallett {"cfg_tx_idle_clr", 22, 22}, // assign cfg_tx_idle_clr = fus_cfg_reg[22] ^ jtg_cfg_reg[22] ^ 1'h0; 79232809Sjmallett {"cfg_rx_idle_set", 21, 21}, // assign cfg_rx_idle_set = fus_cfg_reg[21] ^ jtg_cfg_reg[21] ^ 1'h0; 80232809Sjmallett {"cfg_rx_idle_clr", 20, 20}, // assign cfg_rx_idle_clr = fus_cfg_reg[20] ^ jtg_cfg_reg[20] ^ 1'h0; 81232809Sjmallett {"cfg_rx_idle_thr", 19, 16}, // assign cfg_rx_idle_thr = fus_cfg_reg[19:16] ^ jtg_cfg_reg[19:16] ^ 4'h0; 82232809Sjmallett {"cfg_com_thr", 15, 12}, // assign cfg_com_thr = fus_cfg_reg[15:12] ^ jtg_cfg_reg[15:12] ^ 4'h3; 83232809Sjmallett {"cfg_rx_offset", 11, 8}, // assign cfg_rx_offset = fus_cfg_reg[11:8] ^ jtg_cfg_reg[11:8] ^ 4'h4; 84232809Sjmallett {"cfg_skp_max", 7, 4}, // assign cfg_skp_max = fus_cfg_reg[7:4] ^ jtg_cfg_reg[7:4] ^ 4'hc; 85232809Sjmallett {"cfg_skp_min", 3, 0}, // assign cfg_skp_min = fus_cfg_reg[3:0] ^ jtg_cfg_reg[3:0] ^ 4'h4; 86232809Sjmallett {NULL, -1, -1} 87232809Sjmallett}; 88232809Sjmallett 89232809Sjmallettconst __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn52xx[] = 90232809Sjmallett{ 91232809Sjmallett {"prbs_error_count", 267, 220}, // BIST/PRBS error count (only valid if pbrs_lock asserted) 92232809Sjmallett {"prbs_unlock_count", 219, 212}, // BIST/PRBS unlock count (only valid if pbrs_lock asserted) 93232809Sjmallett {"prbs_locked", 211, 211}, // BIST/PRBS lock (asserted after QLM achieves lock) 94232809Sjmallett {"reset_prbs", 210, 210}, // BIST/PRBS reset (write 0 to reset) 95232809Sjmallett {"run_prbs", 209, 209}, // run PRBS test pattern 96232809Sjmallett {"run_bist", 208, 208}, // run bist (May only work for PCIe ?) 97232809Sjmallett {"unknown", 207, 202}, // 98232809Sjmallett 99232809Sjmallett {"biasdrvsel", 201, 199}, // assign biasdrvsel = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2); 100232809Sjmallett {"biasbuffsel", 198, 196}, // assign biasbuffsel = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4; 101232809Sjmallett {"tcoeff", 195, 192}, // assign tcoeff = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc); 102232809Sjmallett {"mb5000", 181, 181}, // assign mb5000 = fus_cfg_reg[181] ^ jtg_cfg_reg[181] ^ 1'h0; 103232809Sjmallett {"interpbw", 180, 176}, // assign interpbw = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0); 104232809Sjmallett {"mb", 175, 172}, // assign mb = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0; 105232809Sjmallett {"bwoff", 171, 160}, // assign bwoff = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0; 106232809Sjmallett {"bg_ref_sel", 153, 153}, // assign bg_ref_sel = fus_cfg_reg[153] ^ jtg_cfg_reg[153] ^ 1'h0; 107232809Sjmallett {"div2en", 152, 152}, // assign div2en = fus_cfg_reg[152] ^ jtg_cfg_reg[152] ^ 1'h0; 108232809Sjmallett {"trimen", 151, 150}, // assign trimen = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0; 109232809Sjmallett {"clkr", 149, 144}, // assign clkr = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0; 110232809Sjmallett {"clkf", 143, 132}, // assign clkf = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18; 111232809Sjmallett {"bwadj", 131, 120}, // assign bwadj = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30; 112232809Sjmallett {"shlpbck", 119, 118}, // assign shlpbck = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0; 113232809Sjmallett {"serdes_pll_byp", 117, 117}, // assign serdes_pll_byp = fus_cfg_reg[117] ^ jtg_cfg_reg[117] ^ 1'h0; 114232809Sjmallett {"ic50dac", 116, 112}, // assign ic50dac = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11; 115232809Sjmallett {"sl_posedge_sample", 111, 111}, // assign sl_posedge_sample = fus_cfg_reg[111] ^ jtg_cfg_reg[111] ^ 1'h0; 116232809Sjmallett {"sl_enable", 110, 110}, // assign sl_enable = fus_cfg_reg[110] ^ jtg_cfg_reg[110] ^ 1'h0; 117232809Sjmallett {"rx_rout_comp_bypass", 109, 109}, // assign rx_rout_comp_bypass = fus_cfg_reg[109] ^ jtg_cfg_reg[109] ^ 1'h0; 118232809Sjmallett {"ir50dac", 108, 104}, // assign ir50dac = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11; 119232809Sjmallett {"rx_res_offset", 103, 100}, // assign rx_res_offset = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2; 120232809Sjmallett {"rx_rout_comp_value", 99, 96}, // assign rx_rout_comp_value = fus_cfg_reg[99:96] ^ jtg_cfg_reg[99:96] ^ 4'h7; 121232809Sjmallett {"tx_rout_comp_value", 95, 92}, // assign tx_rout_comp_value = fus_cfg_reg[95:92] ^ jtg_cfg_reg[95:92] ^ 4'h7; 122232809Sjmallett {"tx_res_offset", 91, 88}, // assign tx_res_offset = fus_cfg_reg[91:88] ^ jtg_cfg_reg[91:88] ^ 4'h1; 123232809Sjmallett {"tx_rout_comp_bypass", 87, 87}, // assign tx_rout_comp_bypass = fus_cfg_reg[87] ^ jtg_cfg_reg[87] ^ 1'h0; 124232809Sjmallett {"idle_dac", 86, 84}, // assign idle_dac = fus_cfg_reg[86:84] ^ jtg_cfg_reg[86:84] ^ 3'h4; 125232809Sjmallett {"hyst_en", 83, 83}, // assign hyst_en = fus_cfg_reg[83] ^ jtg_cfg_reg[83] ^ 1'h1; 126232809Sjmallett {"rndt", 82, 82}, // assign rndt = fus_cfg_reg[82] ^ jtg_cfg_reg[82] ^ 1'h0; 127232809Sjmallett {"cfg_tx_com", 79, 79}, // CN52XX cfg_tx_com = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0; 128232809Sjmallett {"cfg_cdr_errcor", 78, 78}, // CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0; 129232809Sjmallett {"cfg_cdr_secord", 77, 77}, // CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1; 130232809Sjmallett {"cfg_cdr_rotate", 76, 76}, // assign cfg_cdr_rotate = fus_cfg_reg[76] ^ jtg_cfg_reg[76] ^ 1'h0; 131232809Sjmallett {"cfg_cdr_rqoffs", 75, 68}, // assign cfg_cdr_rqoffs = fus_cfg_reg[75:68] ^ jtg_cfg_reg[75:68] ^ 8'h40; 132232809Sjmallett {"cfg_cdr_incx", 67, 64}, // assign cfg_cdr_incx = fus_cfg_reg[67:64] ^ jtg_cfg_reg[67:64] ^ 4'h2; 133232809Sjmallett {"cfg_cdr_state", 63, 56}, // assign cfg_cdr_state = fus_cfg_reg[63:56] ^ jtg_cfg_reg[63:56] ^ 8'h0; 134232809Sjmallett {"cfg_cdr_bypass", 55, 55}, // assign cfg_cdr_bypass = fus_cfg_reg[55] ^ jtg_cfg_reg[55] ^ 1'h0; 135232809Sjmallett {"cfg_tx_byp", 54, 54}, // assign cfg_tx_byp = fus_cfg_reg[54] ^ jtg_cfg_reg[54] ^ 1'h0; 136232809Sjmallett {"cfg_tx_val", 53, 44}, // assign cfg_tx_val = fus_cfg_reg[53:44] ^ jtg_cfg_reg[53:44] ^ 10'h0; 137232809Sjmallett {"cfg_rx_pol_set", 43, 43}, // assign cfg_rx_pol_set = fus_cfg_reg[43] ^ jtg_cfg_reg[43] ^ 1'h0; 138232809Sjmallett {"cfg_rx_pol_clr", 42, 42}, // assign cfg_rx_pol_clr = fus_cfg_reg[42] ^ jtg_cfg_reg[42] ^ 1'h0; 139232809Sjmallett {"cfg_cdr_bw_ctl", 41, 40}, // assign cfg_cdr_bw_ctl = fus_cfg_reg[41:40] ^ jtg_cfg_reg[41:40] ^ 2'h0; 140232809Sjmallett {"cfg_rst_n_set", 39, 39}, // assign cfg_rst_n_set = fus_cfg_reg[39] ^ jtg_cfg_reg[39] ^ 1'h0; 141232809Sjmallett {"cfg_rst_n_clr", 38, 38}, // assign cfg_rst_n_clr = fus_cfg_reg[38] ^ jtg_cfg_reg[38] ^ 1'h0; 142232809Sjmallett {"cfg_tx_clk2", 37, 37}, // assign cfg_tx_clk2 = fus_cfg_reg[37] ^ jtg_cfg_reg[37] ^ 1'h0; 143232809Sjmallett {"cfg_tx_clk1", 36, 36}, // assign cfg_tx_clk1 = fus_cfg_reg[36] ^ jtg_cfg_reg[36] ^ 1'h0; 144232809Sjmallett {"cfg_tx_pol_set", 35, 35}, // assign cfg_tx_pol_set = fus_cfg_reg[35] ^ jtg_cfg_reg[35] ^ 1'h0; 145232809Sjmallett {"cfg_tx_pol_clr", 34, 34}, // assign cfg_tx_pol_clr = fus_cfg_reg[34] ^ jtg_cfg_reg[34] ^ 1'h0; 146232809Sjmallett {"cfg_tx_one", 33, 33}, // assign cfg_tx_one = fus_cfg_reg[33] ^ jtg_cfg_reg[33] ^ 1'h0; 147232809Sjmallett {"cfg_tx_zero", 32, 32}, // assign cfg_tx_zero = fus_cfg_reg[32] ^ jtg_cfg_reg[32] ^ 1'h0; 148232809Sjmallett {"cfg_rxd_wait", 31, 28}, // assign cfg_rxd_wait = fus_cfg_reg[31:28] ^ jtg_cfg_reg[31:28] ^ 4'h3; 149232809Sjmallett {"cfg_rxd_short", 27, 27}, // assign cfg_rxd_short = fus_cfg_reg[27] ^ jtg_cfg_reg[27] ^ 1'h0; 150232809Sjmallett {"cfg_rxd_set", 26, 26}, // assign cfg_rxd_set = fus_cfg_reg[26] ^ jtg_cfg_reg[26] ^ 1'h0; 151232809Sjmallett {"cfg_rxd_clr", 25, 25}, // assign cfg_rxd_clr = fus_cfg_reg[25] ^ jtg_cfg_reg[25] ^ 1'h0; 152232809Sjmallett {"cfg_loopback", 24, 24}, // assign cfg_loopback = fus_cfg_reg[24] ^ jtg_cfg_reg[24] ^ 1'h0; 153232809Sjmallett {"cfg_tx_idle_set", 23, 23}, // assign cfg_tx_idle_set = fus_cfg_reg[23] ^ jtg_cfg_reg[23] ^ 1'h0; 154232809Sjmallett {"cfg_tx_idle_clr", 22, 22}, // assign cfg_tx_idle_clr = fus_cfg_reg[22] ^ jtg_cfg_reg[22] ^ 1'h0; 155232809Sjmallett {"cfg_rx_idle_set", 21, 21}, // assign cfg_rx_idle_set = fus_cfg_reg[21] ^ jtg_cfg_reg[21] ^ 1'h0; 156232809Sjmallett {"cfg_rx_idle_clr", 20, 20}, // assign cfg_rx_idle_clr = fus_cfg_reg[20] ^ jtg_cfg_reg[20] ^ 1'h0; 157232809Sjmallett {"cfg_rx_idle_thr", 19, 16}, // assign cfg_rx_idle_thr = fus_cfg_reg[19:16] ^ jtg_cfg_reg[19:16] ^ 4'h0; 158232809Sjmallett {"cfg_com_thr", 15, 12}, // assign cfg_com_thr = fus_cfg_reg[15:12] ^ jtg_cfg_reg[15:12] ^ 4'h3; 159232809Sjmallett {"cfg_rx_offset", 11, 8}, // assign cfg_rx_offset = fus_cfg_reg[11:8] ^ jtg_cfg_reg[11:8] ^ 4'h4; 160232809Sjmallett {"cfg_skp_max", 7, 4}, // assign cfg_skp_max = fus_cfg_reg[7:4] ^ jtg_cfg_reg[7:4] ^ 4'hc; 161232809Sjmallett {"cfg_skp_min", 3, 0}, // assign cfg_skp_min = fus_cfg_reg[3:0] ^ jtg_cfg_reg[3:0] ^ 4'h4; 162232809Sjmallett {NULL, -1, -1} 163232809Sjmallett}; 164232809Sjmallett 165232809Sjmallett 166232809Sjmallettconst __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[] = 167232809Sjmallett{ 168232809Sjmallett {"prbs_err_cnt", 299, 252}, // prbs_err_cnt[47..0] 169232809Sjmallett {"prbs_lock", 251, 251}, // prbs_lock 170232809Sjmallett {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 171232809Sjmallett {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 172232809Sjmallett {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 173232809Sjmallett {"Unused1", 247, 245}, // 0 174232809Sjmallett {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 175232809Sjmallett {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 176232809Sjmallett {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 177232809Sjmallett {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 178232809Sjmallett {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 179232809Sjmallett {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 180232809Sjmallett {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 181232809Sjmallett {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 182232809Sjmallett {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 183232809Sjmallett {"cfg_loopback", 226, 226}, // cfg_loopback 184232809Sjmallett {"shlpbck", 225, 224}, // shlpbck[1..0] 185232809Sjmallett {"sl_enable", 223, 223}, // sl_enable 186232809Sjmallett {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 187232809Sjmallett {"trimen", 221, 220}, // trimen[1..0] 188232809Sjmallett {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 189232809Sjmallett {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 190232809Sjmallett {"lowf_byp", 217, 217}, // lowf_byp 191232809Sjmallett {"spdsel_byp", 216, 216}, // spdsel_byp 192232809Sjmallett {"div4_byp", 215, 215}, // div4_byp 193232809Sjmallett {"clkf_byp", 214, 208}, // clkf_byp[6..0] 194232809Sjmallett {"Unused2", 207, 206}, // 0 195232809Sjmallett {"biasdrv_hs_ls_byp", 205, 201}, // biasdrv_hs_ls_byp[4..0] 196232809Sjmallett {"tcoeff_hf_ls_byp", 200, 197}, // tcoeff_hf_ls_byp[3..0] 197232809Sjmallett {"biasdrv_hf_byp", 196, 192}, // biasdrv_hf_byp[4..0] 198232809Sjmallett {"tcoeff_hf_byp", 191, 188}, // tcoeff_hf_byp[3..0] 199232809Sjmallett {"Unused3", 187, 186}, // 0 200232809Sjmallett {"biasdrv_lf_ls_byp", 185, 181}, // biasdrv_lf_ls_byp[4..0] 201232809Sjmallett {"tcoeff_lf_ls_byp", 180, 177}, // tcoeff_lf_ls_byp[3..0] 202232809Sjmallett {"biasdrv_lf_byp", 176, 172}, // biasdrv_lf_byp[4..0] 203232809Sjmallett {"tcoeff_lf_byp", 171, 168}, // tcoeff_lf_byp[3..0] 204232809Sjmallett {"Unused4", 167, 167}, // 0 205232809Sjmallett {"interpbw", 166, 162}, // interpbw[4..0] 206232809Sjmallett {"pll_cpb", 161, 159}, // pll_cpb[2..0] 207232809Sjmallett {"pll_cps", 158, 156}, // pll_cps[2..0] 208232809Sjmallett {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 209232809Sjmallett {"Unused5", 151, 150}, // 0 210232809Sjmallett {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 211232809Sjmallett {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 212232809Sjmallett {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 213232809Sjmallett {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 214232809Sjmallett {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 215232809Sjmallett {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 216232809Sjmallett {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 217232809Sjmallett {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 218232809Sjmallett {"Unused6", 126, 100}, // 0 219232809Sjmallett {"detected_n", 99, 99}, // detected_n 220232809Sjmallett {"detected_p", 98, 98}, // detected_p 221232809Sjmallett {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 222232809Sjmallett {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 223232809Sjmallett {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 224232809Sjmallett {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 225232809Sjmallett {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 226232809Sjmallett {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 227232809Sjmallett {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 228232809Sjmallett {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 229232809Sjmallett {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 230232809Sjmallett {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 231232809Sjmallett {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 232232809Sjmallett {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 233232809Sjmallett {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 234232809Sjmallett {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 235232809Sjmallett {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 236232809Sjmallett {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 237232809Sjmallett {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 238232809Sjmallett {"rndt", 50, 50}, // rndt 239232809Sjmallett {"hcya", 49, 49}, // hcya 240232809Sjmallett {"hyst", 48, 48}, // hyst 241232809Sjmallett {"idle_dac", 47, 45}, // idle_dac[2..0] 242232809Sjmallett {"bg_ref_sel", 44, 44}, // bg_ref_sel 243232809Sjmallett {"ic50dac", 43, 39}, // ic50dac[4..0] 244232809Sjmallett {"ir50dac", 38, 34}, // ir50dac[4..0] 245232809Sjmallett {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 246232809Sjmallett {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 247232809Sjmallett {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 248232809Sjmallett {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 249232809Sjmallett {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 250232809Sjmallett {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 251232809Sjmallett {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 252232809Sjmallett {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 253232809Sjmallett {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 254232809Sjmallett {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 255232809Sjmallett {NULL, -1, -1} 256232809Sjmallett}; 257232809Sjmallett 258232809Sjmallettconst __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[] = 259232809Sjmallett{ 260232809Sjmallett {"prbs_err_cnt", 303, 256}, // prbs_err_cnt[47..0] 261232809Sjmallett {"prbs_lock", 255, 255}, // prbs_lock 262232809Sjmallett {"jtg_prbs_rx_rst_n", 254, 254}, // jtg_prbs_rx_rst_n 263232809Sjmallett {"jtg_prbs_tx_rst_n", 253, 253}, // jtg_prbs_tx_rst_n 264232809Sjmallett {"jtg_prbs_mode", 252, 251}, // jtg_prbs_mode[252:251] 265232809Sjmallett {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 266232809Sjmallett {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 - Use jtg_prbs_mode instead 267232809Sjmallett {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 - Use jtg_prbs_mode instead 268232809Sjmallett {"Unused1", 247, 246}, // 0 269232809Sjmallett {"div5_byp", 245, 245}, // div5_byp 270232809Sjmallett {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 271232809Sjmallett {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 272232809Sjmallett {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 273232809Sjmallett {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 274232809Sjmallett {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 275232809Sjmallett {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 276232809Sjmallett {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 277232809Sjmallett {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 278232809Sjmallett {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 279232809Sjmallett {"cfg_loopback", 226, 226}, // cfg_loopback 280232809Sjmallett {"shlpbck", 225, 224}, // shlpbck[1..0] 281232809Sjmallett {"sl_enable", 223, 223}, // sl_enable 282232809Sjmallett {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 283232809Sjmallett {"trimen", 221, 220}, // trimen[1..0] 284232809Sjmallett {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 285232809Sjmallett {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 286232809Sjmallett {"lowf_byp", 217, 217}, // lowf_byp 287232809Sjmallett {"spdsel_byp", 216, 216}, // spdsel_byp 288232809Sjmallett {"div4_byp", 215, 215}, // div4_byp 289232809Sjmallett {"clkf_byp", 214, 208}, // clkf_byp[6..0] 290232809Sjmallett {"biasdrv_hs_ls_byp", 207, 203}, // biasdrv_hs_ls_byp[4..0] 291232809Sjmallett {"tcoeff_hf_ls_byp", 202, 198}, // tcoeff_hf_ls_byp[4..0] 292232809Sjmallett {"biasdrv_hf_byp", 197, 193}, // biasdrv_hf_byp[4..0] 293232809Sjmallett {"tcoeff_hf_byp", 192, 188}, // tcoeff_hf_byp[4..0] 294232809Sjmallett {"biasdrv_lf_ls_byp", 187, 183}, // biasdrv_lf_ls_byp[4..0] 295232809Sjmallett {"tcoeff_lf_ls_byp", 182, 178}, // tcoeff_lf_ls_byp[4..0] 296232809Sjmallett {"biasdrv_lf_byp", 177, 173}, // biasdrv_lf_byp[4..0] 297232809Sjmallett {"tcoeff_lf_byp", 172, 168}, // tcoeff_lf_byp[4..0] 298232809Sjmallett {"Unused4", 167, 167}, // 0 299232809Sjmallett {"interpbw", 166, 162}, // interpbw[4..0] 300232809Sjmallett {"pll_cpb", 161, 159}, // pll_cpb[2..0] 301232809Sjmallett {"pll_cps", 158, 156}, // pll_cps[2..0] 302232809Sjmallett {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 303232809Sjmallett {"cfg_err_thr", 151, 150}, // cfg_err_thr 304232809Sjmallett {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 305232809Sjmallett {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 306232809Sjmallett {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 307232809Sjmallett {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 308232809Sjmallett {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 309232809Sjmallett {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 310232809Sjmallett {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 311232809Sjmallett {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 312232809Sjmallett {"Unused6", 126, 101}, // 0 313232809Sjmallett {"cfg_indep_dis", 100, 100}, // cfg_indep_dis 314232809Sjmallett {"detected_n", 99, 99}, // detected_n 315232809Sjmallett {"detected_p", 98, 98}, // detected_p 316232809Sjmallett {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 317232809Sjmallett {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 318232809Sjmallett {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 319232809Sjmallett {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 320232809Sjmallett {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 321232809Sjmallett {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 322232809Sjmallett {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 323232809Sjmallett {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 324232809Sjmallett {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 325232809Sjmallett {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 326232809Sjmallett {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 327232809Sjmallett {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 328232809Sjmallett {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 329232809Sjmallett {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 330232809Sjmallett {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 331232809Sjmallett {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 332232809Sjmallett {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 333232809Sjmallett {"rndt", 50, 50}, // rndt 334232809Sjmallett {"hcya", 49, 49}, // hcya 335232809Sjmallett {"hyst", 48, 48}, // hyst 336232809Sjmallett {"idle_dac", 47, 45}, // idle_dac[2..0] 337232809Sjmallett {"bg_ref_sel", 44, 44}, // bg_ref_sel 338232809Sjmallett {"ic50dac", 43, 39}, // ic50dac[4..0] 339232809Sjmallett {"ir50dac", 38, 34}, // ir50dac[4..0] 340232809Sjmallett {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 341232809Sjmallett {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 342232809Sjmallett {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 343232809Sjmallett {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 344232809Sjmallett {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 345232809Sjmallett {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 346232809Sjmallett {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 347232809Sjmallett {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 348232809Sjmallett {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 349232809Sjmallett {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 350232809Sjmallett {NULL, -1, -1} 351232809Sjmallett}; 352232809Sjmallett 353232809Sjmallettconst __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[] = 354232809Sjmallett{ 355232809Sjmallett {"prbs_err_cnt", 303, 256}, // prbs_err_cnt[47..0] 356232809Sjmallett {"prbs_lock", 255, 255}, // prbs_lock 357232809Sjmallett {"jtg_prbs_rx_rst_n", 254, 254}, // jtg_prbs_rx_rst_n 358232809Sjmallett {"jtg_prbs_tx_rst_n", 253, 253}, // jtg_prbs_tx_rst_n 359232809Sjmallett {"jtg_prbs_mode", 252, 251}, // jtg_prbs_mode[252:251] 360232809Sjmallett {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 361232809Sjmallett {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 - Use jtg_prbs_mode instead 362232809Sjmallett {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 - Use jtg_prbs_mode instead 363232809Sjmallett {"Unused1", 247, 245}, // 0 364232809Sjmallett {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 365232809Sjmallett {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 366232809Sjmallett {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 367232809Sjmallett {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 368232809Sjmallett {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 369232809Sjmallett {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 370232809Sjmallett {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 371232809Sjmallett {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 372232809Sjmallett {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 373232809Sjmallett {"cfg_loopback", 226, 226}, // cfg_loopback 374232809Sjmallett {"shlpbck", 225, 224}, // shlpbck[1..0] 375232809Sjmallett {"sl_enable", 223, 223}, // sl_enable 376232809Sjmallett {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 377232809Sjmallett {"trimen", 221, 220}, // trimen[1..0] 378232809Sjmallett {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 379232809Sjmallett {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 380232809Sjmallett {"lowf_byp", 217, 217}, // lowf_byp 381232809Sjmallett {"spdsel_byp", 216, 216}, // spdsel_byp 382232809Sjmallett {"div4_byp", 215, 215}, // div4_byp 383232809Sjmallett {"clkf_byp", 214, 208}, // clkf_byp[6..0] 384232809Sjmallett {"biasdrv_hs_ls_byp", 207, 203}, // biasdrv_hs_ls_byp[4..0] 385232809Sjmallett {"tcoeff_hf_ls_byp", 202, 198}, // tcoeff_hf_ls_byp[4..0] 386232809Sjmallett {"biasdrv_hf_byp", 197, 193}, // biasdrv_hf_byp[4..0] 387232809Sjmallett {"tcoeff_hf_byp", 192, 188}, // tcoeff_hf_byp[4..0] 388232809Sjmallett {"biasdrv_lf_ls_byp", 187, 183}, // biasdrv_lf_ls_byp[4..0] 389232809Sjmallett {"tcoeff_lf_ls_byp", 182, 178}, // tcoeff_lf_ls_byp[4..0] 390232809Sjmallett {"biasdrv_lf_byp", 177, 173}, // biasdrv_lf_byp[4..0] 391232809Sjmallett {"tcoeff_lf_byp", 172, 168}, // tcoeff_lf_byp[4..0] 392232809Sjmallett {"Unused4", 167, 167}, // 0 393232809Sjmallett {"interpbw", 166, 162}, // interpbw[4..0] 394232809Sjmallett {"pll_cpb", 161, 159}, // pll_cpb[2..0] 395232809Sjmallett {"pll_cps", 158, 156}, // pll_cps[2..0] 396232809Sjmallett {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 397232809Sjmallett {"cfg_err_thr", 151, 150}, // cfg_err_thr 398232809Sjmallett {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 399232809Sjmallett {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 400232809Sjmallett {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 401232809Sjmallett {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 402232809Sjmallett {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 403232809Sjmallett {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 404232809Sjmallett {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 405232809Sjmallett {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 406232809Sjmallett {"Unused6", 126, 100}, // 0 407232809Sjmallett {"detected_n", 99, 99}, // detected_n 408232809Sjmallett {"detected_p", 98, 98}, // detected_p 409232809Sjmallett {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 410232809Sjmallett {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 411232809Sjmallett {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 412232809Sjmallett {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 413232809Sjmallett {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 414232809Sjmallett {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 415232809Sjmallett {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 416232809Sjmallett {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 417232809Sjmallett {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 418232809Sjmallett {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 419232809Sjmallett {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 420232809Sjmallett {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 421232809Sjmallett {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 422232809Sjmallett {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 423232809Sjmallett {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 424232809Sjmallett {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 425232809Sjmallett {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 426232809Sjmallett {"rndt", 50, 50}, // rndt 427232809Sjmallett {"hcya", 49, 49}, // hcya 428232809Sjmallett {"hyst", 48, 48}, // hyst 429232809Sjmallett {"idle_dac", 47, 45}, // idle_dac[2..0] 430232809Sjmallett {"bg_ref_sel", 44, 44}, // bg_ref_sel 431232809Sjmallett {"ic50dac", 43, 39}, // ic50dac[4..0] 432232809Sjmallett {"ir50dac", 38, 34}, // ir50dac[4..0] 433232809Sjmallett {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 434232809Sjmallett {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 435232809Sjmallett {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 436232809Sjmallett {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 437232809Sjmallett {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 438232809Sjmallett {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 439232809Sjmallett {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 440232809Sjmallett {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 441232809Sjmallett {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 442232809Sjmallett {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 443232809Sjmallett {NULL, -1, -1} 444232809Sjmallett}; 445232809Sjmallett 446