1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Configuration functions for low latency memory. 50210284Sjmallett * 51232812Sjmallett * <hr>$Revision: 70030 $<hr> 52210284Sjmallett */ 53210284Sjmallett#include "cvmx-config.h" 54210284Sjmallett#include "cvmx.h" 55210284Sjmallett#include "cvmx-llm.h" 56210284Sjmallett#include "cvmx-sysinfo.h" 57210284Sjmallett#include "cvmx-csr-db.h" 58210284Sjmallett 59210284Sjmallett#define MIN(a,b) (((a)<(b))?(a):(b)) 60210284Sjmallett 61210284Sjmalletttypedef struct 62210284Sjmallett{ 63210284Sjmallett uint32_t dfa_memcfg0_base; 64210284Sjmallett uint32_t dfa_memcfg1_base; 65210284Sjmallett uint32_t mrs_dat_p0bunk0; 66210284Sjmallett uint32_t mrs_dat_p0bunk1; 67210284Sjmallett uint32_t mrs_dat_p1bunk0; 68210284Sjmallett uint32_t mrs_dat_p1bunk1; 69210284Sjmallett uint8_t p0_ena; 70210284Sjmallett uint8_t p1_ena; 71210284Sjmallett uint8_t bunkport; 72210284Sjmallett} rldram_csr_config_t; 73210284Sjmallett 74210284Sjmallett 75210284Sjmallett 76210284Sjmallett 77210284Sjmallett 78210284Sjmallettint rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t *cfg_ptr); 79210284Sjmallett 80210284Sjmallett 81210284Sjmallettvoid print_rld_cfg(rldram_csr_config_t *cfg_ptr); 82210284Sjmallettvoid write_rld_cfg(rldram_csr_config_t *cfg_ptr); 83210284Sjmallettstatic void cn31xx_dfa_memory_init(void); 84210284Sjmallett 85210284Sjmallettstatic uint32_t process_address_map_str(uint32_t mrs_dat, char *addr_str); 86210284Sjmallett 87210284Sjmallett 88210284Sjmallett 89210284Sjmallett#ifndef CVMX_LLM_NUM_PORTS 90210284Sjmallett#warning WARNING: default CVMX_LLM_NUM_PORTS used. Defaults deprecated, please set in executive-config.h 91210284Sjmallett#define CVMX_LLM_NUM_PORTS 1 92210284Sjmallett#endif 93210284Sjmallett 94210284Sjmallett 95210284Sjmallett#if (CVMX_LLM_NUM_PORTS != 1) && (CVMX_LLM_NUM_PORTS != 2) 96210284Sjmallett#error "Invalid CVMX_LLM_NUM_PORTS value: must be 1 or 2\n" 97210284Sjmallett#endif 98210284Sjmallett 99210284Sjmallettint cvmx_llm_initialize() 100210284Sjmallett{ 101210284Sjmallett if (cvmx_llm_initialize_desc(NULL) < 0) 102210284Sjmallett return -1; 103210284Sjmallett 104210284Sjmallett return 0; 105210284Sjmallett} 106210284Sjmallett 107210284Sjmallett 108210284Sjmallettint cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr) 109210284Sjmallett{ 110210284Sjmallett cvmx_sysinfo_t *sys_ptr; 111210284Sjmallett sys_ptr = cvmx_sysinfo_get(); 112210284Sjmallett 113210284Sjmallett if (!llm_desc_ptr) 114210284Sjmallett return -1; 115210284Sjmallett 116210284Sjmallett memset(llm_desc_ptr, 0, sizeof(llm_descriptor_t)); 117210284Sjmallett 118215990Sjmallett llm_desc_ptr->cpu_hz = cvmx_clock_get_rate(CVMX_CLOCK_CORE); 119210284Sjmallett 120210284Sjmallett if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBT3000) 121210284Sjmallett { // N3K->RLD0 Address Swizzle 122210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 123210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10"); 124210284Sjmallett // N3K->RLD1 Address Swizzle 125210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 126210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19"); 127210284Sjmallett /* NOTE: The ebt3000 has a strange RLDRAM configuration for validation purposes. It is not recommended to have 128210284Sjmallett ** different amounts of memory on different ports as that renders some memory unusable */ 129210284Sjmallett llm_desc_ptr->rld0_bunks = 2; 130210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 131210284Sjmallett llm_desc_ptr->rld0_mbytes = 128; // RLD0: 4x 32Mx9 132210284Sjmallett llm_desc_ptr->rld1_mbytes = 64; // RLD1: 2x 16Mx18 133210284Sjmallett } 134210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBT5800) 135210284Sjmallett { 136210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 137210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19"); 138210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 139210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19"); 140210284Sjmallett llm_desc_ptr->rld0_bunks = 2; 141210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 142210284Sjmallett llm_desc_ptr->rld0_mbytes = 128; 143210284Sjmallett llm_desc_ptr->rld1_mbytes = 128; 144210284Sjmallett llm_desc_ptr->max_rld_clock_mhz = 400; /* CN58XX needs a max clock speed for selecting optimal divisor */ 145210284Sjmallett } 146210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3000) 147210284Sjmallett { 148210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 149210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10"); 150210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 151210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10"); 152210284Sjmallett llm_desc_ptr->rld0_bunks = 2; 153210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 154210284Sjmallett llm_desc_ptr->rld0_mbytes = 128; 155210284Sjmallett llm_desc_ptr->rld1_mbytes = 128; 156210284Sjmallett } 157210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_THUNDER) 158210284Sjmallett { 159210284Sjmallett 160210284Sjmallett if (sys_ptr->board_rev_major >= 4) 161210284Sjmallett { 162210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 13 11 01 02 07 19 03 18 10 12 20 06 04 08 17 05 14 16 00 09 15"); 163210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 11 13 04 08 17 05 14 16 00 09 15 06 01 02 07 19 03 18 10 12 20"); 164210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 02 19 18 17 16 09 14 13 20 11 10 01 08 03 06 15 04 07 05 12 00"); 165210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 02 08 03 06 15 04 07 05 12 00 01 18 17 16 09 14 13 20 11 10"); 166210284Sjmallett } 167210284Sjmallett else 168210284Sjmallett { 169210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 170210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 171210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 172210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 173210284Sjmallett } 174210284Sjmallett 175210284Sjmallett llm_desc_ptr->rld0_bunks = 2; 176210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 177210284Sjmallett llm_desc_ptr->rld0_mbytes = 128; 178210284Sjmallett llm_desc_ptr->rld1_mbytes = 128; 179210284Sjmallett } 180210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_NICPRO2) 181210284Sjmallett { 182210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 183210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10"); 184210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 185210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10"); 186210284Sjmallett llm_desc_ptr->rld0_bunks = 2; 187210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 188210284Sjmallett llm_desc_ptr->rld0_mbytes = 256; 189210284Sjmallett llm_desc_ptr->rld1_mbytes = 256; 190210284Sjmallett llm_desc_ptr->max_rld_clock_mhz = 400; /* CN58XX needs a max clock speed for selecting optimal divisor */ 191210284Sjmallett } 192210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3100) 193210284Sjmallett { 194210284Sjmallett /* CN31xx DFA memory is DDR based, so it is completely different from the CN38XX DFA memory */ 195210284Sjmallett llm_desc_ptr->rld0_bunks = 1; 196210284Sjmallett llm_desc_ptr->rld0_mbytes = 256; 197210284Sjmallett } 198210284Sjmallett else if (sys_ptr->board_type == CVMX_BOARD_TYPE_KBP) 199210284Sjmallett { 200210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_fb_str, ""); 201210284Sjmallett strcpy(llm_desc_ptr->addr_rld0_bb_str, ""); 202210284Sjmallett llm_desc_ptr->rld0_bunks = 0; 203210284Sjmallett llm_desc_ptr->rld0_mbytes = 0; 204210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 205210284Sjmallett strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00"); 206210284Sjmallett llm_desc_ptr->rld1_bunks = 2; 207210284Sjmallett llm_desc_ptr->rld1_mbytes = 64; 208210284Sjmallett } 209210284Sjmallett else 210210284Sjmallett { 211210284Sjmallett cvmx_dprintf("No default LLM configuration available for board %s (%d)\n", cvmx_board_type_to_string(sys_ptr->board_type), sys_ptr->board_type); 212210284Sjmallett return -1; 213210284Sjmallett } 214210284Sjmallett 215210284Sjmallett return(0); 216210284Sjmallett} 217210284Sjmallett 218210284Sjmallettint cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr) 219210284Sjmallett{ 220210284Sjmallett cvmx_sysinfo_t *sys_ptr; 221210284Sjmallett sys_ptr = cvmx_sysinfo_get(); 222210284Sjmallett llm_descriptor_t default_llm_desc; 223210284Sjmallett 224210284Sjmallett memset(&default_llm_desc, 0, sizeof(default_llm_desc)); 225210284Sjmallett if (sys_ptr->board_type == CVMX_BOARD_TYPE_SIM) 226210284Sjmallett { 227210284Sjmallett cvmx_dprintf("Skipping llm configuration for simulator.\n"); 228210284Sjmallett return 0; 229210284Sjmallett } 230210284Sjmallett 231210284Sjmallett if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3100) 232210284Sjmallett { 233210284Sjmallett /* CN31xx DFA memory is DDR based, so it is completely different from the CN38XX DFA memory 234210284Sjmallett ** config descriptors are not supported yet.*/ 235210284Sjmallett cvmx_dprintf("Warning: preliminary DFA memory configuration\n"); 236210284Sjmallett cn31xx_dfa_memory_init(); 237210284Sjmallett return(256*1024*1024); 238210284Sjmallett } 239210284Sjmallett 240210284Sjmallett /* If no descriptor passed, generate default descriptor based on board type. 241210284Sjmallett ** Fail if no default available for given board type 242210284Sjmallett */ 243210284Sjmallett if (!llm_desc_ptr) 244210284Sjmallett { 245210284Sjmallett /* Get default descriptor */ 246210284Sjmallett if (0 > cvmx_llm_get_default_descriptor(&default_llm_desc)) 247210284Sjmallett return -1; 248210284Sjmallett 249210284Sjmallett /* Disable second port depending on CVMX config */ 250210284Sjmallett if (CVMX_LLM_NUM_PORTS == 1) 251210284Sjmallett default_llm_desc.rld0_bunks = 0; // For single port: Force RLD0(P1) to appear EMPTY 252210284Sjmallett 253210284Sjmallett cvmx_dprintf("Using default LLM configuration for board %s (%d)\n", cvmx_board_type_to_string(sys_ptr->board_type), sys_ptr->board_type); 254210284Sjmallett 255210284Sjmallett llm_desc_ptr = &default_llm_desc; 256210284Sjmallett } 257210284Sjmallett 258210284Sjmallett 259210284Sjmallett 260210284Sjmallett rldram_csr_config_t ebt3000_rld_cfg; 261210284Sjmallett if (!rld_csr_config_generate(llm_desc_ptr, &ebt3000_rld_cfg)) 262210284Sjmallett { 263210284Sjmallett cvmx_dprintf("Configuring %d llm port(s).\n", !!llm_desc_ptr->rld0_bunks + !!llm_desc_ptr->rld1_bunks); 264210284Sjmallett write_rld_cfg(&ebt3000_rld_cfg); 265210284Sjmallett } 266210284Sjmallett else 267210284Sjmallett { 268210284Sjmallett cvmx_dprintf("Error creating rldram configuration\n"); 269210284Sjmallett return(-1); 270210284Sjmallett } 271210284Sjmallett 272210284Sjmallett /* Compute how much memory is configured 273210284Sjmallett ** Memory is interleaved, so if one port has more than the other some memory is not usable */ 274210284Sjmallett 275210284Sjmallett /* If both ports are enabled, handle the case where one port has more than the other. 276210284Sjmallett ** This is an unusual and not recommended configuration that exists on the ebt3000 board */ 277210284Sjmallett if (!!llm_desc_ptr->rld0_bunks && !!llm_desc_ptr->rld1_bunks) 278210284Sjmallett llm_desc_ptr->rld0_mbytes = llm_desc_ptr->rld1_mbytes = MIN(llm_desc_ptr->rld0_mbytes, llm_desc_ptr->rld1_mbytes); 279210284Sjmallett 280210284Sjmallett return(((!!llm_desc_ptr->rld0_bunks) * llm_desc_ptr->rld0_mbytes 281210284Sjmallett + (!!llm_desc_ptr->rld1_bunks) * llm_desc_ptr->rld1_mbytes) * 1024*1024); 282210284Sjmallett} 283210284Sjmallett 284210284Sjmallett//====================== 285210284Sjmallett// SUPPORT FUNCTIONS: 286210284Sjmallett//====================== 287210284Sjmallett//====================================================================== 288210284Sjmallett// Extracts srcvec[srcbitpos] and places it in return int (bit[0]) 289210284Sjmallettint bit_extract ( int srcvec, // source word (to extract) 290210284Sjmallett int srcbitpos // source bit position 291210284Sjmallett ) 292210284Sjmallett{ 293210284Sjmallett return(((1 << srcbitpos) & srcvec) >> srcbitpos); 294210284Sjmallett} 295210284Sjmallett//====================================================================== 296210284Sjmallett// Inserts srcvec[0] into dstvec[dstbitpos] (without affecting other bits) 297210284Sjmallettint bit_insert ( int srcvec, // srcvec[0] = bit to be inserted 298210284Sjmallett int dstbitpos, // Bit position to insert into returned int 299210284Sjmallett int dstvec // dstvec (destination vector) 300210284Sjmallett ) 301210284Sjmallett{ 302210284Sjmallett return((srcvec << dstbitpos) | dstvec); // Shift bit to insert into bit position/OR with accumulated number 303210284Sjmallett} 304210284Sjmallett//====================================================================== 305210284Sjmallett 306210284Sjmallettint rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t *cfg_ptr) 307210284Sjmallett{ 308210284Sjmallett char *addr_rld0_fb_str; 309210284Sjmallett char *addr_rld0_bb_str; 310210284Sjmallett char *addr_rld1_fb_str; 311210284Sjmallett char *addr_rld1_bb_str; 312210284Sjmallett int eclk_ps; 313210284Sjmallett int mtype = 0; // MTYPE (0: RLDRAM/1: FCRAM 314210284Sjmallett int trcmin = 20; // tRC(min) - from RLDRAM data sheet 315210284Sjmallett int trc_cyc; // TRC(cyc) 316210284Sjmallett int trc_mod; 317210284Sjmallett int trl_cyc; // TRL(cyc) 318210284Sjmallett int twl_cyc; // TWL(cyc) 319210284Sjmallett int tmrsc_cyc = 6; // tMRSC(cyc) [2-7] 320210284Sjmallett int mclk_ps; // DFA Memory Clock(in ps) = 2x eclk 321210284Sjmallett int rldcfg = 99; // RLDRAM-II CFG (1,2,3) 322210284Sjmallett int mrs_odt = 0; // RLDRAM MRS A[9]=ODT (default) 323210284Sjmallett int mrs_impmatch = 0; // RLDRAM MRS A[8]=Impedance Matching (default) 324210284Sjmallett int mrs_dllrst = 1; // RLDRAM MRS A[7]=DLL Reset (default) 325210284Sjmallett uint32_t mrs_dat; 326210284Sjmallett int mrs_dat_p0bunk0 = 0; // MRS Register Data After Address Map (for Port0 Bunk0) 327210284Sjmallett int mrs_dat_p0bunk1 = 0; // MRS Register Data After Address Map (for Port0 Bunk1) 328210284Sjmallett int mrs_dat_p1bunk0 = 0; // MRS Register Data After Address Map (for Port1 Bunk0) 329210284Sjmallett int mrs_dat_p1bunk1 = 0; // MRS Register Data After Address Map (for Port1 Bunk1) 330210284Sjmallett int p0_ena = 0; // DFA Port#0 Enabled 331210284Sjmallett int p1_ena = 0; // DFA Port#1 Enabled 332210284Sjmallett int memport = 0; // Memory(MB) per Port [MAX=512] 333210284Sjmallett int membunk; // Memory(MB) per Bunk 334210284Sjmallett int bunkport = 0; // Bunks/Port [1/2] 335210284Sjmallett int pbunk = 0; // Physical Bunk(or Rank) encoding for address bit 336210284Sjmallett int tref_ms = 32; // tREF(ms) (RLDRAM-II overall device refresh interval 337210284Sjmallett int trefi_ns; // tREFI(ns) = tREF(ns)/#rows/bank 338210284Sjmallett int rows = 8; // #rows/bank (K) typically 8K 339210284Sjmallett int ref512int; 340210284Sjmallett int ref512mod; 341210284Sjmallett int tskw_cyc = 0; 342210284Sjmallett int fprch = 1; 343210284Sjmallett int bprch = 0; 344210284Sjmallett int dfa_memcfg0_base = 0; 345210284Sjmallett int dfa_memcfg1_base = 0; 346210284Sjmallett int tbl = 1; // tBL (1: 2-burst /2: 4-burst) 347210284Sjmallett int rw_dly; 348210284Sjmallett int wr_dly; 349210284Sjmallett int r2r = 1; 350210284Sjmallett int sil_lat = 1; 351210284Sjmallett int clkdiv = 2; /* CN38XX is fixed at 2, CN58XX supports 2,3,4 */ 352210284Sjmallett int clkdiv_enc = 0x0; /* Encoded clock divisor, only used for CN58XX */ 353210284Sjmallett 354210284Sjmallett if (!llm_desc_ptr) 355210284Sjmallett return -1; 356210284Sjmallett 357210284Sjmallett /* Setup variables from descriptor */ 358210284Sjmallett 359210284Sjmallett addr_rld0_fb_str = llm_desc_ptr->addr_rld0_fb_str; 360210284Sjmallett addr_rld0_bb_str = llm_desc_ptr->addr_rld0_bb_str; 361210284Sjmallett addr_rld1_fb_str = llm_desc_ptr->addr_rld1_fb_str; 362210284Sjmallett addr_rld1_bb_str = llm_desc_ptr->addr_rld1_bb_str; 363210284Sjmallett 364210284Sjmallett p0_ena = !!llm_desc_ptr->rld1_bunks; // NOTE: P0 == RLD1 365210284Sjmallett p1_ena = !!llm_desc_ptr->rld0_bunks; // NOTE: P1 == RLD0 366210284Sjmallett 367210284Sjmallett // Massage the code, so that if the user had imbalanced memory per-port (or imbalanced bunks/port), we 368210284Sjmallett // at least try to configure 'workable' memory. 369210284Sjmallett if (p0_ena && p1_ena) // IF BOTH PORTS Enabled (imbalanced memory), select smaller of BOTH 370210284Sjmallett { 371210284Sjmallett memport = MIN(llm_desc_ptr->rld0_mbytes, llm_desc_ptr->rld1_mbytes); 372210284Sjmallett bunkport = MIN(llm_desc_ptr->rld0_bunks, llm_desc_ptr->rld1_bunks); 373210284Sjmallett } 374210284Sjmallett else if (p0_ena) // P0=RLD1 Enabled 375210284Sjmallett { 376210284Sjmallett memport = llm_desc_ptr->rld1_mbytes; 377210284Sjmallett bunkport = llm_desc_ptr->rld1_bunks; 378210284Sjmallett } 379210284Sjmallett else if (p1_ena) // P1=RLD0 Enabled 380210284Sjmallett { 381210284Sjmallett memport = llm_desc_ptr->rld0_mbytes; 382210284Sjmallett bunkport = llm_desc_ptr->rld0_bunks; 383210284Sjmallett } 384210284Sjmallett else 385210284Sjmallett return -1; 386210284Sjmallett 387210284Sjmallett uint32_t eclk_mhz = llm_desc_ptr->cpu_hz/1000000; 388210284Sjmallett 389210284Sjmallett 390210284Sjmallett 391210284Sjmallett /* Tweak skew based on cpu clock */ 392210284Sjmallett if (eclk_mhz <= 367) 393210284Sjmallett { 394210284Sjmallett tskw_cyc = 0; 395210284Sjmallett } 396210284Sjmallett else 397210284Sjmallett { 398210284Sjmallett tskw_cyc = 1; 399210284Sjmallett } 400210284Sjmallett 401210284Sjmallett /* Determine clock divider ratio (only required for CN58XX) */ 402210284Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN58XX)) 403210284Sjmallett { 404210284Sjmallett uint32_t max_llm_clock_mhz = llm_desc_ptr->max_rld_clock_mhz; 405210284Sjmallett if (!max_llm_clock_mhz) 406210284Sjmallett { 407210284Sjmallett max_llm_clock_mhz = 400; /* Default to 400 MHz */ 408210284Sjmallett cvmx_dprintf("Warning, using default max_rld_clock_mhz of: %lu MHz\n", (unsigned long)max_llm_clock_mhz); 409210284Sjmallett } 410210284Sjmallett 411210284Sjmallett /* Compute the divisor, and round up */ 412210284Sjmallett clkdiv = eclk_mhz/max_llm_clock_mhz; 413210284Sjmallett if (clkdiv * max_llm_clock_mhz < eclk_mhz) 414210284Sjmallett clkdiv++; 415210284Sjmallett 416210284Sjmallett if (clkdiv > 4) 417210284Sjmallett { 418210284Sjmallett cvmx_dprintf("ERROR: CN58XX LLM clock divisor out of range\n"); 419210284Sjmallett goto TERMINATE; 420210284Sjmallett } 421210284Sjmallett if (clkdiv < 2) 422210284Sjmallett clkdiv = 2; 423210284Sjmallett 424210284Sjmallett cvmx_dprintf("Using llm clock divisor: %d, llm clock is: %lu MHz\n", clkdiv, (unsigned long)eclk_mhz/clkdiv); 425210284Sjmallett /* Translate divisor into bit encoding for register */ 426210284Sjmallett /* 0 -> div 2 427210284Sjmallett ** 1 -> reserved 428210284Sjmallett ** 2 -> div 3 429210284Sjmallett ** 3 -> div 4 430210284Sjmallett */ 431210284Sjmallett if (clkdiv == 2) 432210284Sjmallett clkdiv_enc = 0; 433210284Sjmallett else 434210284Sjmallett clkdiv_enc = clkdiv - 1; 435210284Sjmallett 436210284Sjmallett /* Odd divisor needs sil_lat to be 2 */ 437210284Sjmallett if (clkdiv == 0x3) 438210284Sjmallett sil_lat = 2; 439210284Sjmallett 440210284Sjmallett /* Increment tskw for high clock speeds */ 441215990Sjmallett if ((unsigned long)eclk_mhz/clkdiv >= 375) 442210284Sjmallett tskw_cyc += 1; 443210284Sjmallett } 444210284Sjmallett 445210284Sjmallett eclk_ps = (1000000+(eclk_mhz-1)) / eclk_mhz; // round up if nonzero remainder 446210284Sjmallett //======================================================================= 447210284Sjmallett 448210284Sjmallett //======================================================================= 449210284Sjmallett // Now, Query User for DFA Memory Type 450210284Sjmallett if (mtype != 0) 451210284Sjmallett { 452210284Sjmallett goto TERMINATE; // Complete this code for FCRAM usage on N3K-P2 453210284Sjmallett } 454210284Sjmallett //======================================================================= 455210284Sjmallett // Query what the tRC(min) value is from the data sheets 456210284Sjmallett //======================================================================= 457210284Sjmallett // Now determine the Best CFG based on Memory clock(ps) and tRCmin(ns) 458210284Sjmallett mclk_ps = eclk_ps * clkdiv; 459210284Sjmallett trc_cyc = ((trcmin * 1000)/mclk_ps); 460210284Sjmallett trc_mod = ((trcmin * 1000) % mclk_ps); 461210284Sjmallett // If remainder exists, bump up to the next integer multiple 462210284Sjmallett if (trc_mod != 0) 463210284Sjmallett { 464210284Sjmallett trc_cyc = trc_cyc + 1; 465210284Sjmallett } 466210284Sjmallett // If tRC is now ODD, then bump it to the next EVEN integer (RLDRAM-II does not support odd tRC values at this time). 467210284Sjmallett if (trc_cyc & 1) 468210284Sjmallett { 469210284Sjmallett trc_cyc = trc_cyc + 1; // Bump it to an even # 470210284Sjmallett } 471210284Sjmallett // RLDRAM CFG Range Check: If the computed trc_cyc is less than 4, then set it to min CFG1 [tRC=4] 472210284Sjmallett if (trc_cyc < 4) 473210284Sjmallett { 474210284Sjmallett trc_cyc = 4; // If computed trc_cyc < 4 then clamp to 4 475210284Sjmallett } 476210284Sjmallett else if (trc_cyc > 8) 477210284Sjmallett { // If the computed trc_cyc > 8, then report an error (because RLDRAM cannot support a tRC>8 478210284Sjmallett goto TERMINATE; 479210284Sjmallett } 480210284Sjmallett // Assuming all is ok(up to here) 481210284Sjmallett // At this point the tRC_cyc has been clamped between 4 and 8 (and is even), So it can only be 4,6,8 which are 482210284Sjmallett // the RLDRAM valid CFG range values. 483210284Sjmallett trl_cyc = trc_cyc; // tRL = tRC (for RLDRAM=II) 484210284Sjmallett twl_cyc = trl_cyc + 1; // tWL = tRL + 1 (for RLDRAM-II) 485210284Sjmallett // NOTE: RLDRAM-II (as of 4/25/05) only have 3 supported CFG encodings: 486210284Sjmallett if (trc_cyc == 4) 487210284Sjmallett { 488210284Sjmallett rldcfg = 1; // CFG #1 (tRL=4/tRC=4/tWL=5) 489210284Sjmallett } 490210284Sjmallett else if (trc_cyc == 6) 491210284Sjmallett { 492210284Sjmallett rldcfg = 2; // CFG #2 (tRL=6/tRC=6/tWL=7) 493210284Sjmallett } 494210284Sjmallett else if (trc_cyc == 8) 495210284Sjmallett { 496210284Sjmallett rldcfg = 3; // CFG #3 (tRL=8/tRC=8/tWL=9) 497210284Sjmallett } 498210284Sjmallett else 499210284Sjmallett { 500210284Sjmallett goto TERMINATE; 501210284Sjmallett } 502210284Sjmallett //======================================================================= 503210284Sjmallett mrs_dat = ( (mrs_odt << 9) | (mrs_impmatch << 8) | (mrs_dllrst << 7) | rldcfg ); 504210284Sjmallett //======================================================================= 505210284Sjmallett // If there is only a single bunk, then skip over address mapping queries (which are not required) 506210284Sjmallett if (bunkport == 1) 507210284Sjmallett { 508210284Sjmallett goto CALC_PBUNK; 509210284Sjmallett } 510210284Sjmallett 511210284Sjmallett /* Process the address mappings */ 512210284Sjmallett /* Note that that RLD0 pins corresponds to Port#1, and 513210284Sjmallett ** RLD1 pins corresponds to Port#0. 514210284Sjmallett */ 515210284Sjmallett mrs_dat_p1bunk0 = process_address_map_str(mrs_dat, addr_rld0_fb_str); 516210284Sjmallett mrs_dat_p1bunk1 = process_address_map_str(mrs_dat, addr_rld0_bb_str); 517210284Sjmallett mrs_dat_p0bunk0 = process_address_map_str(mrs_dat, addr_rld1_fb_str); 518210284Sjmallett mrs_dat_p0bunk1 = process_address_map_str(mrs_dat, addr_rld1_bb_str); 519210284Sjmallett 520210284Sjmallett 521210284Sjmallett //======================================================================= 522210284Sjmallett CALC_PBUNK: 523210284Sjmallett // Determine the PBUNK field (based on Memory/Bunk) 524210284Sjmallett // This determines the addr bit used to distinguish when crossing a bunk. 525210284Sjmallett // NOTE: For RLDRAM, the bunk bit is extracted from 'a' programmably selected high 526210284Sjmallett // order addr bit. [linear address per-bunk] 527210284Sjmallett if (bunkport == 2) 528210284Sjmallett { 529210284Sjmallett membunk = (memport / 2); 530210284Sjmallett } 531210284Sjmallett else 532210284Sjmallett { 533210284Sjmallett membunk = memport; 534210284Sjmallett } 535210284Sjmallett if (membunk == 16) 536210284Sjmallett { // 16MB/bunk MA[19] 537210284Sjmallett pbunk = 0; 538210284Sjmallett } 539210284Sjmallett else if (membunk == 32) 540210284Sjmallett { // 32MB/bunk MA[20] 541210284Sjmallett pbunk = 1; 542210284Sjmallett } 543210284Sjmallett else if (membunk == 64) 544210284Sjmallett { // 64MB/bunk MA[21] 545210284Sjmallett pbunk = 2; 546210284Sjmallett } 547210284Sjmallett else if (membunk == 128) 548210284Sjmallett { // 128MB/bunk MA[22] 549210284Sjmallett pbunk = 3; 550210284Sjmallett } 551210284Sjmallett else if (membunk == 256) 552210284Sjmallett { // 256MB/bunk MA[23] 553210284Sjmallett pbunk = 4; 554210284Sjmallett } 555210284Sjmallett else if (membunk == 512) 556210284Sjmallett { // 512MB/bunk 557210284Sjmallett } 558210284Sjmallett //======================================================================= 559210284Sjmallett //======================================================================= 560210284Sjmallett //======================================================================= 561210284Sjmallett // Now determine N3K REFINT 562210284Sjmallett trefi_ns = (tref_ms * 1000 * 1000) / (rows * 1024); 563210284Sjmallett ref512int = ((trefi_ns * 1000) / (eclk_ps * 512)); 564210284Sjmallett ref512mod = ((trefi_ns * 1000) % (eclk_ps * 512)); 565210284Sjmallett //======================================================================= 566210284Sjmallett // Ask about tSKW 567210284Sjmallett#if 0 568210284Sjmallett if (tskw_ps == 0) 569210284Sjmallett { 570210284Sjmallett tskw_cyc = 0; 571210284Sjmallett } 572210284Sjmallett else 573210284Sjmallett { // CEILING function 574210284Sjmallett tskw_cyc = (tskw_ps / eclk_ps); 575210284Sjmallett tskw_mod = (tskw_ps % eclk_ps); 576210284Sjmallett if (tskw_mod != 0) 577210284Sjmallett { // If there's a remainder - then bump to next (+1) 578210284Sjmallett tskw_cyc = tskw_cyc + 1; 579210284Sjmallett } 580210284Sjmallett } 581210284Sjmallett#endif 582210284Sjmallett if (tskw_cyc > 3) 583210284Sjmallett { 584210284Sjmallett goto TERMINATE; 585210284Sjmallett } 586210284Sjmallett 587210284Sjmallett tbl = 1; // BLEN=2 (ALWAYs for RLDRAM) 588210284Sjmallett //======================================================================= 589210284Sjmallett // RW_DLY = (ROUND_UP{[[(TRL+TBL)*2 + tSKW + BPRCH] + 1] / 2}) - tWL 590210284Sjmallett rw_dly = ((((trl_cyc + tbl) * 2 + tskw_cyc + bprch) + 1) / 2); 591210284Sjmallett if (rw_dly & 1) 592210284Sjmallett { // If it's ODD then round up 593210284Sjmallett rw_dly = rw_dly + 1; 594210284Sjmallett } 595210284Sjmallett rw_dly = rw_dly - twl_cyc +1 ; 596210284Sjmallett if (rw_dly < 0) 597210284Sjmallett { // range check - is it positive 598210284Sjmallett goto TERMINATE; 599210284Sjmallett } 600210284Sjmallett //======================================================================= 601210284Sjmallett // WR_DLY = (ROUND_UP[[(tWL + tBL)*2 - tSKW + FPRCH] / 2]) - tRL 602210284Sjmallett wr_dly = (((twl_cyc + tbl) * 2 - tskw_cyc + fprch) / 2); 603210284Sjmallett if (wr_dly & 1) 604210284Sjmallett { // If it's ODD then round up 605210284Sjmallett wr_dly = wr_dly + 1; 606210284Sjmallett } 607210284Sjmallett wr_dly = wr_dly - trl_cyc + 1; 608210284Sjmallett if (wr_dly < 0) 609210284Sjmallett { // range check - is it positive 610210284Sjmallett goto TERMINATE; 611210284Sjmallett } 612210284Sjmallett 613210284Sjmallett 614210284Sjmallett dfa_memcfg0_base = 0; 615210284Sjmallett dfa_memcfg0_base = ( p0_ena | 616210284Sjmallett (p1_ena << 1) | 617210284Sjmallett (mtype << 3) | 618210284Sjmallett (sil_lat << 4) | 619210284Sjmallett (rw_dly << 6) | 620210284Sjmallett (wr_dly << 10) | 621210284Sjmallett (fprch << 14) | 622210284Sjmallett (bprch << 16) | 623210284Sjmallett (0 << 18) | // BLEN=0(2-burst for RLDRAM) 624210284Sjmallett (pbunk << 19) | 625210284Sjmallett (r2r << 22) | // R2R=1 626210284Sjmallett (clkdiv_enc << 28 ) 627210284Sjmallett ); 628210284Sjmallett 629210284Sjmallett 630210284Sjmallett dfa_memcfg1_base = 0; 631210284Sjmallett dfa_memcfg1_base = ( ref512int | 632210284Sjmallett (tskw_cyc << 4) | 633210284Sjmallett (trl_cyc << 8) | 634210284Sjmallett (twl_cyc << 12) | 635210284Sjmallett (trc_cyc << 16) | 636210284Sjmallett (tmrsc_cyc << 20) 637210284Sjmallett ); 638210284Sjmallett 639210284Sjmallett 640210284Sjmallett 641210284Sjmallett 642210284Sjmallett cfg_ptr->dfa_memcfg0_base = dfa_memcfg0_base; 643210284Sjmallett cfg_ptr->dfa_memcfg1_base = dfa_memcfg1_base; 644210284Sjmallett cfg_ptr->mrs_dat_p0bunk0 = mrs_dat_p0bunk0; 645210284Sjmallett cfg_ptr->mrs_dat_p1bunk0 = mrs_dat_p1bunk0; 646210284Sjmallett cfg_ptr->mrs_dat_p0bunk1 = mrs_dat_p0bunk1; 647210284Sjmallett cfg_ptr->mrs_dat_p1bunk1 = mrs_dat_p1bunk1; 648210284Sjmallett cfg_ptr->p0_ena = p0_ena; 649210284Sjmallett cfg_ptr->p1_ena = p1_ena; 650210284Sjmallett cfg_ptr->bunkport = bunkport; 651210284Sjmallett //======================================================================= 652210284Sjmallett 653210284Sjmallett return(0); 654210284Sjmallett TERMINATE: 655210284Sjmallett return(-1); 656210284Sjmallett 657210284Sjmallett} 658210284Sjmallett 659210284Sjmallett 660210284Sjmallett 661210284Sjmallettstatic uint32_t process_address_map_str(uint32_t mrs_dat, char *addr_str) 662210284Sjmallett{ 663210284Sjmallett int count = 0; 664210284Sjmallett int amap [23]; 665210284Sjmallett uint32_t new_mrs_dat = 0; 666210284Sjmallett 667210284Sjmallett// cvmx_dprintf("mrs_dat: 0x%x, str: %x\n", mrs_dat, addr_str); 668210284Sjmallett char *charptr = strtok(addr_str," "); 669210284Sjmallett while ((charptr != NULL) & (count <= 22)) 670210284Sjmallett { 671210284Sjmallett amap[22-count] = atoi(charptr); // Assign the AMAP Array 672210284Sjmallett charptr = strtok(NULL," "); // Get Next char string (which represents next addr bit mapping) 673210284Sjmallett count++; 674210284Sjmallett } 675210284Sjmallett // Now do the bit swap of MRSDAT (based on address mapping) 676210284Sjmallett uint32_t mrsdat_bit; 677210284Sjmallett for (count=0;count<=22;count++) 678210284Sjmallett { 679210284Sjmallett mrsdat_bit = bit_extract(mrs_dat, count); 680210284Sjmallett new_mrs_dat = bit_insert(mrsdat_bit, amap[count], new_mrs_dat); 681210284Sjmallett } 682210284Sjmallett 683210284Sjmallett return new_mrs_dat; 684210284Sjmallett} 685210284Sjmallett 686210284Sjmallett 687210284Sjmallett//#define PRINT_LLM_CONFIG 688210284Sjmallett#ifdef PRINT_LLM_CONFIG 689210284Sjmallett#define ll_printf printf 690210284Sjmallett#else 691210284Sjmallett#define ll_printf(...) 692210284Sjmallett#define cvmx_csr_db_decode(...) 693210284Sjmallett#endif 694210284Sjmallett 695210284Sjmallettstatic void cn31xx_dfa_memory_init(void) 696210284Sjmallett{ 697210284Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN31XX)) 698210284Sjmallett { 699210284Sjmallett cvmx_dfa_ddr2_cfg_t dfaCfg; 700210284Sjmallett cvmx_dfa_eclkcfg_t dfaEcklCfg; 701210284Sjmallett cvmx_dfa_ddr2_addr_t dfaAddr; 702210284Sjmallett cvmx_dfa_ddr2_tmg_t dfaTmg; 703210284Sjmallett cvmx_dfa_ddr2_pll_t dfaPll; 704210284Sjmallett int mem_freq_hz = 533*1000000; 705210284Sjmallett int ref_freq_hz = cvmx_sysinfo_get()->dfa_ref_clock_hz; 706210284Sjmallett if (!ref_freq_hz) 707210284Sjmallett ref_freq_hz = 33*1000000; 708210284Sjmallett 709210284Sjmallett cvmx_dprintf ("Configuring DFA memory for %d MHz operation.\n",mem_freq_hz/1000000); 710210284Sjmallett 711210284Sjmallett /* Turn on the DFA memory port. */ 712210284Sjmallett dfaCfg.u64 = cvmx_read_csr (CVMX_DFA_DDR2_CFG); 713210284Sjmallett dfaCfg.s.prtena = 1; 714210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); 715210284Sjmallett 716210284Sjmallett /* Start the PLL alignment sequence */ 717210284Sjmallett dfaPll.u64 = 0; 718210284Sjmallett dfaPll.s.pll_ratio = mem_freq_hz/ref_freq_hz /*400Mhz / 33MHz*/; 719210284Sjmallett dfaPll.s.pll_div2 = 1 /*400 - 1 */; 720210284Sjmallett dfaPll.s.pll_bypass = 0; 721210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 722210284Sjmallett 723210284Sjmallett dfaPll.s.pll_init = 1; 724210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 725210284Sjmallett 726210284Sjmallett cvmx_wait (RLD_INIT_DELAY); //want 150uS 727210284Sjmallett dfaPll.s.qdll_ena = 1; 728210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 729210284Sjmallett 730210284Sjmallett cvmx_wait (RLD_INIT_DELAY); //want 10us 731210284Sjmallett dfaEcklCfg.u64 = 0; 732210284Sjmallett dfaEcklCfg.s.dfa_frstn = 1; 733210284Sjmallett cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64); 734210284Sjmallett 735210284Sjmallett /* Configure the DFA Memory */ 736210284Sjmallett dfaCfg.s.silo_hc = 1 /*400 - 1 */; 737210284Sjmallett dfaCfg.s.silo_qc = 0 /*400 - 0 */; 738210284Sjmallett dfaCfg.s.tskw = 1 /*400 - 1 */; 739210284Sjmallett dfaCfg.s.ref_int = 0x820 /*533 - 0x820 400 - 0x618*/; 740210284Sjmallett dfaCfg.s.trfc = 0x1A /*533 - 0x23 400 - 0x1A*/; 741210284Sjmallett dfaCfg.s.fprch = 0; /* 1 more conservative*/ 742210284Sjmallett dfaCfg.s.bprch = 0; /* 1 */ 743210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); 744210284Sjmallett 745210284Sjmallett dfaEcklCfg.u64 = cvmx_read_csr (CVMX_DFA_ECLKCFG); 746210284Sjmallett dfaEcklCfg.s.maxbnk = 1; 747210284Sjmallett cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64); 748210284Sjmallett 749210284Sjmallett dfaAddr.u64 = cvmx_read_csr (CVMX_DFA_DDR2_ADDR); 750210284Sjmallett dfaAddr.s.num_cols = 0x1; 751210284Sjmallett dfaAddr.s.num_colrows = 0x2; 752210284Sjmallett dfaAddr.s.num_rnks = 0x1; 753210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_ADDR, dfaAddr.u64); 754210284Sjmallett 755210284Sjmallett dfaTmg.u64 = cvmx_read_csr (CVMX_DFA_DDR2_TMG); 756210284Sjmallett dfaTmg.s.ddr2t = 0; 757210284Sjmallett dfaTmg.s.tmrd = 0x2; 758210284Sjmallett dfaTmg.s.caslat = 0x4 /*400 - 0x3, 500 - 0x4*/; 759210284Sjmallett dfaTmg.s.pocas = 0; 760210284Sjmallett dfaTmg.s.addlat = 0; 761210284Sjmallett dfaTmg.s.trcd = 4 /*400 - 3, 500 - 4*/; 762210284Sjmallett dfaTmg.s.trrd = 2; 763210284Sjmallett dfaTmg.s.tras = 0xB /*400 - 8, 500 - 0xB*/; 764210284Sjmallett dfaTmg.s.trp = 4 /*400 - 3, 500 - 4*/; 765210284Sjmallett dfaTmg.s.twr = 4 /*400 - 3, 500 - 4*/; 766210284Sjmallett dfaTmg.s.twtr = 2 /*400 - 2 */; 767210284Sjmallett dfaTmg.s.tfaw = 0xE /*400 - 0xA, 500 - 0xE*/; 768210284Sjmallett dfaTmg.s.r2r_slot = 0; 769210284Sjmallett dfaTmg.s.dic = 0; /*400 - 0 */ 770210284Sjmallett dfaTmg.s.dqsn_ena = 0; 771210284Sjmallett dfaTmg.s.odt_rtt = 0; 772210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_TMG, dfaTmg.u64); 773210284Sjmallett 774210284Sjmallett /* Turn on the DDR2 interface and wait a bit for the hardware to setup. */ 775210284Sjmallett dfaCfg.s.init = 1; 776210284Sjmallett cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); 777210284Sjmallett cvmx_wait(RLD_INIT_DELAY); // want at least 64K cycles 778210284Sjmallett } 779210284Sjmallett} 780210284Sjmallett 781210284Sjmallettvoid write_rld_cfg(rldram_csr_config_t *cfg_ptr) 782210284Sjmallett{ 783210284Sjmallett cvmx_dfa_memcfg0_t memcfg0; 784210284Sjmallett cvmx_dfa_memcfg2_t memcfg2; 785210284Sjmallett 786210284Sjmallett memcfg0.u64 = cfg_ptr->dfa_memcfg0_base; 787210284Sjmallett 788210284Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 789210284Sjmallett { 790210284Sjmallett uint32_t dfa_memcfg0; 791210284Sjmallett 792210284Sjmallett if (OCTEON_IS_MODEL (OCTEON_CN58XX)) { 793210284Sjmallett // Set RLDQK90_RST and RDLCK_RST to reset all three DLLs. 794210284Sjmallett memcfg0.s.rldck_rst = 1; 795210284Sjmallett memcfg0.s.rldqck90_rst = 1; 796210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64); 797210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x clk/qk90 reset\n", (uint32_t) memcfg0.u64); 798210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64); 799210284Sjmallett 800210284Sjmallett // Clear RDLCK_RST while asserting RLDQK90_RST to bring RLDCK DLL out of reset. 801210284Sjmallett memcfg0.s.rldck_rst = 0; 802210284Sjmallett memcfg0.s.rldqck90_rst = 1; 803210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64); 804210284Sjmallett cvmx_wait(4000000); /* Wait */ 805210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x qk90 reset\n", (uint32_t) memcfg0.u64); 806210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64); 807210284Sjmallett 808210284Sjmallett // Clear both RDLCK90_RST and RLDQK90_RST to bring the RLDQK90 DLL out of reset. 809210284Sjmallett memcfg0.s.rldck_rst = 0; 810210284Sjmallett memcfg0.s.rldqck90_rst = 0; 811210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64); 812210284Sjmallett cvmx_wait(4000000); /* Wait */ 813210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x DLL out of reset\n", (uint32_t) memcfg0.u64); 814210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64); 815210284Sjmallett } 816210284Sjmallett 817210284Sjmallett //======================================================================= 818210284Sjmallett // Now print out the sequence of events: 819210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base); 820210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x port enables\n", cfg_ptr->dfa_memcfg0_base); 821210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base); 822210284Sjmallett cvmx_wait(4000000); /* Wait */ 823210284Sjmallett 824210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG1, cfg_ptr->dfa_memcfg1_base); 825210284Sjmallett ll_printf("CVMX_DFA_MEMCFG1: 0x%08x\n", cfg_ptr->dfa_memcfg1_base); 826210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG1 & ~(1ull<<63), cfg_ptr->dfa_memcfg1_base); 827210284Sjmallett 828210284Sjmallett if (cfg_ptr->p0_ena ==1) 829210284Sjmallett { 830210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p0bunk0); 831210284Sjmallett ll_printf("CVMX_DFA_MEMRLD : 0x%08x p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk0); 832210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk0); 833210284Sjmallett 834210284Sjmallett dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base | 835210284Sjmallett (1 << 23) | // P0_INIT 836210284Sjmallett (1 << 25) // BUNK_INIT[1:0]=Bunk#0 837210284Sjmallett ); 838210284Sjmallett 839210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); 840210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p0_init/bunk_init\n", dfa_memcfg0); 841210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0); 842210284Sjmallett cvmx_wait(RLD_INIT_DELAY); 843210284Sjmallett ll_printf("Delay.....\n"); 844210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base); 845210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x back to base\n", cfg_ptr->dfa_memcfg0_base); 846210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base); 847210284Sjmallett } 848210284Sjmallett 849210284Sjmallett if (cfg_ptr->p1_ena ==1) 850210284Sjmallett { 851210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p1bunk0); 852210284Sjmallett ll_printf("CVMX_DFA_MEMRLD : 0x%08x p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk0); 853210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk0); 854210284Sjmallett 855210284Sjmallett dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base | 856210284Sjmallett (1 << 24) | // P1_INIT 857210284Sjmallett (1 << 25) // BUNK_INIT[1:0]=Bunk#0 858210284Sjmallett ); 859210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); 860210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p1_init/bunk_init\n", dfa_memcfg0); 861210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0); 862210284Sjmallett cvmx_wait(RLD_INIT_DELAY); 863210284Sjmallett ll_printf("Delay.....\n"); 864210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base); 865210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x back to base\n", cfg_ptr->dfa_memcfg0_base); 866210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base); 867210284Sjmallett } 868210284Sjmallett 869210284Sjmallett // P0 Bunk#1 870210284Sjmallett if ((cfg_ptr->p0_ena ==1) && (cfg_ptr->bunkport == 2)) 871210284Sjmallett { 872210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p0bunk1); 873210284Sjmallett ll_printf("CVMX_DFA_MEMRLD : 0x%08x p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk1); 874210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk1); 875210284Sjmallett 876210284Sjmallett dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base | 877210284Sjmallett (1 << 23) | // P0_INIT 878210284Sjmallett (2 << 25) // BUNK_INIT[1:0]=Bunk#1 879210284Sjmallett ); 880210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); 881210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p0_init/bunk_init\n", dfa_memcfg0); 882210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0); 883210284Sjmallett cvmx_wait(RLD_INIT_DELAY); 884210284Sjmallett ll_printf("Delay.....\n"); 885210284Sjmallett 886210284Sjmallett if (cfg_ptr->p1_ena == 1) 887210284Sjmallett { // Re-arm Px_INIT if P1-B1 init is required 888210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base); 889210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x px_init rearm\n", cfg_ptr->dfa_memcfg0_base); 890210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base); 891210284Sjmallett } 892210284Sjmallett } 893210284Sjmallett 894210284Sjmallett if ((cfg_ptr->p1_ena == 1) && (cfg_ptr->bunkport == 2)) 895210284Sjmallett { 896210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p1bunk1); 897210284Sjmallett ll_printf("CVMX_DFA_MEMRLD : 0x%08x p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk1); 898210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk1); 899210284Sjmallett 900210284Sjmallett dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base | 901210284Sjmallett (1 << 24) | // P1_INIT 902210284Sjmallett (2 << 25) // BUNK_INIT[1:0]=10 903210284Sjmallett ); 904210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); 905210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p1_init/bunk_init\n", dfa_memcfg0); 906210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0); 907210284Sjmallett } 908210284Sjmallett cvmx_wait(4000000); // 1/100S, 0.01S, 10mS 909210284Sjmallett ll_printf("Delay.....\n"); 910210284Sjmallett 911210284Sjmallett /* Enable bunks */ 912210284Sjmallett dfa_memcfg0 = cfg_ptr->dfa_memcfg0_base |((cfg_ptr->bunkport >= 1) << 25) | ((cfg_ptr->bunkport == 2) << 26); 913210284Sjmallett cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); 914210284Sjmallett ll_printf("CVMX_DFA_MEMCFG0: 0x%08x enable bunks\n", dfa_memcfg0); 915210284Sjmallett cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0); 916210284Sjmallett cvmx_wait(RLD_INIT_DELAY); 917210284Sjmallett ll_printf("Delay.....\n"); 918210284Sjmallett 919210284Sjmallett /* Issue a Silo reset by toggling SILRST in memcfg2. */ 920210284Sjmallett memcfg2.u64 = cvmx_read_csr (CVMX_DFA_MEMCFG2); 921210284Sjmallett memcfg2.s.silrst = 1; 922210284Sjmallett cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64); 923210284Sjmallett ll_printf("CVMX_DFA_MEMCFG2: 0x%08x silo reset start\n", (uint32_t) memcfg2.u64); 924210284Sjmallett memcfg2.s.silrst = 0; 925210284Sjmallett cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64); 926210284Sjmallett ll_printf("CVMX_DFA_MEMCFG2: 0x%08x silo reset done\n", (uint32_t) memcfg2.u64); 927210284Sjmallett } 928210284Sjmallett} 929210284Sjmallett 930