1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-l2t-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon l2t. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_L2T_DEFS_H__ 53232812Sjmallett#define __CVMX_L2T_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_L2T_ERR_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 60215976Sjmallett cvmx_warn("CVMX_L2T_ERR not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180080000008ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 65215976Sjmallett#endif 66215976Sjmallett 67215976Sjmallett/** 68215976Sjmallett * cvmx_l2t_err 69215976Sjmallett * 70215976Sjmallett * L2T_ERR = L2 Tag Errors 71215976Sjmallett * 72215976Sjmallett * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable 73215976Sjmallett */ 74232812Sjmallettunion cvmx_l2t_err { 75215976Sjmallett uint64_t u64; 76232812Sjmallett struct cvmx_l2t_err_s { 77232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 78215976Sjmallett uint64_t reserved_29_63 : 35; 79215976Sjmallett uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10]) 80215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 81215976Sjmallett the FADRU contains the upper(MSB bit) cacheline index 82215976Sjmallett into the L2 Tag Store. */ 83215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 84215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 85215976Sjmallett could not find an available/unlocked set (for 86215976Sjmallett replacement). 87215976Sjmallett Most likely, this is a result of SW mixing SET 88215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 89215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 90215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 91215976Sjmallett to determine a 'valid' replacement set (since LOCKED 92215976Sjmallett addresses should NEVER be replaced). 93215976Sjmallett If such an event occurs, the HW will select the smallest 94215976Sjmallett available SET(specified by UMSK'x)' as the replacement 95215976Sjmallett set, and the address is unlocked. */ 96215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 97215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 98215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 99215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 100215976Sjmallett successfully, however the address is NOT locked. 101215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 102215976Sjmallett into account. For example, if diagnostic PPx has 103215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 104215976Sjmallett been previously LOCKED, then an attempt to LOCK the 105215976Sjmallett last available SET0 would result in a LCKERR. (This 106215976Sjmallett is to ensure that at least 1 SET at each INDEX is 107215976Sjmallett not LOCKED for general use by other PPs). */ 108215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 109215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 110215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 111215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 112215976Sjmallett is specified by the L2C_DBG[SET]. */ 113215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 114215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 115215976Sjmallett the FADR contains the lower 10bit cacheline index 116215976Sjmallett into the L2 Tag Store. */ 117215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 118215976Sjmallett the contents of this register contain the 6-bit 119215976Sjmallett syndrome for the hit set only. 120215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 121215976Sjmallett the "non-hit" sets at the failing index(FADR). 122215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 123215976Sjmallett is specified by the L2C_DBG[SET]. 124215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 125215976Sjmallett hit set at the failing index(FADR) and failing 126215976Sjmallett set(FSET). 127215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 128215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 129215976Sjmallett read the other sets at the failing index(FADR). When 130215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 131215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 132215976Sjmallett SYNDROME and FADR). */ 133215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 134215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 135215976Sjmallett given index) are checked for double bit errors(DBEs). 136215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 137215976Sjmallett DBEs also generated an interrupt(if enabled). */ 138215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 139215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 140215976Sjmallett given index) are checked for single bit errors(SBEs). 141215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 142215976Sjmallett SBEs are auto corrected in HW and generate an 143215976Sjmallett interrupt(if enabled). */ 144215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 145215976Sjmallett Enable bit. When set, allows interrupts to be 146215976Sjmallett reported on double bit (uncorrectable) errors from 147215976Sjmallett the L2 Tag Arrays. */ 148215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 149215976Sjmallett Enable bit. When set, allows interrupts to be 150215976Sjmallett reported on single bit (correctable) errors from 151215976Sjmallett the L2 Tag Arrays. */ 152215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 153215976Sjmallett When set, enables 6-bit SEC/DED codeword for 19-bit 154215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:18]] */ 155215976Sjmallett#else 156215976Sjmallett uint64_t ecc_ena : 1; 157215976Sjmallett uint64_t sec_intena : 1; 158215976Sjmallett uint64_t ded_intena : 1; 159215976Sjmallett uint64_t sec_err : 1; 160215976Sjmallett uint64_t ded_err : 1; 161215976Sjmallett uint64_t fsyn : 6; 162215976Sjmallett uint64_t fadr : 10; 163215976Sjmallett uint64_t fset : 3; 164215976Sjmallett uint64_t lckerr : 1; 165215976Sjmallett uint64_t lck_intena : 1; 166215976Sjmallett uint64_t lckerr2 : 1; 167215976Sjmallett uint64_t lck_intena2 : 1; 168215976Sjmallett uint64_t fadru : 1; 169215976Sjmallett uint64_t reserved_29_63 : 35; 170215976Sjmallett#endif 171215976Sjmallett } s; 172232812Sjmallett struct cvmx_l2t_err_cn30xx { 173232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 174215976Sjmallett uint64_t reserved_28_63 : 36; 175215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 176215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 177215976Sjmallett could not find an available/unlocked set (for 178215976Sjmallett replacement). 179215976Sjmallett Most likely, this is a result of SW mixing SET 180215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 181215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 182215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 183215976Sjmallett to determine a 'valid' replacement set (since LOCKED 184215976Sjmallett addresses should NEVER be replaced). 185215976Sjmallett If such an event occurs, the HW will select the smallest 186215976Sjmallett available SET(specified by UMSK'x)' as the replacement 187215976Sjmallett set, and the address is unlocked. */ 188215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 189215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 190215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 191215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is 192215976Sjmallett completed successfully, however the address is NOT 193215976Sjmallett locked. 194215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 195215976Sjmallett into account. For example, if diagnostic PPx has 196215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 197215976Sjmallett been previously LOCKED, then an attempt to LOCK the 198215976Sjmallett last available SET0 would result in a LCKERR. (This 199215976Sjmallett is to ensure that at least 1 SET at each INDEX is 200215976Sjmallett not LOCKED for general use by other PPs). */ 201215976Sjmallett uint64_t reserved_23_23 : 1; 202215976Sjmallett uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 203215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 204215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 205215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 206215976Sjmallett is specified by the L2C_DBG[SET]. */ 207215976Sjmallett uint64_t reserved_19_20 : 2; 208215976Sjmallett uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit) 209215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 210215976Sjmallett the FADR contains the 8bit cacheline index into the 211215976Sjmallett L2 Tag Store. */ 212215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 213215976Sjmallett the contents of this register contain the 6-bit 214215976Sjmallett syndrome for the hit set only. 215215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 216215976Sjmallett the "non-hit" sets at the failing index(FADR). 217215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 218215976Sjmallett is specified by the L2C_DBG[SET]. 219215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 220215976Sjmallett hit set at the failing index(FADR) and failing 221215976Sjmallett set(FSET). 222215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 223215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 224215976Sjmallett read the other sets at the failing index(FADR). When 225215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 226215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 227215976Sjmallett SYNDROME and FADR). */ 228215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 229215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 230215976Sjmallett given index) are checked for double bit errors(DBEs). 231215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 232215976Sjmallett DBEs also generated an interrupt(if enabled). */ 233215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 234215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 235215976Sjmallett given index) are checked for single bit errors(SBEs). 236215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 237215976Sjmallett SBEs are auto corrected in HW and generate an 238215976Sjmallett interrupt(if enabled). */ 239215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 240215976Sjmallett Enable bit. When set, allows interrupts to be 241215976Sjmallett reported on double bit (uncorrectable) errors from 242215976Sjmallett the L2 Tag Arrays. */ 243215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 244215976Sjmallett Enable bit. When set, allows interrupts to be 245215976Sjmallett reported on single bit (correctable) errors from 246215976Sjmallett the L2 Tag Arrays. */ 247215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 248215976Sjmallett When set, enables 6-bit SEC/DED codeword for 22-bit 249215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:15]] */ 250215976Sjmallett#else 251215976Sjmallett uint64_t ecc_ena : 1; 252215976Sjmallett uint64_t sec_intena : 1; 253215976Sjmallett uint64_t ded_intena : 1; 254215976Sjmallett uint64_t sec_err : 1; 255215976Sjmallett uint64_t ded_err : 1; 256215976Sjmallett uint64_t fsyn : 6; 257215976Sjmallett uint64_t fadr : 8; 258215976Sjmallett uint64_t reserved_19_20 : 2; 259215976Sjmallett uint64_t fset : 2; 260215976Sjmallett uint64_t reserved_23_23 : 1; 261215976Sjmallett uint64_t lckerr : 1; 262215976Sjmallett uint64_t lck_intena : 1; 263215976Sjmallett uint64_t lckerr2 : 1; 264215976Sjmallett uint64_t lck_intena2 : 1; 265215976Sjmallett uint64_t reserved_28_63 : 36; 266215976Sjmallett#endif 267215976Sjmallett } cn30xx; 268232812Sjmallett struct cvmx_l2t_err_cn31xx { 269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 270215976Sjmallett uint64_t reserved_28_63 : 36; 271215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 272215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 273215976Sjmallett could not find an available/unlocked set (for 274215976Sjmallett replacement). 275215976Sjmallett Most likely, this is a result of SW mixing SET 276215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 277215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 278215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 279215976Sjmallett to determine a 'valid' replacement set (since LOCKED 280215976Sjmallett addresses should NEVER be replaced). 281215976Sjmallett If such an event occurs, the HW will select the smallest 282215976Sjmallett available SET(specified by UMSK'x)' as the replacement 283215976Sjmallett set, and the address is unlocked. */ 284215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 285215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 286215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 287215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 288215976Sjmallett successfully, however the address is NOT locked. 289215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 290215976Sjmallett into account. For example, if diagnostic PPx has 291215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 292215976Sjmallett been previously LOCKED, then an attempt to LOCK the 293215976Sjmallett last available SET0 would result in a LCKERR. (This 294215976Sjmallett is to ensure that at least 1 SET at each INDEX is 295215976Sjmallett not LOCKED for general use by other PPs). */ 296215976Sjmallett uint64_t reserved_23_23 : 1; 297215976Sjmallett uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 298215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 299215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 300215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 301215976Sjmallett is specified by the L2C_DBG[SET]. */ 302215976Sjmallett uint64_t reserved_20_20 : 1; 303215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 304215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 305215976Sjmallett the FADR contains the 9-bit cacheline index into the 306215976Sjmallett L2 Tag Store. */ 307215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 308215976Sjmallett the contents of this register contain the 6-bit 309215976Sjmallett syndrome for the hit set only. 310215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 311215976Sjmallett the "non-hit" sets at the failing index(FADR). 312215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 313215976Sjmallett is specified by the L2C_DBG[SET]. 314215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 315215976Sjmallett hit set at the failing index(FADR) and failing 316215976Sjmallett set(FSET). 317215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 318215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 319215976Sjmallett read the other sets at the failing index(FADR). When 320215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 321215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 322215976Sjmallett SYNDROME and FADR). */ 323215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 324215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 325215976Sjmallett given index) are checked for double bit errors(DBEs). 326215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 327215976Sjmallett DBEs also generated an interrupt(if enabled). */ 328215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 329215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 330215976Sjmallett given index) are checked for single bit errors(SBEs). 331215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 332215976Sjmallett SBEs are auto corrected in HW and generate an 333215976Sjmallett interrupt(if enabled). */ 334215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 335215976Sjmallett Enable bit. When set, allows interrupts to be 336215976Sjmallett reported on double bit (uncorrectable) errors from 337215976Sjmallett the L2 Tag Arrays. */ 338215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 339215976Sjmallett Enable bit. When set, allows interrupts to be 340215976Sjmallett reported on single bit (correctable) errors from 341215976Sjmallett the L2 Tag Arrays. */ 342215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 343215976Sjmallett When set, enables 6-bit SEC/DED codeword for 21-bit 344215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:16]] */ 345215976Sjmallett#else 346215976Sjmallett uint64_t ecc_ena : 1; 347215976Sjmallett uint64_t sec_intena : 1; 348215976Sjmallett uint64_t ded_intena : 1; 349215976Sjmallett uint64_t sec_err : 1; 350215976Sjmallett uint64_t ded_err : 1; 351215976Sjmallett uint64_t fsyn : 6; 352215976Sjmallett uint64_t fadr : 9; 353215976Sjmallett uint64_t reserved_20_20 : 1; 354215976Sjmallett uint64_t fset : 2; 355215976Sjmallett uint64_t reserved_23_23 : 1; 356215976Sjmallett uint64_t lckerr : 1; 357215976Sjmallett uint64_t lck_intena : 1; 358215976Sjmallett uint64_t lckerr2 : 1; 359215976Sjmallett uint64_t lck_intena2 : 1; 360215976Sjmallett uint64_t reserved_28_63 : 36; 361215976Sjmallett#endif 362215976Sjmallett } cn31xx; 363232812Sjmallett struct cvmx_l2t_err_cn38xx { 364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 365215976Sjmallett uint64_t reserved_28_63 : 36; 366215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 367215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 368215976Sjmallett could not find an available/unlocked set (for 369215976Sjmallett replacement). 370215976Sjmallett Most likely, this is a result of SW mixing SET 371215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 372215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 373215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 374215976Sjmallett to determine a 'valid' replacement set (since LOCKED 375215976Sjmallett addresses should NEVER be replaced). 376215976Sjmallett If such an event occurs, the HW will select the smallest 377215976Sjmallett available SET(specified by UMSK'x)' as the replacement 378215976Sjmallett set, and the address is unlocked. */ 379215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 380215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 381215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 382215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 383215976Sjmallett successfully, however the address is NOT locked. 384215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 385215976Sjmallett into account. For example, if diagnostic PPx has 386215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 387215976Sjmallett been previously LOCKED, then an attempt to LOCK the 388215976Sjmallett last available SET0 would result in a LCKERR. (This 389215976Sjmallett is to ensure that at least 1 SET at each INDEX is 390215976Sjmallett not LOCKED for general use by other PPs). */ 391215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 392215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 393215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 394215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 395215976Sjmallett is specified by the L2C_DBG[SET]. */ 396215976Sjmallett uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 397215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 398215976Sjmallett the FADR contains the 10bit cacheline index into the 399215976Sjmallett L2 Tag Store. */ 400215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 401215976Sjmallett the contents of this register contain the 6-bit 402215976Sjmallett syndrome for the hit set only. 403215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 404215976Sjmallett the "non-hit" sets at the failing index(FADR). 405215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 406215976Sjmallett is specified by the L2C_DBG[SET]. 407215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 408215976Sjmallett hit set at the failing index(FADR) and failing 409215976Sjmallett set(FSET). 410215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 411215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 412215976Sjmallett read the other sets at the failing index(FADR). When 413215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 414215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 415215976Sjmallett SYNDROME and FADR). */ 416215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 417215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 418215976Sjmallett given index) are checked for double bit errors(DBEs). 419215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 420215976Sjmallett DBEs also generated an interrupt(if enabled). */ 421215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 422215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 423215976Sjmallett given index) are checked for single bit errors(SBEs). 424215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 425215976Sjmallett SBEs are auto corrected in HW and generate an 426215976Sjmallett interrupt(if enabled). */ 427215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 428215976Sjmallett Enable bit. When set, allows interrupts to be 429215976Sjmallett reported on double bit (uncorrectable) errors from 430215976Sjmallett the L2 Tag Arrays. */ 431215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 432215976Sjmallett Enable bit. When set, allows interrupts to be 433215976Sjmallett reported on single bit (correctable) errors from 434215976Sjmallett the L2 Tag Arrays. */ 435215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 436215976Sjmallett When set, enables 6-bit SEC/DED codeword for 20-bit 437215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:17]] */ 438215976Sjmallett#else 439215976Sjmallett uint64_t ecc_ena : 1; 440215976Sjmallett uint64_t sec_intena : 1; 441215976Sjmallett uint64_t ded_intena : 1; 442215976Sjmallett uint64_t sec_err : 1; 443215976Sjmallett uint64_t ded_err : 1; 444215976Sjmallett uint64_t fsyn : 6; 445215976Sjmallett uint64_t fadr : 10; 446215976Sjmallett uint64_t fset : 3; 447215976Sjmallett uint64_t lckerr : 1; 448215976Sjmallett uint64_t lck_intena : 1; 449215976Sjmallett uint64_t lckerr2 : 1; 450215976Sjmallett uint64_t lck_intena2 : 1; 451215976Sjmallett uint64_t reserved_28_63 : 36; 452215976Sjmallett#endif 453215976Sjmallett } cn38xx; 454215976Sjmallett struct cvmx_l2t_err_cn38xx cn38xxp2; 455232812Sjmallett struct cvmx_l2t_err_cn50xx { 456232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 457215976Sjmallett uint64_t reserved_28_63 : 36; 458215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 459215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 460215976Sjmallett could not find an available/unlocked set (for 461215976Sjmallett replacement). 462215976Sjmallett Most likely, this is a result of SW mixing SET 463215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 464215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 465215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 466215976Sjmallett to determine a 'valid' replacement set (since LOCKED 467215976Sjmallett addresses should NEVER be replaced). 468215976Sjmallett If such an event occurs, the HW will select the smallest 469215976Sjmallett available SET(specified by UMSK'x)' as the replacement 470215976Sjmallett set, and the address is unlocked. */ 471215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 472215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 473215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 474215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 475215976Sjmallett successfully, however the address is NOT locked. 476215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 477215976Sjmallett into account. For example, if diagnostic PPx has 478215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 479215976Sjmallett been previously LOCKED, then an attempt to LOCK the 480215976Sjmallett last available SET0 would result in a LCKERR. (This 481215976Sjmallett is to ensure that at least 1 SET at each INDEX is 482215976Sjmallett not LOCKED for general use by other PPs). */ 483215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 484215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 485215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 486215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 487215976Sjmallett is specified by the L2C_DBG[SET]. */ 488215976Sjmallett uint64_t reserved_18_20 : 3; 489215976Sjmallett uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index) 490215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 491215976Sjmallett the FADR contains the lower 7bit cacheline index 492215976Sjmallett into the L2 Tag Store. */ 493215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 494215976Sjmallett the contents of this register contain the 6-bit 495215976Sjmallett syndrome for the hit set only. 496215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 497215976Sjmallett the "non-hit" sets at the failing index(FADR). 498215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 499215976Sjmallett is specified by the L2C_DBG[SET]. 500215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 501215976Sjmallett hit set at the failing index(FADR) and failing 502215976Sjmallett set(FSET). 503215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 504215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 505215976Sjmallett read the other sets at the failing index(FADR). When 506215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 507215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 508215976Sjmallett SYNDROME and FADR). */ 509215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 510215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 511215976Sjmallett given index) are checked for double bit errors(DBEs). 512215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 513215976Sjmallett DBEs also generated an interrupt(if enabled). */ 514215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 515215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 516215976Sjmallett given index) are checked for single bit errors(SBEs). 517215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 518215976Sjmallett SBEs are auto corrected in HW and generate an 519215976Sjmallett interrupt(if enabled). */ 520215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 521215976Sjmallett Enable bit. When set, allows interrupts to be 522215976Sjmallett reported on double bit (uncorrectable) errors from 523215976Sjmallett the L2 Tag Arrays. */ 524215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 525215976Sjmallett Enable bit. When set, allows interrupts to be 526215976Sjmallett reported on single bit (correctable) errors from 527215976Sjmallett the L2 Tag Arrays. */ 528215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 529215976Sjmallett When set, enables 6-bit SEC/DED codeword for 23-bit 530215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:14]] */ 531215976Sjmallett#else 532215976Sjmallett uint64_t ecc_ena : 1; 533215976Sjmallett uint64_t sec_intena : 1; 534215976Sjmallett uint64_t ded_intena : 1; 535215976Sjmallett uint64_t sec_err : 1; 536215976Sjmallett uint64_t ded_err : 1; 537215976Sjmallett uint64_t fsyn : 6; 538215976Sjmallett uint64_t fadr : 7; 539215976Sjmallett uint64_t reserved_18_20 : 3; 540215976Sjmallett uint64_t fset : 3; 541215976Sjmallett uint64_t lckerr : 1; 542215976Sjmallett uint64_t lck_intena : 1; 543215976Sjmallett uint64_t lckerr2 : 1; 544215976Sjmallett uint64_t lck_intena2 : 1; 545215976Sjmallett uint64_t reserved_28_63 : 36; 546215976Sjmallett#endif 547215976Sjmallett } cn50xx; 548232812Sjmallett struct cvmx_l2t_err_cn52xx { 549232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 550215976Sjmallett uint64_t reserved_28_63 : 36; 551215976Sjmallett uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 552215976Sjmallett uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 553215976Sjmallett could not find an available/unlocked set (for 554215976Sjmallett replacement). 555215976Sjmallett Most likely, this is a result of SW mixing SET 556215976Sjmallett PARTITIONING with ADDRESS LOCKING. If SW allows 557215976Sjmallett another PP to LOCKDOWN all SETs available to PP#n, 558215976Sjmallett then a Rd/Wr Miss from PP#n will be unable 559215976Sjmallett to determine a 'valid' replacement set (since LOCKED 560215976Sjmallett addresses should NEVER be replaced). 561215976Sjmallett If such an event occurs, the HW will select the smallest 562215976Sjmallett available SET(specified by UMSK'x)' as the replacement 563215976Sjmallett set, and the address is unlocked. */ 564215976Sjmallett uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 565215976Sjmallett uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 566215976Sjmallett the INDEX (which is ignored by HW - but reported to SW). 567215976Sjmallett The LDD(L1 load-miss) for the LOCK operation is completed 568215976Sjmallett successfully, however the address is NOT locked. 569215976Sjmallett NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 570215976Sjmallett into account. For example, if diagnostic PPx has 571215976Sjmallett UMSKx defined to only use SETs [1:0], and SET1 had 572215976Sjmallett been previously LOCKED, then an attempt to LOCK the 573215976Sjmallett last available SET0 would result in a LCKERR. (This 574215976Sjmallett is to ensure that at least 1 SET at each INDEX is 575215976Sjmallett not LOCKED for general use by other PPs). */ 576215976Sjmallett uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 577215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 578215976Sjmallett (FSYN != 0), the FSET specifies the failing hit-set. 579215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 580215976Sjmallett is specified by the L2C_DBG[SET]. */ 581215976Sjmallett uint64_t reserved_20_20 : 1; 582215976Sjmallett uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 583215976Sjmallett When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 584215976Sjmallett the FADR contains the lower 9bit cacheline index 585215976Sjmallett into the L2 Tag Store. */ 586215976Sjmallett uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 587215976Sjmallett the contents of this register contain the 6-bit 588215976Sjmallett syndrome for the hit set only. 589215976Sjmallett If (FSYN = 0), the SBE or DBE reported was for one of 590215976Sjmallett the "non-hit" sets at the failing index(FADR). 591215976Sjmallett NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 592215976Sjmallett is specified by the L2C_DBG[SET]. 593215976Sjmallett If (FSYN != 0), the SBE or DBE reported was for the 594215976Sjmallett hit set at the failing index(FADR) and failing 595215976Sjmallett set(FSET). 596215976Sjmallett SW NOTE: To determine which "non-hit" set was in error, 597215976Sjmallett SW can use the L2C_DBG[L2T] debug feature to explicitly 598215976Sjmallett read the other sets at the failing index(FADR). When 599215976Sjmallett (FSYN !=0), then the FSET contains the failing hit-set. 600215976Sjmallett NOTE: A DED Error will always overwrite a SEC Error 601215976Sjmallett SYNDROME and FADR). */ 602215976Sjmallett uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 603215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 604215976Sjmallett given index) are checked for double bit errors(DBEs). 605215976Sjmallett This bit is set if ANY of the 8 sets contains a DBE. 606215976Sjmallett DBEs also generated an interrupt(if enabled). */ 607215976Sjmallett uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 608215976Sjmallett During every L2 Tag Probe, all 8 sets Tag's (at a 609215976Sjmallett given index) are checked for single bit errors(SBEs). 610215976Sjmallett This bit is set if ANY of the 8 sets contains an SBE. 611215976Sjmallett SBEs are auto corrected in HW and generate an 612215976Sjmallett interrupt(if enabled). */ 613215976Sjmallett uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 614215976Sjmallett Enable bit. When set, allows interrupts to be 615215976Sjmallett reported on double bit (uncorrectable) errors from 616215976Sjmallett the L2 Tag Arrays. */ 617215976Sjmallett uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 618215976Sjmallett Enable bit. When set, allows interrupts to be 619215976Sjmallett reported on single bit (correctable) errors from 620215976Sjmallett the L2 Tag Arrays. */ 621215976Sjmallett uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 622215976Sjmallett When set, enables 6-bit SEC/DED codeword for 21-bit 623215976Sjmallett L2 Tag Arrays [V,D,L,TAG[33:16]] */ 624215976Sjmallett#else 625215976Sjmallett uint64_t ecc_ena : 1; 626215976Sjmallett uint64_t sec_intena : 1; 627215976Sjmallett uint64_t ded_intena : 1; 628215976Sjmallett uint64_t sec_err : 1; 629215976Sjmallett uint64_t ded_err : 1; 630215976Sjmallett uint64_t fsyn : 6; 631215976Sjmallett uint64_t fadr : 9; 632215976Sjmallett uint64_t reserved_20_20 : 1; 633215976Sjmallett uint64_t fset : 3; 634215976Sjmallett uint64_t lckerr : 1; 635215976Sjmallett uint64_t lck_intena : 1; 636215976Sjmallett uint64_t lckerr2 : 1; 637215976Sjmallett uint64_t lck_intena2 : 1; 638215976Sjmallett uint64_t reserved_28_63 : 36; 639215976Sjmallett#endif 640215976Sjmallett } cn52xx; 641215976Sjmallett struct cvmx_l2t_err_cn52xx cn52xxp1; 642215976Sjmallett struct cvmx_l2t_err_s cn56xx; 643215976Sjmallett struct cvmx_l2t_err_s cn56xxp1; 644215976Sjmallett struct cvmx_l2t_err_s cn58xx; 645215976Sjmallett struct cvmx_l2t_err_s cn58xxp1; 646215976Sjmallett}; 647215976Sjmalletttypedef union cvmx_l2t_err cvmx_l2t_err_t; 648215976Sjmallett 649215976Sjmallett#endif 650