1210284Sjmallett/***********************license start***************
2232812Sjmallett * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
3215990Sjmallett * reserved.
4210284Sjmallett *
5210284Sjmallett *
6215990Sjmallett * Redistribution and use in source and binary forms, with or without
7215990Sjmallett * modification, are permitted provided that the following conditions are
8215990Sjmallett * met:
9210284Sjmallett *
10215990Sjmallett *   * Redistributions of source code must retain the above copyright
11215990Sjmallett *     notice, this list of conditions and the following disclaimer.
12210284Sjmallett *
13215990Sjmallett *   * Redistributions in binary form must reproduce the above
14215990Sjmallett *     copyright notice, this list of conditions and the following
15215990Sjmallett *     disclaimer in the documentation and/or other materials provided
16215990Sjmallett *     with the distribution.
17215990Sjmallett
18232812Sjmallett *   * Neither the name of Cavium Inc. nor the names of
19215990Sjmallett *     its contributors may be used to endorse or promote products
20215990Sjmallett *     derived from this software without specific prior written
21215990Sjmallett *     permission.
22215990Sjmallett
23215990Sjmallett * This Software, including technical data, may be subject to U.S. export  control
24215990Sjmallett * laws, including the U.S. Export Administration Act and its  associated
25215990Sjmallett * regulations, and may be subject to export or import  regulations in other
26215990Sjmallett * countries.
27215990Sjmallett
28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38210284Sjmallett ***********************license end**************************************/
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45215990Sjmallett
46210284Sjmallett/**
47210284Sjmallett * @file
48210284Sjmallett *
49210284Sjmallett * Interface to the Mips interrupts.
50210284Sjmallett *
51232812Sjmallett * <hr>$Revision: 70030 $<hr>
52210284Sjmallett */
53210284Sjmallett#ifndef __CVMX_INTERRUPT_H__
54210284Sjmallett#define __CVMX_INTERRUPT_H__
55210284Sjmallett
56232812Sjmallett#ifdef  __cplusplus
57210284Sjmallettextern "C" {
58210284Sjmallett#endif
59210284Sjmallett
60210284Sjmallett/**
61210284Sjmallett * Enumeration of Interrupt numbers
62210284Sjmallett */
63210284Sjmalletttypedef enum
64210284Sjmallett{
65210284Sjmallett    /* 0 - 7 represent the 8 MIPS standard interrupt sources */
66210284Sjmallett    CVMX_IRQ_SW0        = 0,
67232812Sjmallett    CVMX_IRQ_SW1,
68232812Sjmallett    CVMX_IRQ_MIPS2,
69232812Sjmallett    CVMX_IRQ_MIPS3,
70232812Sjmallett    CVMX_IRQ_MIPS4,
71232812Sjmallett    CVMX_IRQ_MIPS5,
72232812Sjmallett    CVMX_IRQ_MIPS6,
73232812Sjmallett    CVMX_IRQ_MIPS7,
74232812Sjmallett    /* 64 WORKQ interrupts. */
75232812Sjmallett    CVMX_IRQ_WORKQ0,
76232812Sjmallett    /* 16 GPIO interrupts. */
77232812Sjmallett    CVMX_IRQ_GPIO0      = CVMX_IRQ_WORKQ0 + 64,
78232812Sjmallett    /* 4  MBOX interrupts. */
79232812Sjmallett    CVMX_IRQ_MBOX0      = CVMX_IRQ_GPIO0 + 16,
80232812Sjmallett    /* 3  UART interrupts. */
81232812Sjmallett    CVMX_IRQ_UART0      = CVMX_IRQ_MBOX0 + 4,
82232812Sjmallett    CVMX_IRQ_PCI_INT0   = CVMX_IRQ_UART0 + 3,
83232812Sjmallett    CVMX_IRQ_PCI_INT1,
84232812Sjmallett    CVMX_IRQ_PCI_INT2,
85232812Sjmallett    CVMX_IRQ_PCI_INT3,
86232812Sjmallett    CVMX_IRQ_PCI_MSI0,
87232812Sjmallett    CVMX_IRQ_PCI_MSI1,
88232812Sjmallett    CVMX_IRQ_PCI_MSI2,
89232812Sjmallett    CVMX_IRQ_PCI_MSI3,
90232812Sjmallett    /* 2 TWSI interrupts */
91232812Sjmallett    CVMX_IRQ_TWSI0,
92232812Sjmallett    CVMX_IRQ_RML        = CVMX_IRQ_TWSI0 + 2,
93232812Sjmallett    /* 4 TRACE interrupts added in CN68XX */
94232812Sjmallett    CVMX_IRQ_TRACE0,
95232812Sjmallett    /* 5 GMX_DRP interrupts added in CN68XX */
96232812Sjmallett    CVMX_IRQ_GMX_DRP0 = CVMX_IRQ_TRACE0 + 4,
97232812Sjmallett    CVMX_IRQ_GMX_DRP1,   /* Doesn't apply on CN52XX or CN63XX */
98232812Sjmallett    CVMX_IRQ_IPD_DRP = CVMX_IRQ_GMX_DRP0 + 5,
99232812Sjmallett    CVMX_IRQ_KEY_ZERO,   /* Doesn't apply on CN52XX or CN63XX */
100232812Sjmallett    /* 4 TIMER interrupts. */
101232812Sjmallett    CVMX_IRQ_TIMER0,
102232812Sjmallett    /* 2 USB interrupts. */
103232812Sjmallett    CVMX_IRQ_USB0       = CVMX_IRQ_TIMER0 + 4,   /* Doesn't apply on CN38XX or CN58XX */
104232812Sjmallett    CVMX_IRQ_PCM        = CVMX_IRQ_USB0 + 2,   /* Doesn't apply on CN52XX or CN63XX */
105232812Sjmallett    CVMX_IRQ_MPI,   /* Doesn't apply on CN52XX or CN63XX */
106232812Sjmallett    CVMX_IRQ_POWIQ,   /* Added in CN56XX */
107232812Sjmallett    CVMX_IRQ_IPDPPTHR,   /* Added in CN56XX */
108232812Sjmallett    /* 2 MII interrupts. */
109232812Sjmallett    CVMX_IRQ_MII0,   /* Added in CN56XX */
110232812Sjmallett    CVMX_IRQ_BOOTDMA    = CVMX_IRQ_MII0 + 2,   /* Added in CN56XX */
111210284Sjmallett
112232812Sjmallett    /* 32 WDOG interrupts. */
113232812Sjmallett    CVMX_IRQ_WDOG0,
114232812Sjmallett    CVMX_IRQ_NAND  = CVMX_IRQ_WDOG0 + 32,           /* Added in CN52XX */
115232812Sjmallett    CVMX_IRQ_MIO,           /* Added in CN63XX */
116232812Sjmallett    CVMX_IRQ_IOB,           /* Added in CN63XX */
117232812Sjmallett    CVMX_IRQ_FPA,           /* Added in CN63XX */
118232812Sjmallett    CVMX_IRQ_POW,           /* Added in CN63XX */
119232812Sjmallett    CVMX_IRQ_L2C,           /* Added in CN63XX */
120232812Sjmallett    CVMX_IRQ_IPD,           /* Added in CN63XX */
121232812Sjmallett    CVMX_IRQ_PIP,           /* Added in CN63XX */
122232812Sjmallett    CVMX_IRQ_PKO,           /* Added in CN63XX */
123232812Sjmallett    CVMX_IRQ_ZIP,          /* Added in CN63XX */
124232812Sjmallett    CVMX_IRQ_TIM,          /* Added in CN63XX */
125232812Sjmallett    CVMX_IRQ_RAD,          /* Added in CN63XX */
126232812Sjmallett    CVMX_IRQ_KEY,          /* Added in CN63XX */
127232812Sjmallett    CVMX_IRQ_DFA,          /* Added in CN63XX */
128232812Sjmallett    CVMX_IRQ_USBCTL,          /* Added in CN63XX */
129232812Sjmallett    CVMX_IRQ_SLI,          /* Added in CN63XX */
130232812Sjmallett    CVMX_IRQ_DPI,          /* Added in CN63XX */
131232812Sjmallett    /* 5 AGX interrupts added in CN68XX. */
132232812Sjmallett    CVMX_IRQ_AGX0,          /* Added in CN63XX */
133210284Sjmallett
134232812Sjmallett    CVMX_IRQ_AGL = CVMX_IRQ_AGX0 + 5,          /* Added in CN63XX */
135232812Sjmallett    CVMX_IRQ_PTP,          /* Added in CN63XX */
136232812Sjmallett    CVMX_IRQ_PEM0,          /* Added in CN63XX */
137232812Sjmallett    CVMX_IRQ_PEM1,          /* Added in CN63XX */
138232812Sjmallett    CVMX_IRQ_SRIO0,          /* Added in CN63XX */
139232812Sjmallett    CVMX_IRQ_SRIO1,          /* Added in CN63XX */
140232812Sjmallett    CVMX_IRQ_LMC0,          /* Added in CN63XX */
141232812Sjmallett    /* 4 LMC interrupts added in CN68XX. */
142232812Sjmallett    CVMX_IRQ_DFM = CVMX_IRQ_LMC0 + 4,          /* Added in CN63XX */
143232812Sjmallett    CVMX_IRQ_RST,          /* Added in CN63XX */
144232812Sjmallett    CVMX_IRQ_ILK,         /* Added for CN68XX */
145232812Sjmallett    CVMX_IRQ_SRIO2,       /* Added in CN66XX */
146232812Sjmallett    CVMX_IRQ_DPI_DMA,     /* Added in CN61XX */
147232812Sjmallett    /* 6 addition timers added in CN61XX */
148232812Sjmallett    CVMX_IRQ_TIMER4,      /* Added in CN61XX */
149232812Sjmallett    CVMX_IRQ_MAX = CVMX_IRQ_TIMER4 + 6          /* One greater than the last valid number.*/
150210284Sjmallett} cvmx_irq_t;
151210284Sjmallett
152210284Sjmallett/**
153210284Sjmallett * Function prototype for the exception handler
154210284Sjmallett */
155232812Sjmalletttypedef void (*cvmx_interrupt_exception_t)(uint64_t *registers);
156210284Sjmallett
157210284Sjmallett/**
158210284Sjmallett * Function prototype for interrupt handlers
159210284Sjmallett */
160232812Sjmalletttypedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t *registers, void *user_arg);
161210284Sjmallett
162210284Sjmallett/**
163210284Sjmallett * Register an interrupt handler for the specified interrupt number.
164210284Sjmallett *
165210284Sjmallett * @param irq_number Interrupt number to register for (0-135)
166210284Sjmallett * @param func       Function to call on interrupt.
167210284Sjmallett * @param user_arg   User data to pass to the interrupt handler
168210284Sjmallett */
169232812Sjmallettvoid cvmx_interrupt_register(int irq_number, cvmx_interrupt_func_t func, void *user_arg);
170210284Sjmallett
171210284Sjmallett/**
172210284Sjmallett * Set the exception handler for all non interrupt sources.
173210284Sjmallett *
174210284Sjmallett * @param handler New exception handler
175210284Sjmallett * @return Old exception handler
176210284Sjmallett */
177210284Sjmallettcvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
178210284Sjmallett
179232812Sjmallett
180210284Sjmallett/**
181210284Sjmallett * Masks a given interrupt number.
182210284Sjmallett *
183232812Sjmallett * @param irq_number interrupt number to mask
184210284Sjmallett */
185232812Sjmallettextern void (*cvmx_interrupt_mask_irq)(int irq_number);
186210284Sjmallett
187210284Sjmallett
188210284Sjmallett/**
189210284Sjmallett * Unmasks a given interrupt number
190210284Sjmallett *
191232812Sjmallett * @param irq_number interrupt number to unmask
192210284Sjmallett */
193232812Sjmallettextern void (*cvmx_interrupt_unmask_irq)(int irq_number);
194210284Sjmallett
195210284Sjmallett
196210284Sjmallett/* Disable interrupts by clearing bit 0 of the COP0 status register,
197210284Sjmallett** and return the previous contents of the status register.
198210284Sjmallett** Note: this is only used to track interrupt status. */
199210284Sjmallettstatic inline uint32_t cvmx_interrupt_disable_save(void)
200210284Sjmallett{
201210284Sjmallett    uint32_t flags;
202210284Sjmallett    asm volatile (
203210284Sjmallett        "DI   %[flags]\n"
204210284Sjmallett        : [flags]"=r" (flags));
205210284Sjmallett    return(flags);
206210284Sjmallett}
207210284Sjmallett
208210284Sjmallett/* Restore the contents of the cop0 status register.  Used with
209210284Sjmallett** cvmx_interrupt_disable_save to allow recursive interrupt disabling */
210210284Sjmallettstatic inline void cvmx_interrupt_restore(uint32_t flags)
211210284Sjmallett{
212210284Sjmallett    /* If flags value indicates interrupts should be enabled, then enable them */
213210284Sjmallett    if (flags & 1)
214210284Sjmallett    {
215210284Sjmallett        asm volatile (
216210284Sjmallett            "EI     \n"
217210284Sjmallett            ::);
218210284Sjmallett    }
219210284Sjmallett}
220210284Sjmallett
221215990Sjmallett#define cvmx_local_irq_save(x) ({x = cvmx_interrupt_disable_save();})
222215990Sjmallett#define cvmx_local_irq_restore(x) cvmx_interrupt_restore(x)
223210284Sjmallett
224210284Sjmallett/**
225215990Sjmallett * Utility function to do interrupt safe printf
226210284Sjmallett */
227210284Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
228232812Sjmallett        #define cvmx_safe_printf printk
229210284Sjmallett#elif defined(CVMX_BUILD_FOR_LINUX_USER)
230232812Sjmallett        #define cvmx_safe_printf printf
231210284Sjmallett#else
232232812Sjmallett        extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
233215990Sjmallett#endif
234215990Sjmallett
235215990Sjmallett#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
236215990Sjmallett
237232812Sjmallett#ifdef  __cplusplus
238210284Sjmallett}
239210284Sjmallett#endif
240210284Sjmallett
241210284Sjmallett#endif
242