1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-gmxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon gmxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_GMXX_DEFS_H__ 53232812Sjmallett#define __CVMX_GMXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallettstatic inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) 56215976Sjmallett{ 57232812Sjmallett switch(cvmx_get_octeon_family()) { 58232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 59232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 60232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 61232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 62232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 63232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 64232812Sjmallett if ((block_id == 0)) 65232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull; 66232812Sjmallett break; 67232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 68232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 69232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 70232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 71232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 72232812Sjmallett if ((block_id <= 1)) 73232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull; 74232812Sjmallett break; 75232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 76232812Sjmallett if ((block_id <= 4)) 77232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 7) * 0x1000000ull; 78232812Sjmallett break; 79232812Sjmallett } 80232812Sjmallett cvmx_warn("CVMX_GMXX_BAD_REG (block_id = %lu) not supported on this chip\n", block_id); 81232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull; 82232812Sjmallett} 83232812Sjmallettstatic inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) 84232812Sjmallett{ 85232812Sjmallett switch(cvmx_get_octeon_family()) { 86232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 87232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 88232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 89232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 90232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 91232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 92232812Sjmallett if ((block_id == 0)) 93232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull; 94232812Sjmallett break; 95232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 96232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 97232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 98232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 99232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 100232812Sjmallett if ((block_id <= 1)) 101232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull; 102232812Sjmallett break; 103232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 104232812Sjmallett if ((block_id <= 4)) 105232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 7) * 0x1000000ull; 106232812Sjmallett break; 107232812Sjmallett } 108232812Sjmallett cvmx_warn("CVMX_GMXX_BIST (block_id = %lu) not supported on this chip\n", block_id); 109232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull; 110232812Sjmallett} 111232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 112232812Sjmallettstatic inline uint64_t CVMX_GMXX_BPID_MAPX(unsigned long offset, unsigned long block_id) 113232812Sjmallett{ 114215976Sjmallett if (!( 115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 4)))))) 116232812Sjmallett cvmx_warn("CVMX_GMXX_BPID_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id); 117232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8; 118215976Sjmallett} 119215976Sjmallett#else 120232812Sjmallett#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8) 121215976Sjmallett#endif 122215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 123232812Sjmallettstatic inline uint64_t CVMX_GMXX_BPID_MSK(unsigned long block_id) 124215976Sjmallett{ 125215976Sjmallett if (!( 126232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4))))) 127232812Sjmallett cvmx_warn("CVMX_GMXX_BPID_MSK(%lu) is invalid on this chip\n", block_id); 128232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull; 129215976Sjmallett} 130215976Sjmallett#else 131232812Sjmallett#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull) 132215976Sjmallett#endif 133215976Sjmallettstatic inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id) 134215976Sjmallett{ 135232812Sjmallett switch(cvmx_get_octeon_family()) { 136232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 137232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 138232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 139232812Sjmallett if ((block_id == 0)) 140232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull; 141232812Sjmallett break; 142232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 143232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 144232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 145232812Sjmallett if ((block_id <= 1)) 146232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull; 147232812Sjmallett break; 148232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 149232812Sjmallett if ((block_id <= 4)) 150232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 7) * 0x1000000ull; 151232812Sjmallett break; 152232812Sjmallett } 153232812Sjmallett cvmx_warn("CVMX_GMXX_CLK_EN (block_id = %lu) not supported on this chip\n", block_id); 154232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull; 155232812Sjmallett} 156232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 157232812Sjmallettstatic inline uint64_t CVMX_GMXX_EBP_DIS(unsigned long block_id) 158232812Sjmallett{ 159215976Sjmallett if (!( 160232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4))))) 161232812Sjmallett cvmx_warn("CVMX_GMXX_EBP_DIS(%lu) is invalid on this chip\n", block_id); 162232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull; 163215976Sjmallett} 164215976Sjmallett#else 165232812Sjmallett#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull) 166215976Sjmallett#endif 167215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 168232812Sjmallettstatic inline uint64_t CVMX_GMXX_EBP_MSK(unsigned long block_id) 169215976Sjmallett{ 170215976Sjmallett if (!( 171232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4))))) 172232812Sjmallett cvmx_warn("CVMX_GMXX_EBP_MSK(%lu) is invalid on this chip\n", block_id); 173232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull; 174215976Sjmallett} 175215976Sjmallett#else 176232812Sjmallett#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull) 177215976Sjmallett#endif 178232812Sjmallettstatic inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) 179232812Sjmallett{ 180232812Sjmallett switch(cvmx_get_octeon_family()) { 181232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 182232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 183232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 184232812Sjmallett if ((block_id == 0)) 185232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull; 186232812Sjmallett break; 187232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 188232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 189232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 190232812Sjmallett if ((block_id <= 1)) 191232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull; 192232812Sjmallett break; 193232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 194232812Sjmallett if ((block_id <= 4)) 195232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 7) * 0x1000000ull; 196232812Sjmallett break; 197232812Sjmallett } 198232812Sjmallett cvmx_warn("CVMX_GMXX_HG2_CONTROL (block_id = %lu) not supported on this chip\n", block_id); 199232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull; 200232812Sjmallett} 201215976Sjmallettstatic inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) 202215976Sjmallett{ 203232812Sjmallett switch(cvmx_get_octeon_family()) { 204232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 205232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 206232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 207232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 208232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 209232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 210232812Sjmallett if ((block_id == 0)) 211232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull; 212232812Sjmallett break; 213232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 214232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 215232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 216232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 217232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 218232812Sjmallett if ((block_id <= 1)) 219232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull; 220232812Sjmallett break; 221232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 222232812Sjmallett if ((block_id <= 4)) 223232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 7) * 0x1000000ull; 224232812Sjmallett break; 225232812Sjmallett } 226232812Sjmallett cvmx_warn("CVMX_GMXX_INF_MODE (block_id = %lu) not supported on this chip\n", block_id); 227232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull; 228215976Sjmallett} 229215976Sjmallettstatic inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id) 230215976Sjmallett{ 231232812Sjmallett switch(cvmx_get_octeon_family()) { 232232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 233232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 234232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 235232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 236232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 237232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 238232812Sjmallett if ((block_id == 0)) 239232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull; 240232812Sjmallett break; 241232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 242232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 243232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 244232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 245232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 246232812Sjmallett if ((block_id <= 1)) 247232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull; 248232812Sjmallett break; 249232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 250232812Sjmallett if ((block_id <= 4)) 251232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 7) * 0x1000000ull; 252232812Sjmallett break; 253232812Sjmallett } 254232812Sjmallett cvmx_warn("CVMX_GMXX_NXA_ADR (block_id = %lu) not supported on this chip\n", block_id); 255232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull; 256232812Sjmallett} 257232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258232812Sjmallettstatic inline uint64_t CVMX_GMXX_PIPE_STATUS(unsigned long block_id) 259232812Sjmallett{ 260215976Sjmallett if (!( 261232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4))))) 262232812Sjmallett cvmx_warn("CVMX_GMXX_PIPE_STATUS(%lu) is invalid on this chip\n", block_id); 263232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull; 264215976Sjmallett} 265215976Sjmallett#else 266232812Sjmallett#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull) 267215976Sjmallett#endif 268215976Sjmallettstatic inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id) 269215976Sjmallett{ 270232812Sjmallett switch(cvmx_get_octeon_family()) { 271232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 272232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 273232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 274232812Sjmallett if (((offset == 0)) && ((block_id == 0))) 275232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull; 276232812Sjmallett break; 277232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 278232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 279232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 280232812Sjmallett if (((offset == 0)) && ((block_id <= 1))) 281232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull; 282232812Sjmallett break; 283232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 284232812Sjmallett if (((offset == 0)) && ((block_id <= 4))) 285232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 7) * 0x1000000ull; 286232812Sjmallett break; 287232812Sjmallett } 288232812Sjmallett cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 289232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull; 290215976Sjmallett} 291215976Sjmallettstatic inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) 292215976Sjmallett{ 293232812Sjmallett switch(cvmx_get_octeon_family()) { 294232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 295232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 296232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 297232812Sjmallett break; 298232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 299232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 300232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 301232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 302232812Sjmallett break; 303232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 304232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 305232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 306232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 307232812Sjmallett break; 308232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 309232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 310232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 311232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 312232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 313232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 314232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 315232812Sjmallett break; 316232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 317232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 318232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 319232812Sjmallett break; 320232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 321232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 322232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 323232812Sjmallett break; 324232812Sjmallett } 325232812Sjmallett cvmx_warn("CVMX_GMXX_PRTX_CFG (%lu, %lu) not supported on this chip\n", offset, block_id); 326232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 327232812Sjmallett} 328232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329232812Sjmallettstatic inline uint64_t CVMX_GMXX_RXAUI_CTL(unsigned long block_id) 330232812Sjmallett{ 331215976Sjmallett if (!( 332232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4))))) 333232812Sjmallett cvmx_warn("CVMX_GMXX_RXAUI_CTL(%lu) is invalid on this chip\n", block_id); 334232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull; 335215976Sjmallett} 336215976Sjmallett#else 337232812Sjmallett#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull) 338215976Sjmallett#endif 339215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) 340215976Sjmallett{ 341232812Sjmallett switch(cvmx_get_octeon_family()) { 342232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 343232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 344232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 345232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 346232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 347232812Sjmallett break; 348232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 349232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 350232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 351232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 352232812Sjmallett break; 353232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 354232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 355232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 356232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 357232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 358232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 359232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 360232812Sjmallett break; 361232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 362232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 363232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 364232812Sjmallett break; 365232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 366232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 367232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 368232812Sjmallett break; 369232812Sjmallett } 370232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0 (%lu, %lu) not supported on this chip\n", offset, block_id); 371232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 372215976Sjmallett} 373215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) 374215976Sjmallett{ 375232812Sjmallett switch(cvmx_get_octeon_family()) { 376232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 377232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 378232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 379232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 380232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 381232812Sjmallett break; 382232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 383232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 384232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 385232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 386232812Sjmallett break; 387232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 388232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 389232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 390232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 391232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 392232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 393232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 394232812Sjmallett break; 395232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 396232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 397232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 398232812Sjmallett break; 399232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 400232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 401232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 402232812Sjmallett break; 403232812Sjmallett } 404232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1 (%lu, %lu) not supported on this chip\n", offset, block_id); 405232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 406215976Sjmallett} 407215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) 408215976Sjmallett{ 409232812Sjmallett switch(cvmx_get_octeon_family()) { 410232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 411232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 412232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 413232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 414232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 415232812Sjmallett break; 416232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 417232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 418232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 419232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 420232812Sjmallett break; 421232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 422232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 423232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 424232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 425232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 426232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 427232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 428232812Sjmallett break; 429232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 430232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 431232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 432232812Sjmallett break; 433232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 434232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 435232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 436232812Sjmallett break; 437232812Sjmallett } 438232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2 (%lu, %lu) not supported on this chip\n", offset, block_id); 439232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 440215976Sjmallett} 441215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) 442215976Sjmallett{ 443232812Sjmallett switch(cvmx_get_octeon_family()) { 444232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 445232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 446232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 447232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 448232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 449232812Sjmallett break; 450232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 451232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 452232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 453232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 454232812Sjmallett break; 455232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 456232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 457232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 458232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 459232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 460232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 461232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 462232812Sjmallett break; 463232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 464232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 465232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 466232812Sjmallett break; 467232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 468232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 469232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 470232812Sjmallett break; 471232812Sjmallett } 472232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3 (%lu, %lu) not supported on this chip\n", offset, block_id); 473232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 474215976Sjmallett} 475215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) 476215976Sjmallett{ 477232812Sjmallett switch(cvmx_get_octeon_family()) { 478232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 479232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 480232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 481232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 482232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 483232812Sjmallett break; 484232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 485232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 486232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 487232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 488232812Sjmallett break; 489232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 490232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 491232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 492232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 493232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 494232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 495232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 496232812Sjmallett break; 497232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 498232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 499232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 500232812Sjmallett break; 501232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 502232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 503232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 504232812Sjmallett break; 505232812Sjmallett } 506232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4 (%lu, %lu) not supported on this chip\n", offset, block_id); 507232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 508215976Sjmallett} 509215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) 510215976Sjmallett{ 511232812Sjmallett switch(cvmx_get_octeon_family()) { 512232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 513232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 514232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 515232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 516232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 517232812Sjmallett break; 518232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 519232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 520232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 521232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 522232812Sjmallett break; 523232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 524232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 525232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 526232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 527232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 528232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 529232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 530232812Sjmallett break; 531232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 532232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 533232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 534232812Sjmallett break; 535232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 536232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 537232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 538232812Sjmallett break; 539232812Sjmallett } 540232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5 (%lu, %lu) not supported on this chip\n", offset, block_id); 541232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 542215976Sjmallett} 543232812Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id) 544232812Sjmallett{ 545232812Sjmallett switch(cvmx_get_octeon_family()) { 546232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 547232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 548232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 549232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 550232812Sjmallett break; 551232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 552232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 553232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 554232812Sjmallett break; 555232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 556232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 557232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 558232812Sjmallett break; 559232812Sjmallett } 560232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_ALL_EN (%lu, %lu) not supported on this chip\n", offset, block_id); 561232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 562232812Sjmallett} 563215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) 564215976Sjmallett{ 565232812Sjmallett switch(cvmx_get_octeon_family()) { 566232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 567232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 568232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 569232812Sjmallett break; 570232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 571232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 572232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 573232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 574232812Sjmallett break; 575232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 576232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 577232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 578232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 579232812Sjmallett break; 580232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 581232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 582232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 583232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 584232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 585232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 586232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 587232812Sjmallett break; 588232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 589232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 590232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 591232812Sjmallett break; 592232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 593232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 594232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 595232812Sjmallett break; 596232812Sjmallett } 597232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN (%lu, %lu) not supported on this chip\n", offset, block_id); 598232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 599215976Sjmallett} 600215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) 601215976Sjmallett{ 602232812Sjmallett switch(cvmx_get_octeon_family()) { 603232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 604232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 605232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 606232812Sjmallett break; 607232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 608232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 609232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 610232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 611232812Sjmallett break; 612232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 613232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 614232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 615232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 616232812Sjmallett break; 617232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 618232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 619232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 620232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 621232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 622232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 623232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 624232812Sjmallett break; 625232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 626232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 627232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 628232812Sjmallett break; 629232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 630232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 631232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 632232812Sjmallett break; 633232812Sjmallett } 634232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_ADR_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 635232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 636215976Sjmallett} 637215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id) 638215976Sjmallett{ 639232812Sjmallett switch(cvmx_get_octeon_family()) { 640232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 641232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 642232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 643232812Sjmallett break; 644232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 645232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 646232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 647232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 648232812Sjmallett break; 649232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 650232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 651232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 652232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 653232812Sjmallett break; 654232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 655232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 656232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 657232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 658232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 659232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 660232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 661232812Sjmallett break; 662232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 663232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 664232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 665232812Sjmallett break; 666232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 667232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 668232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 669232812Sjmallett break; 670232812Sjmallett } 671232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_DECISION (%lu, %lu) not supported on this chip\n", offset, block_id); 672232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 673215976Sjmallett} 674215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id) 675215976Sjmallett{ 676232812Sjmallett switch(cvmx_get_octeon_family()) { 677232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 678232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 679232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 680232812Sjmallett break; 681232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 682232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 683232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 684232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 685232812Sjmallett break; 686232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 687232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 688232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 689232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 690232812Sjmallett break; 691232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 692232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 693232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 694232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 695232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 696232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 697232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 698232812Sjmallett break; 699232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 700232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 701232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 702232812Sjmallett break; 703232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 704232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 705232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 706232812Sjmallett break; 707232812Sjmallett } 708232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_FRM_CHK (%lu, %lu) not supported on this chip\n", offset, block_id); 709232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 710215976Sjmallett} 711215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) 712215976Sjmallett{ 713232812Sjmallett switch(cvmx_get_octeon_family()) { 714232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 715232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 716232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 717232812Sjmallett break; 718232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 719232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 720232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 721232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 722232812Sjmallett break; 723232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 724232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 725232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 726232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 727232812Sjmallett break; 728232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 729232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 730232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 731232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 732232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 733232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 734232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 735232812Sjmallett break; 736232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 737232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 738232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 739232812Sjmallett break; 740232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 741232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 742232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 743232812Sjmallett break; 744232812Sjmallett } 745232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_FRM_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 746232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 747215976Sjmallett} 748215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id) 750215976Sjmallett{ 751215976Sjmallett if (!( 752215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 753215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 754215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 755215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 756215976Sjmallett cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id); 757215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 758215976Sjmallett} 759215976Sjmallett#else 760215976Sjmallett#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 761215976Sjmallett#endif 762215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 763215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id) 764215976Sjmallett{ 765215976Sjmallett if (!( 766215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 767215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 768215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 769215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 770215976Sjmallett cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id); 771215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 772215976Sjmallett} 773215976Sjmallett#else 774215976Sjmallett#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 775215976Sjmallett#endif 776215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id) 777215976Sjmallett{ 778232812Sjmallett switch(cvmx_get_octeon_family()) { 779232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 780232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 781232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 782232812Sjmallett break; 783232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 784232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 785232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 786232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 787232812Sjmallett break; 788232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 789232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 790232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 791232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 792232812Sjmallett break; 793232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 794232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 795232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 796232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 797232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 798232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 799232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 800232812Sjmallett break; 801232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 802232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 803232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 804232812Sjmallett break; 805232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 806232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 807232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 808232812Sjmallett break; 809232812Sjmallett } 810232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_IFG (%lu, %lu) not supported on this chip\n", offset, block_id); 811232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 812215976Sjmallett} 813215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) 814215976Sjmallett{ 815232812Sjmallett switch(cvmx_get_octeon_family()) { 816232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 817232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 818232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 819232812Sjmallett break; 820232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 821232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 822232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 823232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 824232812Sjmallett break; 825232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 826232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 827232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 828232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 829232812Sjmallett break; 830232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 831232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 832232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 833232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 834232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 835232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 836232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 837232812Sjmallett break; 838232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 839232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 840232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 841232812Sjmallett break; 842232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 843232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 844232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 845232812Sjmallett break; 846232812Sjmallett } 847232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_INT_EN (%lu, %lu) not supported on this chip\n", offset, block_id); 848232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 849215976Sjmallett} 850215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) 851215976Sjmallett{ 852232812Sjmallett switch(cvmx_get_octeon_family()) { 853232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 854232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 855232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 856232812Sjmallett break; 857232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 858232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 859232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 860232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 861232812Sjmallett break; 862232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 863232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 864232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 865232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 866232812Sjmallett break; 867232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 868232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 869232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 870232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 871232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 872232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 873232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 874232812Sjmallett break; 875232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 876232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 877232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 878232812Sjmallett break; 879232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 880232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 881232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 882232812Sjmallett break; 883232812Sjmallett } 884232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_INT_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 885232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 886215976Sjmallett} 887215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) 888215976Sjmallett{ 889232812Sjmallett switch(cvmx_get_octeon_family()) { 890232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 891232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 892232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 893232812Sjmallett break; 894232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 895232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 896232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 897232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 898232812Sjmallett break; 899232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 900232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 901232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 902232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 903232812Sjmallett break; 904232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 905232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 906232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 907232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 908232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 909232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 910232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 911232812Sjmallett break; 912232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 913232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 914232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 915232812Sjmallett break; 916232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 917232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 918232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 919232812Sjmallett break; 920232812Sjmallett } 921232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_JABBER (%lu, %lu) not supported on this chip\n", offset, block_id); 922232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 923215976Sjmallett} 924215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id) 925215976Sjmallett{ 926232812Sjmallett switch(cvmx_get_octeon_family()) { 927232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 928232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 929232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 930232812Sjmallett break; 931232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 932232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 933232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 934232812Sjmallett break; 935232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 936232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 937232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 938232812Sjmallett break; 939232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 940232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 941232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 942232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 943232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 944232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 945232812Sjmallett break; 946232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 947232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 948232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 949232812Sjmallett break; 950232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 951232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 952232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 953232812Sjmallett break; 954232812Sjmallett } 955232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME (%lu, %lu) not supported on this chip\n", offset, block_id); 956232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 957215976Sjmallett} 958215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 959215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id) 960215976Sjmallett{ 961215976Sjmallett if (!( 962215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 963215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 964215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 965215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 966215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 967215976Sjmallett cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id); 968215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 969215976Sjmallett} 970215976Sjmallett#else 971215976Sjmallett#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 972215976Sjmallett#endif 973215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id) 974215976Sjmallett{ 975232812Sjmallett switch(cvmx_get_octeon_family()) { 976232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 977232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 978232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 979232812Sjmallett break; 980232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 981232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 982232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 983232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 984232812Sjmallett break; 985232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 986232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 987232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 988232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 989232812Sjmallett break; 990232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 991232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 992232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 993232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 994232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 995232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 996232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 997232812Sjmallett break; 998232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 999232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1000232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1001232812Sjmallett break; 1002232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1003232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1004232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1005232812Sjmallett break; 1006232812Sjmallett } 1007232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 1008232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1009215976Sjmallett} 1010215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id) 1011215976Sjmallett{ 1012232812Sjmallett switch(cvmx_get_octeon_family()) { 1013232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1014232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1015232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1016232812Sjmallett break; 1017232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1018232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1019232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1020232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1021232812Sjmallett break; 1022232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1023232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1024232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1025232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1026232812Sjmallett break; 1027232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1028232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1029232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1030232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1031232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1032232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1033232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1034232812Sjmallett break; 1035232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1036232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1037232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1038232812Sjmallett break; 1039232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1040232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1041232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1042232812Sjmallett break; 1043232812Sjmallett } 1044232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS (%lu, %lu) not supported on this chip\n", offset, block_id); 1045232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1046215976Sjmallett} 1047215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id) 1048215976Sjmallett{ 1049232812Sjmallett switch(cvmx_get_octeon_family()) { 1050232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1051232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1052232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1053232812Sjmallett break; 1054232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1055232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1056232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1057232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1058232812Sjmallett break; 1059232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1060232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1061232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1062232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1063232812Sjmallett break; 1064232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1065232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1066232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1067232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1068232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1069232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1070232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1071232812Sjmallett break; 1072232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1073232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1074232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1075232812Sjmallett break; 1076232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1077232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1078232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1079232812Sjmallett break; 1080232812Sjmallett } 1081232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 1082232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1083215976Sjmallett} 1084215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id) 1085215976Sjmallett{ 1086232812Sjmallett switch(cvmx_get_octeon_family()) { 1087232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1088232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1089232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1090232812Sjmallett break; 1091232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1092232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1093232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1094232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1095232812Sjmallett break; 1096232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1097232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1098232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1099232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1100232812Sjmallett break; 1101232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1102232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1103232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1104232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1105232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1106232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1107232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1108232812Sjmallett break; 1109232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1110232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1111232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1112232812Sjmallett break; 1113232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1114232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1115232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1116232812Sjmallett break; 1117232812Sjmallett } 1118232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id); 1119232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1120215976Sjmallett} 1121215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id) 1122215976Sjmallett{ 1123232812Sjmallett switch(cvmx_get_octeon_family()) { 1124232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1125232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1126232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1127232812Sjmallett break; 1128232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1129232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1130232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1131232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1132232812Sjmallett break; 1133232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1134232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1135232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1136232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1137232812Sjmallett break; 1138232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1139232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1140232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1141232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1142232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1143232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1144232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1145232812Sjmallett break; 1146232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1147232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1148232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1149232812Sjmallett break; 1150232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1151232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1152232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1153232812Sjmallett break; 1154232812Sjmallett } 1155232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id); 1156232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1157215976Sjmallett} 1158215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id) 1159215976Sjmallett{ 1160232812Sjmallett switch(cvmx_get_octeon_family()) { 1161232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1162232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1163232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1164232812Sjmallett break; 1165232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1166232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1167232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1168232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1169232812Sjmallett break; 1170232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1171232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1172232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1173232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1174232812Sjmallett break; 1175232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1176232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1177232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1178232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1179232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1180232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1181232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1182232812Sjmallett break; 1183232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1184232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1185232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1186232812Sjmallett break; 1187232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1188232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1189232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1190232812Sjmallett break; 1191232812Sjmallett } 1192232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS (%lu, %lu) not supported on this chip\n", offset, block_id); 1193232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1194215976Sjmallett} 1195215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id) 1196215976Sjmallett{ 1197232812Sjmallett switch(cvmx_get_octeon_family()) { 1198232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1199232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1200232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1201232812Sjmallett break; 1202232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1203232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1204232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1205232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1206232812Sjmallett break; 1207232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1208232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1209232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1210232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1211232812Sjmallett break; 1212232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1213232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1214232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1215232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1216232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1217232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1218232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1219232812Sjmallett break; 1220232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1221232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1222232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1223232812Sjmallett break; 1224232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1225232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1226232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1227232812Sjmallett break; 1228232812Sjmallett } 1229232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD (%lu, %lu) not supported on this chip\n", offset, block_id); 1230232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1231215976Sjmallett} 1232215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id) 1233215976Sjmallett{ 1234232812Sjmallett switch(cvmx_get_octeon_family()) { 1235232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1236232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1237232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1238232812Sjmallett break; 1239232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1240232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1241232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1242232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1243232812Sjmallett break; 1244232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1245232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1246232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1247232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1248232812Sjmallett break; 1249232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1250232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1251232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1252232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1253232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1254232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1255232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1256232812Sjmallett break; 1257232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1258232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1259232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1260232812Sjmallett break; 1261232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1262232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1263232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1264232812Sjmallett break; 1265232812Sjmallett } 1266232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 1267232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1268215976Sjmallett} 1269215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id) 1270215976Sjmallett{ 1271232812Sjmallett switch(cvmx_get_octeon_family()) { 1272232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1273232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1274232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1275232812Sjmallett break; 1276232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1277232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1278232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1279232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1280232812Sjmallett break; 1281232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1282232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1283232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1284232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1285232812Sjmallett break; 1286232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1287232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1288232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1289232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1290232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1291232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1292232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1293232812Sjmallett break; 1294232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1295232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1296232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1297232812Sjmallett break; 1298232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1299232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1300232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1301232812Sjmallett break; 1302232812Sjmallett } 1303232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id); 1304232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1305215976Sjmallett} 1306215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id) 1307215976Sjmallett{ 1308232812Sjmallett switch(cvmx_get_octeon_family()) { 1309232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1310232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1311232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1312232812Sjmallett break; 1313232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1314232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1315232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1316232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1317232812Sjmallett break; 1318232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1319232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1320232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1321232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1322232812Sjmallett break; 1323232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1324232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1325232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1326232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1327232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1328232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1329232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1330232812Sjmallett break; 1331232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1332232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1333232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1334232812Sjmallett break; 1335232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1336232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1337232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1338232812Sjmallett break; 1339232812Sjmallett } 1340232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id); 1341232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1342215976Sjmallett} 1343215976Sjmallettstatic inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id) 1344215976Sjmallett{ 1345232812Sjmallett switch(cvmx_get_octeon_family()) { 1346232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1347232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1348232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1349232812Sjmallett break; 1350232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1351232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1352232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1353232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1354232812Sjmallett break; 1355232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1356232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1357232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1358232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1359232812Sjmallett break; 1360232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1361232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1362232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1363232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1364232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1365232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1366232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1367232812Sjmallett break; 1368232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1369232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1370232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1371232812Sjmallett break; 1372232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1373232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1374232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1375232812Sjmallett break; 1376232812Sjmallett } 1377232812Sjmallett cvmx_warn("CVMX_GMXX_RXX_UDD_SKP (%lu, %lu) not supported on this chip\n", offset, block_id); 1378232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1379215976Sjmallett} 1380215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id) 1381215976Sjmallett{ 1382232812Sjmallett switch(cvmx_get_octeon_family()) { 1383232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1384232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1385232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1386232812Sjmallett break; 1387232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1388232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1389232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1390232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1391232812Sjmallett break; 1392232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1393232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1394232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1395232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1396232812Sjmallett break; 1397232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1398232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1399232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1400232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1401232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1402232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1403232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 1404232812Sjmallett break; 1405232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1406232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1407232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8; 1408232812Sjmallett break; 1409232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1410232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1411232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8; 1412232812Sjmallett break; 1413232812Sjmallett } 1414232812Sjmallett cvmx_warn("CVMX_GMXX_RX_BP_DROPX (%lu, %lu) not supported on this chip\n", offset, block_id); 1415232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1416215976Sjmallett} 1417215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id) 1418215976Sjmallett{ 1419232812Sjmallett switch(cvmx_get_octeon_family()) { 1420232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1421232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1422232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1423232812Sjmallett break; 1424232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1425232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1426232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1427232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1428232812Sjmallett break; 1429232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1430232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1431232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1432232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1433232812Sjmallett break; 1434232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1435232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1436232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1437232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1438232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1439232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1440232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 1441232812Sjmallett break; 1442232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1443232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1444232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8; 1445232812Sjmallett break; 1446232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1447232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1448232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8; 1449232812Sjmallett break; 1450232812Sjmallett } 1451232812Sjmallett cvmx_warn("CVMX_GMXX_RX_BP_OFFX (%lu, %lu) not supported on this chip\n", offset, block_id); 1452232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1453215976Sjmallett} 1454215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id) 1455215976Sjmallett{ 1456232812Sjmallett switch(cvmx_get_octeon_family()) { 1457232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1458232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1459232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1460232812Sjmallett break; 1461232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1462232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1463232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1464232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1465232812Sjmallett break; 1466232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1467232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1468232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1469232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8; 1470232812Sjmallett break; 1471232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1472232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1473232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1474232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1475232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1476232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1477232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 1478232812Sjmallett break; 1479232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1480232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1481232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8; 1482232812Sjmallett break; 1483232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1484232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1485232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8; 1486232812Sjmallett break; 1487232812Sjmallett } 1488232812Sjmallett cvmx_warn("CVMX_GMXX_RX_BP_ONX (%lu, %lu) not supported on this chip\n", offset, block_id); 1489232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8; 1490215976Sjmallett} 1491215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id) 1492215976Sjmallett{ 1493232812Sjmallett switch(cvmx_get_octeon_family()) { 1494232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1495232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1496232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1497232812Sjmallett if ((block_id == 0)) 1498232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull; 1499232812Sjmallett break; 1500232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1501232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1502232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1503232812Sjmallett if ((block_id <= 1)) 1504232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull; 1505232812Sjmallett break; 1506232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1507232812Sjmallett if ((block_id <= 4)) 1508232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 7) * 0x1000000ull; 1509232812Sjmallett break; 1510232812Sjmallett } 1511232812Sjmallett cvmx_warn("CVMX_GMXX_RX_HG2_STATUS (block_id = %lu) not supported on this chip\n", block_id); 1512232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull; 1513215976Sjmallett} 1514215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1515215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id) 1516215976Sjmallett{ 1517215976Sjmallett if (!( 1518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 1519215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 1520215976Sjmallett cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n", block_id); 1521215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull; 1522215976Sjmallett} 1523215976Sjmallett#else 1524215976Sjmallett#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull) 1525215976Sjmallett#endif 1526215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1527215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id) 1528215976Sjmallett{ 1529215976Sjmallett if (!( 1530215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) || 1531215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1)))))) 1532215976Sjmallett cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id); 1533215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8; 1534215976Sjmallett} 1535215976Sjmallett#else 1536215976Sjmallett#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8) 1537215976Sjmallett#endif 1538215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id) 1539215976Sjmallett{ 1540232812Sjmallett switch(cvmx_get_octeon_family()) { 1541232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1542232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1543232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1544232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1545232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1546232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1547232812Sjmallett if ((block_id == 0)) 1548232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull; 1549232812Sjmallett break; 1550232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1551232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1552232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1553232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1554232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1555232812Sjmallett if ((block_id <= 1)) 1556232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull; 1557232812Sjmallett break; 1558232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1559232812Sjmallett if ((block_id <= 4)) 1560232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 7) * 0x1000000ull; 1561232812Sjmallett break; 1562232812Sjmallett } 1563232812Sjmallett cvmx_warn("CVMX_GMXX_RX_PRTS (block_id = %lu) not supported on this chip\n", block_id); 1564232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull; 1565215976Sjmallett} 1566215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id) 1567215976Sjmallett{ 1568232812Sjmallett switch(cvmx_get_octeon_family()) { 1569232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1570232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1571232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1572232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1573232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1574232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1575232812Sjmallett if ((block_id == 0)) 1576232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull; 1577232812Sjmallett break; 1578232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1579232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1580232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1581232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1582232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1583232812Sjmallett if ((block_id <= 1)) 1584232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull; 1585232812Sjmallett break; 1586232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1587232812Sjmallett if ((block_id <= 4)) 1588232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 7) * 0x1000000ull; 1589232812Sjmallett break; 1590232812Sjmallett } 1591232812Sjmallett cvmx_warn("CVMX_GMXX_RX_PRT_INFO (block_id = %lu) not supported on this chip\n", block_id); 1592232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull; 1593215976Sjmallett} 1594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1595215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id) 1596215976Sjmallett{ 1597215976Sjmallett if (!( 1598215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 1599215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 1600215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 1601215976Sjmallett cvmx_warn("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n", block_id); 1602215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E8ull); 1603215976Sjmallett} 1604215976Sjmallett#else 1605215976Sjmallett#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull)) 1606215976Sjmallett#endif 1607215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id) 1608215976Sjmallett{ 1609232812Sjmallett switch(cvmx_get_octeon_family()) { 1610232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1611232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1612232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1613232812Sjmallett if ((block_id == 0)) 1614232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull; 1615232812Sjmallett break; 1616232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1617232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1618232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1619232812Sjmallett if ((block_id <= 1)) 1620232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull; 1621232812Sjmallett break; 1622232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1623232812Sjmallett if ((block_id <= 4)) 1624232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 7) * 0x1000000ull; 1625232812Sjmallett break; 1626232812Sjmallett } 1627232812Sjmallett cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL (block_id = %lu) not supported on this chip\n", block_id); 1628232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull; 1629215976Sjmallett} 1630215976Sjmallettstatic inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) 1631215976Sjmallett{ 1632232812Sjmallett switch(cvmx_get_octeon_family()) { 1633232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1634232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1635232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1636232812Sjmallett if ((block_id == 0)) 1637232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull; 1638232812Sjmallett break; 1639232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1640232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1641232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1642232812Sjmallett if ((block_id <= 1)) 1643232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull; 1644232812Sjmallett break; 1645232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1646232812Sjmallett if ((block_id <= 4)) 1647232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 7) * 0x1000000ull; 1648232812Sjmallett break; 1649232812Sjmallett } 1650232812Sjmallett cvmx_warn("CVMX_GMXX_RX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id); 1651232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull; 1652215976Sjmallett} 1653215976Sjmallettstatic inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) 1654215976Sjmallett{ 1655232812Sjmallett switch(cvmx_get_octeon_family()) { 1656232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1657232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1658232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1659232812Sjmallett break; 1660232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1661232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1662232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1663232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1664232812Sjmallett break; 1665232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1666232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1667232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1668232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1669232812Sjmallett break; 1670232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1671232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1672232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1673232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1674232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1675232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1676232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1677232812Sjmallett break; 1678232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1679232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1680232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1681232812Sjmallett break; 1682232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1683232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1684232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1685232812Sjmallett break; 1686232812Sjmallett } 1687232812Sjmallett cvmx_warn("CVMX_GMXX_SMACX (%lu, %lu) not supported on this chip\n", offset, block_id); 1688232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1689215976Sjmallett} 1690215976Sjmallettstatic inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id) 1691215976Sjmallett{ 1692232812Sjmallett switch(cvmx_get_octeon_family()) { 1693232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1694232812Sjmallett if ((block_id <= 1)) 1695232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 1) * 0x8000000ull; 1696232812Sjmallett break; 1697232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1698232812Sjmallett if ((block_id == 0)) 1699232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 0) * 0x8000000ull; 1700232812Sjmallett break; 1701232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1702232812Sjmallett if ((block_id <= 4)) 1703232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull; 1704232812Sjmallett break; 1705232812Sjmallett } 1706232812Sjmallett cvmx_warn("CVMX_GMXX_SOFT_BIST (block_id = %lu) not supported on this chip\n", block_id); 1707232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull; 1708215976Sjmallett} 1709215976Sjmallettstatic inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id) 1710215976Sjmallett{ 1711232812Sjmallett switch(cvmx_get_octeon_family()) { 1712232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1713232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1714232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1715232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1716232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1717232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1718232812Sjmallett if ((block_id == 0)) 1719232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull; 1720232812Sjmallett break; 1721232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1722232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1723232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1724232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1725232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1726232812Sjmallett if ((block_id <= 1)) 1727232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull; 1728232812Sjmallett break; 1729232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1730232812Sjmallett if ((block_id <= 4)) 1731232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 7) * 0x1000000ull; 1732232812Sjmallett break; 1733232812Sjmallett } 1734232812Sjmallett cvmx_warn("CVMX_GMXX_STAT_BP (block_id = %lu) not supported on this chip\n", block_id); 1735232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull; 1736215976Sjmallett} 1737232812Sjmallettstatic inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id) 1738232812Sjmallett{ 1739232812Sjmallett switch(cvmx_get_octeon_family()) { 1740232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1741232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1742232812Sjmallett if ((block_id <= 1)) 1743232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 1) * 0x8000000ull; 1744232812Sjmallett break; 1745232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1746232812Sjmallett if ((block_id == 0)) 1747232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull; 1748232812Sjmallett break; 1749232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1750232812Sjmallett if ((block_id <= 4)) 1751232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 7) * 0x1000000ull; 1752232812Sjmallett break; 1753232812Sjmallett } 1754232812Sjmallett cvmx_warn("CVMX_GMXX_TB_REG (block_id = %lu) not supported on this chip\n", block_id); 1755232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull; 1756232812Sjmallett} 1757215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id) 1758215976Sjmallett{ 1759232812Sjmallett switch(cvmx_get_octeon_family()) { 1760232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1761232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1762232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1763232812Sjmallett break; 1764232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1765232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1766232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1767232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1768232812Sjmallett break; 1769232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1770232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1771232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1772232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1773232812Sjmallett break; 1774232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1775232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1776232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1777232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1778232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1779232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1780232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1781232812Sjmallett break; 1782232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1783232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1784232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1785232812Sjmallett break; 1786232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1787232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1788232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1789232812Sjmallett break; 1790232812Sjmallett } 1791232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_APPEND (%lu, %lu) not supported on this chip\n", offset, block_id); 1792232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1793215976Sjmallett} 1794215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) 1795215976Sjmallett{ 1796232812Sjmallett switch(cvmx_get_octeon_family()) { 1797232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1798232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1799232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1800232812Sjmallett break; 1801232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1802232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1803232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1804232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1805232812Sjmallett break; 1806232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1807232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1808232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1809232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1810232812Sjmallett break; 1811232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1812232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1813232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1814232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1815232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1816232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1817232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1818232812Sjmallett break; 1819232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1820232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1821232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1822232812Sjmallett break; 1823232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1824232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1825232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1826232812Sjmallett break; 1827232812Sjmallett } 1828232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_BURST (%lu, %lu) not supported on this chip\n", offset, block_id); 1829232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1830215976Sjmallett} 1831215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id) 1832215976Sjmallett{ 1833232812Sjmallett switch(cvmx_get_octeon_family()) { 1834232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1835232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1836232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1837232812Sjmallett if (((offset == 0)) && ((block_id == 0))) 1838232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull; 1839232812Sjmallett break; 1840232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1841232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1842232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1843232812Sjmallett if (((offset == 0)) && ((block_id <= 1))) 1844232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull; 1845232812Sjmallett break; 1846232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1847232812Sjmallett if (((offset == 0)) && ((block_id <= 4))) 1848232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 7) * 0x1000000ull; 1849232812Sjmallett break; 1850232812Sjmallett } 1851232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF (%lu, %lu) not supported on this chip\n", offset, block_id); 1852232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull; 1853215976Sjmallett} 1854215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id) 1855215976Sjmallett{ 1856232812Sjmallett switch(cvmx_get_octeon_family()) { 1857232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1858232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1859232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1860232812Sjmallett if (((offset == 0)) && ((block_id == 0))) 1861232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull; 1862232812Sjmallett break; 1863232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1864232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1865232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1866232812Sjmallett if (((offset == 0)) && ((block_id <= 1))) 1867232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull; 1868232812Sjmallett break; 1869232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1870232812Sjmallett if (((offset == 0)) && ((block_id <= 4))) 1871232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 7) * 0x1000000ull; 1872232812Sjmallett break; 1873232812Sjmallett } 1874232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_CBFC_XON (%lu, %lu) not supported on this chip\n", offset, block_id); 1875232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull; 1876215976Sjmallett} 1877215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1878215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id) 1879215976Sjmallett{ 1880215976Sjmallett if (!( 1881215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 1882215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 1883215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 1884215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 1885215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 1886215976Sjmallett cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id); 1887215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1888215976Sjmallett} 1889215976Sjmallett#else 1890215976Sjmallett#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 1891215976Sjmallett#endif 1892215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) 1893215976Sjmallett{ 1894232812Sjmallett switch(cvmx_get_octeon_family()) { 1895232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1896232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1897232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1898232812Sjmallett break; 1899232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1900232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1901232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1902232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1903232812Sjmallett break; 1904232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1905232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1906232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1907232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1908232812Sjmallett break; 1909232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1910232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1911232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1912232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1913232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1914232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1915232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1916232812Sjmallett break; 1917232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1918232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1919232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1920232812Sjmallett break; 1921232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1922232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1923232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1924232812Sjmallett break; 1925232812Sjmallett } 1926232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 1927232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1928215976Sjmallett} 1929215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id) 1930215976Sjmallett{ 1931232812Sjmallett switch(cvmx_get_octeon_family()) { 1932232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1933232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1934232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1935232812Sjmallett break; 1936232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1937232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1938232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1939232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1940232812Sjmallett break; 1941232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1942232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1943232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1944232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1945232812Sjmallett break; 1946232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1947232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1948232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1949232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1950232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1951232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1952232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1953232812Sjmallett break; 1954232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1955232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1956232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1957232812Sjmallett break; 1958232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1959232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1960232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1961232812Sjmallett break; 1962232812Sjmallett } 1963232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_MIN_PKT (%lu, %lu) not supported on this chip\n", offset, block_id); 1964232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1965215976Sjmallett} 1966215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) 1967215976Sjmallett{ 1968232812Sjmallett switch(cvmx_get_octeon_family()) { 1969232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1970232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 1971232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 1972232812Sjmallett break; 1973232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1974232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1975232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1976232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1977232812Sjmallett break; 1978232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1979232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1980232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 1981232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 1982232812Sjmallett break; 1983232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1984232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1985232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1986232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1987232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1988232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 1989232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 1990232812Sjmallett break; 1991232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1992232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 1993232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 1994232812Sjmallett break; 1995232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1996232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 1997232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 1998232812Sjmallett break; 1999232812Sjmallett } 2000232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL (%lu, %lu) not supported on this chip\n", offset, block_id); 2001232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2002215976Sjmallett} 2003215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) 2004215976Sjmallett{ 2005232812Sjmallett switch(cvmx_get_octeon_family()) { 2006232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2007232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2008232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2009232812Sjmallett break; 2010232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2011232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2012232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2013232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2014232812Sjmallett break; 2015232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2016232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2017232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2018232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2019232812Sjmallett break; 2020232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2021232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2022232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2023232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2024232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2025232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2026232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2027232812Sjmallett break; 2028232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2029232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2030232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2031232812Sjmallett break; 2032232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2033232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2034232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2035232812Sjmallett break; 2036232812Sjmallett } 2037232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME (%lu, %lu) not supported on this chip\n", offset, block_id); 2038232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2039215976Sjmallett} 2040215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id) 2041215976Sjmallett{ 2042232812Sjmallett switch(cvmx_get_octeon_family()) { 2043232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2044232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2045232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2046232812Sjmallett break; 2047232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2048232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2049232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2050232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2051232812Sjmallett break; 2052232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2053232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2054232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2055232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2056232812Sjmallett break; 2057232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2058232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2059232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2060232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2061232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2062232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2063232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2064232812Sjmallett break; 2065232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2066232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2067232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2068232812Sjmallett break; 2069232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2070232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2071232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2072232812Sjmallett break; 2073232812Sjmallett } 2074232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO (%lu, %lu) not supported on this chip\n", offset, block_id); 2075232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2076215976Sjmallett} 2077215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id) 2078215976Sjmallett{ 2079232812Sjmallett switch(cvmx_get_octeon_family()) { 2080232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2081232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2082232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2083232812Sjmallett break; 2084232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2085232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2086232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2087232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2088232812Sjmallett break; 2089232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2090232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2091232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2092232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2093232812Sjmallett break; 2094232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2095232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2096232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2097232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2098232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2099232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2100232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2101232812Sjmallett break; 2102232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2103232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2104232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2105232812Sjmallett break; 2106232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2107232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2108232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2109232812Sjmallett break; 2110232812Sjmallett } 2111232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO (%lu, %lu) not supported on this chip\n", offset, block_id); 2112232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2113232812Sjmallett} 2114232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2115232812Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_PIPE(unsigned long offset, unsigned long block_id) 2116232812Sjmallett{ 2117215976Sjmallett if (!( 2118232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 4)))))) 2119232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_PIPE(%lu,%lu) is invalid on this chip\n", offset, block_id); 2120232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2121215976Sjmallett} 2122215976Sjmallett#else 2123232812Sjmallett#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048) 2124215976Sjmallett#endif 2125215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id) 2126215976Sjmallett{ 2127232812Sjmallett switch(cvmx_get_octeon_family()) { 2128232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2129232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2130232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2131232812Sjmallett break; 2132232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2133232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2134232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2135232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2136232812Sjmallett break; 2137232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2138232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2139232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2140232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2141232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2142232812Sjmallett break; 2143232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2144232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2145232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2146232812Sjmallett break; 2147232812Sjmallett } 2148232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 2149232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2150215976Sjmallett} 2151215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) 2152215976Sjmallett{ 2153232812Sjmallett switch(cvmx_get_octeon_family()) { 2154232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2155232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2156232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2157232812Sjmallett break; 2158232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2159232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2160232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2161232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2162232812Sjmallett break; 2163232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2164232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2165232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2166232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2167232812Sjmallett break; 2168232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2169232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2170232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2171232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2172232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2173232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2174232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2175232812Sjmallett break; 2176232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2177232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2178232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2179232812Sjmallett break; 2180232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2181232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2182232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2183232812Sjmallett break; 2184232812Sjmallett } 2185232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_SLOT (%lu, %lu) not supported on this chip\n", offset, block_id); 2186232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2187215976Sjmallett} 2188215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id) 2189215976Sjmallett{ 2190232812Sjmallett switch(cvmx_get_octeon_family()) { 2191232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2192232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2193232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2194232812Sjmallett break; 2195232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2196232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2197232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2198232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2199232812Sjmallett break; 2200232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2201232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2202232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2203232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2204232812Sjmallett break; 2205232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2206232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2207232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2208232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2209232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2210232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2211232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2212232812Sjmallett break; 2213232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2214232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2215232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2216232812Sjmallett break; 2217232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2218232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2219232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2220232812Sjmallett break; 2221232812Sjmallett } 2222232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE (%lu, %lu) not supported on this chip\n", offset, block_id); 2223232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2224215976Sjmallett} 2225215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id) 2226215976Sjmallett{ 2227232812Sjmallett switch(cvmx_get_octeon_family()) { 2228232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2229232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2230232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2231232812Sjmallett break; 2232232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2233232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2234232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2235232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2236232812Sjmallett break; 2237232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2238232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2239232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2240232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2241232812Sjmallett break; 2242232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2243232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2244232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2245232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2246232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2247232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2248232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2249232812Sjmallett break; 2250232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2251232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2252232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2253232812Sjmallett break; 2254232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2255232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2256232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2257232812Sjmallett break; 2258232812Sjmallett } 2259232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT0 (%lu, %lu) not supported on this chip\n", offset, block_id); 2260232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2261215976Sjmallett} 2262215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id) 2263215976Sjmallett{ 2264232812Sjmallett switch(cvmx_get_octeon_family()) { 2265232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2266232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2267232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2268232812Sjmallett break; 2269232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2270232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2271232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2272232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2273232812Sjmallett break; 2274232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2275232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2276232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2277232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2278232812Sjmallett break; 2279232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2280232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2281232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2282232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2283232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2284232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2285232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2286232812Sjmallett break; 2287232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2288232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2289232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2290232812Sjmallett break; 2291232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2292232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2293232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2294232812Sjmallett break; 2295232812Sjmallett } 2296232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT1 (%lu, %lu) not supported on this chip\n", offset, block_id); 2297232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2298215976Sjmallett} 2299215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id) 2300215976Sjmallett{ 2301232812Sjmallett switch(cvmx_get_octeon_family()) { 2302232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2303232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2304232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2305232812Sjmallett break; 2306232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2307232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2308232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2309232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2310232812Sjmallett break; 2311232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2312232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2313232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2314232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2315232812Sjmallett break; 2316232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2317232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2318232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2319232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2320232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2321232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2322232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2323232812Sjmallett break; 2324232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2325232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2326232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2327232812Sjmallett break; 2328232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2329232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2330232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2331232812Sjmallett break; 2332232812Sjmallett } 2333232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT2 (%lu, %lu) not supported on this chip\n", offset, block_id); 2334232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2335215976Sjmallett} 2336215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id) 2337215976Sjmallett{ 2338232812Sjmallett switch(cvmx_get_octeon_family()) { 2339232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2340232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2341232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2342232812Sjmallett break; 2343232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2344232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2345232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2346232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2347232812Sjmallett break; 2348232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2349232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2350232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2351232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2352232812Sjmallett break; 2353232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2354232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2355232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2356232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2357232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2358232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2359232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2360232812Sjmallett break; 2361232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2362232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2363232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2364232812Sjmallett break; 2365232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2366232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2367232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2368232812Sjmallett break; 2369232812Sjmallett } 2370232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT3 (%lu, %lu) not supported on this chip\n", offset, block_id); 2371232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2372215976Sjmallett} 2373215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id) 2374215976Sjmallett{ 2375232812Sjmallett switch(cvmx_get_octeon_family()) { 2376232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2377232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2378232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2379232812Sjmallett break; 2380232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2381232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2382232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2383232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2384232812Sjmallett break; 2385232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2386232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2387232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2388232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2389232812Sjmallett break; 2390232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2391232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2392232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2393232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2394232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2395232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2396232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2397232812Sjmallett break; 2398232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2399232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2400232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2401232812Sjmallett break; 2402232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2403232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2404232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2405232812Sjmallett break; 2406232812Sjmallett } 2407232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT4 (%lu, %lu) not supported on this chip\n", offset, block_id); 2408232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2409215976Sjmallett} 2410215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id) 2411215976Sjmallett{ 2412232812Sjmallett switch(cvmx_get_octeon_family()) { 2413232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2414232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2415232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2416232812Sjmallett break; 2417232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2418232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2419232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2420232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2421232812Sjmallett break; 2422232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2423232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2424232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2425232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2426232812Sjmallett break; 2427232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2428232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2429232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2430232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2431232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2432232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2433232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2434232812Sjmallett break; 2435232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2436232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2437232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2438232812Sjmallett break; 2439232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2440232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2441232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2442232812Sjmallett break; 2443232812Sjmallett } 2444232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT5 (%lu, %lu) not supported on this chip\n", offset, block_id); 2445232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2446215976Sjmallett} 2447215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id) 2448215976Sjmallett{ 2449232812Sjmallett switch(cvmx_get_octeon_family()) { 2450232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2451232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2452232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2453232812Sjmallett break; 2454232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2455232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2456232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2457232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2458232812Sjmallett break; 2459232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2460232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2461232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2462232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2463232812Sjmallett break; 2464232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2465232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2466232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2467232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2468232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2469232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2470232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2471232812Sjmallett break; 2472232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2473232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2474232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2475232812Sjmallett break; 2476232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2477232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2478232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2479232812Sjmallett break; 2480232812Sjmallett } 2481232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT6 (%lu, %lu) not supported on this chip\n", offset, block_id); 2482232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2483215976Sjmallett} 2484215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id) 2485215976Sjmallett{ 2486232812Sjmallett switch(cvmx_get_octeon_family()) { 2487232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2488232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2489232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2490232812Sjmallett break; 2491232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2492232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2493232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2494232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2495232812Sjmallett break; 2496232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2497232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2498232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2499232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2500232812Sjmallett break; 2501232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2502232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2503232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2504232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2505232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2506232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2507232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2508232812Sjmallett break; 2509232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2510232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2511232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2512232812Sjmallett break; 2513232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2514232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2515232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2516232812Sjmallett break; 2517232812Sjmallett } 2518232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT7 (%lu, %lu) not supported on this chip\n", offset, block_id); 2519232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2520215976Sjmallett} 2521215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id) 2522215976Sjmallett{ 2523232812Sjmallett switch(cvmx_get_octeon_family()) { 2524232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2525232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2526232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2527232812Sjmallett break; 2528232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2529232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2530232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2531232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2532232812Sjmallett break; 2533232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2534232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2535232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2536232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2537232812Sjmallett break; 2538232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2539232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2540232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2541232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2542232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2543232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2544232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2545232812Sjmallett break; 2546232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2547232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2548232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2549232812Sjmallett break; 2550232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2551232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2552232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2553232812Sjmallett break; 2554232812Sjmallett } 2555232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT8 (%lu, %lu) not supported on this chip\n", offset, block_id); 2556232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2557215976Sjmallett} 2558215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id) 2559215976Sjmallett{ 2560232812Sjmallett switch(cvmx_get_octeon_family()) { 2561232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2562232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2563232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2564232812Sjmallett break; 2565232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2566232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2567232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2568232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2569232812Sjmallett break; 2570232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2571232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2572232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2573232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2574232812Sjmallett break; 2575232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2576232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2577232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2578232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2579232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2580232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2581232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2582232812Sjmallett break; 2583232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2584232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2585232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2586232812Sjmallett break; 2587232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2588232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2589232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2590232812Sjmallett break; 2591232812Sjmallett } 2592232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STAT9 (%lu, %lu) not supported on this chip\n", offset, block_id); 2593232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2594215976Sjmallett} 2595215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id) 2596215976Sjmallett{ 2597232812Sjmallett switch(cvmx_get_octeon_family()) { 2598232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2599232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2600232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2601232812Sjmallett break; 2602232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2603232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2604232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2605232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2606232812Sjmallett break; 2607232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2608232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2609232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2610232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2611232812Sjmallett break; 2612232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2613232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2614232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2615232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2616232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2617232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2618232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2619232812Sjmallett break; 2620232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2621232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2622232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2623232812Sjmallett break; 2624232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2625232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2626232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2627232812Sjmallett break; 2628232812Sjmallett } 2629232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id); 2630232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2631215976Sjmallett} 2632215976Sjmallettstatic inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) 2633215976Sjmallett{ 2634232812Sjmallett switch(cvmx_get_octeon_family()) { 2635232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2636232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 2637232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2638232812Sjmallett break; 2639232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2640232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2641232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2642232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2643232812Sjmallett break; 2644232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2645232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2646232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 2647232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048; 2648232812Sjmallett break; 2649232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2650232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2651232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2652232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2653232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2654232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 2655232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048; 2656232812Sjmallett break; 2657232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2658232812Sjmallett if (((offset <= 2)) && ((block_id == 0))) 2659232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048; 2660232812Sjmallett break; 2661232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2662232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 2663232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048; 2664232812Sjmallett break; 2665232812Sjmallett } 2666232812Sjmallett cvmx_warn("CVMX_GMXX_TXX_THRESH (%lu, %lu) not supported on this chip\n", offset, block_id); 2667232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048; 2668215976Sjmallett} 2669215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id) 2670215976Sjmallett{ 2671232812Sjmallett switch(cvmx_get_octeon_family()) { 2672232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2673232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2674232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2675232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2676232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2677232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2678232812Sjmallett if ((block_id == 0)) 2679232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull; 2680232812Sjmallett break; 2681232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2682232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2683232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2684232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2685232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2686232812Sjmallett if ((block_id <= 1)) 2687232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull; 2688232812Sjmallett break; 2689232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2690232812Sjmallett if ((block_id <= 4)) 2691232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 7) * 0x1000000ull; 2692232812Sjmallett break; 2693232812Sjmallett } 2694232812Sjmallett cvmx_warn("CVMX_GMXX_TX_BP (block_id = %lu) not supported on this chip\n", block_id); 2695232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull; 2696215976Sjmallett} 2697215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2698215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id) 2699215976Sjmallett{ 2700215976Sjmallett if (!( 2701215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) || 2702215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0)))))) 2703215976Sjmallett cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id); 2704215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8; 2705215976Sjmallett} 2706215976Sjmallett#else 2707215976Sjmallett#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 2708215976Sjmallett#endif 2709215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id) 2710215976Sjmallett{ 2711232812Sjmallett switch(cvmx_get_octeon_family()) { 2712232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2713232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2714232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2715232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2716232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2717232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2718232812Sjmallett if ((block_id == 0)) 2719232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull; 2720232812Sjmallett break; 2721232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2722232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2723232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2724232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2725232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2726232812Sjmallett if ((block_id <= 1)) 2727232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull; 2728232812Sjmallett break; 2729232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2730232812Sjmallett if ((block_id <= 4)) 2731232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 7) * 0x1000000ull; 2732232812Sjmallett break; 2733232812Sjmallett } 2734232812Sjmallett cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT (block_id = %lu) not supported on this chip\n", block_id); 2735232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull; 2736215976Sjmallett} 2737215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id) 2738215976Sjmallett{ 2739232812Sjmallett switch(cvmx_get_octeon_family()) { 2740232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2741232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2742232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2743232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2744232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2745232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2746232812Sjmallett if ((block_id == 0)) 2747232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull; 2748232812Sjmallett break; 2749232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2750232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2751232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2752232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2753232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2754232812Sjmallett if ((block_id <= 1)) 2755232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull; 2756232812Sjmallett break; 2757232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2758232812Sjmallett if ((block_id <= 4)) 2759232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 7) * 0x1000000ull; 2760232812Sjmallett break; 2761232812Sjmallett } 2762232812Sjmallett cvmx_warn("CVMX_GMXX_TX_CORRUPT (block_id = %lu) not supported on this chip\n", block_id); 2763232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull; 2764215976Sjmallett} 2765215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id) 2766215976Sjmallett{ 2767232812Sjmallett switch(cvmx_get_octeon_family()) { 2768232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2769232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2770232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2771232812Sjmallett if ((block_id == 0)) 2772232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull; 2773232812Sjmallett break; 2774232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2775232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2776232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2777232812Sjmallett if ((block_id <= 1)) 2778232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull; 2779232812Sjmallett break; 2780232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2781232812Sjmallett if ((block_id <= 4)) 2782232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 7) * 0x1000000ull; 2783232812Sjmallett break; 2784232812Sjmallett } 2785232812Sjmallett cvmx_warn("CVMX_GMXX_TX_HG2_REG1 (block_id = %lu) not supported on this chip\n", block_id); 2786232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull; 2787215976Sjmallett} 2788215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id) 2789215976Sjmallett{ 2790232812Sjmallett switch(cvmx_get_octeon_family()) { 2791232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2792232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2793232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2794232812Sjmallett if ((block_id == 0)) 2795232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull; 2796232812Sjmallett break; 2797232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2798232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2799232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2800232812Sjmallett if ((block_id <= 1)) 2801232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull; 2802232812Sjmallett break; 2803232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2804232812Sjmallett if ((block_id <= 4)) 2805232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 7) * 0x1000000ull; 2806232812Sjmallett break; 2807232812Sjmallett } 2808232812Sjmallett cvmx_warn("CVMX_GMXX_TX_HG2_REG2 (block_id = %lu) not supported on this chip\n", block_id); 2809232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull; 2810215976Sjmallett} 2811215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id) 2812215976Sjmallett{ 2813232812Sjmallett switch(cvmx_get_octeon_family()) { 2814232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2815232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2816232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2817232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2818232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2819232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2820232812Sjmallett if ((block_id == 0)) 2821232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull; 2822232812Sjmallett break; 2823232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2824232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2825232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2826232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2827232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2828232812Sjmallett if ((block_id <= 1)) 2829232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull; 2830232812Sjmallett break; 2831232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2832232812Sjmallett if ((block_id <= 4)) 2833232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 7) * 0x1000000ull; 2834232812Sjmallett break; 2835232812Sjmallett } 2836232812Sjmallett cvmx_warn("CVMX_GMXX_TX_IFG (block_id = %lu) not supported on this chip\n", block_id); 2837232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull; 2838215976Sjmallett} 2839215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id) 2840215976Sjmallett{ 2841232812Sjmallett switch(cvmx_get_octeon_family()) { 2842232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2843232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2844232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2845232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2846232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2847232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2848232812Sjmallett if ((block_id == 0)) 2849232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull; 2850232812Sjmallett break; 2851232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2852232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2853232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2854232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2855232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2856232812Sjmallett if ((block_id <= 1)) 2857232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull; 2858232812Sjmallett break; 2859232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2860232812Sjmallett if ((block_id <= 4)) 2861232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 7) * 0x1000000ull; 2862232812Sjmallett break; 2863232812Sjmallett } 2864232812Sjmallett cvmx_warn("CVMX_GMXX_TX_INT_EN (block_id = %lu) not supported on this chip\n", block_id); 2865232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull; 2866215976Sjmallett} 2867215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id) 2868215976Sjmallett{ 2869232812Sjmallett switch(cvmx_get_octeon_family()) { 2870232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2871232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2872232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2873232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2874232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2875232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2876232812Sjmallett if ((block_id == 0)) 2877232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull; 2878232812Sjmallett break; 2879232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2880232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2881232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2882232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2883232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2884232812Sjmallett if ((block_id <= 1)) 2885232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull; 2886232812Sjmallett break; 2887232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2888232812Sjmallett if ((block_id <= 4)) 2889232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 7) * 0x1000000ull; 2890232812Sjmallett break; 2891232812Sjmallett } 2892232812Sjmallett cvmx_warn("CVMX_GMXX_TX_INT_REG (block_id = %lu) not supported on this chip\n", block_id); 2893232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull; 2894215976Sjmallett} 2895215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id) 2896215976Sjmallett{ 2897232812Sjmallett switch(cvmx_get_octeon_family()) { 2898232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2899232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2900232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2901232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2902232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2903232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2904232812Sjmallett if ((block_id == 0)) 2905232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull; 2906232812Sjmallett break; 2907232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2908232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2909232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2910232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2911232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2912232812Sjmallett if ((block_id <= 1)) 2913232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull; 2914232812Sjmallett break; 2915232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2916232812Sjmallett if ((block_id <= 4)) 2917232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 7) * 0x1000000ull; 2918232812Sjmallett break; 2919232812Sjmallett } 2920232812Sjmallett cvmx_warn("CVMX_GMXX_TX_JAM (block_id = %lu) not supported on this chip\n", block_id); 2921232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull; 2922215976Sjmallett} 2923215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id) 2924215976Sjmallett{ 2925232812Sjmallett switch(cvmx_get_octeon_family()) { 2926232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2927232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2928232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2929232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2930232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2931232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2932232812Sjmallett if ((block_id == 0)) 2933232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull; 2934232812Sjmallett break; 2935232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2936232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2937232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2938232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2939232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2940232812Sjmallett if ((block_id <= 1)) 2941232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull; 2942232812Sjmallett break; 2943232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2944232812Sjmallett if ((block_id <= 4)) 2945232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 7) * 0x1000000ull; 2946232812Sjmallett break; 2947232812Sjmallett } 2948232812Sjmallett cvmx_warn("CVMX_GMXX_TX_LFSR (block_id = %lu) not supported on this chip\n", block_id); 2949232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull; 2950215976Sjmallett} 2951215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id) 2952215976Sjmallett{ 2953232812Sjmallett switch(cvmx_get_octeon_family()) { 2954232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2955232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2956232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2957232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2958232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2959232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2960232812Sjmallett if ((block_id == 0)) 2961232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull; 2962232812Sjmallett break; 2963232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2964232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2965232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2966232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2967232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2968232812Sjmallett if ((block_id <= 1)) 2969232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull; 2970232812Sjmallett break; 2971232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2972232812Sjmallett if ((block_id <= 4)) 2973232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 7) * 0x1000000ull; 2974232812Sjmallett break; 2975232812Sjmallett } 2976232812Sjmallett cvmx_warn("CVMX_GMXX_TX_OVR_BP (block_id = %lu) not supported on this chip\n", block_id); 2977232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull; 2978215976Sjmallett} 2979215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id) 2980215976Sjmallett{ 2981232812Sjmallett switch(cvmx_get_octeon_family()) { 2982232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2983232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2984232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2985232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2986232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2987232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2988232812Sjmallett if ((block_id == 0)) 2989232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull; 2990232812Sjmallett break; 2991232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2992232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2993232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2994232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2995232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2996232812Sjmallett if ((block_id <= 1)) 2997232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull; 2998232812Sjmallett break; 2999232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 3000232812Sjmallett if ((block_id <= 4)) 3001232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 7) * 0x1000000ull; 3002232812Sjmallett break; 3003232812Sjmallett } 3004232812Sjmallett cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC (block_id = %lu) not supported on this chip\n", block_id); 3005232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull; 3006215976Sjmallett} 3007215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id) 3008215976Sjmallett{ 3009232812Sjmallett switch(cvmx_get_octeon_family()) { 3010232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 3011232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 3012232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 3013232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 3014232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 3015232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 3016232812Sjmallett if ((block_id == 0)) 3017232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull; 3018232812Sjmallett break; 3019232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 3020232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 3021232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 3022232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 3023232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 3024232812Sjmallett if ((block_id <= 1)) 3025232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull; 3026232812Sjmallett break; 3027232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 3028232812Sjmallett if ((block_id <= 4)) 3029232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 7) * 0x1000000ull; 3030232812Sjmallett break; 3031232812Sjmallett } 3032232812Sjmallett cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE (block_id = %lu) not supported on this chip\n", block_id); 3033232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull; 3034215976Sjmallett} 3035215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id) 3036215976Sjmallett{ 3037232812Sjmallett switch(cvmx_get_octeon_family()) { 3038232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 3039232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 3040232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 3041232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 3042232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 3043232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 3044232812Sjmallett if ((block_id == 0)) 3045232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull; 3046232812Sjmallett break; 3047232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 3048232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 3049232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 3050232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 3051232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 3052232812Sjmallett if ((block_id <= 1)) 3053232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull; 3054232812Sjmallett break; 3055232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 3056232812Sjmallett if ((block_id <= 4)) 3057232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 7) * 0x1000000ull; 3058232812Sjmallett break; 3059232812Sjmallett } 3060232812Sjmallett cvmx_warn("CVMX_GMXX_TX_PRTS (block_id = %lu) not supported on this chip\n", block_id); 3061232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull; 3062215976Sjmallett} 3063215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3064215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id) 3065215976Sjmallett{ 3066215976Sjmallett if (!( 3067215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 3068215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 3069215976Sjmallett cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n", block_id); 3070215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull; 3071215976Sjmallett} 3072215976Sjmallett#else 3073215976Sjmallett#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) 3074215976Sjmallett#endif 3075215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3076215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id) 3077215976Sjmallett{ 3078215976Sjmallett if (!( 3079215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 3080215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 3081215976Sjmallett cvmx_warn("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n", block_id); 3082215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull; 3083215976Sjmallett} 3084215976Sjmallett#else 3085215976Sjmallett#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull) 3086215976Sjmallett#endif 3087215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3088215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id) 3089215976Sjmallett{ 3090215976Sjmallett if (!( 3091215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 3092215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 3093215976Sjmallett cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n", block_id); 3094215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull; 3095215976Sjmallett} 3096215976Sjmallett#else 3097215976Sjmallett#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) 3098215976Sjmallett#endif 3099215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3100215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id) 3101215976Sjmallett{ 3102215976Sjmallett if (!( 3103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 3104215976Sjmallett cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id); 3105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 3106215976Sjmallett} 3107215976Sjmallett#else 3108215976Sjmallett#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 3109215976Sjmallett#endif 3110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3111215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id) 3112215976Sjmallett{ 3113215976Sjmallett if (!( 3114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 3115215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 3116215976Sjmallett cvmx_warn("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n", block_id); 3117215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull; 3118215976Sjmallett} 3119215976Sjmallett#else 3120215976Sjmallett#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) 3121215976Sjmallett#endif 3122215976Sjmallettstatic inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) 3123215976Sjmallett{ 3124232812Sjmallett switch(cvmx_get_octeon_family()) { 3125232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 3126232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 3127232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 3128232812Sjmallett if ((block_id == 0)) 3129232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull; 3130232812Sjmallett break; 3131232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 3132232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 3133232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 3134232812Sjmallett if ((block_id <= 1)) 3135232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull; 3136232812Sjmallett break; 3137232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 3138232812Sjmallett if ((block_id <= 4)) 3139232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 7) * 0x1000000ull; 3140232812Sjmallett break; 3141232812Sjmallett } 3142232812Sjmallett cvmx_warn("CVMX_GMXX_TX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id); 3143232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull; 3144215976Sjmallett} 3145215976Sjmallettstatic inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id) 3146215976Sjmallett{ 3147232812Sjmallett switch(cvmx_get_octeon_family()) { 3148232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 3149232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 3150232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 3151232812Sjmallett if ((block_id == 0)) 3152232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull; 3153232812Sjmallett break; 3154232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 3155232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 3156232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 3157232812Sjmallett if ((block_id <= 1)) 3158232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull; 3159232812Sjmallett break; 3160232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 3161232812Sjmallett if ((block_id <= 4)) 3162232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 7) * 0x1000000ull; 3163232812Sjmallett break; 3164232812Sjmallett } 3165232812Sjmallett cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK (block_id = %lu) not supported on this chip\n", block_id); 3166232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull; 3167215976Sjmallett} 3168215976Sjmallett 3169215976Sjmallett/** 3170215976Sjmallett * cvmx_gmx#_bad_reg 3171215976Sjmallett * 3172215976Sjmallett * GMX_BAD_REG = A collection of things that have gone very, very wrong 3173215976Sjmallett * 3174215976Sjmallett * 3175215976Sjmallett * Notes: 3176215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used. 3177215976Sjmallett * 3178215976Sjmallett */ 3179232812Sjmallettunion cvmx_gmxx_bad_reg { 3180215976Sjmallett uint64_t u64; 3181232812Sjmallett struct cvmx_gmxx_bad_reg_s { 3182232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3183215976Sjmallett uint64_t reserved_31_63 : 33; 3184215976Sjmallett uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */ 3185215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow 3186215976Sjmallett The common FIFO to SGMII and XAUI had an overflow 3187215976Sjmallett TX Stats are corrupted */ 3188215976Sjmallett uint64_t loststat : 4; /**< TX Statistics data was over-written 3189215976Sjmallett In SGMII, one bit per port 3190215976Sjmallett In XAUI, only port0 is used 3191215976Sjmallett TX Stats are corrupted */ 3192215976Sjmallett uint64_t reserved_18_21 : 4; 3193215976Sjmallett uint64_t out_ovr : 16; /**< Outbound data FIFO overflow (per port) */ 3194215976Sjmallett uint64_t ncb_ovr : 1; /**< Outbound NCB FIFO Overflow */ 3195215976Sjmallett uint64_t out_col : 1; /**< Outbound collision occured between PKO and NCB */ 3196215976Sjmallett#else 3197215976Sjmallett uint64_t out_col : 1; 3198215976Sjmallett uint64_t ncb_ovr : 1; 3199215976Sjmallett uint64_t out_ovr : 16; 3200215976Sjmallett uint64_t reserved_18_21 : 4; 3201215976Sjmallett uint64_t loststat : 4; 3202215976Sjmallett uint64_t statovr : 1; 3203215976Sjmallett uint64_t inb_nxa : 4; 3204215976Sjmallett uint64_t reserved_31_63 : 33; 3205215976Sjmallett#endif 3206215976Sjmallett } s; 3207232812Sjmallett struct cvmx_gmxx_bad_reg_cn30xx { 3208232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3209215976Sjmallett uint64_t reserved_31_63 : 33; 3210215976Sjmallett uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */ 3211215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 3212215976Sjmallett uint64_t reserved_25_25 : 1; 3213215976Sjmallett uint64_t loststat : 3; /**< TX Statistics data was over-written (per RGM port) 3214215976Sjmallett TX Stats are corrupted */ 3215215976Sjmallett uint64_t reserved_5_21 : 17; 3216215976Sjmallett uint64_t out_ovr : 3; /**< Outbound data FIFO overflow (per port) */ 3217215976Sjmallett uint64_t reserved_0_1 : 2; 3218215976Sjmallett#else 3219215976Sjmallett uint64_t reserved_0_1 : 2; 3220215976Sjmallett uint64_t out_ovr : 3; 3221215976Sjmallett uint64_t reserved_5_21 : 17; 3222215976Sjmallett uint64_t loststat : 3; 3223215976Sjmallett uint64_t reserved_25_25 : 1; 3224215976Sjmallett uint64_t statovr : 1; 3225215976Sjmallett uint64_t inb_nxa : 4; 3226215976Sjmallett uint64_t reserved_31_63 : 33; 3227215976Sjmallett#endif 3228215976Sjmallett } cn30xx; 3229215976Sjmallett struct cvmx_gmxx_bad_reg_cn30xx cn31xx; 3230215976Sjmallett struct cvmx_gmxx_bad_reg_s cn38xx; 3231215976Sjmallett struct cvmx_gmxx_bad_reg_s cn38xxp2; 3232215976Sjmallett struct cvmx_gmxx_bad_reg_cn30xx cn50xx; 3233232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx { 3234232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3235215976Sjmallett uint64_t reserved_31_63 : 33; 3236215976Sjmallett uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */ 3237215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow 3238215976Sjmallett The common FIFO to SGMII and XAUI had an overflow 3239215976Sjmallett TX Stats are corrupted */ 3240215976Sjmallett uint64_t loststat : 4; /**< TX Statistics data was over-written 3241215976Sjmallett In SGMII, one bit per port 3242215976Sjmallett In XAUI, only port0 is used 3243215976Sjmallett TX Stats are corrupted */ 3244215976Sjmallett uint64_t reserved_6_21 : 16; 3245215976Sjmallett uint64_t out_ovr : 4; /**< Outbound data FIFO overflow (per port) */ 3246215976Sjmallett uint64_t reserved_0_1 : 2; 3247215976Sjmallett#else 3248215976Sjmallett uint64_t reserved_0_1 : 2; 3249215976Sjmallett uint64_t out_ovr : 4; 3250215976Sjmallett uint64_t reserved_6_21 : 16; 3251215976Sjmallett uint64_t loststat : 4; 3252215976Sjmallett uint64_t statovr : 1; 3253215976Sjmallett uint64_t inb_nxa : 4; 3254215976Sjmallett uint64_t reserved_31_63 : 33; 3255215976Sjmallett#endif 3256215976Sjmallett } cn52xx; 3257215976Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; 3258215976Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn56xx; 3259215976Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; 3260215976Sjmallett struct cvmx_gmxx_bad_reg_s cn58xx; 3261215976Sjmallett struct cvmx_gmxx_bad_reg_s cn58xxp1; 3262232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn61xx; 3263215976Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn63xx; 3264215976Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1; 3265232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn66xx; 3266232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn68xx; 3267232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1; 3268232812Sjmallett struct cvmx_gmxx_bad_reg_cn52xx cnf71xx; 3269215976Sjmallett}; 3270215976Sjmalletttypedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t; 3271215976Sjmallett 3272215976Sjmallett/** 3273215976Sjmallett * cvmx_gmx#_bist 3274215976Sjmallett * 3275215976Sjmallett * GMX_BIST = GMX BIST Results 3276215976Sjmallett * 3277215976Sjmallett */ 3278232812Sjmallettunion cvmx_gmxx_bist { 3279215976Sjmallett uint64_t u64; 3280232812Sjmallett struct cvmx_gmxx_bist_s { 3281232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3282215976Sjmallett uint64_t reserved_25_63 : 39; 3283215976Sjmallett uint64_t status : 25; /**< BIST Results. 3284215976Sjmallett HW sets a bit in BIST for for memory that fails 3285215976Sjmallett - 0: gmx#.inb.fif_bnk0 3286215976Sjmallett - 1: gmx#.inb.fif_bnk1 3287215976Sjmallett - 2: gmx#.inb.fif_bnk2 3288215976Sjmallett - 3: gmx#.inb.fif_bnk3 3289215976Sjmallett - 4: gmx#.inb.fif_bnk_ext0 3290215976Sjmallett - 5: gmx#.inb.fif_bnk_ext1 3291215976Sjmallett - 6: gmx#.inb.fif_bnk_ext2 3292215976Sjmallett - 7: gmx#.inb.fif_bnk_ext3 3293215976Sjmallett - 8: gmx#.outb.fif.fif_bnk0 3294215976Sjmallett - 9: gmx#.outb.fif.fif_bnk1 3295215976Sjmallett - 10: gmx#.outb.fif.fif_bnk2 3296215976Sjmallett - 11: gmx#.outb.fif.fif_bnk3 3297215976Sjmallett - 12: gmx#.outb.fif.fif_bnk_ext0 3298215976Sjmallett - 13: gmx#.outb.fif.fif_bnk_ext1 3299215976Sjmallett - 14: gmx#.outb.fif.fif_bnk_ext2 3300215976Sjmallett - 15: gmx#.outb.fif.fif_bnk_ext3 3301215976Sjmallett - 16: gmx#.csr.gmi0.srf8x64m1_bist 3302215976Sjmallett - 17: gmx#.csr.gmi1.srf8x64m1_bist 3303215976Sjmallett - 18: gmx#.csr.gmi2.srf8x64m1_bist 3304215976Sjmallett - 19: gmx#.csr.gmi3.srf8x64m1_bist 3305215976Sjmallett - 20: gmx#.csr.drf20x32m2_bist 3306215976Sjmallett - 21: gmx#.csr.drf20x48m2_bist 3307215976Sjmallett - 22: gmx#.outb.stat.drf16x27m1_bist 3308215976Sjmallett - 23: gmx#.outb.stat.drf40x64m1_bist 3309215976Sjmallett - 24: xgmii.tx.drf16x38m1_async_bist */ 3310215976Sjmallett#else 3311215976Sjmallett uint64_t status : 25; 3312215976Sjmallett uint64_t reserved_25_63 : 39; 3313215976Sjmallett#endif 3314215976Sjmallett } s; 3315232812Sjmallett struct cvmx_gmxx_bist_cn30xx { 3316232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3317215976Sjmallett uint64_t reserved_10_63 : 54; 3318215976Sjmallett uint64_t status : 10; /**< BIST Results. 3319215976Sjmallett HW sets a bit in BIST for for memory that fails 3320215976Sjmallett - 0: gmx#.inb.dpr512x78m4_bist 3321215976Sjmallett - 1: gmx#.outb.fif.dpr512x71m4_bist 3322215976Sjmallett - 2: gmx#.csr.gmi0.srf8x64m1_bist 3323215976Sjmallett - 3: gmx#.csr.gmi1.srf8x64m1_bist 3324215976Sjmallett - 4: gmx#.csr.gmi2.srf8x64m1_bist 3325215976Sjmallett - 5: 0 3326215976Sjmallett - 6: gmx#.csr.drf20x80m1_bist 3327215976Sjmallett - 7: gmx#.outb.stat.drf16x27m1_bist 3328215976Sjmallett - 8: gmx#.outb.stat.drf40x64m1_bist 3329215976Sjmallett - 9: 0 */ 3330215976Sjmallett#else 3331215976Sjmallett uint64_t status : 10; 3332215976Sjmallett uint64_t reserved_10_63 : 54; 3333215976Sjmallett#endif 3334215976Sjmallett } cn30xx; 3335215976Sjmallett struct cvmx_gmxx_bist_cn30xx cn31xx; 3336215976Sjmallett struct cvmx_gmxx_bist_cn30xx cn38xx; 3337215976Sjmallett struct cvmx_gmxx_bist_cn30xx cn38xxp2; 3338232812Sjmallett struct cvmx_gmxx_bist_cn50xx { 3339232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3340215976Sjmallett uint64_t reserved_12_63 : 52; 3341215976Sjmallett uint64_t status : 12; /**< BIST Results. 3342215976Sjmallett HW sets a bit in BIST for for memory that fails */ 3343215976Sjmallett#else 3344215976Sjmallett uint64_t status : 12; 3345215976Sjmallett uint64_t reserved_12_63 : 52; 3346215976Sjmallett#endif 3347215976Sjmallett } cn50xx; 3348232812Sjmallett struct cvmx_gmxx_bist_cn52xx { 3349232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3350215976Sjmallett uint64_t reserved_16_63 : 48; 3351215976Sjmallett uint64_t status : 16; /**< BIST Results. 3352215976Sjmallett HW sets a bit in BIST for for memory that fails 3353215976Sjmallett - 0: gmx#.inb.fif_bnk0 3354215976Sjmallett - 1: gmx#.inb.fif_bnk1 3355215976Sjmallett - 2: gmx#.inb.fif_bnk2 3356215976Sjmallett - 3: gmx#.inb.fif_bnk3 3357215976Sjmallett - 4: gmx#.outb.fif.fif_bnk0 3358215976Sjmallett - 5: gmx#.outb.fif.fif_bnk1 3359215976Sjmallett - 6: gmx#.outb.fif.fif_bnk2 3360215976Sjmallett - 7: gmx#.outb.fif.fif_bnk3 3361215976Sjmallett - 8: gmx#.csr.gmi0.srf8x64m1_bist 3362215976Sjmallett - 9: gmx#.csr.gmi1.srf8x64m1_bist 3363215976Sjmallett - 10: gmx#.csr.gmi2.srf8x64m1_bist 3364215976Sjmallett - 11: gmx#.csr.gmi3.srf8x64m1_bist 3365215976Sjmallett - 12: gmx#.csr.drf20x80m1_bist 3366215976Sjmallett - 13: gmx#.outb.stat.drf16x27m1_bist 3367215976Sjmallett - 14: gmx#.outb.stat.drf40x64m1_bist 3368215976Sjmallett - 15: xgmii.tx.drf16x38m1_async_bist */ 3369215976Sjmallett#else 3370215976Sjmallett uint64_t status : 16; 3371215976Sjmallett uint64_t reserved_16_63 : 48; 3372215976Sjmallett#endif 3373215976Sjmallett } cn52xx; 3374215976Sjmallett struct cvmx_gmxx_bist_cn52xx cn52xxp1; 3375215976Sjmallett struct cvmx_gmxx_bist_cn52xx cn56xx; 3376215976Sjmallett struct cvmx_gmxx_bist_cn52xx cn56xxp1; 3377232812Sjmallett struct cvmx_gmxx_bist_cn58xx { 3378232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3379215976Sjmallett uint64_t reserved_17_63 : 47; 3380215976Sjmallett uint64_t status : 17; /**< BIST Results. 3381215976Sjmallett HW sets a bit in BIST for for memory that fails 3382215976Sjmallett - 0: gmx#.inb.fif_bnk0 3383215976Sjmallett - 1: gmx#.inb.fif_bnk1 3384215976Sjmallett - 2: gmx#.inb.fif_bnk2 3385215976Sjmallett - 3: gmx#.inb.fif_bnk3 3386215976Sjmallett - 4: gmx#.outb.fif.fif_bnk0 3387215976Sjmallett - 5: gmx#.outb.fif.fif_bnk1 3388215976Sjmallett - 6: gmx#.outb.fif.fif_bnk2 3389215976Sjmallett - 7: gmx#.outb.fif.fif_bnk3 3390215976Sjmallett - 8: gmx#.csr.gmi0.srf8x64m1_bist 3391215976Sjmallett - 9: gmx#.csr.gmi1.srf8x64m1_bist 3392215976Sjmallett - 10: gmx#.csr.gmi2.srf8x64m1_bist 3393215976Sjmallett - 11: gmx#.csr.gmi3.srf8x64m1_bist 3394215976Sjmallett - 12: gmx#.csr.drf20x80m1_bist 3395215976Sjmallett - 13: gmx#.outb.stat.drf16x27m1_bist 3396215976Sjmallett - 14: gmx#.outb.stat.drf40x64m1_bist 3397215976Sjmallett - 15: gmx#.outb.ncb.drf16x76m1_bist 3398215976Sjmallett - 16: gmx#.outb.fif.srf32x16m2_bist */ 3399215976Sjmallett#else 3400215976Sjmallett uint64_t status : 17; 3401215976Sjmallett uint64_t reserved_17_63 : 47; 3402215976Sjmallett#endif 3403215976Sjmallett } cn58xx; 3404215976Sjmallett struct cvmx_gmxx_bist_cn58xx cn58xxp1; 3405232812Sjmallett struct cvmx_gmxx_bist_s cn61xx; 3406215976Sjmallett struct cvmx_gmxx_bist_s cn63xx; 3407215976Sjmallett struct cvmx_gmxx_bist_s cn63xxp1; 3408232812Sjmallett struct cvmx_gmxx_bist_s cn66xx; 3409232812Sjmallett struct cvmx_gmxx_bist_s cn68xx; 3410232812Sjmallett struct cvmx_gmxx_bist_s cn68xxp1; 3411232812Sjmallett struct cvmx_gmxx_bist_s cnf71xx; 3412215976Sjmallett}; 3413215976Sjmalletttypedef union cvmx_gmxx_bist cvmx_gmxx_bist_t; 3414215976Sjmallett 3415215976Sjmallett/** 3416232812Sjmallett * cvmx_gmx#_bpid_map# 3417232812Sjmallett * 3418232812Sjmallett * Notes: 3419232812Sjmallett * GMX will build BPID_VECTOR<15:0> using the 16 GMX_BPID_MAP entries and the BPID 3420232812Sjmallett * state from IPD. In XAUI/RXAUI mode when PFC/CBFC/HiGig2 is used, the 3421232812Sjmallett * BPID_VECTOR becomes the logical backpressure. In XAUI/RXAUI mode when 3422232812Sjmallett * PFC/CBFC/HiGig2 is not used or when in 4xSGMII mode, the BPID_VECTOR can be used 3423232812Sjmallett * with the GMX_BPID_MSK register to determine the physical backpressure. 3424232812Sjmallett * 3425232812Sjmallett * In XAUI/RXAUI mode, the entire BPID_VECTOR<15:0> is available determining physical 3426232812Sjmallett * backpressure for the single XAUI/RXAUI interface. 3427232812Sjmallett * 3428232812Sjmallett * In SGMII mode, BPID_VECTOR is broken up as follows: 3429232812Sjmallett * SGMII interface0 uses BPID_VECTOR<3:0> 3430232812Sjmallett * SGMII interface1 uses BPID_VECTOR<7:4> 3431232812Sjmallett * SGMII interface2 uses BPID_VECTOR<11:8> 3432232812Sjmallett * SGMII interface3 uses BPID_VECTOR<15:12> 3433232812Sjmallett * 3434232812Sjmallett * In all SGMII configurations, and in some XAUI/RXAUI configurations, the 3435232812Sjmallett * interface protocols only support physical backpressure. In these cases, a single 3436232812Sjmallett * BPID will commonly drive the physical backpressure for the physical 3437232812Sjmallett * interface. We provide example programmings for these simple cases. 3438232812Sjmallett * 3439232812Sjmallett * In XAUI/RXAUI mode where PFC/CBFC/HiGig2 is not used, an example programming 3440232812Sjmallett * would be as follows: 3441232812Sjmallett * 3442232812Sjmallett * @verbatim 3443232812Sjmallett * GMX_BPID_MAP0[VAL] = 1; 3444232812Sjmallett * GMX_BPID_MAP0[BPID] = xaui_bpid; 3445232812Sjmallett * GMX_BPID_MSK[MSK_OR] = 1; 3446232812Sjmallett * GMX_BPID_MSK[MSK_AND] = 0; 3447232812Sjmallett * @endverbatim 3448232812Sjmallett * 3449232812Sjmallett * In SGMII mode, an example programming would be as follows: 3450232812Sjmallett * 3451232812Sjmallett * @verbatim 3452232812Sjmallett * for (i=0; i<4; i++) [ 3453232812Sjmallett * if (GMX_PRTi_CFG[EN]) [ 3454232812Sjmallett * GMX_BPID_MAP(i*4)[VAL] = 1; 3455232812Sjmallett * GMX_BPID_MAP(i*4)[BPID] = sgmii_bpid(i); 3456232812Sjmallett * GMX_BPID_MSK[MSK_OR] = (1 << (i*4)) | GMX_BPID_MSK[MSK_OR]; 3457232812Sjmallett * ] 3458232812Sjmallett * ] 3459232812Sjmallett * GMX_BPID_MSK[MSK_AND] = 0; 3460232812Sjmallett * @endverbatim 3461232812Sjmallett */ 3462232812Sjmallettunion cvmx_gmxx_bpid_mapx { 3463232812Sjmallett uint64_t u64; 3464232812Sjmallett struct cvmx_gmxx_bpid_mapx_s { 3465232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3466232812Sjmallett uint64_t reserved_17_63 : 47; 3467232812Sjmallett uint64_t status : 1; /**< Current received BP from IPD */ 3468232812Sjmallett uint64_t reserved_9_15 : 7; 3469232812Sjmallett uint64_t val : 1; /**< Table entry is valid */ 3470232812Sjmallett uint64_t reserved_6_7 : 2; 3471232812Sjmallett uint64_t bpid : 6; /**< Backpressure ID the entry maps to */ 3472232812Sjmallett#else 3473232812Sjmallett uint64_t bpid : 6; 3474232812Sjmallett uint64_t reserved_6_7 : 2; 3475232812Sjmallett uint64_t val : 1; 3476232812Sjmallett uint64_t reserved_9_15 : 7; 3477232812Sjmallett uint64_t status : 1; 3478232812Sjmallett uint64_t reserved_17_63 : 47; 3479232812Sjmallett#endif 3480232812Sjmallett } s; 3481232812Sjmallett struct cvmx_gmxx_bpid_mapx_s cn68xx; 3482232812Sjmallett struct cvmx_gmxx_bpid_mapx_s cn68xxp1; 3483232812Sjmallett}; 3484232812Sjmalletttypedef union cvmx_gmxx_bpid_mapx cvmx_gmxx_bpid_mapx_t; 3485232812Sjmallett 3486232812Sjmallett/** 3487232812Sjmallett * cvmx_gmx#_bpid_msk 3488232812Sjmallett */ 3489232812Sjmallettunion cvmx_gmxx_bpid_msk { 3490232812Sjmallett uint64_t u64; 3491232812Sjmallett struct cvmx_gmxx_bpid_msk_s { 3492232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3493232812Sjmallett uint64_t reserved_48_63 : 16; 3494232812Sjmallett uint64_t msk_or : 16; /**< Assert physical BP when the backpressure ID vector 3495232812Sjmallett combined with MSK_OR indicates BP as follows. 3496232812Sjmallett phys_bp_msk_or = 3497232812Sjmallett (BPID_VECTOR<x:y> & MSK_OR<x:y>) != 0 3498232812Sjmallett phys_bp = phys_bp_msk_or || phys_bp_msk_and 3499232812Sjmallett In XAUI/RXAUI mode, x=15, y=0 3500232812Sjmallett In SGMII mode, x/y are set depending on the SGMII 3501232812Sjmallett interface. 3502232812Sjmallett SGMII interface0, x=3, y=0 3503232812Sjmallett SGMII interface1, x=7, y=4 3504232812Sjmallett SGMII interface2, x=11, y=8 3505232812Sjmallett SGMII interface3, x=15, y=12 */ 3506232812Sjmallett uint64_t reserved_16_31 : 16; 3507232812Sjmallett uint64_t msk_and : 16; /**< Assert physical BP when the backpressure ID vector 3508232812Sjmallett combined with MSK_AND indicates BP as follows. 3509232812Sjmallett phys_bp_msk_and = 3510232812Sjmallett (BPID_VECTOR<x:y> & MSK_AND<x:y>) == MSK_AND<x:y> 3511232812Sjmallett phys_bp = phys_bp_msk_or || phys_bp_msk_and 3512232812Sjmallett In XAUI/RXAUI mode, x=15, y=0 3513232812Sjmallett In SGMII mode, x/y are set depending on the SGMII 3514232812Sjmallett interface. 3515232812Sjmallett SGMII interface0, x=3, y=0 3516232812Sjmallett SGMII interface1, x=7, y=4 3517232812Sjmallett SGMII interface2, x=11, y=8 3518232812Sjmallett SGMII interface3, x=15, y=12 */ 3519232812Sjmallett#else 3520232812Sjmallett uint64_t msk_and : 16; 3521232812Sjmallett uint64_t reserved_16_31 : 16; 3522232812Sjmallett uint64_t msk_or : 16; 3523232812Sjmallett uint64_t reserved_48_63 : 16; 3524232812Sjmallett#endif 3525232812Sjmallett } s; 3526232812Sjmallett struct cvmx_gmxx_bpid_msk_s cn68xx; 3527232812Sjmallett struct cvmx_gmxx_bpid_msk_s cn68xxp1; 3528232812Sjmallett}; 3529232812Sjmalletttypedef union cvmx_gmxx_bpid_msk cvmx_gmxx_bpid_msk_t; 3530232812Sjmallett 3531232812Sjmallett/** 3532215976Sjmallett * cvmx_gmx#_clk_en 3533215976Sjmallett * 3534232812Sjmallett * DON'T PUT IN HRM* 3535215976Sjmallett * 3536215976Sjmallett */ 3537232812Sjmallettunion cvmx_gmxx_clk_en { 3538215976Sjmallett uint64_t u64; 3539232812Sjmallett struct cvmx_gmxx_clk_en_s { 3540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3541215976Sjmallett uint64_t reserved_1_63 : 63; 3542215976Sjmallett uint64_t clk_en : 1; /**< Force the clock enables on */ 3543215976Sjmallett#else 3544215976Sjmallett uint64_t clk_en : 1; 3545215976Sjmallett uint64_t reserved_1_63 : 63; 3546215976Sjmallett#endif 3547215976Sjmallett } s; 3548215976Sjmallett struct cvmx_gmxx_clk_en_s cn52xx; 3549215976Sjmallett struct cvmx_gmxx_clk_en_s cn52xxp1; 3550215976Sjmallett struct cvmx_gmxx_clk_en_s cn56xx; 3551215976Sjmallett struct cvmx_gmxx_clk_en_s cn56xxp1; 3552232812Sjmallett struct cvmx_gmxx_clk_en_s cn61xx; 3553215976Sjmallett struct cvmx_gmxx_clk_en_s cn63xx; 3554215976Sjmallett struct cvmx_gmxx_clk_en_s cn63xxp1; 3555232812Sjmallett struct cvmx_gmxx_clk_en_s cn66xx; 3556232812Sjmallett struct cvmx_gmxx_clk_en_s cn68xx; 3557232812Sjmallett struct cvmx_gmxx_clk_en_s cn68xxp1; 3558232812Sjmallett struct cvmx_gmxx_clk_en_s cnf71xx; 3559215976Sjmallett}; 3560215976Sjmalletttypedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t; 3561215976Sjmallett 3562215976Sjmallett/** 3563232812Sjmallett * cvmx_gmx#_ebp_dis 3564232812Sjmallett */ 3565232812Sjmallettunion cvmx_gmxx_ebp_dis { 3566232812Sjmallett uint64_t u64; 3567232812Sjmallett struct cvmx_gmxx_ebp_dis_s { 3568232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3569232812Sjmallett uint64_t reserved_16_63 : 48; 3570232812Sjmallett uint64_t dis : 16; /**< BP channel disable 3571232812Sjmallett GMX has the ability to remap unused channels 3572232812Sjmallett in order to get down to GMX_TX_PIPE[NUMP] 3573232812Sjmallett channels. */ 3574232812Sjmallett#else 3575232812Sjmallett uint64_t dis : 16; 3576232812Sjmallett uint64_t reserved_16_63 : 48; 3577232812Sjmallett#endif 3578232812Sjmallett } s; 3579232812Sjmallett struct cvmx_gmxx_ebp_dis_s cn68xx; 3580232812Sjmallett struct cvmx_gmxx_ebp_dis_s cn68xxp1; 3581232812Sjmallett}; 3582232812Sjmalletttypedef union cvmx_gmxx_ebp_dis cvmx_gmxx_ebp_dis_t; 3583232812Sjmallett 3584232812Sjmallett/** 3585232812Sjmallett * cvmx_gmx#_ebp_msk 3586232812Sjmallett */ 3587232812Sjmallettunion cvmx_gmxx_ebp_msk { 3588232812Sjmallett uint64_t u64; 3589232812Sjmallett struct cvmx_gmxx_ebp_msk_s { 3590232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3591232812Sjmallett uint64_t reserved_16_63 : 48; 3592232812Sjmallett uint64_t msk : 16; /**< BP channel mask 3593232812Sjmallett GMX can completely ignore the channel BP for 3594232812Sjmallett channels specified by the MSK field. Any channel 3595232812Sjmallett in which MSK == 1, will never send BP information 3596232812Sjmallett to PKO. */ 3597232812Sjmallett#else 3598232812Sjmallett uint64_t msk : 16; 3599232812Sjmallett uint64_t reserved_16_63 : 48; 3600232812Sjmallett#endif 3601232812Sjmallett } s; 3602232812Sjmallett struct cvmx_gmxx_ebp_msk_s cn68xx; 3603232812Sjmallett struct cvmx_gmxx_ebp_msk_s cn68xxp1; 3604232812Sjmallett}; 3605232812Sjmalletttypedef union cvmx_gmxx_ebp_msk cvmx_gmxx_ebp_msk_t; 3606232812Sjmallett 3607232812Sjmallett/** 3608215976Sjmallett * cvmx_gmx#_hg2_control 3609215976Sjmallett * 3610215976Sjmallett * Notes: 3611215976Sjmallett * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However 3612215976Sjmallett * setting just the TX or RX bit will result in only the HG2 message transmit or the receive 3613215976Sjmallett * capability. 3614215976Sjmallett * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received 3615215976Sjmallett * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages 3616215976Sjmallett * are disabled. 3617215976Sjmallett * 3618215976Sjmallett * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN 3619215976Sjmallett * are set. 3620215976Sjmallett * 3621215976Sjmallett * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN 3622215976Sjmallett * are set. 3623215976Sjmallett * 3624215976Sjmallett * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero 3625215976Sjmallett * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when 3626215976Sjmallett * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1 3627215976Sjmallett * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages 3628215976Sjmallett * (optionally, when HG2TX_EN=1) with the HiGig2 protocol. 3629215976Sjmallett */ 3630232812Sjmallettunion cvmx_gmxx_hg2_control { 3631215976Sjmallett uint64_t u64; 3632232812Sjmallett struct cvmx_gmxx_hg2_control_s { 3633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3634215976Sjmallett uint64_t reserved_19_63 : 45; 3635215976Sjmallett uint64_t hg2tx_en : 1; /**< Enable Transmission of HG2 phys and logl messages 3636215976Sjmallett When set, also disables HW auto-generated (802.3 3637215976Sjmallett and CBFC) pause frames. (OCTEON cannot generate 3638215976Sjmallett proper 802.3 or CBFC pause frames in HiGig2 mode.) */ 3639215976Sjmallett uint64_t hg2rx_en : 1; /**< Enable extraction and processing of HG2 message 3640215976Sjmallett packet from RX flow. Physical logical pause info 3641215976Sjmallett is used to pause physical link, back pressure PKO 3642215976Sjmallett HG2RX_EN must be set when HiGig2 messages are 3643215976Sjmallett present in the receive stream. */ 3644215976Sjmallett uint64_t phys_en : 1; /**< 1 bit physical link pause enable for recevied 3645215976Sjmallett HiGig2 physical pause message */ 3646215976Sjmallett uint64_t logl_en : 16; /**< 16 bit xof enables for recevied HiGig2 messages 3647215976Sjmallett or CBFC packets */ 3648215976Sjmallett#else 3649215976Sjmallett uint64_t logl_en : 16; 3650215976Sjmallett uint64_t phys_en : 1; 3651215976Sjmallett uint64_t hg2rx_en : 1; 3652215976Sjmallett uint64_t hg2tx_en : 1; 3653215976Sjmallett uint64_t reserved_19_63 : 45; 3654215976Sjmallett#endif 3655215976Sjmallett } s; 3656215976Sjmallett struct cvmx_gmxx_hg2_control_s cn52xx; 3657215976Sjmallett struct cvmx_gmxx_hg2_control_s cn52xxp1; 3658215976Sjmallett struct cvmx_gmxx_hg2_control_s cn56xx; 3659232812Sjmallett struct cvmx_gmxx_hg2_control_s cn61xx; 3660215976Sjmallett struct cvmx_gmxx_hg2_control_s cn63xx; 3661215976Sjmallett struct cvmx_gmxx_hg2_control_s cn63xxp1; 3662232812Sjmallett struct cvmx_gmxx_hg2_control_s cn66xx; 3663232812Sjmallett struct cvmx_gmxx_hg2_control_s cn68xx; 3664232812Sjmallett struct cvmx_gmxx_hg2_control_s cn68xxp1; 3665232812Sjmallett struct cvmx_gmxx_hg2_control_s cnf71xx; 3666215976Sjmallett}; 3667215976Sjmalletttypedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t; 3668215976Sjmallett 3669215976Sjmallett/** 3670215976Sjmallett * cvmx_gmx#_inf_mode 3671215976Sjmallett * 3672215976Sjmallett * GMX_INF_MODE = Interface Mode 3673215976Sjmallett * 3674215976Sjmallett */ 3675232812Sjmallettunion cvmx_gmxx_inf_mode { 3676215976Sjmallett uint64_t u64; 3677232812Sjmallett struct cvmx_gmxx_inf_mode_s { 3678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3679232812Sjmallett uint64_t reserved_20_63 : 44; 3680232812Sjmallett uint64_t rate : 4; /**< SERDES speed rate 3681232812Sjmallett reset value is based on the QLM speed select 3682232812Sjmallett 0 = 1.25 Gbaud 3683232812Sjmallett 1 = 3.125 Gbaud 3684232812Sjmallett (only valid for GMX0 instance) 3685232812Sjmallett Software must not change RATE from its reset value */ 3686232812Sjmallett uint64_t reserved_12_15 : 4; 3687232812Sjmallett uint64_t speed : 4; /**< Interface Speed 3688232812Sjmallett QLM speed pins which select reference clock 3689232812Sjmallett period and interface data rate. If the QLM PLL 3690232812Sjmallett inputs are correct, the speed setting correspond 3691232812Sjmallett to the following data rates (in Gbaud). 3692232812Sjmallett 0 = 5 3693232812Sjmallett 1 = 2.5 3694232812Sjmallett 2 = 2.5 3695232812Sjmallett 3 = 1.25 3696232812Sjmallett 4 = 1.25 3697232812Sjmallett 5 = 6.25 3698232812Sjmallett 6 = 5 3699232812Sjmallett 7 = 2.5 3700232812Sjmallett 8 = 3.125 3701232812Sjmallett 9 = 2.5 3702232812Sjmallett 10 = 1.25 3703232812Sjmallett 11 = 5 3704232812Sjmallett 12 = 6.25 3705232812Sjmallett 13 = 3.75 3706232812Sjmallett 14 = 3.125 3707232812Sjmallett 15 = QLM disabled */ 3708232812Sjmallett uint64_t reserved_7_7 : 1; 3709232812Sjmallett uint64_t mode : 3; /**< Interface Electrical Operating Mode 3710215976Sjmallett - 0: SGMII (v1.8) 3711215976Sjmallett - 1: XAUI (IEEE 802.3-2005) */ 3712215976Sjmallett uint64_t reserved_3_3 : 1; 3713215976Sjmallett uint64_t p0mii : 1; /**< Port 0 Interface Mode 3714215976Sjmallett - 0: Port 0 is RGMII 3715215976Sjmallett - 1: Port 0 is MII */ 3716215976Sjmallett uint64_t en : 1; /**< Interface Enable 3717215976Sjmallett Must be set to enable the packet interface. 3718215976Sjmallett Should be enabled before any other requests to 3719215976Sjmallett GMX including enabling port back pressure with 3720215976Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3721215976Sjmallett uint64_t type : 1; /**< Interface Protocol Type 3722215976Sjmallett - 0: SGMII/1000Base-X 3723215976Sjmallett - 1: XAUI */ 3724215976Sjmallett#else 3725215976Sjmallett uint64_t type : 1; 3726215976Sjmallett uint64_t en : 1; 3727215976Sjmallett uint64_t p0mii : 1; 3728215976Sjmallett uint64_t reserved_3_3 : 1; 3729232812Sjmallett uint64_t mode : 3; 3730232812Sjmallett uint64_t reserved_7_7 : 1; 3731215976Sjmallett uint64_t speed : 4; 3732232812Sjmallett uint64_t reserved_12_15 : 4; 3733232812Sjmallett uint64_t rate : 4; 3734232812Sjmallett uint64_t reserved_20_63 : 44; 3735215976Sjmallett#endif 3736215976Sjmallett } s; 3737232812Sjmallett struct cvmx_gmxx_inf_mode_cn30xx { 3738232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3739215976Sjmallett uint64_t reserved_3_63 : 61; 3740215976Sjmallett uint64_t p0mii : 1; /**< Port 0 Interface Mode 3741215976Sjmallett - 0: Port 0 is RGMII 3742215976Sjmallett - 1: Port 0 is MII */ 3743215976Sjmallett uint64_t en : 1; /**< Interface Enable 3744215976Sjmallett Must be set to enable the packet interface. 3745215976Sjmallett Should be enabled before any other requests to 3746215976Sjmallett GMX including enabling port back pressure with 3747215976Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3748215976Sjmallett uint64_t type : 1; /**< Port 1/2 Interface Mode 3749215976Sjmallett - 0: Ports 1 and 2 are RGMII 3750215976Sjmallett - 1: Port 1 is GMII/MII, Port 2 is unused 3751215976Sjmallett GMII/MII is selected by GMX_PRT1_CFG[SPEED] */ 3752215976Sjmallett#else 3753215976Sjmallett uint64_t type : 1; 3754215976Sjmallett uint64_t en : 1; 3755215976Sjmallett uint64_t p0mii : 1; 3756215976Sjmallett uint64_t reserved_3_63 : 61; 3757215976Sjmallett#endif 3758215976Sjmallett } cn30xx; 3759232812Sjmallett struct cvmx_gmxx_inf_mode_cn31xx { 3760232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3761215976Sjmallett uint64_t reserved_2_63 : 62; 3762215976Sjmallett uint64_t en : 1; /**< Interface Enable 3763215976Sjmallett Must be set to enable the packet interface. 3764215976Sjmallett Should be enabled before any other requests to 3765215976Sjmallett GMX including enabling port back pressure with 3766215976Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3767215976Sjmallett uint64_t type : 1; /**< Interface Mode 3768215976Sjmallett - 0: All three ports are RGMII ports 3769215976Sjmallett - 1: prt0 is RGMII, prt1 is GMII, and prt2 is unused */ 3770215976Sjmallett#else 3771215976Sjmallett uint64_t type : 1; 3772215976Sjmallett uint64_t en : 1; 3773215976Sjmallett uint64_t reserved_2_63 : 62; 3774215976Sjmallett#endif 3775215976Sjmallett } cn31xx; 3776215976Sjmallett struct cvmx_gmxx_inf_mode_cn31xx cn38xx; 3777215976Sjmallett struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; 3778215976Sjmallett struct cvmx_gmxx_inf_mode_cn30xx cn50xx; 3779232812Sjmallett struct cvmx_gmxx_inf_mode_cn52xx { 3780232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3781215976Sjmallett uint64_t reserved_10_63 : 54; 3782215976Sjmallett uint64_t speed : 2; /**< Interface Speed 3783215976Sjmallett - 0: 1.250GHz 3784215976Sjmallett - 1: 2.500GHz 3785215976Sjmallett - 2: 3.125GHz 3786215976Sjmallett - 3: 3.750GHz */ 3787215976Sjmallett uint64_t reserved_6_7 : 2; 3788215976Sjmallett uint64_t mode : 2; /**< Interface Electrical Operating Mode 3789215976Sjmallett - 0: Disabled (PCIe) 3790215976Sjmallett - 1: XAUI (IEEE 802.3-2005) 3791215976Sjmallett - 2: SGMII (v1.8) 3792215976Sjmallett - 3: PICMG3.1 */ 3793215976Sjmallett uint64_t reserved_2_3 : 2; 3794215976Sjmallett uint64_t en : 1; /**< Interface Enable 3795215976Sjmallett Must be set to enable the packet interface. 3796215976Sjmallett Should be enabled before any other requests to 3797215976Sjmallett GMX including enabling port back pressure with 3798215976Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3799215976Sjmallett uint64_t type : 1; /**< Interface Protocol Type 3800215976Sjmallett - 0: SGMII/1000Base-X 3801215976Sjmallett - 1: XAUI */ 3802215976Sjmallett#else 3803215976Sjmallett uint64_t type : 1; 3804215976Sjmallett uint64_t en : 1; 3805215976Sjmallett uint64_t reserved_2_3 : 2; 3806215976Sjmallett uint64_t mode : 2; 3807215976Sjmallett uint64_t reserved_6_7 : 2; 3808215976Sjmallett uint64_t speed : 2; 3809215976Sjmallett uint64_t reserved_10_63 : 54; 3810215976Sjmallett#endif 3811215976Sjmallett } cn52xx; 3812215976Sjmallett struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; 3813215976Sjmallett struct cvmx_gmxx_inf_mode_cn52xx cn56xx; 3814215976Sjmallett struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; 3815215976Sjmallett struct cvmx_gmxx_inf_mode_cn31xx cn58xx; 3816215976Sjmallett struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; 3817232812Sjmallett struct cvmx_gmxx_inf_mode_cn61xx { 3818232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3819215976Sjmallett uint64_t reserved_12_63 : 52; 3820232812Sjmallett uint64_t speed : 4; /**< Interface Speed 3821232812Sjmallett QLM speed pins which select reference clock 3822232812Sjmallett period and interface data rate. If the QLM PLL 3823232812Sjmallett inputs are correct, the speed setting correspond 3824232812Sjmallett to the following data rates (in Gbaud). 3825232812Sjmallett 0 = 5 3826232812Sjmallett 1 = 2.5 3827232812Sjmallett 2 = 2.5 3828232812Sjmallett 3 = 1.25 3829232812Sjmallett 4 = 1.25 3830232812Sjmallett 5 = 6.25 3831232812Sjmallett 6 = 5 3832232812Sjmallett 7 = 2.5 3833232812Sjmallett 8 = 3.125 3834232812Sjmallett 9 = 2.5 3835232812Sjmallett 10 = 1.25 3836232812Sjmallett 11 = 5 3837232812Sjmallett 12 = 6.25 3838232812Sjmallett 13 = 3.75 3839232812Sjmallett 14 = 3.125 3840232812Sjmallett 15 = QLM disabled */ 3841215976Sjmallett uint64_t reserved_5_7 : 3; 3842215976Sjmallett uint64_t mode : 1; /**< Interface Electrical Operating Mode 3843215976Sjmallett - 0: SGMII (v1.8) 3844215976Sjmallett - 1: XAUI (IEEE 802.3-2005) */ 3845215976Sjmallett uint64_t reserved_2_3 : 2; 3846215976Sjmallett uint64_t en : 1; /**< Interface Enable 3847215976Sjmallett Must be set to enable the packet interface. 3848215976Sjmallett Should be enabled before any other requests to 3849215976Sjmallett GMX including enabling port back pressure with 3850215976Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3851215976Sjmallett uint64_t type : 1; /**< Interface Protocol Type 3852215976Sjmallett - 0: SGMII/1000Base-X 3853215976Sjmallett - 1: XAUI */ 3854215976Sjmallett#else 3855215976Sjmallett uint64_t type : 1; 3856215976Sjmallett uint64_t en : 1; 3857215976Sjmallett uint64_t reserved_2_3 : 2; 3858215976Sjmallett uint64_t mode : 1; 3859215976Sjmallett uint64_t reserved_5_7 : 3; 3860215976Sjmallett uint64_t speed : 4; 3861215976Sjmallett uint64_t reserved_12_63 : 52; 3862215976Sjmallett#endif 3863232812Sjmallett } cn61xx; 3864232812Sjmallett struct cvmx_gmxx_inf_mode_cn61xx cn63xx; 3865232812Sjmallett struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1; 3866232812Sjmallett struct cvmx_gmxx_inf_mode_cn66xx { 3867232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3868232812Sjmallett uint64_t reserved_20_63 : 44; 3869232812Sjmallett uint64_t rate : 4; /**< SERDES speed rate 3870232812Sjmallett reset value is based on the QLM speed select 3871232812Sjmallett 0 = 1.25 Gbaud 3872232812Sjmallett 1 = 3.125 Gbaud 3873232812Sjmallett (only valid for GMX0 instance) 3874232812Sjmallett Software must not change RATE from its reset value */ 3875232812Sjmallett uint64_t reserved_12_15 : 4; 3876232812Sjmallett uint64_t speed : 4; /**< Interface Speed 3877232812Sjmallett QLM speed pins which select reference clock 3878232812Sjmallett period and interface data rate. If the QLM PLL 3879232812Sjmallett inputs are correct, the speed setting correspond 3880232812Sjmallett to the following data rates (in Gbaud). 3881232812Sjmallett 0 = 5 3882232812Sjmallett 1 = 2.5 3883232812Sjmallett 2 = 2.5 3884232812Sjmallett 3 = 1.25 3885232812Sjmallett 4 = 1.25 3886232812Sjmallett 5 = 6.25 3887232812Sjmallett 6 = 5 3888232812Sjmallett 7 = 2.5 3889232812Sjmallett 8 = 3.125 3890232812Sjmallett 9 = 2.5 3891232812Sjmallett 10 = 1.25 3892232812Sjmallett 11 = 5 3893232812Sjmallett 12 = 6.25 3894232812Sjmallett 13 = 3.75 3895232812Sjmallett 14 = 3.125 3896232812Sjmallett 15 = QLM disabled */ 3897232812Sjmallett uint64_t reserved_5_7 : 3; 3898232812Sjmallett uint64_t mode : 1; /**< Interface Electrical Operating Mode 3899232812Sjmallett - 0: SGMII (v1.8) 3900232812Sjmallett - 1: XAUI (IEEE 802.3-2005) */ 3901232812Sjmallett uint64_t reserved_2_3 : 2; 3902232812Sjmallett uint64_t en : 1; /**< Interface Enable 3903232812Sjmallett Must be set to enable the packet interface. 3904232812Sjmallett Should be enabled before any other requests to 3905232812Sjmallett GMX including enabling port back pressure with 3906232812Sjmallett IPD_CTL_STATUS[PBP_EN] */ 3907232812Sjmallett uint64_t type : 1; /**< Interface Protocol Type 3908232812Sjmallett - 0: SGMII/1000Base-X 3909232812Sjmallett - 1: XAUI */ 3910232812Sjmallett#else 3911232812Sjmallett uint64_t type : 1; 3912232812Sjmallett uint64_t en : 1; 3913232812Sjmallett uint64_t reserved_2_3 : 2; 3914232812Sjmallett uint64_t mode : 1; 3915232812Sjmallett uint64_t reserved_5_7 : 3; 3916232812Sjmallett uint64_t speed : 4; 3917232812Sjmallett uint64_t reserved_12_15 : 4; 3918232812Sjmallett uint64_t rate : 4; 3919232812Sjmallett uint64_t reserved_20_63 : 44; 3920232812Sjmallett#endif 3921232812Sjmallett } cn66xx; 3922232812Sjmallett struct cvmx_gmxx_inf_mode_cn68xx { 3923232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3924232812Sjmallett uint64_t reserved_12_63 : 52; 3925232812Sjmallett uint64_t speed : 4; /**< Interface Speed 3926232812Sjmallett QLM speed pins which select reference clock 3927232812Sjmallett period and interface data rate. If the QLM PLL 3928232812Sjmallett inputs are correct, the speed setting correspond 3929232812Sjmallett to the following data rates (in Gbaud). 3930232812Sjmallett 0 = 5 3931232812Sjmallett 1 = 2.5 3932232812Sjmallett 2 = 2.5 3933232812Sjmallett 3 = 1.25 3934232812Sjmallett 4 = 1.25 3935232812Sjmallett 5 = 6.25 3936232812Sjmallett 6 = 5 3937232812Sjmallett 7 = 2.5 3938232812Sjmallett 8 = 3.125 3939232812Sjmallett 9 = 2.5 3940232812Sjmallett 10 = 1.25 3941232812Sjmallett 11 = 5 3942232812Sjmallett 12 = 6.25 3943232812Sjmallett 13 = 3.75 3944232812Sjmallett 14 = 3.125 3945232812Sjmallett 15 = QLM disabled */ 3946232812Sjmallett uint64_t reserved_7_7 : 1; 3947232812Sjmallett uint64_t mode : 3; /**< Interface Electrical Operating Mode 3948232812Sjmallett - 0: Reserved 3949232812Sjmallett - 1: Reserved 3950232812Sjmallett - 2: SGMII (v1.8) 3951232812Sjmallett - 3: XAUI (IEEE 802.3-2005) 3952232812Sjmallett - 4: Reserved 3953232812Sjmallett - 5: Reserved 3954232812Sjmallett - 6: Reserved 3955232812Sjmallett - 7: RXAUI */ 3956232812Sjmallett uint64_t reserved_2_3 : 2; 3957232812Sjmallett uint64_t en : 1; /**< Interface Enable 3958232812Sjmallett Must be set to enable the packet interface. 3959232812Sjmallett Should be enabled before any other requests to 3960232812Sjmallett GMX including enabling port back pressure with 3961232812Sjmallett b IPD_CTL_STATUS[PBP_EN] */ 3962232812Sjmallett uint64_t type : 1; /**< Interface Protocol Type 3963232812Sjmallett - 0: SGMII/1000Base-X 3964232812Sjmallett - 1: XAUI/RXAUI */ 3965232812Sjmallett#else 3966232812Sjmallett uint64_t type : 1; 3967232812Sjmallett uint64_t en : 1; 3968232812Sjmallett uint64_t reserved_2_3 : 2; 3969232812Sjmallett uint64_t mode : 3; 3970232812Sjmallett uint64_t reserved_7_7 : 1; 3971232812Sjmallett uint64_t speed : 4; 3972232812Sjmallett uint64_t reserved_12_63 : 52; 3973232812Sjmallett#endif 3974232812Sjmallett } cn68xx; 3975232812Sjmallett struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1; 3976232812Sjmallett struct cvmx_gmxx_inf_mode_cn61xx cnf71xx; 3977215976Sjmallett}; 3978215976Sjmalletttypedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t; 3979215976Sjmallett 3980215976Sjmallett/** 3981215976Sjmallett * cvmx_gmx#_nxa_adr 3982215976Sjmallett * 3983215976Sjmallett * GMX_NXA_ADR = NXA Port Address 3984215976Sjmallett * 3985215976Sjmallett */ 3986232812Sjmallettunion cvmx_gmxx_nxa_adr { 3987215976Sjmallett uint64_t u64; 3988232812Sjmallett struct cvmx_gmxx_nxa_adr_s { 3989232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3990232812Sjmallett uint64_t reserved_23_63 : 41; 3991232812Sjmallett uint64_t pipe : 7; /**< Logged pipe for NXP exceptions */ 3992232812Sjmallett uint64_t reserved_6_15 : 10; 3993215976Sjmallett uint64_t prt : 6; /**< Logged address for NXA exceptions 3994215976Sjmallett The logged address will be from the first 3995215976Sjmallett exception that caused the problem. NCB has 3996215976Sjmallett higher priority than PKO and will win. 3997215976Sjmallett (only PRT[3:0]) */ 3998215976Sjmallett#else 3999215976Sjmallett uint64_t prt : 6; 4000232812Sjmallett uint64_t reserved_6_15 : 10; 4001232812Sjmallett uint64_t pipe : 7; 4002232812Sjmallett uint64_t reserved_23_63 : 41; 4003232812Sjmallett#endif 4004232812Sjmallett } s; 4005232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx { 4006232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4007215976Sjmallett uint64_t reserved_6_63 : 58; 4008232812Sjmallett uint64_t prt : 6; /**< Logged address for NXA exceptions 4009232812Sjmallett The logged address will be from the first 4010232812Sjmallett exception that caused the problem. NCB has 4011232812Sjmallett higher priority than PKO and will win. */ 4012232812Sjmallett#else 4013232812Sjmallett uint64_t prt : 6; 4014232812Sjmallett uint64_t reserved_6_63 : 58; 4015215976Sjmallett#endif 4016232812Sjmallett } cn30xx; 4017232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn31xx; 4018232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn38xx; 4019232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2; 4020232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn50xx; 4021232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn52xx; 4022232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1; 4023232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn56xx; 4024232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1; 4025232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn58xx; 4026232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1; 4027232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn61xx; 4028232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn63xx; 4029232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1; 4030232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cn66xx; 4031232812Sjmallett struct cvmx_gmxx_nxa_adr_s cn68xx; 4032232812Sjmallett struct cvmx_gmxx_nxa_adr_s cn68xxp1; 4033232812Sjmallett struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx; 4034215976Sjmallett}; 4035215976Sjmalletttypedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t; 4036215976Sjmallett 4037215976Sjmallett/** 4038232812Sjmallett * cvmx_gmx#_pipe_status 4039232812Sjmallett * 4040232812Sjmallett * DON'T PUT IN HRM* 4041232812Sjmallett * 4042232812Sjmallett */ 4043232812Sjmallettunion cvmx_gmxx_pipe_status { 4044232812Sjmallett uint64_t u64; 4045232812Sjmallett struct cvmx_gmxx_pipe_status_s { 4046232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4047232812Sjmallett uint64_t reserved_20_63 : 44; 4048232812Sjmallett uint64_t ovr : 4; /**< Pipe credit return FIFO has overflowed. */ 4049232812Sjmallett uint64_t reserved_12_15 : 4; 4050232812Sjmallett uint64_t bp : 4; /**< Pipe credit return FIFO has filled up and asserted 4051232812Sjmallett backpressure to the datapath. */ 4052232812Sjmallett uint64_t reserved_4_7 : 4; 4053232812Sjmallett uint64_t stop : 4; /**< PKO has asserted backpressure on the pipe credit 4054232812Sjmallett return interface. */ 4055232812Sjmallett#else 4056232812Sjmallett uint64_t stop : 4; 4057232812Sjmallett uint64_t reserved_4_7 : 4; 4058232812Sjmallett uint64_t bp : 4; 4059232812Sjmallett uint64_t reserved_12_15 : 4; 4060232812Sjmallett uint64_t ovr : 4; 4061232812Sjmallett uint64_t reserved_20_63 : 44; 4062232812Sjmallett#endif 4063232812Sjmallett } s; 4064232812Sjmallett struct cvmx_gmxx_pipe_status_s cn68xx; 4065232812Sjmallett struct cvmx_gmxx_pipe_status_s cn68xxp1; 4066232812Sjmallett}; 4067232812Sjmalletttypedef union cvmx_gmxx_pipe_status cvmx_gmxx_pipe_status_t; 4068232812Sjmallett 4069232812Sjmallett/** 4070215976Sjmallett * cvmx_gmx#_prt#_cbfc_ctl 4071215976Sjmallett * 4072215976Sjmallett * ** HG2 message CSRs end 4073215976Sjmallett * 4074215976Sjmallett * 4075215976Sjmallett * Notes: 4076215976Sjmallett * XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>) 4077215976Sjmallett * 4078215976Sjmallett */ 4079232812Sjmallettunion cvmx_gmxx_prtx_cbfc_ctl { 4080215976Sjmallett uint64_t u64; 4081232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s { 4082232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4083215976Sjmallett uint64_t phys_en : 16; /**< Determines which ports will have physical 4084215976Sjmallett backpressure pause packets. 4085215976Sjmallett The value pplaced in the Class Enable Vector 4086215976Sjmallett field of the CBFC pause packet will be 4087215976Sjmallett PHYS_EN | LOGL_EN */ 4088215976Sjmallett uint64_t logl_en : 16; /**< Determines which ports will have logical 4089215976Sjmallett backpressure pause packets. 4090215976Sjmallett The value pplaced in the Class Enable Vector 4091215976Sjmallett field of the CBFC pause packet will be 4092215976Sjmallett PHYS_EN | LOGL_EN */ 4093215976Sjmallett uint64_t phys_bp : 16; /**< When RX_EN is set and the HW is backpressuring any 4094215976Sjmallett ports (from either CBFC pause packets or the 4095215976Sjmallett GMX_TX_OVR_BP[TX_PRT_BP] register) and all ports 4096215976Sjmallett indiciated by PHYS_BP are backpressured, simulate 4097215976Sjmallett physical backpressure by defering all packets on 4098215976Sjmallett the transmitter. */ 4099215976Sjmallett uint64_t reserved_4_15 : 12; 4100215976Sjmallett uint64_t bck_en : 1; /**< Forward CBFC Pause information to BP block */ 4101215976Sjmallett uint64_t drp_en : 1; /**< Drop Control CBFC Pause Frames */ 4102215976Sjmallett uint64_t tx_en : 1; /**< When set, allow for CBFC Pause Packets 4103215976Sjmallett Must be clear in HiGig2 mode i.e. when 4104215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 4105215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 4106215976Sjmallett uint64_t rx_en : 1; /**< When set, allow for CBFC Pause Packets 4107215976Sjmallett Must be clear in HiGig2 mode i.e. when 4108215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 4109215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 4110215976Sjmallett#else 4111215976Sjmallett uint64_t rx_en : 1; 4112215976Sjmallett uint64_t tx_en : 1; 4113215976Sjmallett uint64_t drp_en : 1; 4114215976Sjmallett uint64_t bck_en : 1; 4115215976Sjmallett uint64_t reserved_4_15 : 12; 4116215976Sjmallett uint64_t phys_bp : 16; 4117215976Sjmallett uint64_t logl_en : 16; 4118215976Sjmallett uint64_t phys_en : 16; 4119215976Sjmallett#endif 4120215976Sjmallett } s; 4121215976Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; 4122215976Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; 4123232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx; 4124215976Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx; 4125215976Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1; 4126232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx; 4127232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx; 4128232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1; 4129232812Sjmallett struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx; 4130215976Sjmallett}; 4131215976Sjmalletttypedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t; 4132215976Sjmallett 4133215976Sjmallett/** 4134215976Sjmallett * cvmx_gmx#_prt#_cfg 4135215976Sjmallett * 4136215976Sjmallett * GMX_PRT_CFG = Port description 4137215976Sjmallett * 4138215976Sjmallett */ 4139232812Sjmallettunion cvmx_gmxx_prtx_cfg { 4140215976Sjmallett uint64_t u64; 4141232812Sjmallett struct cvmx_gmxx_prtx_cfg_s { 4142232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4143232812Sjmallett uint64_t reserved_22_63 : 42; 4144232812Sjmallett uint64_t pknd : 6; /**< Port Kind used for processing the packet by PKI */ 4145232812Sjmallett uint64_t reserved_14_15 : 2; 4146215976Sjmallett uint64_t tx_idle : 1; /**< TX Machine is idle */ 4147215976Sjmallett uint64_t rx_idle : 1; /**< RX Machine is idle */ 4148215976Sjmallett uint64_t reserved_9_11 : 3; 4149215976Sjmallett uint64_t speed_msb : 1; /**< Link Speed MSB [SPEED_MSB:SPEED] 4150215976Sjmallett 10 = 10Mbs operation 4151215976Sjmallett 00 = 100Mbs operation 4152215976Sjmallett 01 = 1000Mbs operation 4153215976Sjmallett 11 = Reserved 4154215976Sjmallett (SGMII/1000Base-X only) */ 4155215976Sjmallett uint64_t reserved_4_7 : 4; 4156215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 4157215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 4158215976Sjmallett 1 = 4096 bitimes (1000Mbs operation) 4159215976Sjmallett (SGMII/1000Base-X only) */ 4160215976Sjmallett uint64_t duplex : 1; /**< Duplex 4161215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 4162215976Sjmallett 1 = Full Duplex 4163215976Sjmallett (SGMII/1000Base-X only) */ 4164215976Sjmallett uint64_t speed : 1; /**< Link Speed LSB [SPEED_MSB:SPEED] 4165215976Sjmallett 10 = 10Mbs operation 4166215976Sjmallett 00 = 100Mbs operation 4167215976Sjmallett 01 = 1000Mbs operation 4168215976Sjmallett 11 = Reserved 4169215976Sjmallett (SGMII/1000Base-X only) */ 4170215976Sjmallett uint64_t en : 1; /**< Link Enable 4171215976Sjmallett When EN is clear, packets will not be received 4172215976Sjmallett or transmitted (including PAUSE and JAM packets). 4173215976Sjmallett If EN is cleared while a packet is currently 4174215976Sjmallett being received or transmitted, the packet will 4175215976Sjmallett be allowed to complete before the bus is idled. 4176215976Sjmallett On the RX side, subsequent packets in a burst 4177215976Sjmallett will be ignored. */ 4178215976Sjmallett#else 4179215976Sjmallett uint64_t en : 1; 4180215976Sjmallett uint64_t speed : 1; 4181215976Sjmallett uint64_t duplex : 1; 4182215976Sjmallett uint64_t slottime : 1; 4183215976Sjmallett uint64_t reserved_4_7 : 4; 4184215976Sjmallett uint64_t speed_msb : 1; 4185215976Sjmallett uint64_t reserved_9_11 : 3; 4186215976Sjmallett uint64_t rx_idle : 1; 4187215976Sjmallett uint64_t tx_idle : 1; 4188232812Sjmallett uint64_t reserved_14_15 : 2; 4189232812Sjmallett uint64_t pknd : 6; 4190232812Sjmallett uint64_t reserved_22_63 : 42; 4191215976Sjmallett#endif 4192215976Sjmallett } s; 4193232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx { 4194232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4195215976Sjmallett uint64_t reserved_4_63 : 60; 4196215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 4197215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 4198215976Sjmallett 1 = 4096 bitimes (1000Mbs operation) */ 4199215976Sjmallett uint64_t duplex : 1; /**< Duplex 4200215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 4201215976Sjmallett 1 = Full Duplex */ 4202215976Sjmallett uint64_t speed : 1; /**< Link Speed 4203215976Sjmallett 0 = 10/100Mbs operation 4204215976Sjmallett (in RGMII mode, GMX_TX_CLK[CLK_CNT] > 1) 4205215976Sjmallett (in MII mode, GMX_TX_CLK[CLK_CNT] == 1) 4206215976Sjmallett 1 = 1000Mbs operation */ 4207215976Sjmallett uint64_t en : 1; /**< Link Enable 4208215976Sjmallett When EN is clear, packets will not be received 4209215976Sjmallett or transmitted (including PAUSE and JAM packets). 4210215976Sjmallett If EN is cleared while a packet is currently 4211215976Sjmallett being received or transmitted, the packet will 4212215976Sjmallett be allowed to complete before the bus is idled. 4213215976Sjmallett On the RX side, subsequent packets in a burst 4214215976Sjmallett will be ignored. */ 4215215976Sjmallett#else 4216215976Sjmallett uint64_t en : 1; 4217215976Sjmallett uint64_t speed : 1; 4218215976Sjmallett uint64_t duplex : 1; 4219215976Sjmallett uint64_t slottime : 1; 4220215976Sjmallett uint64_t reserved_4_63 : 60; 4221215976Sjmallett#endif 4222215976Sjmallett } cn30xx; 4223215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; 4224215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; 4225215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; 4226215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; 4227232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx { 4228232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4229232812Sjmallett uint64_t reserved_14_63 : 50; 4230232812Sjmallett uint64_t tx_idle : 1; /**< TX Machine is idle */ 4231232812Sjmallett uint64_t rx_idle : 1; /**< RX Machine is idle */ 4232232812Sjmallett uint64_t reserved_9_11 : 3; 4233232812Sjmallett uint64_t speed_msb : 1; /**< Link Speed MSB [SPEED_MSB:SPEED] 4234232812Sjmallett 10 = 10Mbs operation 4235232812Sjmallett 00 = 100Mbs operation 4236232812Sjmallett 01 = 1000Mbs operation 4237232812Sjmallett 11 = Reserved 4238232812Sjmallett (SGMII/1000Base-X only) */ 4239232812Sjmallett uint64_t reserved_4_7 : 4; 4240232812Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 4241232812Sjmallett 0 = 512 bitimes (10/100Mbs operation) 4242232812Sjmallett 1 = 4096 bitimes (1000Mbs operation) 4243232812Sjmallett (SGMII/1000Base-X only) */ 4244232812Sjmallett uint64_t duplex : 1; /**< Duplex 4245232812Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 4246232812Sjmallett 1 = Full Duplex 4247232812Sjmallett (SGMII/1000Base-X only) */ 4248232812Sjmallett uint64_t speed : 1; /**< Link Speed LSB [SPEED_MSB:SPEED] 4249232812Sjmallett 10 = 10Mbs operation 4250232812Sjmallett 00 = 100Mbs operation 4251232812Sjmallett 01 = 1000Mbs operation 4252232812Sjmallett 11 = Reserved 4253232812Sjmallett (SGMII/1000Base-X only) */ 4254232812Sjmallett uint64_t en : 1; /**< Link Enable 4255232812Sjmallett When EN is clear, packets will not be received 4256232812Sjmallett or transmitted (including PAUSE and JAM packets). 4257232812Sjmallett If EN is cleared while a packet is currently 4258232812Sjmallett being received or transmitted, the packet will 4259232812Sjmallett be allowed to complete before the bus is idled. 4260232812Sjmallett On the RX side, subsequent packets in a burst 4261232812Sjmallett will be ignored. */ 4262232812Sjmallett#else 4263232812Sjmallett uint64_t en : 1; 4264232812Sjmallett uint64_t speed : 1; 4265232812Sjmallett uint64_t duplex : 1; 4266232812Sjmallett uint64_t slottime : 1; 4267232812Sjmallett uint64_t reserved_4_7 : 4; 4268232812Sjmallett uint64_t speed_msb : 1; 4269232812Sjmallett uint64_t reserved_9_11 : 3; 4270232812Sjmallett uint64_t rx_idle : 1; 4271232812Sjmallett uint64_t tx_idle : 1; 4272232812Sjmallett uint64_t reserved_14_63 : 50; 4273232812Sjmallett#endif 4274232812Sjmallett } cn52xx; 4275232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1; 4276232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx; 4277232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1; 4278215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; 4279215976Sjmallett struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; 4280232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx; 4281232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx; 4282232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1; 4283232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx; 4284232812Sjmallett struct cvmx_gmxx_prtx_cfg_s cn68xx; 4285232812Sjmallett struct cvmx_gmxx_prtx_cfg_s cn68xxp1; 4286232812Sjmallett struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx; 4287215976Sjmallett}; 4288215976Sjmalletttypedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t; 4289215976Sjmallett 4290215976Sjmallett/** 4291215976Sjmallett * cvmx_gmx#_rx#_adr_cam0 4292215976Sjmallett * 4293215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4294215976Sjmallett * 4295215976Sjmallett */ 4296232812Sjmallettunion cvmx_gmxx_rxx_adr_cam0 { 4297215976Sjmallett uint64_t u64; 4298232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s { 4299232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4300215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4301232812Sjmallett 4302232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4303215976Sjmallett The CAM matches against unicst or multicst DMAC 4304215976Sjmallett addresses. 4305232812Sjmallett 4306232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4307232812Sjmallett in either SGMII or XAUI mode such that any GMX 4308232812Sjmallett MAC can use any of the 32 common DMAC entries. 4309232812Sjmallett 4310232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4311232812Sjmallett registers used in XAUI mode. */ 4312215976Sjmallett#else 4313215976Sjmallett uint64_t adr : 64; 4314215976Sjmallett#endif 4315215976Sjmallett } s; 4316215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; 4317215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; 4318215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; 4319215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; 4320215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; 4321215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; 4322215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; 4323215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; 4324215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; 4325215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; 4326215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; 4327232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn61xx; 4328215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn63xx; 4329215976Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1; 4330232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn66xx; 4331232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn68xx; 4332232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1; 4333232812Sjmallett struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx; 4334215976Sjmallett}; 4335215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t; 4336215976Sjmallett 4337215976Sjmallett/** 4338215976Sjmallett * cvmx_gmx#_rx#_adr_cam1 4339215976Sjmallett * 4340215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4341215976Sjmallett * 4342215976Sjmallett */ 4343232812Sjmallettunion cvmx_gmxx_rxx_adr_cam1 { 4344215976Sjmallett uint64_t u64; 4345232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s { 4346232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4347215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4348232812Sjmallett 4349232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4350215976Sjmallett The CAM matches against unicst or multicst DMAC 4351215976Sjmallett addresses. 4352232812Sjmallett 4353232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4354232812Sjmallett in either SGMII or XAUI mode such that any GMX 4355232812Sjmallett MAC can use any of the 32 common DMAC entries. 4356232812Sjmallett 4357232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4358232812Sjmallett registers used in XAUI mode. */ 4359215976Sjmallett#else 4360215976Sjmallett uint64_t adr : 64; 4361215976Sjmallett#endif 4362215976Sjmallett } s; 4363215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; 4364215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; 4365215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; 4366215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; 4367215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; 4368215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; 4369215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; 4370215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; 4371215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; 4372215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; 4373215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; 4374232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn61xx; 4375215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn63xx; 4376215976Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1; 4377232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn66xx; 4378232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn68xx; 4379232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1; 4380232812Sjmallett struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx; 4381215976Sjmallett}; 4382215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t; 4383215976Sjmallett 4384215976Sjmallett/** 4385215976Sjmallett * cvmx_gmx#_rx#_adr_cam2 4386215976Sjmallett * 4387215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4388215976Sjmallett * 4389215976Sjmallett */ 4390232812Sjmallettunion cvmx_gmxx_rxx_adr_cam2 { 4391215976Sjmallett uint64_t u64; 4392232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s { 4393232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4394215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4395232812Sjmallett 4396232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4397215976Sjmallett The CAM matches against unicst or multicst DMAC 4398215976Sjmallett addresses. 4399232812Sjmallett 4400232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4401232812Sjmallett in either SGMII or XAUI mode such that any GMX 4402232812Sjmallett MAC can use any of the 32 common DMAC entries. 4403232812Sjmallett 4404232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4405232812Sjmallett registers used in XAUI mode. */ 4406215976Sjmallett#else 4407215976Sjmallett uint64_t adr : 64; 4408215976Sjmallett#endif 4409215976Sjmallett } s; 4410215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; 4411215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; 4412215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; 4413215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; 4414215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; 4415215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; 4416215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; 4417215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; 4418215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; 4419215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; 4420215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; 4421232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn61xx; 4422215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn63xx; 4423215976Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1; 4424232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn66xx; 4425232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn68xx; 4426232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1; 4427232812Sjmallett struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx; 4428215976Sjmallett}; 4429215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t; 4430215976Sjmallett 4431215976Sjmallett/** 4432215976Sjmallett * cvmx_gmx#_rx#_adr_cam3 4433215976Sjmallett * 4434215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4435215976Sjmallett * 4436215976Sjmallett */ 4437232812Sjmallettunion cvmx_gmxx_rxx_adr_cam3 { 4438215976Sjmallett uint64_t u64; 4439232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s { 4440232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4441215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4442232812Sjmallett 4443232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4444215976Sjmallett The CAM matches against unicst or multicst DMAC 4445215976Sjmallett addresses. 4446232812Sjmallett 4447232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4448232812Sjmallett in either SGMII or XAUI mode such that any GMX 4449232812Sjmallett MAC can use any of the 32 common DMAC entries. 4450232812Sjmallett 4451232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4452232812Sjmallett registers used in XAUI mode. */ 4453215976Sjmallett#else 4454215976Sjmallett uint64_t adr : 64; 4455215976Sjmallett#endif 4456215976Sjmallett } s; 4457215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; 4458215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; 4459215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; 4460215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; 4461215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; 4462215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; 4463215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; 4464215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; 4465215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; 4466215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; 4467215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; 4468232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn61xx; 4469215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn63xx; 4470215976Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1; 4471232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn66xx; 4472232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn68xx; 4473232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1; 4474232812Sjmallett struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx; 4475215976Sjmallett}; 4476215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t; 4477215976Sjmallett 4478215976Sjmallett/** 4479215976Sjmallett * cvmx_gmx#_rx#_adr_cam4 4480215976Sjmallett * 4481215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4482215976Sjmallett * 4483215976Sjmallett */ 4484232812Sjmallettunion cvmx_gmxx_rxx_adr_cam4 { 4485215976Sjmallett uint64_t u64; 4486232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s { 4487232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4488215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4489232812Sjmallett 4490232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4491215976Sjmallett The CAM matches against unicst or multicst DMAC 4492215976Sjmallett addresses. 4493232812Sjmallett 4494232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4495232812Sjmallett in either SGMII or XAUI mode such that any GMX 4496232812Sjmallett MAC can use any of the 32 common DMAC entries. 4497232812Sjmallett 4498232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4499232812Sjmallett registers used in XAUI mode. */ 4500215976Sjmallett#else 4501215976Sjmallett uint64_t adr : 64; 4502215976Sjmallett#endif 4503215976Sjmallett } s; 4504215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; 4505215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; 4506215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; 4507215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; 4508215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; 4509215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; 4510215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; 4511215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; 4512215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; 4513215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; 4514215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; 4515232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn61xx; 4516215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn63xx; 4517215976Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1; 4518232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn66xx; 4519232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn68xx; 4520232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1; 4521232812Sjmallett struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx; 4522215976Sjmallett}; 4523215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t; 4524215976Sjmallett 4525215976Sjmallett/** 4526215976Sjmallett * cvmx_gmx#_rx#_adr_cam5 4527215976Sjmallett * 4528215976Sjmallett * GMX_RX_ADR_CAM = Address Filtering Control 4529215976Sjmallett * 4530215976Sjmallett */ 4531232812Sjmallettunion cvmx_gmxx_rxx_adr_cam5 { 4532215976Sjmallett uint64_t u64; 4533232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s { 4534232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4535215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 4536232812Sjmallett 4537232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 4538215976Sjmallett The CAM matches against unicst or multicst DMAC 4539215976Sjmallett addresses. 4540232812Sjmallett 4541232812Sjmallett ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used 4542232812Sjmallett in either SGMII or XAUI mode such that any GMX 4543232812Sjmallett MAC can use any of the 32 common DMAC entries. 4544232812Sjmallett 4545232812Sjmallett GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0 4546232812Sjmallett registers used in XAUI mode. */ 4547215976Sjmallett#else 4548215976Sjmallett uint64_t adr : 64; 4549215976Sjmallett#endif 4550215976Sjmallett } s; 4551215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; 4552215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; 4553215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; 4554215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; 4555215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; 4556215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; 4557215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; 4558215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; 4559215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; 4560215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; 4561215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; 4562232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn61xx; 4563215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn63xx; 4564215976Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1; 4565232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn66xx; 4566232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn68xx; 4567232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1; 4568232812Sjmallett struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx; 4569215976Sjmallett}; 4570215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t; 4571215976Sjmallett 4572215976Sjmallett/** 4573232812Sjmallett * cvmx_gmx#_rx#_adr_cam_all_en 4574232812Sjmallett * 4575232812Sjmallett * GMX_RX_ADR_CAM_ALL_EN = Address Filtering Control Enable 4576232812Sjmallett * 4577232812Sjmallett */ 4578232812Sjmallettunion cvmx_gmxx_rxx_adr_cam_all_en { 4579232812Sjmallett uint64_t u64; 4580232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_all_en_s { 4581232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4582232812Sjmallett uint64_t reserved_32_63 : 32; 4583232812Sjmallett uint64_t en : 32; /**< CAM Entry Enables 4584232812Sjmallett 4585232812Sjmallett GMX has 32 DMAC entries that can be accessed with 4586232812Sjmallett the GMX_RX[0..3]_ADR_CAM[0..5] CSRs. 4587232812Sjmallett These 32 DMAC entries can be used by any of the 4588232812Sjmallett four SGMII MACs or the XAUI MAC. 4589232812Sjmallett 4590232812Sjmallett Each port interface has independent control of 4591232812Sjmallett which of the 32 DMAC entries to include in the 4592232812Sjmallett CAM lookup. 4593232812Sjmallett 4594232812Sjmallett GMX_RXx_ADR_CAM_ALL_EN was not present in legacy 4595232812Sjmallett GMX implemenations which had only eight DMAC CAM 4596232812Sjmallett entries. New applications may choose to ignore 4597232812Sjmallett GMX_RXx_ADR_CAM_EN using GMX_RX_ADR_CAM_ALL_EN 4598232812Sjmallett instead. 4599232812Sjmallett 4600232812Sjmallett EN represents the full 32 indepedent per MAC 4601232812Sjmallett enables. 4602232812Sjmallett 4603232812Sjmallett Writes to EN will be reflected in 4604232812Sjmallett GMX_RXx_ADR_CAM_EN[EN] and writes to 4605232812Sjmallett GMX_RXx_ADR_CAM_EN[EN] will be reflected in EN. 4606232812Sjmallett Refer to GMX_RXx_ADR_CAM_EN for the CSR mapping. 4607232812Sjmallett 4608232812Sjmallett In XAUI mode, only GMX_RX0_ADR_CAM_ALL_EN is used 4609232812Sjmallett and GMX_RX[1,2,3]_ADR_CAM_ALL_EN should not be 4610232812Sjmallett used. */ 4611232812Sjmallett#else 4612232812Sjmallett uint64_t en : 32; 4613232812Sjmallett uint64_t reserved_32_63 : 32; 4614232812Sjmallett#endif 4615232812Sjmallett } s; 4616232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx; 4617232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx; 4618232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx; 4619232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx; 4620232812Sjmallett}; 4621232812Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam_all_en cvmx_gmxx_rxx_adr_cam_all_en_t; 4622232812Sjmallett 4623232812Sjmallett/** 4624215976Sjmallett * cvmx_gmx#_rx#_adr_cam_en 4625215976Sjmallett * 4626215976Sjmallett * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable 4627215976Sjmallett * 4628215976Sjmallett */ 4629232812Sjmallettunion cvmx_gmxx_rxx_adr_cam_en { 4630215976Sjmallett uint64_t u64; 4631232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s { 4632232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4633215976Sjmallett uint64_t reserved_8_63 : 56; 4634232812Sjmallett uint64_t en : 8; /**< CAM Entry Enables 4635232812Sjmallett 4636232812Sjmallett GMX has 32 DMAC entries that can be accessed with 4637232812Sjmallett the GMX_RX[0..3]_ADR_CAM[0..5] CSRs. 4638232812Sjmallett These 32 DMAC entries can be used by any of the 4639232812Sjmallett four SGMII MACs or the XAUI MAC. 4640232812Sjmallett 4641232812Sjmallett Each port interface has independent control of 4642232812Sjmallett which of the 32 DMAC entries to include in the 4643232812Sjmallett CAM lookup. 4644232812Sjmallett 4645232812Sjmallett Legacy GMX implementations were able to CAM 4646232812Sjmallett against eight DMAC entries while current 4647232812Sjmallett implementations use 32 common entries. 4648232812Sjmallett This register is intended for legacy applications 4649232812Sjmallett that only require eight DMAC CAM entries per MAC. 4650232812Sjmallett New applications may choose to ignore 4651232812Sjmallett GMX_RXx_ADR_CAM_EN using GMX_RXx_ADR_CAM_ALL_EN 4652232812Sjmallett instead. 4653232812Sjmallett 4654232812Sjmallett EN controls the enables for the eight legacy CAM 4655232812Sjmallett entries as follows: 4656232812Sjmallett port0, EN = GMX_RX0_ADR_CAM_ALL_EN[EN<7:0>] 4657232812Sjmallett port1, EN = GMX_RX1_ADR_CAM_ALL_EN[EN<15:8>] 4658232812Sjmallett port2, EN = GMX_RX2_ADR_CAM_ALL_EN[EN<23:16>] 4659232812Sjmallett port3, EN = GMX_RX3_ADR_CAM_ALL_EN[EN<31:24>] 4660232812Sjmallett 4661232812Sjmallett The full 32 indepedent per MAC enables are in 4662232812Sjmallett GMX_RX_ADR_CAM_ALL_EN. 4663232812Sjmallett 4664232812Sjmallett Therefore, writes to GMX_RXX_ADR_CAM_ALL_EN[EN] 4665232812Sjmallett will be reflected in EN and writes to EN will be 4666232812Sjmallett reflected in GMX_RXX_ADR_CAM_ALL_EN[EN]. 4667232812Sjmallett 4668232812Sjmallett In XAUI mode, only GMX_RX0_ADR_CAM_EN is used and 4669232812Sjmallett GMX_RX[1,2,3]_ADR_CAM_EN should not be used. */ 4670215976Sjmallett#else 4671215976Sjmallett uint64_t en : 8; 4672215976Sjmallett uint64_t reserved_8_63 : 56; 4673215976Sjmallett#endif 4674215976Sjmallett } s; 4675215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; 4676215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; 4677215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; 4678215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; 4679215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; 4680215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; 4681215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; 4682215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; 4683215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; 4684215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; 4685215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; 4686232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx; 4687215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx; 4688215976Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1; 4689232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx; 4690232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx; 4691232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1; 4692232812Sjmallett struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx; 4693215976Sjmallett}; 4694215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t; 4695215976Sjmallett 4696215976Sjmallett/** 4697215976Sjmallett * cvmx_gmx#_rx#_adr_ctl 4698215976Sjmallett * 4699215976Sjmallett * GMX_RX_ADR_CTL = Address Filtering Control 4700215976Sjmallett * 4701215976Sjmallett * 4702215976Sjmallett * Notes: 4703215976Sjmallett * * ALGORITHM 4704232812Sjmallett * Here is some pseudo code that represents the address filter behavior. 4705215976Sjmallett * 4706232812Sjmallett * @verbatim 4707232812Sjmallett * bool dmac_addr_filter(uint8 prt, uint48 dmac) [ 4708232812Sjmallett * ASSERT(prt >= 0 && prt <= 3); 4709232812Sjmallett * if (is_bcst(dmac)) // broadcast accept 4710232812Sjmallett * return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT); 4711232812Sjmallett * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject 4712232812Sjmallett * return REJECT; 4713232812Sjmallett * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept 4714232812Sjmallett * return ACCEPT; 4715215976Sjmallett * 4716232812Sjmallett * cam_hit = 0; 4717215976Sjmallett * 4718232812Sjmallett * for (i=0; i<32; i++) [ 4719232812Sjmallett * if (GMX_RX[prt]_ADR_CAM_ALL_EN[EN<i>] == 0) 4720232812Sjmallett * continue; 4721232812Sjmallett * uint48 unswizzled_mac_adr = 0x0; 4722232812Sjmallett * for (j=5; j>=0; j--) [ 4723232812Sjmallett * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[i>>3]_ADR_CAM[j][ADR<(i&7)*8+7:(i&7)*8>]; 4724232812Sjmallett * ] 4725232812Sjmallett * if (unswizzled_mac_adr == dmac) [ 4726232812Sjmallett * cam_hit = 1; 4727232812Sjmallett * break; 4728232812Sjmallett * ] 4729215976Sjmallett * ] 4730232812Sjmallett * 4731232812Sjmallett * if (cam_hit) 4732232812Sjmallett * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT); 4733232812Sjmallett * else 4734232812Sjmallett * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT); 4735215976Sjmallett * ] 4736232812Sjmallett * @endverbatim 4737215976Sjmallett * 4738232812Sjmallett * * XAUI Mode 4739232812Sjmallett * 4740232812Sjmallett * In XAUI mode, only GMX_RX0_ADR_CTL is used. GMX_RX[1,2,3]_ADR_CTL should not be used. 4741215976Sjmallett */ 4742232812Sjmallettunion cvmx_gmxx_rxx_adr_ctl { 4743215976Sjmallett uint64_t u64; 4744232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s { 4745232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4746215976Sjmallett uint64_t reserved_4_63 : 60; 4747215976Sjmallett uint64_t cam_mode : 1; /**< Allow or deny DMAC address filter 4748215976Sjmallett 0 = reject the packet on DMAC address match 4749215976Sjmallett 1 = accept the packet on DMAC address match */ 4750215976Sjmallett uint64_t mcst : 2; /**< Multicast Mode 4751215976Sjmallett 0 = Use the Address Filter CAM 4752215976Sjmallett 1 = Force reject all multicast packets 4753215976Sjmallett 2 = Force accept all multicast packets 4754215976Sjmallett 3 = Reserved */ 4755215976Sjmallett uint64_t bcst : 1; /**< Accept All Broadcast Packets */ 4756215976Sjmallett#else 4757215976Sjmallett uint64_t bcst : 1; 4758215976Sjmallett uint64_t mcst : 2; 4759215976Sjmallett uint64_t cam_mode : 1; 4760215976Sjmallett uint64_t reserved_4_63 : 60; 4761215976Sjmallett#endif 4762215976Sjmallett } s; 4763215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; 4764215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; 4765215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; 4766215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; 4767215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; 4768215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; 4769215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; 4770215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; 4771215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; 4772215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; 4773215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; 4774232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn61xx; 4775215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn63xx; 4776215976Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1; 4777232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn66xx; 4778232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn68xx; 4779232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1; 4780232812Sjmallett struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx; 4781215976Sjmallett}; 4782215976Sjmalletttypedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t; 4783215976Sjmallett 4784215976Sjmallett/** 4785215976Sjmallett * cvmx_gmx#_rx#_decision 4786215976Sjmallett * 4787215976Sjmallett * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet 4788215976Sjmallett * 4789215976Sjmallett * 4790215976Sjmallett * Notes: 4791215976Sjmallett * As each byte in a packet is received by GMX, the L2 byte count is compared 4792215976Sjmallett * against the GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes 4793215976Sjmallett * from the beginning of the L2 header (DMAC). In normal operation, the L2 4794215976Sjmallett * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any 4795215976Sjmallett * optional UDD skip data (GMX_RX_UDD_SKP[LEN]). 4796215976Sjmallett * 4797215976Sjmallett * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the 4798215976Sjmallett * packet and would require UDD skip length to account for them. 4799215976Sjmallett * 4800215976Sjmallett * L2 Size 4801215976Sjmallett * Port Mode <GMX_RX_DECISION bytes (default=24) >=GMX_RX_DECISION bytes (default=24) 4802215976Sjmallett * 4803215976Sjmallett * Full Duplex accept packet apply filters 4804215976Sjmallett * no filtering is applied accept packet based on DMAC and PAUSE packet filters 4805215976Sjmallett * 4806215976Sjmallett * Half Duplex drop packet apply filters 4807215976Sjmallett * packet is unconditionally dropped accept packet based on DMAC 4808215976Sjmallett * 4809215976Sjmallett * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8) 4810215976Sjmallett */ 4811232812Sjmallettunion cvmx_gmxx_rxx_decision { 4812215976Sjmallett uint64_t u64; 4813232812Sjmallett struct cvmx_gmxx_rxx_decision_s { 4814232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4815215976Sjmallett uint64_t reserved_5_63 : 59; 4816215976Sjmallett uint64_t cnt : 5; /**< The byte count to decide when to accept or filter 4817215976Sjmallett a packet. */ 4818215976Sjmallett#else 4819215976Sjmallett uint64_t cnt : 5; 4820215976Sjmallett uint64_t reserved_5_63 : 59; 4821215976Sjmallett#endif 4822215976Sjmallett } s; 4823215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn30xx; 4824215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn31xx; 4825215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn38xx; 4826215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn38xxp2; 4827215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn50xx; 4828215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn52xx; 4829215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn52xxp1; 4830215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn56xx; 4831215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn56xxp1; 4832215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn58xx; 4833215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn58xxp1; 4834232812Sjmallett struct cvmx_gmxx_rxx_decision_s cn61xx; 4835215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn63xx; 4836215976Sjmallett struct cvmx_gmxx_rxx_decision_s cn63xxp1; 4837232812Sjmallett struct cvmx_gmxx_rxx_decision_s cn66xx; 4838232812Sjmallett struct cvmx_gmxx_rxx_decision_s cn68xx; 4839232812Sjmallett struct cvmx_gmxx_rxx_decision_s cn68xxp1; 4840232812Sjmallett struct cvmx_gmxx_rxx_decision_s cnf71xx; 4841215976Sjmallett}; 4842215976Sjmalletttypedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t; 4843215976Sjmallett 4844215976Sjmallett/** 4845215976Sjmallett * cvmx_gmx#_rx#_frm_chk 4846215976Sjmallett * 4847215976Sjmallett * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame 4848215976Sjmallett * 4849215976Sjmallett * 4850215976Sjmallett * Notes: 4851215976Sjmallett * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW. 4852215976Sjmallett * 4853215976Sjmallett * In XAUI mode prt0 is used for checking. 4854215976Sjmallett */ 4855232812Sjmallettunion cvmx_gmxx_rxx_frm_chk { 4856215976Sjmallett uint64_t u64; 4857232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_s { 4858232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4859215976Sjmallett uint64_t reserved_10_63 : 54; 4860215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 4861215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 4862215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 4863215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 4864215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 4865215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 4866215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 4867215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 4868215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 4869215976Sjmallett (SGMII/1000Base-X only) */ 4870215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize */ 4871215976Sjmallett#else 4872215976Sjmallett uint64_t minerr : 1; 4873215976Sjmallett uint64_t carext : 1; 4874215976Sjmallett uint64_t maxerr : 1; 4875215976Sjmallett uint64_t jabber : 1; 4876215976Sjmallett uint64_t fcserr : 1; 4877215976Sjmallett uint64_t alnerr : 1; 4878215976Sjmallett uint64_t lenerr : 1; 4879215976Sjmallett uint64_t rcverr : 1; 4880215976Sjmallett uint64_t skperr : 1; 4881215976Sjmallett uint64_t niberr : 1; 4882215976Sjmallett uint64_t reserved_10_63 : 54; 4883215976Sjmallett#endif 4884215976Sjmallett } s; 4885215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn30xx; 4886215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn31xx; 4887215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn38xx; 4888215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; 4889232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn50xx { 4890232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4891215976Sjmallett uint64_t reserved_10_63 : 54; 4892215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 4893215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 4894215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 4895215976Sjmallett uint64_t reserved_6_6 : 1; 4896215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 4897215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 4898215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 4899215976Sjmallett uint64_t reserved_2_2 : 1; 4900215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 4901215976Sjmallett uint64_t reserved_0_0 : 1; 4902215976Sjmallett#else 4903215976Sjmallett uint64_t reserved_0_0 : 1; 4904215976Sjmallett uint64_t carext : 1; 4905215976Sjmallett uint64_t reserved_2_2 : 1; 4906215976Sjmallett uint64_t jabber : 1; 4907215976Sjmallett uint64_t fcserr : 1; 4908215976Sjmallett uint64_t alnerr : 1; 4909215976Sjmallett uint64_t reserved_6_6 : 1; 4910215976Sjmallett uint64_t rcverr : 1; 4911215976Sjmallett uint64_t skperr : 1; 4912215976Sjmallett uint64_t niberr : 1; 4913215976Sjmallett uint64_t reserved_10_63 : 54; 4914215976Sjmallett#endif 4915215976Sjmallett } cn50xx; 4916232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn52xx { 4917232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4918215976Sjmallett uint64_t reserved_9_63 : 55; 4919215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 4920215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 4921215976Sjmallett uint64_t reserved_5_6 : 2; 4922215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 4923215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 4924215976Sjmallett uint64_t reserved_2_2 : 1; 4925215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 4926215976Sjmallett (SGMII/1000Base-X only) */ 4927215976Sjmallett uint64_t reserved_0_0 : 1; 4928215976Sjmallett#else 4929215976Sjmallett uint64_t reserved_0_0 : 1; 4930215976Sjmallett uint64_t carext : 1; 4931215976Sjmallett uint64_t reserved_2_2 : 1; 4932215976Sjmallett uint64_t jabber : 1; 4933215976Sjmallett uint64_t fcserr : 1; 4934215976Sjmallett uint64_t reserved_5_6 : 2; 4935215976Sjmallett uint64_t rcverr : 1; 4936215976Sjmallett uint64_t skperr : 1; 4937215976Sjmallett uint64_t reserved_9_63 : 55; 4938215976Sjmallett#endif 4939215976Sjmallett } cn52xx; 4940215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; 4941215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; 4942215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; 4943215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn58xx; 4944215976Sjmallett struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; 4945232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx { 4946232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4947215976Sjmallett uint64_t reserved_9_63 : 55; 4948215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 4949215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 4950215976Sjmallett uint64_t reserved_5_6 : 2; 4951215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 4952215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 4953215976Sjmallett uint64_t reserved_2_2 : 1; 4954215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 4955215976Sjmallett (SGMII/1000Base-X only) */ 4956215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize */ 4957215976Sjmallett#else 4958215976Sjmallett uint64_t minerr : 1; 4959215976Sjmallett uint64_t carext : 1; 4960215976Sjmallett uint64_t reserved_2_2 : 1; 4961215976Sjmallett uint64_t jabber : 1; 4962215976Sjmallett uint64_t fcserr : 1; 4963215976Sjmallett uint64_t reserved_5_6 : 2; 4964215976Sjmallett uint64_t rcverr : 1; 4965215976Sjmallett uint64_t skperr : 1; 4966215976Sjmallett uint64_t reserved_9_63 : 55; 4967215976Sjmallett#endif 4968232812Sjmallett } cn61xx; 4969232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx; 4970232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1; 4971232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx; 4972232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx; 4973232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1; 4974232812Sjmallett struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx; 4975215976Sjmallett}; 4976215976Sjmalletttypedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t; 4977215976Sjmallett 4978215976Sjmallett/** 4979215976Sjmallett * cvmx_gmx#_rx#_frm_ctl 4980215976Sjmallett * 4981215976Sjmallett * GMX_RX_FRM_CTL = Frame Control 4982215976Sjmallett * 4983215976Sjmallett * 4984215976Sjmallett * Notes: 4985215976Sjmallett * * PRE_STRP 4986215976Sjmallett * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP 4987215976Sjmallett * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane 4988215976Sjmallett * core as part of the packet. 4989215976Sjmallett * 4990215976Sjmallett * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet 4991215976Sjmallett * size when checking against the MIN and MAX bounds. Furthermore, the bytes 4992215976Sjmallett * are skipped when locating the start of the L2 header for DMAC and Control 4993215976Sjmallett * frame recognition. 4994215976Sjmallett * 4995215976Sjmallett * * CTL_BCK/CTL_DRP 4996215976Sjmallett * These bits control how the HW handles incoming PAUSE packets. Here are 4997215976Sjmallett * the most common modes of operation: 4998215976Sjmallett * CTL_BCK=1,CTL_DRP=1 - HW does it all 4999215976Sjmallett * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames 5000215976Sjmallett * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored 5001215976Sjmallett * 5002215976Sjmallett * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode. 5003215976Sjmallett * Since PAUSE packets only apply to fulldup operation, any PAUSE packet 5004215976Sjmallett * would constitute an exception which should be handled by the processing 5005215976Sjmallett * cores. PAUSE packets should not be forwarded. 5006215976Sjmallett */ 5007232812Sjmallettunion cvmx_gmxx_rxx_frm_ctl { 5008215976Sjmallett uint64_t u64; 5009232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_s { 5010232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5011215976Sjmallett uint64_t reserved_13_63 : 51; 5012215976Sjmallett uint64_t ptp_mode : 1; /**< Timestamp mode 5013215976Sjmallett When PTP_MODE is set, a 64-bit timestamp will be 5014215976Sjmallett prepended to every incoming packet. The timestamp 5015215976Sjmallett bytes are added to the packet in such a way as to 5016215976Sjmallett not modify the packet's receive byte count. This 5017215976Sjmallett implies that the GMX_RX_JABBER, MINERR, 5018215976Sjmallett GMX_RX_DECISION, GMX_RX_UDD_SKP, and the 5019215976Sjmallett GMX_RX_STATS_* do not require any adjustment as 5020215976Sjmallett they operate on the received packet size. 5021215976Sjmallett When the packet reaches PKI, its size will 5022215976Sjmallett reflect the additional bytes and is subject to 5023215976Sjmallett the restrictions below. 5024215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. 5025215976Sjmallett If PTP_MODE=1, 5026215976Sjmallett PIP_PRT_CFGx[SKIP] should be increased by 8. 5027215976Sjmallett PIP_PRT_CFGx[HIGIG_EN] should be 0. 5028215976Sjmallett PIP_FRM_CHKx[MAXLEN] should be increased by 8. 5029215976Sjmallett PIP_FRM_CHKx[MINLEN] should be increased by 8. 5030232812Sjmallett PIP_TAG_INCx[EN] should be adjusted. 5031232812Sjmallett PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */ 5032215976Sjmallett uint64_t reserved_11_11 : 1; 5033215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 5034215976Sjmallett due to PARITAL packets */ 5035215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 5036215976Sjmallett regardless of the number of previous PREAMBLE 5037215976Sjmallett nibbles. In this mode, PRE_STRP should be set to 5038215976Sjmallett account for the variable nature of the PREAMBLE. 5039215976Sjmallett PRE_CHK must be set to enable this and all 5040215976Sjmallett PREAMBLE features. 5041215976Sjmallett (SGMII at 10/100Mbs only) */ 5042215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 5043215976Sjmallett sized pkts with padding in the client data 5044215976Sjmallett (PASS3 Only) */ 5045215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 5046215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 5047215976Sjmallett GMX will begin the frame at the first SFD. 5048215976Sjmallett PRE_CHK must be set to enable this and all 5049215976Sjmallett PREAMBLE features. 5050215976Sjmallett (SGMII/1000Base-X only) */ 5051215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5052215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5053215976Sjmallett Multicast address */ 5054215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5055215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5056215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5057215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5058215976Sjmallett 1=PREAMBLE+SFD is dropped 5059215976Sjmallett PRE_CHK must be set to enable this and all 5060215976Sjmallett PREAMBLE features. 5061215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 5062215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send a valid 802.3 5063215976Sjmallett PREAMBLE to begin every frame. GMX checks that a 5064215976Sjmallett valid PREAMBLE is received (based on PRE_FREE). 5065215976Sjmallett When a problem does occur within the PREAMBLE 5066215976Sjmallett seqeunce, the frame is marked as bad and not sent 5067215976Sjmallett into the core. The GMX_GMX_RX_INT_REG[PCTERR] 5068215976Sjmallett interrupt is also raised. 5069215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK 5070215976Sjmallett must be zero. 5071215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 5072215976Sjmallett#else 5073215976Sjmallett uint64_t pre_chk : 1; 5074215976Sjmallett uint64_t pre_strp : 1; 5075215976Sjmallett uint64_t ctl_drp : 1; 5076215976Sjmallett uint64_t ctl_bck : 1; 5077215976Sjmallett uint64_t ctl_mcst : 1; 5078215976Sjmallett uint64_t ctl_smac : 1; 5079215976Sjmallett uint64_t pre_free : 1; 5080215976Sjmallett uint64_t vlan_len : 1; 5081215976Sjmallett uint64_t pad_len : 1; 5082215976Sjmallett uint64_t pre_align : 1; 5083215976Sjmallett uint64_t null_dis : 1; 5084215976Sjmallett uint64_t reserved_11_11 : 1; 5085215976Sjmallett uint64_t ptp_mode : 1; 5086215976Sjmallett uint64_t reserved_13_63 : 51; 5087215976Sjmallett#endif 5088215976Sjmallett } s; 5089232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn30xx { 5090232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5091215976Sjmallett uint64_t reserved_9_63 : 55; 5092215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 5093215976Sjmallett sized pkts with padding in the client data */ 5094215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 5095215976Sjmallett uint64_t pre_free : 1; /**< Allows for less strict PREAMBLE checking. 5096215976Sjmallett 0-7 cycles of PREAMBLE followed by SFD (pass 1.0) 5097215976Sjmallett 0-254 cycles of PREAMBLE followed by SFD (else) */ 5098215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5099215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5100215976Sjmallett Multicast address */ 5101215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5102215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5103215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5104215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5105215976Sjmallett 1=PREAMBLE+SFD is dropped */ 5106215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 5107215976Sjmallett to begin every frame. GMX checks that the 5108215976Sjmallett PREAMBLE is sent correctly */ 5109215976Sjmallett#else 5110215976Sjmallett uint64_t pre_chk : 1; 5111215976Sjmallett uint64_t pre_strp : 1; 5112215976Sjmallett uint64_t ctl_drp : 1; 5113215976Sjmallett uint64_t ctl_bck : 1; 5114215976Sjmallett uint64_t ctl_mcst : 1; 5115215976Sjmallett uint64_t ctl_smac : 1; 5116215976Sjmallett uint64_t pre_free : 1; 5117215976Sjmallett uint64_t vlan_len : 1; 5118215976Sjmallett uint64_t pad_len : 1; 5119215976Sjmallett uint64_t reserved_9_63 : 55; 5120215976Sjmallett#endif 5121215976Sjmallett } cn30xx; 5122232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn31xx { 5123232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5124215976Sjmallett uint64_t reserved_8_63 : 56; 5125215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 5126215976Sjmallett uint64_t pre_free : 1; /**< Allows for less strict PREAMBLE checking. 5127215976Sjmallett 0 - 7 cycles of PREAMBLE followed by SFD (pass1.0) 5128215976Sjmallett 0 - 254 cycles of PREAMBLE followed by SFD (else) */ 5129215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5130215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5131215976Sjmallett Multicast address */ 5132215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5133215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5134215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5135215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5136215976Sjmallett 1=PREAMBLE+SFD is dropped */ 5137215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 5138215976Sjmallett to begin every frame. GMX checks that the 5139215976Sjmallett PREAMBLE is sent correctly */ 5140215976Sjmallett#else 5141215976Sjmallett uint64_t pre_chk : 1; 5142215976Sjmallett uint64_t pre_strp : 1; 5143215976Sjmallett uint64_t ctl_drp : 1; 5144215976Sjmallett uint64_t ctl_bck : 1; 5145215976Sjmallett uint64_t ctl_mcst : 1; 5146215976Sjmallett uint64_t ctl_smac : 1; 5147215976Sjmallett uint64_t pre_free : 1; 5148215976Sjmallett uint64_t vlan_len : 1; 5149215976Sjmallett uint64_t reserved_8_63 : 56; 5150215976Sjmallett#endif 5151215976Sjmallett } cn31xx; 5152215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; 5153215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; 5154232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn50xx { 5155232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5156215976Sjmallett uint64_t reserved_11_63 : 53; 5157215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 5158215976Sjmallett due to PARITAL packets */ 5159215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 5160215976Sjmallett regardless of the number of previous PREAMBLE 5161215976Sjmallett nibbles. In this mode, PREAMBLE can be consumed 5162215976Sjmallett by the HW so when PRE_ALIGN is set, PRE_FREE, 5163215976Sjmallett PRE_STRP must be set for correct operation. 5164215976Sjmallett PRE_CHK must be set to enable this and all 5165215976Sjmallett PREAMBLE features. */ 5166215976Sjmallett uint64_t reserved_7_8 : 2; 5167215976Sjmallett uint64_t pre_free : 1; /**< Allows for less strict PREAMBLE checking. 5168215976Sjmallett 0-254 cycles of PREAMBLE followed by SFD */ 5169215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5170215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5171215976Sjmallett Multicast address */ 5172215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5173215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5174215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5175215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5176215976Sjmallett 1=PREAMBLE+SFD is dropped */ 5177215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 5178215976Sjmallett to begin every frame. GMX checks that the 5179215976Sjmallett PREAMBLE is sent correctly */ 5180215976Sjmallett#else 5181215976Sjmallett uint64_t pre_chk : 1; 5182215976Sjmallett uint64_t pre_strp : 1; 5183215976Sjmallett uint64_t ctl_drp : 1; 5184215976Sjmallett uint64_t ctl_bck : 1; 5185215976Sjmallett uint64_t ctl_mcst : 1; 5186215976Sjmallett uint64_t ctl_smac : 1; 5187215976Sjmallett uint64_t pre_free : 1; 5188215976Sjmallett uint64_t reserved_7_8 : 2; 5189215976Sjmallett uint64_t pre_align : 1; 5190215976Sjmallett uint64_t null_dis : 1; 5191215976Sjmallett uint64_t reserved_11_63 : 53; 5192215976Sjmallett#endif 5193215976Sjmallett } cn50xx; 5194215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; 5195215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; 5196215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; 5197232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { 5198232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5199215976Sjmallett uint64_t reserved_10_63 : 54; 5200215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 5201215976Sjmallett regardless of the number of previous PREAMBLE 5202215976Sjmallett nibbles. In this mode, PRE_STRP should be set to 5203215976Sjmallett account for the variable nature of the PREAMBLE. 5204215976Sjmallett PRE_CHK must be set to enable this and all 5205215976Sjmallett PREAMBLE features. 5206215976Sjmallett (SGMII at 10/100Mbs only) */ 5207215976Sjmallett uint64_t reserved_7_8 : 2; 5208215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 5209215976Sjmallett 0 - 254 cycles of PREAMBLE followed by SFD 5210215976Sjmallett PRE_CHK must be set to enable this and all 5211215976Sjmallett PREAMBLE features. 5212215976Sjmallett (SGMII/1000Base-X only) */ 5213215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5214215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5215215976Sjmallett Multicast address */ 5216215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5217215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5218215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5219215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5220215976Sjmallett 1=PREAMBLE+SFD is dropped 5221215976Sjmallett PRE_CHK must be set to enable this and all 5222215976Sjmallett PREAMBLE features. */ 5223215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 5224215976Sjmallett to begin every frame. GMX checks that the 5225215976Sjmallett PREAMBLE is sent correctly. 5226215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK 5227215976Sjmallett must be zero. */ 5228215976Sjmallett#else 5229215976Sjmallett uint64_t pre_chk : 1; 5230215976Sjmallett uint64_t pre_strp : 1; 5231215976Sjmallett uint64_t ctl_drp : 1; 5232215976Sjmallett uint64_t ctl_bck : 1; 5233215976Sjmallett uint64_t ctl_mcst : 1; 5234215976Sjmallett uint64_t ctl_smac : 1; 5235215976Sjmallett uint64_t pre_free : 1; 5236215976Sjmallett uint64_t reserved_7_8 : 2; 5237215976Sjmallett uint64_t pre_align : 1; 5238215976Sjmallett uint64_t reserved_10_63 : 54; 5239215976Sjmallett#endif 5240215976Sjmallett } cn56xxp1; 5241232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn58xx { 5242232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5243215976Sjmallett uint64_t reserved_11_63 : 53; 5244215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 5245215976Sjmallett due to PARITAL packets 5246215976Sjmallett In spi4 mode, all ports use prt0 for checking. */ 5247215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 5248215976Sjmallett regardless of the number of previous PREAMBLE 5249215976Sjmallett nibbles. In this mode, PREAMBLE can be consumed 5250215976Sjmallett by the HW so when PRE_ALIGN is set, PRE_FREE, 5251215976Sjmallett PRE_STRP must be set for correct operation. 5252215976Sjmallett PRE_CHK must be set to enable this and all 5253215976Sjmallett PREAMBLE features. */ 5254215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 5255215976Sjmallett sized pkts with padding in the client data 5256215976Sjmallett (PASS3 Only) */ 5257215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 5258215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 5259215976Sjmallett 0 - 254 cycles of PREAMBLE followed by SFD */ 5260215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5261215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5262215976Sjmallett Multicast address */ 5263215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5264215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5265215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5266215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5267215976Sjmallett 1=PREAMBLE+SFD is dropped */ 5268215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 5269215976Sjmallett to begin every frame. GMX checks that the 5270215976Sjmallett PREAMBLE is sent correctly */ 5271215976Sjmallett#else 5272215976Sjmallett uint64_t pre_chk : 1; 5273215976Sjmallett uint64_t pre_strp : 1; 5274215976Sjmallett uint64_t ctl_drp : 1; 5275215976Sjmallett uint64_t ctl_bck : 1; 5276215976Sjmallett uint64_t ctl_mcst : 1; 5277215976Sjmallett uint64_t ctl_smac : 1; 5278215976Sjmallett uint64_t pre_free : 1; 5279215976Sjmallett uint64_t vlan_len : 1; 5280215976Sjmallett uint64_t pad_len : 1; 5281215976Sjmallett uint64_t pre_align : 1; 5282215976Sjmallett uint64_t null_dis : 1; 5283215976Sjmallett uint64_t reserved_11_63 : 53; 5284215976Sjmallett#endif 5285215976Sjmallett } cn58xx; 5286215976Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; 5287232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx { 5288232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5289215976Sjmallett uint64_t reserved_13_63 : 51; 5290215976Sjmallett uint64_t ptp_mode : 1; /**< Timestamp mode 5291215976Sjmallett When PTP_MODE is set, a 64-bit timestamp will be 5292215976Sjmallett prepended to every incoming packet. The timestamp 5293215976Sjmallett bytes are added to the packet in such a way as to 5294215976Sjmallett not modify the packet's receive byte count. This 5295215976Sjmallett implies that the GMX_RX_JABBER, MINERR, 5296215976Sjmallett GMX_RX_DECISION, GMX_RX_UDD_SKP, and the 5297215976Sjmallett GMX_RX_STATS_* do not require any adjustment as 5298215976Sjmallett they operate on the received packet size. 5299215976Sjmallett When the packet reaches PKI, its size will 5300215976Sjmallett reflect the additional bytes and is subject to 5301215976Sjmallett the restrictions below. 5302215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. 5303215976Sjmallett If PTP_MODE=1, 5304215976Sjmallett PIP_PRT_CFGx[SKIP] should be increased by 8. 5305215976Sjmallett PIP_PRT_CFGx[HIGIG_EN] should be 0. 5306215976Sjmallett PIP_FRM_CHKx[MAXLEN] should be increased by 8. 5307215976Sjmallett PIP_FRM_CHKx[MINLEN] should be increased by 8. 5308232812Sjmallett PIP_TAG_INCx[EN] should be adjusted. 5309232812Sjmallett PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */ 5310215976Sjmallett uint64_t reserved_11_11 : 1; 5311215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 5312215976Sjmallett due to PARITAL packets */ 5313215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 5314215976Sjmallett regardless of the number of previous PREAMBLE 5315215976Sjmallett nibbles. In this mode, PRE_STRP should be set to 5316215976Sjmallett account for the variable nature of the PREAMBLE. 5317215976Sjmallett PRE_CHK must be set to enable this and all 5318215976Sjmallett PREAMBLE features. 5319215976Sjmallett (SGMII at 10/100Mbs only) */ 5320215976Sjmallett uint64_t reserved_7_8 : 2; 5321215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 5322215976Sjmallett GMX will begin the frame at the first SFD. 5323215976Sjmallett PRE_CHK must be set to enable this and all 5324215976Sjmallett PREAMBLE features. 5325215976Sjmallett (SGMII/1000Base-X only) */ 5326215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 5327215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 5328215976Sjmallett Multicast address */ 5329215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 5330215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 5331215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 5332215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 5333215976Sjmallett 1=PREAMBLE+SFD is dropped 5334215976Sjmallett PRE_CHK must be set to enable this and all 5335215976Sjmallett PREAMBLE features. 5336215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 5337215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send a valid 802.3 5338215976Sjmallett PREAMBLE to begin every frame. GMX checks that a 5339215976Sjmallett valid PREAMBLE is received (based on PRE_FREE). 5340215976Sjmallett When a problem does occur within the PREAMBLE 5341215976Sjmallett seqeunce, the frame is marked as bad and not sent 5342215976Sjmallett into the core. The GMX_GMX_RX_INT_REG[PCTERR] 5343215976Sjmallett interrupt is also raised. 5344215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK 5345215976Sjmallett must be zero. 5346215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 5347215976Sjmallett#else 5348215976Sjmallett uint64_t pre_chk : 1; 5349215976Sjmallett uint64_t pre_strp : 1; 5350215976Sjmallett uint64_t ctl_drp : 1; 5351215976Sjmallett uint64_t ctl_bck : 1; 5352215976Sjmallett uint64_t ctl_mcst : 1; 5353215976Sjmallett uint64_t ctl_smac : 1; 5354215976Sjmallett uint64_t pre_free : 1; 5355215976Sjmallett uint64_t reserved_7_8 : 2; 5356215976Sjmallett uint64_t pre_align : 1; 5357215976Sjmallett uint64_t null_dis : 1; 5358215976Sjmallett uint64_t reserved_11_11 : 1; 5359215976Sjmallett uint64_t ptp_mode : 1; 5360215976Sjmallett uint64_t reserved_13_63 : 51; 5361215976Sjmallett#endif 5362232812Sjmallett } cn61xx; 5363232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx; 5364232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1; 5365232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx; 5366232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx; 5367232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1; 5368232812Sjmallett struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx; 5369215976Sjmallett}; 5370215976Sjmalletttypedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t; 5371215976Sjmallett 5372215976Sjmallett/** 5373215976Sjmallett * cvmx_gmx#_rx#_frm_max 5374215976Sjmallett * 5375215976Sjmallett * GMX_RX_FRM_MAX = Frame Max length 5376215976Sjmallett * 5377215976Sjmallett * 5378215976Sjmallett * Notes: 5379215976Sjmallett * In spi4 mode, all spi4 ports use prt0 for checking. 5380215976Sjmallett * 5381215976Sjmallett * When changing the LEN field, be sure that LEN does not exceed 5382215976Sjmallett * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that 5383215976Sjmallett * are within the maximum length parameter to be rejected because they exceed 5384215976Sjmallett * the GMX_RX_JABBER[CNT] limit. 5385215976Sjmallett */ 5386232812Sjmallettunion cvmx_gmxx_rxx_frm_max { 5387215976Sjmallett uint64_t u64; 5388232812Sjmallett struct cvmx_gmxx_rxx_frm_max_s { 5389232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5390215976Sjmallett uint64_t reserved_16_63 : 48; 5391215976Sjmallett uint64_t len : 16; /**< Byte count for Max-sized frame check 5392215976Sjmallett GMX_RXn_FRM_CHK[MAXERR] enables the check for 5393215976Sjmallett port n. 5394215976Sjmallett If enabled, failing packets set the MAXERR 5395215976Sjmallett interrupt and work-queue entry WORD2[opcode] is 5396215976Sjmallett set to OVER_FCS (0x3, if packet has bad FCS) or 5397215976Sjmallett OVER_ERR (0x4, if packet has good FCS). 5398215976Sjmallett LEN =< GMX_RX_JABBER[CNT] */ 5399215976Sjmallett#else 5400215976Sjmallett uint64_t len : 16; 5401215976Sjmallett uint64_t reserved_16_63 : 48; 5402215976Sjmallett#endif 5403215976Sjmallett } s; 5404215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn30xx; 5405215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn31xx; 5406215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn38xx; 5407215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; 5408215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn58xx; 5409215976Sjmallett struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; 5410215976Sjmallett}; 5411215976Sjmalletttypedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t; 5412215976Sjmallett 5413215976Sjmallett/** 5414215976Sjmallett * cvmx_gmx#_rx#_frm_min 5415215976Sjmallett * 5416215976Sjmallett * GMX_RX_FRM_MIN = Frame Min length 5417215976Sjmallett * 5418215976Sjmallett * 5419215976Sjmallett * Notes: 5420215976Sjmallett * In spi4 mode, all spi4 ports use prt0 for checking. 5421215976Sjmallett * 5422215976Sjmallett */ 5423232812Sjmallettunion cvmx_gmxx_rxx_frm_min { 5424215976Sjmallett uint64_t u64; 5425232812Sjmallett struct cvmx_gmxx_rxx_frm_min_s { 5426232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5427215976Sjmallett uint64_t reserved_16_63 : 48; 5428215976Sjmallett uint64_t len : 16; /**< Byte count for Min-sized frame check 5429215976Sjmallett GMX_RXn_FRM_CHK[MINERR] enables the check for 5430215976Sjmallett port n. 5431215976Sjmallett If enabled, failing packets set the MINERR 5432215976Sjmallett interrupt and work-queue entry WORD2[opcode] is 5433215976Sjmallett set to UNDER_FCS (0x6, if packet has bad FCS) or 5434215976Sjmallett UNDER_ERR (0x8, if packet has good FCS). */ 5435215976Sjmallett#else 5436215976Sjmallett uint64_t len : 16; 5437215976Sjmallett uint64_t reserved_16_63 : 48; 5438215976Sjmallett#endif 5439215976Sjmallett } s; 5440215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn30xx; 5441215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn31xx; 5442215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn38xx; 5443215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; 5444215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn58xx; 5445215976Sjmallett struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; 5446215976Sjmallett}; 5447215976Sjmalletttypedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t; 5448215976Sjmallett 5449215976Sjmallett/** 5450215976Sjmallett * cvmx_gmx#_rx#_ifg 5451215976Sjmallett * 5452215976Sjmallett * GMX_RX_IFG = RX Min IFG 5453215976Sjmallett * 5454215976Sjmallett */ 5455232812Sjmallettunion cvmx_gmxx_rxx_ifg { 5456215976Sjmallett uint64_t u64; 5457232812Sjmallett struct cvmx_gmxx_rxx_ifg_s { 5458232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5459215976Sjmallett uint64_t reserved_4_63 : 60; 5460215976Sjmallett uint64_t ifg : 4; /**< Min IFG (in IFG*8 bits) between packets used to 5461215976Sjmallett determine IFGERR. Normally IFG is 96 bits. 5462215976Sjmallett Note in some operating modes, IFG cycles can be 5463215976Sjmallett inserted or removed in order to achieve clock rate 5464215976Sjmallett adaptation. For these reasons, the default value 5465215976Sjmallett is slightly conservative and does not check upto 5466215976Sjmallett the full 96 bits of IFG. 5467215976Sjmallett (SGMII/1000Base-X only) */ 5468215976Sjmallett#else 5469215976Sjmallett uint64_t ifg : 4; 5470215976Sjmallett uint64_t reserved_4_63 : 60; 5471215976Sjmallett#endif 5472215976Sjmallett } s; 5473215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn30xx; 5474215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn31xx; 5475215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn38xx; 5476215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn38xxp2; 5477215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn50xx; 5478215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn52xx; 5479215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn52xxp1; 5480215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn56xx; 5481215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn56xxp1; 5482215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn58xx; 5483215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn58xxp1; 5484232812Sjmallett struct cvmx_gmxx_rxx_ifg_s cn61xx; 5485215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn63xx; 5486215976Sjmallett struct cvmx_gmxx_rxx_ifg_s cn63xxp1; 5487232812Sjmallett struct cvmx_gmxx_rxx_ifg_s cn66xx; 5488232812Sjmallett struct cvmx_gmxx_rxx_ifg_s cn68xx; 5489232812Sjmallett struct cvmx_gmxx_rxx_ifg_s cn68xxp1; 5490232812Sjmallett struct cvmx_gmxx_rxx_ifg_s cnf71xx; 5491215976Sjmallett}; 5492215976Sjmalletttypedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t; 5493215976Sjmallett 5494215976Sjmallett/** 5495215976Sjmallett * cvmx_gmx#_rx#_int_en 5496215976Sjmallett * 5497215976Sjmallett * GMX_RX_INT_EN = Interrupt Enable 5498215976Sjmallett * 5499215976Sjmallett * 5500215976Sjmallett * Notes: 5501215976Sjmallett * In XAUI mode prt0 is used for checking. 5502215976Sjmallett * 5503215976Sjmallett */ 5504232812Sjmallettunion cvmx_gmxx_rxx_int_en { 5505215976Sjmallett uint64_t u64; 5506232812Sjmallett struct cvmx_gmxx_rxx_int_en_s { 5507232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5508215976Sjmallett uint64_t reserved_29_63 : 35; 5509215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */ 5510215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */ 5511215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 5512215976Sjmallett (XAUI Mode only) */ 5513215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 5514215976Sjmallett (XAUI Mode only) */ 5515215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 5516215976Sjmallett (XAUI Mode only) */ 5517215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 5518215976Sjmallett than /T/. The error propagation control 5519215976Sjmallett character /E/ will be included as part of the 5520215976Sjmallett frame and does not cause a frame termination. 5521215976Sjmallett (XAUI Mode only) */ 5522215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 5523215976Sjmallett (XAUI Mode only) */ 5524215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 5525215976Sjmallett (XAUI Mode only) */ 5526215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 5527215976Sjmallett (XAUI Mode only) */ 5528215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5529215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 5530215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 5531215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 5532215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 5533215976Sjmallett (SGMII/1000Base-X only) */ 5534215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 5535215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 5536215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 5537215976Sjmallett (SGMII/1000Base-X only) */ 5538215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 5539215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5540215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 5541215976Sjmallett (SGMII/1000Base-X only) */ 5542215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 5543215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5544215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 5545215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 5546215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 5547215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5548215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5549215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 5550215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 5551215976Sjmallett (SGMII/1000Base-X only) */ 5552215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize */ 5553215976Sjmallett#else 5554215976Sjmallett uint64_t minerr : 1; 5555215976Sjmallett uint64_t carext : 1; 5556215976Sjmallett uint64_t maxerr : 1; 5557215976Sjmallett uint64_t jabber : 1; 5558215976Sjmallett uint64_t fcserr : 1; 5559215976Sjmallett uint64_t alnerr : 1; 5560215976Sjmallett uint64_t lenerr : 1; 5561215976Sjmallett uint64_t rcverr : 1; 5562215976Sjmallett uint64_t skperr : 1; 5563215976Sjmallett uint64_t niberr : 1; 5564215976Sjmallett uint64_t ovrerr : 1; 5565215976Sjmallett uint64_t pcterr : 1; 5566215976Sjmallett uint64_t rsverr : 1; 5567215976Sjmallett uint64_t falerr : 1; 5568215976Sjmallett uint64_t coldet : 1; 5569215976Sjmallett uint64_t ifgerr : 1; 5570215976Sjmallett uint64_t phy_link : 1; 5571215976Sjmallett uint64_t phy_spd : 1; 5572215976Sjmallett uint64_t phy_dupx : 1; 5573215976Sjmallett uint64_t pause_drp : 1; 5574215976Sjmallett uint64_t loc_fault : 1; 5575215976Sjmallett uint64_t rem_fault : 1; 5576215976Sjmallett uint64_t bad_seq : 1; 5577215976Sjmallett uint64_t bad_term : 1; 5578215976Sjmallett uint64_t unsop : 1; 5579215976Sjmallett uint64_t uneop : 1; 5580215976Sjmallett uint64_t undat : 1; 5581215976Sjmallett uint64_t hg2fld : 1; 5582215976Sjmallett uint64_t hg2cc : 1; 5583215976Sjmallett uint64_t reserved_29_63 : 35; 5584215976Sjmallett#endif 5585215976Sjmallett } s; 5586232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn30xx { 5587232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5588215976Sjmallett uint64_t reserved_19_63 : 45; 5589215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 5590215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 5591215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 5592215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 5593215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 5594215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 5595215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 5596215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5597215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 5598215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 5599215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5600215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 5601215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 5602215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 5603215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5604215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5605215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 5606215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 5607215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 5608215976Sjmallett#else 5609215976Sjmallett uint64_t minerr : 1; 5610215976Sjmallett uint64_t carext : 1; 5611215976Sjmallett uint64_t maxerr : 1; 5612215976Sjmallett uint64_t jabber : 1; 5613215976Sjmallett uint64_t fcserr : 1; 5614215976Sjmallett uint64_t alnerr : 1; 5615215976Sjmallett uint64_t lenerr : 1; 5616215976Sjmallett uint64_t rcverr : 1; 5617215976Sjmallett uint64_t skperr : 1; 5618215976Sjmallett uint64_t niberr : 1; 5619215976Sjmallett uint64_t ovrerr : 1; 5620215976Sjmallett uint64_t pcterr : 1; 5621215976Sjmallett uint64_t rsverr : 1; 5622215976Sjmallett uint64_t falerr : 1; 5623215976Sjmallett uint64_t coldet : 1; 5624215976Sjmallett uint64_t ifgerr : 1; 5625215976Sjmallett uint64_t phy_link : 1; 5626215976Sjmallett uint64_t phy_spd : 1; 5627215976Sjmallett uint64_t phy_dupx : 1; 5628215976Sjmallett uint64_t reserved_19_63 : 45; 5629215976Sjmallett#endif 5630215976Sjmallett } cn30xx; 5631215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; 5632215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; 5633215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; 5634232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn50xx { 5635232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5636215976Sjmallett uint64_t reserved_20_63 : 44; 5637215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5638215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 5639215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 5640215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 5641215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 5642215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 5643215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 5644215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 5645215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5646215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 5647215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 5648215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5649215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 5650215976Sjmallett uint64_t reserved_6_6 : 1; 5651215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 5652215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5653215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5654215976Sjmallett uint64_t reserved_2_2 : 1; 5655215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 5656215976Sjmallett uint64_t reserved_0_0 : 1; 5657215976Sjmallett#else 5658215976Sjmallett uint64_t reserved_0_0 : 1; 5659215976Sjmallett uint64_t carext : 1; 5660215976Sjmallett uint64_t reserved_2_2 : 1; 5661215976Sjmallett uint64_t jabber : 1; 5662215976Sjmallett uint64_t fcserr : 1; 5663215976Sjmallett uint64_t alnerr : 1; 5664215976Sjmallett uint64_t reserved_6_6 : 1; 5665215976Sjmallett uint64_t rcverr : 1; 5666215976Sjmallett uint64_t skperr : 1; 5667215976Sjmallett uint64_t niberr : 1; 5668215976Sjmallett uint64_t ovrerr : 1; 5669215976Sjmallett uint64_t pcterr : 1; 5670215976Sjmallett uint64_t rsverr : 1; 5671215976Sjmallett uint64_t falerr : 1; 5672215976Sjmallett uint64_t coldet : 1; 5673215976Sjmallett uint64_t ifgerr : 1; 5674215976Sjmallett uint64_t phy_link : 1; 5675215976Sjmallett uint64_t phy_spd : 1; 5676215976Sjmallett uint64_t phy_dupx : 1; 5677215976Sjmallett uint64_t pause_drp : 1; 5678215976Sjmallett uint64_t reserved_20_63 : 44; 5679215976Sjmallett#endif 5680215976Sjmallett } cn50xx; 5681232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn52xx { 5682232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5683215976Sjmallett uint64_t reserved_29_63 : 35; 5684215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */ 5685215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */ 5686215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 5687215976Sjmallett (XAUI Mode only) */ 5688215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 5689215976Sjmallett (XAUI Mode only) */ 5690215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 5691215976Sjmallett (XAUI Mode only) */ 5692215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 5693215976Sjmallett than /T/. The error propagation control 5694215976Sjmallett character /E/ will be included as part of the 5695215976Sjmallett frame and does not cause a frame termination. 5696215976Sjmallett (XAUI Mode only) */ 5697215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 5698215976Sjmallett (XAUI Mode only) */ 5699215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 5700215976Sjmallett (XAUI Mode only) */ 5701215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 5702215976Sjmallett (XAUI Mode only) */ 5703215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5704215976Sjmallett uint64_t reserved_16_18 : 3; 5705215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 5706215976Sjmallett (SGMII/1000Base-X only) */ 5707215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 5708215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 5709215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 5710215976Sjmallett (SGMII/1000Base-X only) */ 5711215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 5712215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5713215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 5714215976Sjmallett (SGMII/1000Base-X only) */ 5715215976Sjmallett uint64_t reserved_9_9 : 1; 5716215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5717215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 5718215976Sjmallett uint64_t reserved_5_6 : 2; 5719215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5720215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5721215976Sjmallett uint64_t reserved_2_2 : 1; 5722215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 5723215976Sjmallett (SGMII/1000Base-X only) */ 5724215976Sjmallett uint64_t reserved_0_0 : 1; 5725215976Sjmallett#else 5726215976Sjmallett uint64_t reserved_0_0 : 1; 5727215976Sjmallett uint64_t carext : 1; 5728215976Sjmallett uint64_t reserved_2_2 : 1; 5729215976Sjmallett uint64_t jabber : 1; 5730215976Sjmallett uint64_t fcserr : 1; 5731215976Sjmallett uint64_t reserved_5_6 : 2; 5732215976Sjmallett uint64_t rcverr : 1; 5733215976Sjmallett uint64_t skperr : 1; 5734215976Sjmallett uint64_t reserved_9_9 : 1; 5735215976Sjmallett uint64_t ovrerr : 1; 5736215976Sjmallett uint64_t pcterr : 1; 5737215976Sjmallett uint64_t rsverr : 1; 5738215976Sjmallett uint64_t falerr : 1; 5739215976Sjmallett uint64_t coldet : 1; 5740215976Sjmallett uint64_t ifgerr : 1; 5741215976Sjmallett uint64_t reserved_16_18 : 3; 5742215976Sjmallett uint64_t pause_drp : 1; 5743215976Sjmallett uint64_t loc_fault : 1; 5744215976Sjmallett uint64_t rem_fault : 1; 5745215976Sjmallett uint64_t bad_seq : 1; 5746215976Sjmallett uint64_t bad_term : 1; 5747215976Sjmallett uint64_t unsop : 1; 5748215976Sjmallett uint64_t uneop : 1; 5749215976Sjmallett uint64_t undat : 1; 5750215976Sjmallett uint64_t hg2fld : 1; 5751215976Sjmallett uint64_t hg2cc : 1; 5752215976Sjmallett uint64_t reserved_29_63 : 35; 5753215976Sjmallett#endif 5754215976Sjmallett } cn52xx; 5755215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; 5756215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; 5757232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn56xxp1 { 5758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5759215976Sjmallett uint64_t reserved_27_63 : 37; 5760215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 5761215976Sjmallett (XAUI Mode only) */ 5762215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 5763215976Sjmallett (XAUI Mode only) */ 5764215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 5765215976Sjmallett (XAUI Mode only) */ 5766215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 5767215976Sjmallett than /T/. The error propagation control 5768215976Sjmallett character /E/ will be included as part of the 5769215976Sjmallett frame and does not cause a frame termination. 5770215976Sjmallett (XAUI Mode only) */ 5771215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 5772215976Sjmallett (XAUI Mode only) */ 5773215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 5774215976Sjmallett (XAUI Mode only) */ 5775215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 5776215976Sjmallett (XAUI Mode only) */ 5777215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5778215976Sjmallett uint64_t reserved_16_18 : 3; 5779215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 5780215976Sjmallett (SGMII/1000Base-X only) */ 5781215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 5782215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 5783215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 5784215976Sjmallett (SGMII/1000Base-X only) */ 5785215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 5786215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5787215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 5788215976Sjmallett (SGMII/1000Base-X only) */ 5789215976Sjmallett uint64_t reserved_9_9 : 1; 5790215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5791215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 5792215976Sjmallett uint64_t reserved_5_6 : 2; 5793215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5794215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5795215976Sjmallett uint64_t reserved_2_2 : 1; 5796215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 5797215976Sjmallett (SGMII/1000Base-X only) */ 5798215976Sjmallett uint64_t reserved_0_0 : 1; 5799215976Sjmallett#else 5800215976Sjmallett uint64_t reserved_0_0 : 1; 5801215976Sjmallett uint64_t carext : 1; 5802215976Sjmallett uint64_t reserved_2_2 : 1; 5803215976Sjmallett uint64_t jabber : 1; 5804215976Sjmallett uint64_t fcserr : 1; 5805215976Sjmallett uint64_t reserved_5_6 : 2; 5806215976Sjmallett uint64_t rcverr : 1; 5807215976Sjmallett uint64_t skperr : 1; 5808215976Sjmallett uint64_t reserved_9_9 : 1; 5809215976Sjmallett uint64_t ovrerr : 1; 5810215976Sjmallett uint64_t pcterr : 1; 5811215976Sjmallett uint64_t rsverr : 1; 5812215976Sjmallett uint64_t falerr : 1; 5813215976Sjmallett uint64_t coldet : 1; 5814215976Sjmallett uint64_t ifgerr : 1; 5815215976Sjmallett uint64_t reserved_16_18 : 3; 5816215976Sjmallett uint64_t pause_drp : 1; 5817215976Sjmallett uint64_t loc_fault : 1; 5818215976Sjmallett uint64_t rem_fault : 1; 5819215976Sjmallett uint64_t bad_seq : 1; 5820215976Sjmallett uint64_t bad_term : 1; 5821215976Sjmallett uint64_t unsop : 1; 5822215976Sjmallett uint64_t uneop : 1; 5823215976Sjmallett uint64_t undat : 1; 5824215976Sjmallett uint64_t reserved_27_63 : 37; 5825215976Sjmallett#endif 5826215976Sjmallett } cn56xxp1; 5827232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn58xx { 5828232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5829215976Sjmallett uint64_t reserved_20_63 : 44; 5830215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5831215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 5832215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 5833215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 5834215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 5835215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 5836215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 5837215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 5838215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5839215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 5840215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 5841215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5842215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 5843215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 5844215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 5845215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5846215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5847215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 5848215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 5849215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 5850215976Sjmallett#else 5851215976Sjmallett uint64_t minerr : 1; 5852215976Sjmallett uint64_t carext : 1; 5853215976Sjmallett uint64_t maxerr : 1; 5854215976Sjmallett uint64_t jabber : 1; 5855215976Sjmallett uint64_t fcserr : 1; 5856215976Sjmallett uint64_t alnerr : 1; 5857215976Sjmallett uint64_t lenerr : 1; 5858215976Sjmallett uint64_t rcverr : 1; 5859215976Sjmallett uint64_t skperr : 1; 5860215976Sjmallett uint64_t niberr : 1; 5861215976Sjmallett uint64_t ovrerr : 1; 5862215976Sjmallett uint64_t pcterr : 1; 5863215976Sjmallett uint64_t rsverr : 1; 5864215976Sjmallett uint64_t falerr : 1; 5865215976Sjmallett uint64_t coldet : 1; 5866215976Sjmallett uint64_t ifgerr : 1; 5867215976Sjmallett uint64_t phy_link : 1; 5868215976Sjmallett uint64_t phy_spd : 1; 5869215976Sjmallett uint64_t phy_dupx : 1; 5870215976Sjmallett uint64_t pause_drp : 1; 5871215976Sjmallett uint64_t reserved_20_63 : 44; 5872215976Sjmallett#endif 5873215976Sjmallett } cn58xx; 5874215976Sjmallett struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; 5875232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx { 5876232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5877215976Sjmallett uint64_t reserved_29_63 : 35; 5878215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */ 5879215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */ 5880215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 5881215976Sjmallett (XAUI Mode only) */ 5882215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 5883215976Sjmallett (XAUI Mode only) */ 5884215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 5885215976Sjmallett (XAUI Mode only) */ 5886215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 5887215976Sjmallett than /T/. The error propagation control 5888215976Sjmallett character /E/ will be included as part of the 5889215976Sjmallett frame and does not cause a frame termination. 5890215976Sjmallett (XAUI Mode only) */ 5891215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 5892215976Sjmallett (XAUI Mode only) */ 5893215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 5894215976Sjmallett (XAUI Mode only) */ 5895215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 5896215976Sjmallett (XAUI Mode only) */ 5897215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 5898215976Sjmallett uint64_t reserved_16_18 : 3; 5899215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 5900215976Sjmallett (SGMII/1000Base-X only) */ 5901215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 5902215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 5903215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 5904215976Sjmallett (SGMII/1000Base-X only) */ 5905215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 5906215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 5907215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 5908215976Sjmallett (SGMII/1000Base-X only) */ 5909215976Sjmallett uint64_t reserved_9_9 : 1; 5910215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 5911215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 5912215976Sjmallett uint64_t reserved_5_6 : 2; 5913215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 5914215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 5915215976Sjmallett uint64_t reserved_2_2 : 1; 5916215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 5917215976Sjmallett (SGMII/1000Base-X only) */ 5918215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize */ 5919215976Sjmallett#else 5920215976Sjmallett uint64_t minerr : 1; 5921215976Sjmallett uint64_t carext : 1; 5922215976Sjmallett uint64_t reserved_2_2 : 1; 5923215976Sjmallett uint64_t jabber : 1; 5924215976Sjmallett uint64_t fcserr : 1; 5925215976Sjmallett uint64_t reserved_5_6 : 2; 5926215976Sjmallett uint64_t rcverr : 1; 5927215976Sjmallett uint64_t skperr : 1; 5928215976Sjmallett uint64_t reserved_9_9 : 1; 5929215976Sjmallett uint64_t ovrerr : 1; 5930215976Sjmallett uint64_t pcterr : 1; 5931215976Sjmallett uint64_t rsverr : 1; 5932215976Sjmallett uint64_t falerr : 1; 5933215976Sjmallett uint64_t coldet : 1; 5934215976Sjmallett uint64_t ifgerr : 1; 5935215976Sjmallett uint64_t reserved_16_18 : 3; 5936215976Sjmallett uint64_t pause_drp : 1; 5937215976Sjmallett uint64_t loc_fault : 1; 5938215976Sjmallett uint64_t rem_fault : 1; 5939215976Sjmallett uint64_t bad_seq : 1; 5940215976Sjmallett uint64_t bad_term : 1; 5941215976Sjmallett uint64_t unsop : 1; 5942215976Sjmallett uint64_t uneop : 1; 5943215976Sjmallett uint64_t undat : 1; 5944215976Sjmallett uint64_t hg2fld : 1; 5945215976Sjmallett uint64_t hg2cc : 1; 5946215976Sjmallett uint64_t reserved_29_63 : 35; 5947215976Sjmallett#endif 5948232812Sjmallett } cn61xx; 5949232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx; 5950232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1; 5951232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx; 5952232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx; 5953232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1; 5954232812Sjmallett struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx; 5955215976Sjmallett}; 5956215976Sjmalletttypedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t; 5957215976Sjmallett 5958215976Sjmallett/** 5959215976Sjmallett * cvmx_gmx#_rx#_int_reg 5960215976Sjmallett * 5961215976Sjmallett * GMX_RX_INT_REG = Interrupt Register 5962215976Sjmallett * 5963215976Sjmallett * 5964215976Sjmallett * Notes: 5965215976Sjmallett * (1) exceptions will only be raised to the control processor if the 5966215976Sjmallett * corresponding bit in the GMX_RX_INT_EN register is set. 5967215976Sjmallett * 5968215976Sjmallett * (2) exception conditions 10:0 can also set the rcv/opcode in the received 5969215976Sjmallett * packet's workQ entry. The GMX_RX_FRM_CHK register provides a bit mask 5970215976Sjmallett * for configuring which conditions set the error. 5971215976Sjmallett * 5972215976Sjmallett * (3) in half duplex operation, the expectation is that collisions will appear 5973215976Sjmallett * as either MINERR o r CAREXT errors. 5974215976Sjmallett * 5975215976Sjmallett * (4) JABBER - An RX Jabber error indicates that a packet was received which 5976215976Sjmallett * is longer than the maximum allowed packet as defined by the 5977215976Sjmallett * system. GMX will truncate the packet at the JABBER count. 5978215976Sjmallett * Failure to do so could lead to system instabilty. 5979215976Sjmallett * 5980215976Sjmallett * (5) NIBERR - This error is illegal at 1000Mbs speeds 5981215976Sjmallett * (GMX_RX_PRT_CFG[SPEED]==0) and will never assert. 5982215976Sjmallett * 5983215976Sjmallett * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS > 5984215976Sjmallett * GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS 5985215976Sjmallett * > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED. 5986215976Sjmallett * 5987215976Sjmallett * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < 64 5988215976Sjmallett * 5989215976Sjmallett * (8) ALNERR - Indicates that the packet received was not an integer number of 5990215976Sjmallett * bytes. If FCS checking is enabled, ALNERR will only assert if 5991215976Sjmallett * the FCS is bad. If FCS checking is disabled, ALNERR will 5992215976Sjmallett * assert in all non-integer frame cases. 5993215976Sjmallett * 5994215976Sjmallett * (9) Collisions - Collisions can only occur in half-duplex mode. A collision 5995215976Sjmallett * is assumed by the receiver when the slottime 5996215976Sjmallett * (GMX_PRT_CFG[SLOTTIME]) is not satisfied. In 10/100 mode, 5997215976Sjmallett * this will result in a frame < SLOTTIME. In 1000 mode, it 5998215976Sjmallett * could result either in frame < SLOTTIME or a carrier extend 5999215976Sjmallett * error with the SLOTTIME. These conditions are visible by... 6000215976Sjmallett * 6001215976Sjmallett * . transfer ended before slottime - COLDET 6002215976Sjmallett * . carrier extend error - CAREXT 6003215976Sjmallett * 6004215976Sjmallett * (A) LENERR - Length errors occur when the received packet does not match the 6005215976Sjmallett * length field. LENERR is only checked for packets between 64 6006215976Sjmallett * and 1500 bytes. For untagged frames, the length must exact 6007215976Sjmallett * match. For tagged frames the length or length+4 must match. 6008215976Sjmallett * 6009215976Sjmallett * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence. 6010215976Sjmallett * Does not check the number of PREAMBLE cycles. 6011215976Sjmallett * 6012232812Sjmallett * (C) OVRERR - 6013215976Sjmallett * 6014215976Sjmallett * OVRERR is an architectural assertion check internal to GMX to 6015215976Sjmallett * make sure no assumption was violated. In a correctly operating 6016215976Sjmallett * system, this interrupt can never fire. 6017215976Sjmallett * 6018215976Sjmallett * GMX has an internal arbiter which selects which of 4 ports to 6019215976Sjmallett * buffer in the main RX FIFO. If we normally buffer 8 bytes, 6020215976Sjmallett * then each port will typically push a tick every 8 cycles - if 6021215976Sjmallett * the packet interface is going as fast as possible. If there 6022215976Sjmallett * are four ports, they push every two cycles. So that's the 6023215976Sjmallett * assumption. That the inbound module will always be able to 6024215976Sjmallett * consume the tick before another is produced. If that doesn't 6025215976Sjmallett * happen - that's when OVRERR will assert. 6026215976Sjmallett * 6027215976Sjmallett * (D) In XAUI mode prt0 is used for interrupt logging. 6028215976Sjmallett */ 6029232812Sjmallettunion cvmx_gmxx_rxx_int_reg { 6030215976Sjmallett uint64_t u64; 6031232812Sjmallett struct cvmx_gmxx_rxx_int_reg_s { 6032232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6033215976Sjmallett uint64_t reserved_29_63 : 35; 6034215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error 6035215976Sjmallett Set when either CRC8 error detected or when 6036215976Sjmallett a Control Character is found in the message 6037215976Sjmallett bytes after the K.SOM 6038215976Sjmallett NOTE: HG2CC has higher priority than HG2FLD 6039215976Sjmallett i.e. a HiGig2 message that results in HG2CC 6040215976Sjmallett getting set, will never set HG2FLD. */ 6041215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 received message field error, as below 6042215976Sjmallett 1) MSG_TYPE field not 6'b00_0000 6043215976Sjmallett i.e. it is not a FLOW CONTROL message, which 6044215976Sjmallett is the only defined type for HiGig2 6045215976Sjmallett 2) FWD_TYPE field not 2'b00 i.e. Link Level msg 6046215976Sjmallett which is the only defined type for HiGig2 6047215976Sjmallett 3) FC_OBJECT field is neither 4'b0000 for 6048215976Sjmallett Physical Link nor 4'b0010 for Logical Link. 6049215976Sjmallett Those are the only two defined types in HiGig2 */ 6050215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 6051215976Sjmallett (XAUI Mode only) */ 6052215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 6053215976Sjmallett (XAUI Mode only) */ 6054215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 6055215976Sjmallett (XAUI Mode only) */ 6056215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 6057215976Sjmallett than /T/. The error propagation control 6058215976Sjmallett character /E/ will be included as part of the 6059215976Sjmallett frame and does not cause a frame termination. 6060215976Sjmallett (XAUI Mode only) */ 6061215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 6062215976Sjmallett (XAUI Mode only) */ 6063215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 6064215976Sjmallett (XAUI Mode only) */ 6065215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 6066215976Sjmallett (XAUI Mode only) */ 6067215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6068215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 6069215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 6070215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 6071215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6072215976Sjmallett Does not necessarily indicate a failure 6073215976Sjmallett (SGMII/1000Base-X only) */ 6074215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 6075215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 6076215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 6077215976Sjmallett (SGMII/1000Base-X only) */ 6078215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 6079215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol 6080215976Sjmallett In XAUI mode, the column of data that was bad 6081215976Sjmallett will be logged in GMX_RX_XAUI_BAD_COL */ 6082215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6083215976Sjmallett This interrupt should never assert 6084215976Sjmallett (SGMII/1000Base-X only) */ 6085215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 6086215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6087215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 6088215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 6089215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 6090215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6091215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6092215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 6093215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 6094215976Sjmallett (SGMII/1000Base-X only) */ 6095215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize 6096215976Sjmallett Frame length checks are typically handled in PIP 6097215976Sjmallett (PIP_INT_REG[MINERR]), but pause frames are 6098215976Sjmallett normally discarded before being inspected by PIP. */ 6099215976Sjmallett#else 6100215976Sjmallett uint64_t minerr : 1; 6101215976Sjmallett uint64_t carext : 1; 6102215976Sjmallett uint64_t maxerr : 1; 6103215976Sjmallett uint64_t jabber : 1; 6104215976Sjmallett uint64_t fcserr : 1; 6105215976Sjmallett uint64_t alnerr : 1; 6106215976Sjmallett uint64_t lenerr : 1; 6107215976Sjmallett uint64_t rcverr : 1; 6108215976Sjmallett uint64_t skperr : 1; 6109215976Sjmallett uint64_t niberr : 1; 6110215976Sjmallett uint64_t ovrerr : 1; 6111215976Sjmallett uint64_t pcterr : 1; 6112215976Sjmallett uint64_t rsverr : 1; 6113215976Sjmallett uint64_t falerr : 1; 6114215976Sjmallett uint64_t coldet : 1; 6115215976Sjmallett uint64_t ifgerr : 1; 6116215976Sjmallett uint64_t phy_link : 1; 6117215976Sjmallett uint64_t phy_spd : 1; 6118215976Sjmallett uint64_t phy_dupx : 1; 6119215976Sjmallett uint64_t pause_drp : 1; 6120215976Sjmallett uint64_t loc_fault : 1; 6121215976Sjmallett uint64_t rem_fault : 1; 6122215976Sjmallett uint64_t bad_seq : 1; 6123215976Sjmallett uint64_t bad_term : 1; 6124215976Sjmallett uint64_t unsop : 1; 6125215976Sjmallett uint64_t uneop : 1; 6126215976Sjmallett uint64_t undat : 1; 6127215976Sjmallett uint64_t hg2fld : 1; 6128215976Sjmallett uint64_t hg2cc : 1; 6129215976Sjmallett uint64_t reserved_29_63 : 35; 6130215976Sjmallett#endif 6131215976Sjmallett } s; 6132232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn30xx { 6133232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6134215976Sjmallett uint64_t reserved_19_63 : 45; 6135215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 6136215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 6137215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 6138215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6139215976Sjmallett Does not necessarily indicate a failure */ 6140215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 6141215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 6142215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 6143215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 6144215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6145215976Sjmallett This interrupt should never assert */ 6146215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 6147215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6148215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 6149215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 6150215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 6151215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6152215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6153215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 6154215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 6155215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 6156215976Sjmallett#else 6157215976Sjmallett uint64_t minerr : 1; 6158215976Sjmallett uint64_t carext : 1; 6159215976Sjmallett uint64_t maxerr : 1; 6160215976Sjmallett uint64_t jabber : 1; 6161215976Sjmallett uint64_t fcserr : 1; 6162215976Sjmallett uint64_t alnerr : 1; 6163215976Sjmallett uint64_t lenerr : 1; 6164215976Sjmallett uint64_t rcverr : 1; 6165215976Sjmallett uint64_t skperr : 1; 6166215976Sjmallett uint64_t niberr : 1; 6167215976Sjmallett uint64_t ovrerr : 1; 6168215976Sjmallett uint64_t pcterr : 1; 6169215976Sjmallett uint64_t rsverr : 1; 6170215976Sjmallett uint64_t falerr : 1; 6171215976Sjmallett uint64_t coldet : 1; 6172215976Sjmallett uint64_t ifgerr : 1; 6173215976Sjmallett uint64_t phy_link : 1; 6174215976Sjmallett uint64_t phy_spd : 1; 6175215976Sjmallett uint64_t phy_dupx : 1; 6176215976Sjmallett uint64_t reserved_19_63 : 45; 6177215976Sjmallett#endif 6178215976Sjmallett } cn30xx; 6179215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; 6180215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; 6181215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; 6182232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn50xx { 6183232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6184215976Sjmallett uint64_t reserved_20_63 : 44; 6185215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6186215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 6187215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 6188215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 6189215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6190215976Sjmallett Does not necessarily indicate a failure */ 6191215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 6192215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 6193215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 6194215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 6195215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6196215976Sjmallett This interrupt should never assert */ 6197215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 6198215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6199215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 6200215976Sjmallett uint64_t reserved_6_6 : 1; 6201215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 6202215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6203215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6204215976Sjmallett uint64_t reserved_2_2 : 1; 6205215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 6206215976Sjmallett uint64_t reserved_0_0 : 1; 6207215976Sjmallett#else 6208215976Sjmallett uint64_t reserved_0_0 : 1; 6209215976Sjmallett uint64_t carext : 1; 6210215976Sjmallett uint64_t reserved_2_2 : 1; 6211215976Sjmallett uint64_t jabber : 1; 6212215976Sjmallett uint64_t fcserr : 1; 6213215976Sjmallett uint64_t alnerr : 1; 6214215976Sjmallett uint64_t reserved_6_6 : 1; 6215215976Sjmallett uint64_t rcverr : 1; 6216215976Sjmallett uint64_t skperr : 1; 6217215976Sjmallett uint64_t niberr : 1; 6218215976Sjmallett uint64_t ovrerr : 1; 6219215976Sjmallett uint64_t pcterr : 1; 6220215976Sjmallett uint64_t rsverr : 1; 6221215976Sjmallett uint64_t falerr : 1; 6222215976Sjmallett uint64_t coldet : 1; 6223215976Sjmallett uint64_t ifgerr : 1; 6224215976Sjmallett uint64_t phy_link : 1; 6225215976Sjmallett uint64_t phy_spd : 1; 6226215976Sjmallett uint64_t phy_dupx : 1; 6227215976Sjmallett uint64_t pause_drp : 1; 6228215976Sjmallett uint64_t reserved_20_63 : 44; 6229215976Sjmallett#endif 6230215976Sjmallett } cn50xx; 6231232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn52xx { 6232232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6233215976Sjmallett uint64_t reserved_29_63 : 35; 6234215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error 6235215976Sjmallett Set when either CRC8 error detected or when 6236215976Sjmallett a Control Character is found in the message 6237215976Sjmallett bytes after the K.SOM 6238215976Sjmallett NOTE: HG2CC has higher priority than HG2FLD 6239215976Sjmallett i.e. a HiGig2 message that results in HG2CC 6240215976Sjmallett getting set, will never set HG2FLD. */ 6241215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 received message field error, as below 6242215976Sjmallett 1) MSG_TYPE field not 6'b00_0000 6243215976Sjmallett i.e. it is not a FLOW CONTROL message, which 6244215976Sjmallett is the only defined type for HiGig2 6245215976Sjmallett 2) FWD_TYPE field not 2'b00 i.e. Link Level msg 6246215976Sjmallett which is the only defined type for HiGig2 6247215976Sjmallett 3) FC_OBJECT field is neither 4'b0000 for 6248215976Sjmallett Physical Link nor 4'b0010 for Logical Link. 6249215976Sjmallett Those are the only two defined types in HiGig2 */ 6250215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 6251215976Sjmallett (XAUI Mode only) */ 6252215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 6253215976Sjmallett (XAUI Mode only) */ 6254215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 6255215976Sjmallett (XAUI Mode only) */ 6256215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 6257215976Sjmallett than /T/. The error propagation control 6258215976Sjmallett character /E/ will be included as part of the 6259215976Sjmallett frame and does not cause a frame termination. 6260215976Sjmallett (XAUI Mode only) */ 6261215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 6262215976Sjmallett (XAUI Mode only) */ 6263215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 6264215976Sjmallett (XAUI Mode only) */ 6265215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 6266215976Sjmallett (XAUI Mode only) */ 6267215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6268215976Sjmallett uint64_t reserved_16_18 : 3; 6269215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6270215976Sjmallett Does not necessarily indicate a failure 6271215976Sjmallett (SGMII/1000Base-X only) */ 6272215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 6273215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 6274215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 6275215976Sjmallett (SGMII/1000Base-X only) */ 6276215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 6277215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol 6278215976Sjmallett In XAUI mode, the column of data that was bad 6279215976Sjmallett will be logged in GMX_RX_XAUI_BAD_COL */ 6280215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6281215976Sjmallett This interrupt should never assert 6282215976Sjmallett (SGMII/1000Base-X only) */ 6283215976Sjmallett uint64_t reserved_9_9 : 1; 6284215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6285215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 6286215976Sjmallett uint64_t reserved_5_6 : 2; 6287215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6288215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6289215976Sjmallett uint64_t reserved_2_2 : 1; 6290215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 6291215976Sjmallett (SGMII/1000Base-X only) */ 6292215976Sjmallett uint64_t reserved_0_0 : 1; 6293215976Sjmallett#else 6294215976Sjmallett uint64_t reserved_0_0 : 1; 6295215976Sjmallett uint64_t carext : 1; 6296215976Sjmallett uint64_t reserved_2_2 : 1; 6297215976Sjmallett uint64_t jabber : 1; 6298215976Sjmallett uint64_t fcserr : 1; 6299215976Sjmallett uint64_t reserved_5_6 : 2; 6300215976Sjmallett uint64_t rcverr : 1; 6301215976Sjmallett uint64_t skperr : 1; 6302215976Sjmallett uint64_t reserved_9_9 : 1; 6303215976Sjmallett uint64_t ovrerr : 1; 6304215976Sjmallett uint64_t pcterr : 1; 6305215976Sjmallett uint64_t rsverr : 1; 6306215976Sjmallett uint64_t falerr : 1; 6307215976Sjmallett uint64_t coldet : 1; 6308215976Sjmallett uint64_t ifgerr : 1; 6309215976Sjmallett uint64_t reserved_16_18 : 3; 6310215976Sjmallett uint64_t pause_drp : 1; 6311215976Sjmallett uint64_t loc_fault : 1; 6312215976Sjmallett uint64_t rem_fault : 1; 6313215976Sjmallett uint64_t bad_seq : 1; 6314215976Sjmallett uint64_t bad_term : 1; 6315215976Sjmallett uint64_t unsop : 1; 6316215976Sjmallett uint64_t uneop : 1; 6317215976Sjmallett uint64_t undat : 1; 6318215976Sjmallett uint64_t hg2fld : 1; 6319215976Sjmallett uint64_t hg2cc : 1; 6320215976Sjmallett uint64_t reserved_29_63 : 35; 6321215976Sjmallett#endif 6322215976Sjmallett } cn52xx; 6323215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; 6324215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; 6325232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { 6326232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6327215976Sjmallett uint64_t reserved_27_63 : 37; 6328215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 6329215976Sjmallett (XAUI Mode only) */ 6330215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 6331215976Sjmallett (XAUI Mode only) */ 6332215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 6333215976Sjmallett (XAUI Mode only) */ 6334215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 6335215976Sjmallett than /T/. The error propagation control 6336215976Sjmallett character /E/ will be included as part of the 6337215976Sjmallett frame and does not cause a frame termination. 6338215976Sjmallett (XAUI Mode only) */ 6339215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 6340215976Sjmallett (XAUI Mode only) */ 6341215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 6342215976Sjmallett (XAUI Mode only) */ 6343215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 6344215976Sjmallett (XAUI Mode only) */ 6345215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6346215976Sjmallett uint64_t reserved_16_18 : 3; 6347215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6348215976Sjmallett Does not necessarily indicate a failure 6349215976Sjmallett (SGMII/1000Base-X only) */ 6350215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 6351215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 6352215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 6353215976Sjmallett (SGMII/1000Base-X only) */ 6354215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 6355215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol 6356215976Sjmallett In XAUI mode, the column of data that was bad 6357215976Sjmallett will be logged in GMX_RX_XAUI_BAD_COL */ 6358215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6359215976Sjmallett This interrupt should never assert 6360215976Sjmallett (SGMII/1000Base-X only) */ 6361215976Sjmallett uint64_t reserved_9_9 : 1; 6362215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6363215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 6364215976Sjmallett uint64_t reserved_5_6 : 2; 6365215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6366215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6367215976Sjmallett uint64_t reserved_2_2 : 1; 6368215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 6369215976Sjmallett (SGMII/1000Base-X only) */ 6370215976Sjmallett uint64_t reserved_0_0 : 1; 6371215976Sjmallett#else 6372215976Sjmallett uint64_t reserved_0_0 : 1; 6373215976Sjmallett uint64_t carext : 1; 6374215976Sjmallett uint64_t reserved_2_2 : 1; 6375215976Sjmallett uint64_t jabber : 1; 6376215976Sjmallett uint64_t fcserr : 1; 6377215976Sjmallett uint64_t reserved_5_6 : 2; 6378215976Sjmallett uint64_t rcverr : 1; 6379215976Sjmallett uint64_t skperr : 1; 6380215976Sjmallett uint64_t reserved_9_9 : 1; 6381215976Sjmallett uint64_t ovrerr : 1; 6382215976Sjmallett uint64_t pcterr : 1; 6383215976Sjmallett uint64_t rsverr : 1; 6384215976Sjmallett uint64_t falerr : 1; 6385215976Sjmallett uint64_t coldet : 1; 6386215976Sjmallett uint64_t ifgerr : 1; 6387215976Sjmallett uint64_t reserved_16_18 : 3; 6388215976Sjmallett uint64_t pause_drp : 1; 6389215976Sjmallett uint64_t loc_fault : 1; 6390215976Sjmallett uint64_t rem_fault : 1; 6391215976Sjmallett uint64_t bad_seq : 1; 6392215976Sjmallett uint64_t bad_term : 1; 6393215976Sjmallett uint64_t unsop : 1; 6394215976Sjmallett uint64_t uneop : 1; 6395215976Sjmallett uint64_t undat : 1; 6396215976Sjmallett uint64_t reserved_27_63 : 37; 6397215976Sjmallett#endif 6398215976Sjmallett } cn56xxp1; 6399232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn58xx { 6400232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6401215976Sjmallett uint64_t reserved_20_63 : 44; 6402215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6403215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */ 6404215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */ 6405215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus */ 6406215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6407215976Sjmallett Does not necessarily indicate a failure */ 6408215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 6409215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 6410215976Sjmallett uint64_t rsverr : 1; /**< RGMII reserved opcodes */ 6411215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 6412215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6413215976Sjmallett This interrupt should never assert */ 6414215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */ 6415215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6416215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 6417215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 6418215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 6419215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6420215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6421215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 6422215976Sjmallett uint64_t carext : 1; /**< RGMII carrier extend error */ 6423215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 6424215976Sjmallett#else 6425215976Sjmallett uint64_t minerr : 1; 6426215976Sjmallett uint64_t carext : 1; 6427215976Sjmallett uint64_t maxerr : 1; 6428215976Sjmallett uint64_t jabber : 1; 6429215976Sjmallett uint64_t fcserr : 1; 6430215976Sjmallett uint64_t alnerr : 1; 6431215976Sjmallett uint64_t lenerr : 1; 6432215976Sjmallett uint64_t rcverr : 1; 6433215976Sjmallett uint64_t skperr : 1; 6434215976Sjmallett uint64_t niberr : 1; 6435215976Sjmallett uint64_t ovrerr : 1; 6436215976Sjmallett uint64_t pcterr : 1; 6437215976Sjmallett uint64_t rsverr : 1; 6438215976Sjmallett uint64_t falerr : 1; 6439215976Sjmallett uint64_t coldet : 1; 6440215976Sjmallett uint64_t ifgerr : 1; 6441215976Sjmallett uint64_t phy_link : 1; 6442215976Sjmallett uint64_t phy_spd : 1; 6443215976Sjmallett uint64_t phy_dupx : 1; 6444215976Sjmallett uint64_t pause_drp : 1; 6445215976Sjmallett uint64_t reserved_20_63 : 44; 6446215976Sjmallett#endif 6447215976Sjmallett } cn58xx; 6448215976Sjmallett struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; 6449232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx { 6450232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6451215976Sjmallett uint64_t reserved_29_63 : 35; 6452215976Sjmallett uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error 6453215976Sjmallett Set when either CRC8 error detected or when 6454215976Sjmallett a Control Character is found in the message 6455215976Sjmallett bytes after the K.SOM 6456215976Sjmallett NOTE: HG2CC has higher priority than HG2FLD 6457215976Sjmallett i.e. a HiGig2 message that results in HG2CC 6458215976Sjmallett getting set, will never set HG2FLD. */ 6459215976Sjmallett uint64_t hg2fld : 1; /**< HiGig2 received message field error, as below 6460215976Sjmallett 1) MSG_TYPE field not 6'b00_0000 6461215976Sjmallett i.e. it is not a FLOW CONTROL message, which 6462215976Sjmallett is the only defined type for HiGig2 6463215976Sjmallett 2) FWD_TYPE field not 2'b00 i.e. Link Level msg 6464215976Sjmallett which is the only defined type for HiGig2 6465215976Sjmallett 3) FC_OBJECT field is neither 4'b0000 for 6466215976Sjmallett Physical Link nor 4'b0010 for Logical Link. 6467215976Sjmallett Those are the only two defined types in HiGig2 */ 6468215976Sjmallett uint64_t undat : 1; /**< Unexpected Data 6469215976Sjmallett (XAUI Mode only) */ 6470215976Sjmallett uint64_t uneop : 1; /**< Unexpected EOP 6471215976Sjmallett (XAUI Mode only) */ 6472215976Sjmallett uint64_t unsop : 1; /**< Unexpected SOP 6473215976Sjmallett (XAUI Mode only) */ 6474215976Sjmallett uint64_t bad_term : 1; /**< Frame is terminated by control character other 6475215976Sjmallett than /T/. The error propagation control 6476215976Sjmallett character /E/ will be included as part of the 6477215976Sjmallett frame and does not cause a frame termination. 6478215976Sjmallett (XAUI Mode only) */ 6479215976Sjmallett uint64_t bad_seq : 1; /**< Reserved Sequence Deteted 6480215976Sjmallett (XAUI Mode only) */ 6481215976Sjmallett uint64_t rem_fault : 1; /**< Remote Fault Sequence Deteted 6482215976Sjmallett (XAUI Mode only) */ 6483215976Sjmallett uint64_t loc_fault : 1; /**< Local Fault Sequence Deteted 6484215976Sjmallett (XAUI Mode only) */ 6485215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 6486215976Sjmallett uint64_t reserved_16_18 : 3; 6487215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 6488215976Sjmallett Does not necessarily indicate a failure 6489215976Sjmallett (SGMII/1000Base-X only) */ 6490215976Sjmallett uint64_t coldet : 1; /**< Collision Detection 6491215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 6492215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime 6493215976Sjmallett (SGMII/1000Base-X only) */ 6494215976Sjmallett uint64_t rsverr : 1; /**< Reserved opcodes */ 6495215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol 6496215976Sjmallett In XAUI mode, the column of data that was bad 6497215976Sjmallett will be logged in GMX_RX_XAUI_BAD_COL */ 6498215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 6499215976Sjmallett This interrupt should never assert 6500215976Sjmallett (SGMII/1000Base-X only) */ 6501215976Sjmallett uint64_t reserved_9_9 : 1; 6502215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 6503215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Data reception error */ 6504215976Sjmallett uint64_t reserved_5_6 : 2; 6505215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 6506215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 6507215976Sjmallett uint64_t reserved_2_2 : 1; 6508215976Sjmallett uint64_t carext : 1; /**< Carrier extend error 6509215976Sjmallett (SGMII/1000Base-X only) */ 6510215976Sjmallett uint64_t minerr : 1; /**< Pause Frame was received with length<minFrameSize 6511215976Sjmallett Frame length checks are typically handled in PIP 6512215976Sjmallett (PIP_INT_REG[MINERR]), but pause frames are 6513215976Sjmallett normally discarded before being inspected by PIP. */ 6514215976Sjmallett#else 6515215976Sjmallett uint64_t minerr : 1; 6516215976Sjmallett uint64_t carext : 1; 6517215976Sjmallett uint64_t reserved_2_2 : 1; 6518215976Sjmallett uint64_t jabber : 1; 6519215976Sjmallett uint64_t fcserr : 1; 6520215976Sjmallett uint64_t reserved_5_6 : 2; 6521215976Sjmallett uint64_t rcverr : 1; 6522215976Sjmallett uint64_t skperr : 1; 6523215976Sjmallett uint64_t reserved_9_9 : 1; 6524215976Sjmallett uint64_t ovrerr : 1; 6525215976Sjmallett uint64_t pcterr : 1; 6526215976Sjmallett uint64_t rsverr : 1; 6527215976Sjmallett uint64_t falerr : 1; 6528215976Sjmallett uint64_t coldet : 1; 6529215976Sjmallett uint64_t ifgerr : 1; 6530215976Sjmallett uint64_t reserved_16_18 : 3; 6531215976Sjmallett uint64_t pause_drp : 1; 6532215976Sjmallett uint64_t loc_fault : 1; 6533215976Sjmallett uint64_t rem_fault : 1; 6534215976Sjmallett uint64_t bad_seq : 1; 6535215976Sjmallett uint64_t bad_term : 1; 6536215976Sjmallett uint64_t unsop : 1; 6537215976Sjmallett uint64_t uneop : 1; 6538215976Sjmallett uint64_t undat : 1; 6539215976Sjmallett uint64_t hg2fld : 1; 6540215976Sjmallett uint64_t hg2cc : 1; 6541215976Sjmallett uint64_t reserved_29_63 : 35; 6542215976Sjmallett#endif 6543232812Sjmallett } cn61xx; 6544232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx; 6545232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1; 6546232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx; 6547232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx; 6548232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1; 6549232812Sjmallett struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx; 6550215976Sjmallett}; 6551215976Sjmalletttypedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t; 6552215976Sjmallett 6553215976Sjmallett/** 6554215976Sjmallett * cvmx_gmx#_rx#_jabber 6555215976Sjmallett * 6556215976Sjmallett * GMX_RX_JABBER = The max size packet after which GMX will truncate 6557215976Sjmallett * 6558215976Sjmallett * 6559215976Sjmallett * Notes: 6560215976Sjmallett * CNT must be 8-byte aligned such that CNT[2:0] == 0 6561215976Sjmallett * 6562215976Sjmallett * The packet that will be sent to the packet input logic will have an 6563215976Sjmallett * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and 6564215976Sjmallett * GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is 6565215976Sjmallett * defined as... 6566215976Sjmallett * 6567215976Sjmallett * max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8) 6568215976Sjmallett * 6569215976Sjmallett * In XAUI mode prt0 is used for checking. 6570215976Sjmallett */ 6571232812Sjmallettunion cvmx_gmxx_rxx_jabber { 6572215976Sjmallett uint64_t u64; 6573232812Sjmallett struct cvmx_gmxx_rxx_jabber_s { 6574232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6575215976Sjmallett uint64_t reserved_16_63 : 48; 6576215976Sjmallett uint64_t cnt : 16; /**< Byte count for jabber check 6577215976Sjmallett Failing packets set the JABBER interrupt and are 6578215976Sjmallett optionally sent with opcode==JABBER 6579215976Sjmallett GMX will truncate the packet to CNT bytes */ 6580215976Sjmallett#else 6581215976Sjmallett uint64_t cnt : 16; 6582215976Sjmallett uint64_t reserved_16_63 : 48; 6583215976Sjmallett#endif 6584215976Sjmallett } s; 6585215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn30xx; 6586215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn31xx; 6587215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn38xx; 6588215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn38xxp2; 6589215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn50xx; 6590215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn52xx; 6591215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn52xxp1; 6592215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn56xx; 6593215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn56xxp1; 6594215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn58xx; 6595215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn58xxp1; 6596232812Sjmallett struct cvmx_gmxx_rxx_jabber_s cn61xx; 6597215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn63xx; 6598215976Sjmallett struct cvmx_gmxx_rxx_jabber_s cn63xxp1; 6599232812Sjmallett struct cvmx_gmxx_rxx_jabber_s cn66xx; 6600232812Sjmallett struct cvmx_gmxx_rxx_jabber_s cn68xx; 6601232812Sjmallett struct cvmx_gmxx_rxx_jabber_s cn68xxp1; 6602232812Sjmallett struct cvmx_gmxx_rxx_jabber_s cnf71xx; 6603215976Sjmallett}; 6604215976Sjmalletttypedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t; 6605215976Sjmallett 6606215976Sjmallett/** 6607215976Sjmallett * cvmx_gmx#_rx#_pause_drop_time 6608215976Sjmallett * 6609215976Sjmallett * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition 6610215976Sjmallett * 6611215976Sjmallett */ 6612232812Sjmallettunion cvmx_gmxx_rxx_pause_drop_time { 6613215976Sjmallett uint64_t u64; 6614232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s { 6615232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6616215976Sjmallett uint64_t reserved_16_63 : 48; 6617215976Sjmallett uint64_t status : 16; /**< Time extracted from the dropped PAUSE packet */ 6618215976Sjmallett#else 6619215976Sjmallett uint64_t status : 16; 6620215976Sjmallett uint64_t reserved_16_63 : 48; 6621215976Sjmallett#endif 6622215976Sjmallett } s; 6623215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; 6624215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; 6625215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; 6626215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; 6627215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; 6628215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; 6629215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; 6630232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx; 6631215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx; 6632215976Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1; 6633232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx; 6634232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx; 6635232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1; 6636232812Sjmallett struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx; 6637215976Sjmallett}; 6638215976Sjmalletttypedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t; 6639215976Sjmallett 6640215976Sjmallett/** 6641215976Sjmallett * cvmx_gmx#_rx#_rx_inbnd 6642215976Sjmallett * 6643215976Sjmallett * GMX_RX_INBND = RGMII InBand Link Status 6644215976Sjmallett * 6645215976Sjmallett * 6646215976Sjmallett * Notes: 6647215976Sjmallett * These fields are only valid if the attached PHY is operating in RGMII mode 6648215976Sjmallett * and supports the optional in-band status (see section 3.4.1 of the RGMII 6649215976Sjmallett * specification, version 1.3 for more information). 6650215976Sjmallett */ 6651232812Sjmallettunion cvmx_gmxx_rxx_rx_inbnd { 6652215976Sjmallett uint64_t u64; 6653232812Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s { 6654232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6655215976Sjmallett uint64_t reserved_4_63 : 60; 6656215976Sjmallett uint64_t duplex : 1; /**< RGMII Inbound LinkDuplex 6657215976Sjmallett 0=half-duplex 6658215976Sjmallett 1=full-duplex */ 6659215976Sjmallett uint64_t speed : 2; /**< RGMII Inbound LinkSpeed 6660215976Sjmallett 00=2.5MHz 6661215976Sjmallett 01=25MHz 6662215976Sjmallett 10=125MHz 6663215976Sjmallett 11=Reserved */ 6664215976Sjmallett uint64_t status : 1; /**< RGMII Inbound LinkStatus 6665215976Sjmallett 0=down 6666215976Sjmallett 1=up */ 6667215976Sjmallett#else 6668215976Sjmallett uint64_t status : 1; 6669215976Sjmallett uint64_t speed : 2; 6670215976Sjmallett uint64_t duplex : 1; 6671215976Sjmallett uint64_t reserved_4_63 : 60; 6672215976Sjmallett#endif 6673215976Sjmallett } s; 6674215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; 6675215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; 6676215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; 6677215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; 6678215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; 6679215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; 6680215976Sjmallett struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; 6681215976Sjmallett}; 6682215976Sjmalletttypedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t; 6683215976Sjmallett 6684215976Sjmallett/** 6685215976Sjmallett * cvmx_gmx#_rx#_stats_ctl 6686215976Sjmallett * 6687215976Sjmallett * GMX_RX_STATS_CTL = RX Stats Control register 6688215976Sjmallett * 6689215976Sjmallett */ 6690232812Sjmallettunion cvmx_gmxx_rxx_stats_ctl { 6691215976Sjmallett uint64_t u64; 6692232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s { 6693232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6694215976Sjmallett uint64_t reserved_1_63 : 63; 6695215976Sjmallett uint64_t rd_clr : 1; /**< RX Stats registers will clear on reads */ 6696215976Sjmallett#else 6697215976Sjmallett uint64_t rd_clr : 1; 6698215976Sjmallett uint64_t reserved_1_63 : 63; 6699215976Sjmallett#endif 6700215976Sjmallett } s; 6701215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; 6702215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; 6703215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; 6704215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; 6705215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; 6706215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; 6707215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; 6708215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; 6709215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; 6710215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; 6711215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; 6712232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn61xx; 6713215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn63xx; 6714215976Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1; 6715232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn66xx; 6716232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn68xx; 6717232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1; 6718232812Sjmallett struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx; 6719215976Sjmallett}; 6720215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t; 6721215976Sjmallett 6722215976Sjmallett/** 6723215976Sjmallett * cvmx_gmx#_rx#_stats_octs 6724215976Sjmallett * 6725215976Sjmallett * Notes: 6726215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6727215976Sjmallett * - Counters will wrap 6728215976Sjmallett */ 6729232812Sjmallettunion cvmx_gmxx_rxx_stats_octs { 6730215976Sjmallett uint64_t u64; 6731232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s { 6732232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6733215976Sjmallett uint64_t reserved_48_63 : 16; 6734215976Sjmallett uint64_t cnt : 48; /**< Octet count of received good packets */ 6735215976Sjmallett#else 6736215976Sjmallett uint64_t cnt : 48; 6737215976Sjmallett uint64_t reserved_48_63 : 16; 6738215976Sjmallett#endif 6739215976Sjmallett } s; 6740215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn30xx; 6741215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn31xx; 6742215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn38xx; 6743215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; 6744215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn50xx; 6745215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn52xx; 6746215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; 6747215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn56xx; 6748215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; 6749215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn58xx; 6750215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; 6751232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn61xx; 6752215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn63xx; 6753215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1; 6754232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn66xx; 6755232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn68xx; 6756232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1; 6757232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_s cnf71xx; 6758215976Sjmallett}; 6759215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t; 6760215976Sjmallett 6761215976Sjmallett/** 6762215976Sjmallett * cvmx_gmx#_rx#_stats_octs_ctl 6763215976Sjmallett * 6764215976Sjmallett * Notes: 6765215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6766215976Sjmallett * - Counters will wrap 6767215976Sjmallett */ 6768232812Sjmallettunion cvmx_gmxx_rxx_stats_octs_ctl { 6769215976Sjmallett uint64_t u64; 6770232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s { 6771232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6772215976Sjmallett uint64_t reserved_48_63 : 16; 6773215976Sjmallett uint64_t cnt : 48; /**< Octet count of received pause packets */ 6774215976Sjmallett#else 6775215976Sjmallett uint64_t cnt : 48; 6776215976Sjmallett uint64_t reserved_48_63 : 16; 6777215976Sjmallett#endif 6778215976Sjmallett } s; 6779215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; 6780215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; 6781215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; 6782215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; 6783215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; 6784215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; 6785215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; 6786215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; 6787215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; 6788215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; 6789215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; 6790232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx; 6791215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx; 6792215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1; 6793232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx; 6794232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx; 6795232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1; 6796232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx; 6797215976Sjmallett}; 6798215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t; 6799215976Sjmallett 6800215976Sjmallett/** 6801215976Sjmallett * cvmx_gmx#_rx#_stats_octs_dmac 6802215976Sjmallett * 6803215976Sjmallett * Notes: 6804215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6805215976Sjmallett * - Counters will wrap 6806215976Sjmallett */ 6807232812Sjmallettunion cvmx_gmxx_rxx_stats_octs_dmac { 6808215976Sjmallett uint64_t u64; 6809232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s { 6810232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6811215976Sjmallett uint64_t reserved_48_63 : 16; 6812215976Sjmallett uint64_t cnt : 48; /**< Octet count of filtered dmac packets */ 6813215976Sjmallett#else 6814215976Sjmallett uint64_t cnt : 48; 6815215976Sjmallett uint64_t reserved_48_63 : 16; 6816215976Sjmallett#endif 6817215976Sjmallett } s; 6818215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; 6819215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; 6820215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; 6821215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; 6822215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; 6823215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; 6824215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; 6825215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; 6826215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; 6827215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; 6828215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; 6829232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx; 6830215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx; 6831215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1; 6832232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx; 6833232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx; 6834232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1; 6835232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx; 6836215976Sjmallett}; 6837215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t; 6838215976Sjmallett 6839215976Sjmallett/** 6840215976Sjmallett * cvmx_gmx#_rx#_stats_octs_drp 6841215976Sjmallett * 6842215976Sjmallett * Notes: 6843215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6844215976Sjmallett * - Counters will wrap 6845215976Sjmallett */ 6846232812Sjmallettunion cvmx_gmxx_rxx_stats_octs_drp { 6847215976Sjmallett uint64_t u64; 6848232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s { 6849232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6850215976Sjmallett uint64_t reserved_48_63 : 16; 6851215976Sjmallett uint64_t cnt : 48; /**< Octet count of dropped packets */ 6852215976Sjmallett#else 6853215976Sjmallett uint64_t cnt : 48; 6854215976Sjmallett uint64_t reserved_48_63 : 16; 6855215976Sjmallett#endif 6856215976Sjmallett } s; 6857215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; 6858215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; 6859215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; 6860215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; 6861215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; 6862215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; 6863215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; 6864215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; 6865215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; 6866215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; 6867215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; 6868232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx; 6869215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx; 6870215976Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1; 6871232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx; 6872232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx; 6873232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1; 6874232812Sjmallett struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx; 6875215976Sjmallett}; 6876215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t; 6877215976Sjmallett 6878215976Sjmallett/** 6879215976Sjmallett * cvmx_gmx#_rx#_stats_pkts 6880215976Sjmallett * 6881215976Sjmallett * GMX_RX_STATS_PKTS 6882215976Sjmallett * 6883215976Sjmallett * Count of good received packets - packets that are not recognized as PAUSE 6884215976Sjmallett * packets, dropped due the DMAC filter, dropped due FIFO full status, or 6885215976Sjmallett * have any other OPCODE (FCS, Length, etc). 6886215976Sjmallett * 6887215976Sjmallett * Notes: 6888215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6889215976Sjmallett * - Counters will wrap 6890215976Sjmallett */ 6891232812Sjmallettunion cvmx_gmxx_rxx_stats_pkts { 6892215976Sjmallett uint64_t u64; 6893232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s { 6894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6895215976Sjmallett uint64_t reserved_32_63 : 32; 6896215976Sjmallett uint64_t cnt : 32; /**< Count of received good packets */ 6897215976Sjmallett#else 6898215976Sjmallett uint64_t cnt : 32; 6899215976Sjmallett uint64_t reserved_32_63 : 32; 6900215976Sjmallett#endif 6901215976Sjmallett } s; 6902215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; 6903215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; 6904215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; 6905215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; 6906215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; 6907215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; 6908215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; 6909215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; 6910215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; 6911215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; 6912215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; 6913232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn61xx; 6914215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn63xx; 6915215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1; 6916232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn66xx; 6917232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn68xx; 6918232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1; 6919232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx; 6920215976Sjmallett}; 6921215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t; 6922215976Sjmallett 6923215976Sjmallett/** 6924215976Sjmallett * cvmx_gmx#_rx#_stats_pkts_bad 6925215976Sjmallett * 6926215976Sjmallett * GMX_RX_STATS_PKTS_BAD 6927215976Sjmallett * 6928215976Sjmallett * Count of all packets received with some error that were not dropped 6929215976Sjmallett * either due to the dmac filter or lack of room in the receive FIFO. 6930215976Sjmallett * 6931215976Sjmallett * Notes: 6932215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6933215976Sjmallett * - Counters will wrap 6934215976Sjmallett */ 6935232812Sjmallettunion cvmx_gmxx_rxx_stats_pkts_bad { 6936215976Sjmallett uint64_t u64; 6937232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s { 6938232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6939215976Sjmallett uint64_t reserved_32_63 : 32; 6940215976Sjmallett uint64_t cnt : 32; /**< Count of bad packets */ 6941215976Sjmallett#else 6942215976Sjmallett uint64_t cnt : 32; 6943215976Sjmallett uint64_t reserved_32_63 : 32; 6944215976Sjmallett#endif 6945215976Sjmallett } s; 6946215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; 6947215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; 6948215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; 6949215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; 6950215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; 6951215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; 6952215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; 6953215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; 6954215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; 6955215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; 6956215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; 6957232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx; 6958215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx; 6959215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1; 6960232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx; 6961232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx; 6962232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1; 6963232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx; 6964215976Sjmallett}; 6965215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t; 6966215976Sjmallett 6967215976Sjmallett/** 6968215976Sjmallett * cvmx_gmx#_rx#_stats_pkts_ctl 6969215976Sjmallett * 6970215976Sjmallett * GMX_RX_STATS_PKTS_CTL 6971215976Sjmallett * 6972215976Sjmallett * Count of all packets received that were recognized as Flow Control or 6973215976Sjmallett * PAUSE packets. PAUSE packets with any kind of error are counted in 6974215976Sjmallett * GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or 6975215976Sjmallett * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit. This count 6976215976Sjmallett * increments regardless of whether the packet is dropped. Pause packets 6977215976Sjmallett * will never be counted in GMX_RX_STATS_PKTS. Packets dropped due the dmac 6978215976Sjmallett * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here. 6979215976Sjmallett * 6980215976Sjmallett * Notes: 6981215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 6982215976Sjmallett * - Counters will wrap 6983215976Sjmallett */ 6984232812Sjmallettunion cvmx_gmxx_rxx_stats_pkts_ctl { 6985215976Sjmallett uint64_t u64; 6986232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s { 6987232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6988215976Sjmallett uint64_t reserved_32_63 : 32; 6989215976Sjmallett uint64_t cnt : 32; /**< Count of received pause packets */ 6990215976Sjmallett#else 6991215976Sjmallett uint64_t cnt : 32; 6992215976Sjmallett uint64_t reserved_32_63 : 32; 6993215976Sjmallett#endif 6994215976Sjmallett } s; 6995215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; 6996215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; 6997215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; 6998215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; 6999215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; 7000215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; 7001215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; 7002215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; 7003215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; 7004215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; 7005215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; 7006232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx; 7007215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx; 7008215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1; 7009232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx; 7010232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx; 7011232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1; 7012232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx; 7013215976Sjmallett}; 7014215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t; 7015215976Sjmallett 7016215976Sjmallett/** 7017215976Sjmallett * cvmx_gmx#_rx#_stats_pkts_dmac 7018215976Sjmallett * 7019215976Sjmallett * GMX_RX_STATS_PKTS_DMAC 7020215976Sjmallett * 7021215976Sjmallett * Count of all packets received that were dropped by the dmac filter. 7022215976Sjmallett * Packets that match the DMAC will be dropped and counted here regardless 7023215976Sjmallett * of if they were bad packets. These packets will never be counted in 7024215976Sjmallett * GMX_RX_STATS_PKTS. 7025215976Sjmallett * 7026215976Sjmallett * Some packets that were not able to satisify the DECISION_CNT may not 7027215976Sjmallett * actually be dropped by Octeon, but they will be counted here as if they 7028215976Sjmallett * were dropped. 7029215976Sjmallett * 7030215976Sjmallett * Notes: 7031215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 7032215976Sjmallett * - Counters will wrap 7033215976Sjmallett */ 7034232812Sjmallettunion cvmx_gmxx_rxx_stats_pkts_dmac { 7035215976Sjmallett uint64_t u64; 7036232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s { 7037232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7038215976Sjmallett uint64_t reserved_32_63 : 32; 7039215976Sjmallett uint64_t cnt : 32; /**< Count of filtered dmac packets */ 7040215976Sjmallett#else 7041215976Sjmallett uint64_t cnt : 32; 7042215976Sjmallett uint64_t reserved_32_63 : 32; 7043215976Sjmallett#endif 7044215976Sjmallett } s; 7045215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; 7046215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; 7047215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; 7048215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; 7049215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; 7050215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; 7051215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; 7052215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; 7053215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; 7054215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; 7055215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; 7056232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx; 7057215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx; 7058215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1; 7059232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx; 7060232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx; 7061232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1; 7062232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx; 7063215976Sjmallett}; 7064215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t; 7065215976Sjmallett 7066215976Sjmallett/** 7067215976Sjmallett * cvmx_gmx#_rx#_stats_pkts_drp 7068215976Sjmallett * 7069215976Sjmallett * GMX_RX_STATS_PKTS_DRP 7070215976Sjmallett * 7071232812Sjmallett * Count of all packets received that were dropped due to a full receive FIFO. 7072232812Sjmallett * This counts both partial packets in which there was enough space in the RX 7073232812Sjmallett * FIFO to begin to buffer and the packet and total drops in which no packet was 7074232812Sjmallett * sent to PKI. This counts good and bad packets received - all packets dropped 7075232812Sjmallett * by the FIFO. It does not count packets dropped by the dmac or pause packet 7076215976Sjmallett * filters. 7077215976Sjmallett * 7078215976Sjmallett * Notes: 7079215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set 7080215976Sjmallett * - Counters will wrap 7081215976Sjmallett */ 7082232812Sjmallettunion cvmx_gmxx_rxx_stats_pkts_drp { 7083215976Sjmallett uint64_t u64; 7084232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s { 7085232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7086215976Sjmallett uint64_t reserved_32_63 : 32; 7087215976Sjmallett uint64_t cnt : 32; /**< Count of dropped packets */ 7088215976Sjmallett#else 7089215976Sjmallett uint64_t cnt : 32; 7090215976Sjmallett uint64_t reserved_32_63 : 32; 7091215976Sjmallett#endif 7092215976Sjmallett } s; 7093215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; 7094215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; 7095215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; 7096215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; 7097215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; 7098215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; 7099215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; 7100215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; 7101215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; 7102215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; 7103215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; 7104232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx; 7105215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx; 7106215976Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1; 7107232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx; 7108232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx; 7109232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1; 7110232812Sjmallett struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx; 7111215976Sjmallett}; 7112215976Sjmalletttypedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t; 7113215976Sjmallett 7114215976Sjmallett/** 7115215976Sjmallett * cvmx_gmx#_rx#_udd_skp 7116215976Sjmallett * 7117215976Sjmallett * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data 7118215976Sjmallett * 7119215976Sjmallett * 7120215976Sjmallett * Notes: 7121215976Sjmallett * (1) The skip bytes are part of the packet and will be sent down the NCB 7122215976Sjmallett * packet interface and will be handled by PKI. 7123215976Sjmallett * 7124215976Sjmallett * (2) The system can determine if the UDD bytes are included in the FCS check 7125215976Sjmallett * by using the FCSSEL field - if the FCS check is enabled. 7126215976Sjmallett * 7127215976Sjmallett * (3) Assume that the preamble/sfd is always at the start of the frame - even 7128215976Sjmallett * before UDD bytes. In most cases, there will be no preamble in these 7129215976Sjmallett * cases since it will be packet interface in direct communication to 7130215976Sjmallett * another packet interface (MAC to MAC) without a PHY involved. 7131215976Sjmallett * 7132215976Sjmallett * (4) We can still do address filtering and control packet filtering is the 7133215976Sjmallett * user desires. 7134215976Sjmallett * 7135215976Sjmallett * (5) UDD_SKP must be 0 in half-duplex operation unless 7136215976Sjmallett * GMX_RX_FRM_CTL[PRE_CHK] is clear. If GMX_RX_FRM_CTL[PRE_CHK] is clear, 7137215976Sjmallett * then UDD_SKP will normally be 8. 7138215976Sjmallett * 7139215976Sjmallett * (6) In all cases, the UDD bytes will be sent down the packet interface as 7140215976Sjmallett * part of the packet. The UDD bytes are never stripped from the actual 7141215976Sjmallett * packet. 7142215976Sjmallett * 7143215976Sjmallett * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero 7144215976Sjmallett */ 7145232812Sjmallettunion cvmx_gmxx_rxx_udd_skp { 7146215976Sjmallett uint64_t u64; 7147232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s { 7148232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7149215976Sjmallett uint64_t reserved_9_63 : 55; 7150215976Sjmallett uint64_t fcssel : 1; /**< Include the skip bytes in the FCS calculation 7151215976Sjmallett 0 = all skip bytes are included in FCS 7152215976Sjmallett 1 = the skip bytes are not included in FCS 7153215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, FCSSEL must 7154215976Sjmallett be zero. */ 7155215976Sjmallett uint64_t reserved_7_7 : 1; 7156215976Sjmallett uint64_t len : 7; /**< Amount of User-defined data before the start of 7157215976Sjmallett the L2 data. Zero means L2 comes first. 7158215976Sjmallett Max value is 64. 7159215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, LEN must be 7160215976Sjmallett set to 12 or 16 (depending on HiGig header size) 7161215976Sjmallett to account for the HiGig header. LEN=12 selects 7162215976Sjmallett HiGig/HiGig+, and LEN=16 selects HiGig2. */ 7163215976Sjmallett#else 7164215976Sjmallett uint64_t len : 7; 7165215976Sjmallett uint64_t reserved_7_7 : 1; 7166215976Sjmallett uint64_t fcssel : 1; 7167215976Sjmallett uint64_t reserved_9_63 : 55; 7168215976Sjmallett#endif 7169215976Sjmallett } s; 7170215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn30xx; 7171215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn31xx; 7172215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn38xx; 7173215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; 7174215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn50xx; 7175215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn52xx; 7176215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; 7177215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn56xx; 7178215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; 7179215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn58xx; 7180215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; 7181232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn61xx; 7182215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn63xx; 7183215976Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1; 7184232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn66xx; 7185232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn68xx; 7186232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1; 7187232812Sjmallett struct cvmx_gmxx_rxx_udd_skp_s cnf71xx; 7188215976Sjmallett}; 7189215976Sjmalletttypedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t; 7190215976Sjmallett 7191215976Sjmallett/** 7192215976Sjmallett * cvmx_gmx#_rx_bp_drop# 7193215976Sjmallett * 7194215976Sjmallett * GMX_RX_BP_DROP = FIFO mark for packet drop 7195215976Sjmallett * 7196215976Sjmallett * 7197215976Sjmallett * Notes: 7198215976Sjmallett * The actual watermark is dynamic with respect to the GMX_RX_PRTS 7199215976Sjmallett * register. The GMX_RX_PRTS controls the depth of the port's 7200215976Sjmallett * FIFO so as ports are added or removed, the drop point may change. 7201215976Sjmallett * 7202215976Sjmallett * In XAUI mode prt0 is used for checking. 7203215976Sjmallett */ 7204232812Sjmallettunion cvmx_gmxx_rx_bp_dropx { 7205215976Sjmallett uint64_t u64; 7206232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s { 7207232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7208215976Sjmallett uint64_t reserved_6_63 : 58; 7209215976Sjmallett uint64_t mark : 6; /**< Number of 8B ticks to reserve in the RX FIFO. 7210215976Sjmallett When the FIFO exceeds this count, packets will 7211215976Sjmallett be dropped and not buffered. 7212215976Sjmallett MARK should typically be programmed to ports+1. 7213215976Sjmallett Failure to program correctly can lead to system 7214215976Sjmallett instability. */ 7215215976Sjmallett#else 7216215976Sjmallett uint64_t mark : 6; 7217215976Sjmallett uint64_t reserved_6_63 : 58; 7218215976Sjmallett#endif 7219215976Sjmallett } s; 7220215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn30xx; 7221215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn31xx; 7222215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn38xx; 7223215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; 7224215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn50xx; 7225215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn52xx; 7226215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; 7227215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn56xx; 7228215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; 7229215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn58xx; 7230215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; 7231232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn61xx; 7232215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn63xx; 7233215976Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1; 7234232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn66xx; 7235232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn68xx; 7236232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1; 7237232812Sjmallett struct cvmx_gmxx_rx_bp_dropx_s cnf71xx; 7238215976Sjmallett}; 7239215976Sjmalletttypedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t; 7240215976Sjmallett 7241215976Sjmallett/** 7242215976Sjmallett * cvmx_gmx#_rx_bp_off# 7243215976Sjmallett * 7244215976Sjmallett * GMX_RX_BP_OFF = Lowater mark for packet drop 7245215976Sjmallett * 7246215976Sjmallett * 7247215976Sjmallett * Notes: 7248215976Sjmallett * In XAUI mode, prt0 is used for checking. 7249215976Sjmallett * 7250215976Sjmallett */ 7251232812Sjmallettunion cvmx_gmxx_rx_bp_offx { 7252215976Sjmallett uint64_t u64; 7253232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s { 7254232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7255215976Sjmallett uint64_t reserved_6_63 : 58; 7256215976Sjmallett uint64_t mark : 6; /**< Water mark (8B ticks) to deassert backpressure */ 7257215976Sjmallett#else 7258215976Sjmallett uint64_t mark : 6; 7259215976Sjmallett uint64_t reserved_6_63 : 58; 7260215976Sjmallett#endif 7261215976Sjmallett } s; 7262215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn30xx; 7263215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn31xx; 7264215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn38xx; 7265215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; 7266215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn50xx; 7267215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn52xx; 7268215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; 7269215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn56xx; 7270215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; 7271215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn58xx; 7272215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; 7273232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn61xx; 7274215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn63xx; 7275215976Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn63xxp1; 7276232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn66xx; 7277232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn68xx; 7278232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s cn68xxp1; 7279232812Sjmallett struct cvmx_gmxx_rx_bp_offx_s cnf71xx; 7280215976Sjmallett}; 7281215976Sjmalletttypedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t; 7282215976Sjmallett 7283215976Sjmallett/** 7284215976Sjmallett * cvmx_gmx#_rx_bp_on# 7285215976Sjmallett * 7286215976Sjmallett * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure 7287215976Sjmallett * 7288215976Sjmallett * 7289215976Sjmallett * Notes: 7290215976Sjmallett * In XAUI mode, prt0 is used for checking. 7291215976Sjmallett * 7292215976Sjmallett */ 7293232812Sjmallettunion cvmx_gmxx_rx_bp_onx { 7294215976Sjmallett uint64_t u64; 7295232812Sjmallett struct cvmx_gmxx_rx_bp_onx_s { 7296232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7297232812Sjmallett uint64_t reserved_11_63 : 53; 7298232812Sjmallett uint64_t mark : 11; /**< Hiwater mark (8B ticks) for backpressure. 7299215976Sjmallett Each register is for an individual port. In XAUI 7300215976Sjmallett mode, prt0 is used for the unified RX FIFO 7301215976Sjmallett GMX_RX_BP_ON must satisfy 7302215976Sjmallett BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP) 7303215976Sjmallett A value of zero will immediately assert back 7304215976Sjmallett pressure. */ 7305215976Sjmallett#else 7306232812Sjmallett uint64_t mark : 11; 7307232812Sjmallett uint64_t reserved_11_63 : 53; 7308232812Sjmallett#endif 7309232812Sjmallett } s; 7310232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx { 7311232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7312232812Sjmallett uint64_t reserved_9_63 : 55; 7313232812Sjmallett uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure. 7314232812Sjmallett In RGMII mode, the backpressure is given per 7315232812Sjmallett port. In Spi4 mode, the backpressure is for the 7316232812Sjmallett entire interface. GMX_RX_BP_ON must satisfy 7317232812Sjmallett BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP) 7318232812Sjmallett The reset value is half the FIFO. 7319232812Sjmallett Reset value RGMII mode = 0x40 (512bytes) 7320232812Sjmallett Reset value Spi4 mode = 0x100 (2048bytes) 7321232812Sjmallett A value of zero will immediately assert back 7322232812Sjmallett pressure. */ 7323232812Sjmallett#else 7324215976Sjmallett uint64_t mark : 9; 7325215976Sjmallett uint64_t reserved_9_63 : 55; 7326215976Sjmallett#endif 7327232812Sjmallett } cn30xx; 7328232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx; 7329232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx; 7330232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2; 7331232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx; 7332232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx; 7333232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1; 7334232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx; 7335232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1; 7336232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx; 7337232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1; 7338232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx; 7339232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx; 7340232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1; 7341232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx; 7342232812Sjmallett struct cvmx_gmxx_rx_bp_onx_s cn68xx; 7343232812Sjmallett struct cvmx_gmxx_rx_bp_onx_s cn68xxp1; 7344232812Sjmallett struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx; 7345215976Sjmallett}; 7346215976Sjmalletttypedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t; 7347215976Sjmallett 7348215976Sjmallett/** 7349215976Sjmallett * cvmx_gmx#_rx_hg2_status 7350215976Sjmallett * 7351215976Sjmallett * ** HG2 message CSRs 7352215976Sjmallett * 7353215976Sjmallett */ 7354232812Sjmallettunion cvmx_gmxx_rx_hg2_status { 7355215976Sjmallett uint64_t u64; 7356232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s { 7357232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7358215976Sjmallett uint64_t reserved_48_63 : 16; 7359215976Sjmallett uint64_t phtim2go : 16; /**< Physical time to go for removal of physical link 7360215976Sjmallett pause. Initial value from received HiGig2 msg pkt 7361215976Sjmallett Non-zero only when physical back pressure active */ 7362215976Sjmallett uint64_t xof : 16; /**< 16 bit xof back pressure vector from HiGig2 msg pkt 7363215976Sjmallett or from CBFC packets. 7364215976Sjmallett Non-zero only when logical back pressure is active 7365215976Sjmallett All bits will be 0 when LGTIM2GO=0 */ 7366215976Sjmallett uint64_t lgtim2go : 16; /**< Logical packet flow back pressure time remaining 7367215976Sjmallett Initial value set from xof time field of HiGig2 7368215976Sjmallett message packet received or a function of the 7369215976Sjmallett enabled and current timers for CBFC packets. 7370215976Sjmallett Non-zero only when logical back pressure is active */ 7371215976Sjmallett#else 7372215976Sjmallett uint64_t lgtim2go : 16; 7373215976Sjmallett uint64_t xof : 16; 7374215976Sjmallett uint64_t phtim2go : 16; 7375215976Sjmallett uint64_t reserved_48_63 : 16; 7376215976Sjmallett#endif 7377215976Sjmallett } s; 7378215976Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn52xx; 7379215976Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; 7380215976Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn56xx; 7381232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn61xx; 7382215976Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn63xx; 7383215976Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn63xxp1; 7384232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn66xx; 7385232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn68xx; 7386232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s cn68xxp1; 7387232812Sjmallett struct cvmx_gmxx_rx_hg2_status_s cnf71xx; 7388215976Sjmallett}; 7389215976Sjmalletttypedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t; 7390215976Sjmallett 7391215976Sjmallett/** 7392215976Sjmallett * cvmx_gmx#_rx_pass_en 7393215976Sjmallett * 7394215976Sjmallett * GMX_RX_PASS_EN = Packet pass through mode enable 7395215976Sjmallett * 7396215976Sjmallett * When both Octane ports are running in Spi4 mode, packets can be directly 7397215976Sjmallett * passed from one SPX interface to the other without being processed by the 7398215976Sjmallett * core or PP's. The register has one bit for each port to enable the pass 7399215976Sjmallett * through feature. 7400215976Sjmallett * 7401215976Sjmallett * Notes: 7402215976Sjmallett * (1) Can only be used in dual Spi4 configs 7403215976Sjmallett * 7404215976Sjmallett * (2) The mapped pass through output port cannot be the destination port for 7405215976Sjmallett * any Octane core traffic. 7406215976Sjmallett */ 7407232812Sjmallettunion cvmx_gmxx_rx_pass_en { 7408215976Sjmallett uint64_t u64; 7409232812Sjmallett struct cvmx_gmxx_rx_pass_en_s { 7410232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7411215976Sjmallett uint64_t reserved_16_63 : 48; 7412215976Sjmallett uint64_t en : 16; /**< Which ports to configure in pass through mode */ 7413215976Sjmallett#else 7414215976Sjmallett uint64_t en : 16; 7415215976Sjmallett uint64_t reserved_16_63 : 48; 7416215976Sjmallett#endif 7417215976Sjmallett } s; 7418215976Sjmallett struct cvmx_gmxx_rx_pass_en_s cn38xx; 7419215976Sjmallett struct cvmx_gmxx_rx_pass_en_s cn38xxp2; 7420215976Sjmallett struct cvmx_gmxx_rx_pass_en_s cn58xx; 7421215976Sjmallett struct cvmx_gmxx_rx_pass_en_s cn58xxp1; 7422215976Sjmallett}; 7423215976Sjmalletttypedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t; 7424215976Sjmallett 7425215976Sjmallett/** 7426215976Sjmallett * cvmx_gmx#_rx_pass_map# 7427215976Sjmallett * 7428215976Sjmallett * GMX_RX_PASS_MAP = Packet pass through port map 7429215976Sjmallett * 7430215976Sjmallett */ 7431232812Sjmallettunion cvmx_gmxx_rx_pass_mapx { 7432215976Sjmallett uint64_t u64; 7433232812Sjmallett struct cvmx_gmxx_rx_pass_mapx_s { 7434232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7435215976Sjmallett uint64_t reserved_4_63 : 60; 7436215976Sjmallett uint64_t dprt : 4; /**< Destination port to map Spi pass through traffic */ 7437215976Sjmallett#else 7438215976Sjmallett uint64_t dprt : 4; 7439215976Sjmallett uint64_t reserved_4_63 : 60; 7440215976Sjmallett#endif 7441215976Sjmallett } s; 7442215976Sjmallett struct cvmx_gmxx_rx_pass_mapx_s cn38xx; 7443215976Sjmallett struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; 7444215976Sjmallett struct cvmx_gmxx_rx_pass_mapx_s cn58xx; 7445215976Sjmallett struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; 7446215976Sjmallett}; 7447215976Sjmalletttypedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t; 7448215976Sjmallett 7449215976Sjmallett/** 7450215976Sjmallett * cvmx_gmx#_rx_prt_info 7451215976Sjmallett * 7452215976Sjmallett * GMX_RX_PRT_INFO = Report the RX status for port 7453215976Sjmallett * 7454215976Sjmallett * 7455215976Sjmallett * Notes: 7456215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used. 7457215976Sjmallett * 7458215976Sjmallett */ 7459232812Sjmallettunion cvmx_gmxx_rx_prt_info { 7460215976Sjmallett uint64_t u64; 7461232812Sjmallett struct cvmx_gmxx_rx_prt_info_s { 7462232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7463215976Sjmallett uint64_t reserved_32_63 : 32; 7464215976Sjmallett uint64_t drop : 16; /**< Per port indication that data was dropped */ 7465215976Sjmallett uint64_t commit : 16; /**< Per port indication that SOP was accepted */ 7466215976Sjmallett#else 7467215976Sjmallett uint64_t commit : 16; 7468215976Sjmallett uint64_t drop : 16; 7469215976Sjmallett uint64_t reserved_32_63 : 32; 7470215976Sjmallett#endif 7471215976Sjmallett } s; 7472232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn30xx { 7473232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7474215976Sjmallett uint64_t reserved_19_63 : 45; 7475215976Sjmallett uint64_t drop : 3; /**< Per port indication that data was dropped */ 7476215976Sjmallett uint64_t reserved_3_15 : 13; 7477215976Sjmallett uint64_t commit : 3; /**< Per port indication that SOP was accepted */ 7478215976Sjmallett#else 7479215976Sjmallett uint64_t commit : 3; 7480215976Sjmallett uint64_t reserved_3_15 : 13; 7481215976Sjmallett uint64_t drop : 3; 7482215976Sjmallett uint64_t reserved_19_63 : 45; 7483215976Sjmallett#endif 7484215976Sjmallett } cn30xx; 7485215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; 7486215976Sjmallett struct cvmx_gmxx_rx_prt_info_s cn38xx; 7487215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; 7488232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx { 7489232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7490215976Sjmallett uint64_t reserved_20_63 : 44; 7491215976Sjmallett uint64_t drop : 4; /**< Per port indication that data was dropped */ 7492215976Sjmallett uint64_t reserved_4_15 : 12; 7493215976Sjmallett uint64_t commit : 4; /**< Per port indication that SOP was accepted */ 7494215976Sjmallett#else 7495215976Sjmallett uint64_t commit : 4; 7496215976Sjmallett uint64_t reserved_4_15 : 12; 7497215976Sjmallett uint64_t drop : 4; 7498215976Sjmallett uint64_t reserved_20_63 : 44; 7499215976Sjmallett#endif 7500215976Sjmallett } cn52xx; 7501215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; 7502215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; 7503215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; 7504215976Sjmallett struct cvmx_gmxx_rx_prt_info_s cn58xx; 7505215976Sjmallett struct cvmx_gmxx_rx_prt_info_s cn58xxp1; 7506232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx; 7507215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx; 7508215976Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1; 7509232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx; 7510232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx; 7511232812Sjmallett struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1; 7512232812Sjmallett struct cvmx_gmxx_rx_prt_info_cnf71xx { 7513232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7514232812Sjmallett uint64_t reserved_18_63 : 46; 7515232812Sjmallett uint64_t drop : 2; /**< Per port indication that data was dropped */ 7516232812Sjmallett uint64_t reserved_2_15 : 14; 7517232812Sjmallett uint64_t commit : 2; /**< Per port indication that SOP was accepted */ 7518232812Sjmallett#else 7519232812Sjmallett uint64_t commit : 2; 7520232812Sjmallett uint64_t reserved_2_15 : 14; 7521232812Sjmallett uint64_t drop : 2; 7522232812Sjmallett uint64_t reserved_18_63 : 46; 7523232812Sjmallett#endif 7524232812Sjmallett } cnf71xx; 7525215976Sjmallett}; 7526215976Sjmalletttypedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t; 7527215976Sjmallett 7528215976Sjmallett/** 7529215976Sjmallett * cvmx_gmx#_rx_prts 7530215976Sjmallett * 7531215976Sjmallett * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into 7532215976Sjmallett * 7533215976Sjmallett * 7534215976Sjmallett * Notes: 7535215976Sjmallett * GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode. 7536215976Sjmallett * 7537215976Sjmallett */ 7538232812Sjmallettunion cvmx_gmxx_rx_prts { 7539215976Sjmallett uint64_t u64; 7540232812Sjmallett struct cvmx_gmxx_rx_prts_s { 7541232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7542215976Sjmallett uint64_t reserved_3_63 : 61; 7543215976Sjmallett uint64_t prts : 3; /**< In SGMII/1000Base-X mode, the RX buffer can be 7544215976Sjmallett carved into several logical buffers depending on 7545215976Sjmallett the number or implemented ports. 7546215976Sjmallett 0 or 1 port = 512ticks / 4096bytes 7547215976Sjmallett 2 ports = 256ticks / 2048bytes 7548215976Sjmallett 3 or 4 ports = 128ticks / 1024bytes */ 7549215976Sjmallett#else 7550215976Sjmallett uint64_t prts : 3; 7551215976Sjmallett uint64_t reserved_3_63 : 61; 7552215976Sjmallett#endif 7553215976Sjmallett } s; 7554215976Sjmallett struct cvmx_gmxx_rx_prts_s cn30xx; 7555215976Sjmallett struct cvmx_gmxx_rx_prts_s cn31xx; 7556215976Sjmallett struct cvmx_gmxx_rx_prts_s cn38xx; 7557215976Sjmallett struct cvmx_gmxx_rx_prts_s cn38xxp2; 7558215976Sjmallett struct cvmx_gmxx_rx_prts_s cn50xx; 7559215976Sjmallett struct cvmx_gmxx_rx_prts_s cn52xx; 7560215976Sjmallett struct cvmx_gmxx_rx_prts_s cn52xxp1; 7561215976Sjmallett struct cvmx_gmxx_rx_prts_s cn56xx; 7562215976Sjmallett struct cvmx_gmxx_rx_prts_s cn56xxp1; 7563215976Sjmallett struct cvmx_gmxx_rx_prts_s cn58xx; 7564215976Sjmallett struct cvmx_gmxx_rx_prts_s cn58xxp1; 7565232812Sjmallett struct cvmx_gmxx_rx_prts_s cn61xx; 7566215976Sjmallett struct cvmx_gmxx_rx_prts_s cn63xx; 7567215976Sjmallett struct cvmx_gmxx_rx_prts_s cn63xxp1; 7568232812Sjmallett struct cvmx_gmxx_rx_prts_s cn66xx; 7569232812Sjmallett struct cvmx_gmxx_rx_prts_s cn68xx; 7570232812Sjmallett struct cvmx_gmxx_rx_prts_s cn68xxp1; 7571232812Sjmallett struct cvmx_gmxx_rx_prts_s cnf71xx; 7572215976Sjmallett}; 7573215976Sjmalletttypedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t; 7574215976Sjmallett 7575215976Sjmallett/** 7576215976Sjmallett * cvmx_gmx#_rx_tx_status 7577215976Sjmallett * 7578215976Sjmallett * GMX_RX_TX_STATUS = GMX RX/TX Status 7579215976Sjmallett * 7580215976Sjmallett */ 7581232812Sjmallettunion cvmx_gmxx_rx_tx_status { 7582215976Sjmallett uint64_t u64; 7583232812Sjmallett struct cvmx_gmxx_rx_tx_status_s { 7584232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7585215976Sjmallett uint64_t reserved_7_63 : 57; 7586215976Sjmallett uint64_t tx : 3; /**< Transmit data since last read */ 7587215976Sjmallett uint64_t reserved_3_3 : 1; 7588215976Sjmallett uint64_t rx : 3; /**< Receive data since last read */ 7589215976Sjmallett#else 7590215976Sjmallett uint64_t rx : 3; 7591215976Sjmallett uint64_t reserved_3_3 : 1; 7592215976Sjmallett uint64_t tx : 3; 7593215976Sjmallett uint64_t reserved_7_63 : 57; 7594215976Sjmallett#endif 7595215976Sjmallett } s; 7596215976Sjmallett struct cvmx_gmxx_rx_tx_status_s cn30xx; 7597215976Sjmallett struct cvmx_gmxx_rx_tx_status_s cn31xx; 7598215976Sjmallett struct cvmx_gmxx_rx_tx_status_s cn50xx; 7599215976Sjmallett}; 7600215976Sjmalletttypedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t; 7601215976Sjmallett 7602215976Sjmallett/** 7603215976Sjmallett * cvmx_gmx#_rx_xaui_bad_col 7604215976Sjmallett */ 7605232812Sjmallettunion cvmx_gmxx_rx_xaui_bad_col { 7606215976Sjmallett uint64_t u64; 7607232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s { 7608232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7609215976Sjmallett uint64_t reserved_40_63 : 24; 7610215976Sjmallett uint64_t val : 1; /**< Set when GMX_RX_INT_REG[PCTERR] is set. 7611215976Sjmallett (XAUI mode only) */ 7612215976Sjmallett uint64_t state : 3; /**< When GMX_RX_INT_REG[PCTERR] is set, STATE will 7613215976Sjmallett conatin the receive state at the time of the 7614215976Sjmallett error. 7615215976Sjmallett (XAUI mode only) */ 7616215976Sjmallett uint64_t lane_rxc : 4; /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXC will 7617215976Sjmallett conatin the XAUI column at the time of the error. 7618215976Sjmallett (XAUI mode only) */ 7619215976Sjmallett uint64_t lane_rxd : 32; /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXD will 7620215976Sjmallett conatin the XAUI column at the time of the error. 7621215976Sjmallett (XAUI mode only) */ 7622215976Sjmallett#else 7623215976Sjmallett uint64_t lane_rxd : 32; 7624215976Sjmallett uint64_t lane_rxc : 4; 7625215976Sjmallett uint64_t state : 3; 7626215976Sjmallett uint64_t val : 1; 7627215976Sjmallett uint64_t reserved_40_63 : 24; 7628215976Sjmallett#endif 7629215976Sjmallett } s; 7630215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; 7631215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; 7632215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; 7633215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; 7634232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx; 7635215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx; 7636215976Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1; 7637232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx; 7638232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx; 7639232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1; 7640232812Sjmallett struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx; 7641215976Sjmallett}; 7642215976Sjmalletttypedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t; 7643215976Sjmallett 7644215976Sjmallett/** 7645215976Sjmallett * cvmx_gmx#_rx_xaui_ctl 7646215976Sjmallett */ 7647232812Sjmallettunion cvmx_gmxx_rx_xaui_ctl { 7648215976Sjmallett uint64_t u64; 7649232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s { 7650232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7651215976Sjmallett uint64_t reserved_2_63 : 62; 7652215976Sjmallett uint64_t status : 2; /**< Link Status 7653215976Sjmallett 0=Link OK 7654215976Sjmallett 1=Local Fault 7655215976Sjmallett 2=Remote Fault 7656215976Sjmallett 3=Reserved 7657215976Sjmallett (XAUI mode only) */ 7658215976Sjmallett#else 7659215976Sjmallett uint64_t status : 2; 7660215976Sjmallett uint64_t reserved_2_63 : 62; 7661215976Sjmallett#endif 7662215976Sjmallett } s; 7663215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; 7664215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; 7665215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; 7666215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; 7667232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn61xx; 7668215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn63xx; 7669215976Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1; 7670232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn66xx; 7671232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn68xx; 7672232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1; 7673232812Sjmallett struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx; 7674215976Sjmallett}; 7675215976Sjmalletttypedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t; 7676215976Sjmallett 7677215976Sjmallett/** 7678232812Sjmallett * cvmx_gmx#_rxaui_ctl 7679232812Sjmallett */ 7680232812Sjmallettunion cvmx_gmxx_rxaui_ctl { 7681232812Sjmallett uint64_t u64; 7682232812Sjmallett struct cvmx_gmxx_rxaui_ctl_s { 7683232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7684232812Sjmallett uint64_t reserved_1_63 : 63; 7685232812Sjmallett uint64_t disparity : 1; /**< Selects which disparity calculation to use when 7686232812Sjmallett combining or splitting the RXAUI lanes. 7687232812Sjmallett 0=Interleave lanes before PCS layer 7688232812Sjmallett As described in the Dune Networks/Broadcom 7689232812Sjmallett RXAUI v2.1 specification. 7690232812Sjmallett (obeys 6.25GHz SERDES disparity) 7691232812Sjmallett 1=Interleave lanes after PCS layer 7692232812Sjmallett As described in the Marvell RXAUI Interface 7693232812Sjmallett specification. 7694232812Sjmallett (does not obey 6.25GHz SERDES disparity) 7695232812Sjmallett (RXAUI mode only) */ 7696232812Sjmallett#else 7697232812Sjmallett uint64_t disparity : 1; 7698232812Sjmallett uint64_t reserved_1_63 : 63; 7699232812Sjmallett#endif 7700232812Sjmallett } s; 7701232812Sjmallett struct cvmx_gmxx_rxaui_ctl_s cn68xx; 7702232812Sjmallett struct cvmx_gmxx_rxaui_ctl_s cn68xxp1; 7703232812Sjmallett}; 7704232812Sjmalletttypedef union cvmx_gmxx_rxaui_ctl cvmx_gmxx_rxaui_ctl_t; 7705232812Sjmallett 7706232812Sjmallett/** 7707215976Sjmallett * cvmx_gmx#_smac# 7708215976Sjmallett * 7709215976Sjmallett * GMX_SMAC = Packet SMAC 7710215976Sjmallett * 7711215976Sjmallett */ 7712232812Sjmallettunion cvmx_gmxx_smacx { 7713215976Sjmallett uint64_t u64; 7714232812Sjmallett struct cvmx_gmxx_smacx_s { 7715232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7716215976Sjmallett uint64_t reserved_48_63 : 16; 7717215976Sjmallett uint64_t smac : 48; /**< The SMAC field is used for generating and 7718215976Sjmallett accepting Control Pause packets */ 7719215976Sjmallett#else 7720215976Sjmallett uint64_t smac : 48; 7721215976Sjmallett uint64_t reserved_48_63 : 16; 7722215976Sjmallett#endif 7723215976Sjmallett } s; 7724215976Sjmallett struct cvmx_gmxx_smacx_s cn30xx; 7725215976Sjmallett struct cvmx_gmxx_smacx_s cn31xx; 7726215976Sjmallett struct cvmx_gmxx_smacx_s cn38xx; 7727215976Sjmallett struct cvmx_gmxx_smacx_s cn38xxp2; 7728215976Sjmallett struct cvmx_gmxx_smacx_s cn50xx; 7729215976Sjmallett struct cvmx_gmxx_smacx_s cn52xx; 7730215976Sjmallett struct cvmx_gmxx_smacx_s cn52xxp1; 7731215976Sjmallett struct cvmx_gmxx_smacx_s cn56xx; 7732215976Sjmallett struct cvmx_gmxx_smacx_s cn56xxp1; 7733215976Sjmallett struct cvmx_gmxx_smacx_s cn58xx; 7734215976Sjmallett struct cvmx_gmxx_smacx_s cn58xxp1; 7735232812Sjmallett struct cvmx_gmxx_smacx_s cn61xx; 7736215976Sjmallett struct cvmx_gmxx_smacx_s cn63xx; 7737215976Sjmallett struct cvmx_gmxx_smacx_s cn63xxp1; 7738232812Sjmallett struct cvmx_gmxx_smacx_s cn66xx; 7739232812Sjmallett struct cvmx_gmxx_smacx_s cn68xx; 7740232812Sjmallett struct cvmx_gmxx_smacx_s cn68xxp1; 7741232812Sjmallett struct cvmx_gmxx_smacx_s cnf71xx; 7742215976Sjmallett}; 7743215976Sjmalletttypedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t; 7744215976Sjmallett 7745215976Sjmallett/** 7746215976Sjmallett * cvmx_gmx#_soft_bist 7747215976Sjmallett * 7748215976Sjmallett * GMX_SOFT_BIST = Software BIST Control 7749215976Sjmallett * 7750215976Sjmallett */ 7751232812Sjmallettunion cvmx_gmxx_soft_bist { 7752215976Sjmallett uint64_t u64; 7753232812Sjmallett struct cvmx_gmxx_soft_bist_s { 7754232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7755215976Sjmallett uint64_t reserved_2_63 : 62; 7756232812Sjmallett uint64_t start_bist : 1; /**< Run BIST on all memories in the XAUI/RXAUI 7757232812Sjmallett CLK domain */ 7758215976Sjmallett uint64_t clear_bist : 1; /**< Choose between full BIST and CLEAR bist 7759215976Sjmallett 0=Run full BIST 7760215976Sjmallett 1=Only run clear BIST */ 7761215976Sjmallett#else 7762215976Sjmallett uint64_t clear_bist : 1; 7763215976Sjmallett uint64_t start_bist : 1; 7764215976Sjmallett uint64_t reserved_2_63 : 62; 7765215976Sjmallett#endif 7766215976Sjmallett } s; 7767215976Sjmallett struct cvmx_gmxx_soft_bist_s cn63xx; 7768215976Sjmallett struct cvmx_gmxx_soft_bist_s cn63xxp1; 7769232812Sjmallett struct cvmx_gmxx_soft_bist_s cn66xx; 7770232812Sjmallett struct cvmx_gmxx_soft_bist_s cn68xx; 7771232812Sjmallett struct cvmx_gmxx_soft_bist_s cn68xxp1; 7772215976Sjmallett}; 7773215976Sjmalletttypedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t; 7774215976Sjmallett 7775215976Sjmallett/** 7776215976Sjmallett * cvmx_gmx#_stat_bp 7777215976Sjmallett * 7778215976Sjmallett * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation 7779215976Sjmallett * 7780232812Sjmallett * 7781232812Sjmallett * Notes: 7782232812Sjmallett * It has no relationship with the TX FIFO per se. The TX engine sends packets 7783232812Sjmallett * from PKO and upon completion, sends a command to the TX stats block for an 7784232812Sjmallett * update based on the packet size. The stats operation can take a few cycles - 7785232812Sjmallett * normally not enough to be visible considering the 64B min packet size that is 7786232812Sjmallett * ethernet convention. 7787232812Sjmallett * 7788232812Sjmallett * In the rare case in which SW attempted to schedule really, really, small packets 7789232812Sjmallett * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in 7790232812Sjmallett * real time and can back up the TX engine. 7791232812Sjmallett * 7792232812Sjmallett * This counter is the number of cycles in which the TX engine was stalled. In 7793232812Sjmallett * normal operation, it should always be zeros. 7794215976Sjmallett */ 7795232812Sjmallettunion cvmx_gmxx_stat_bp { 7796215976Sjmallett uint64_t u64; 7797232812Sjmallett struct cvmx_gmxx_stat_bp_s { 7798232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7799215976Sjmallett uint64_t reserved_17_63 : 47; 7800232812Sjmallett uint64_t bp : 1; /**< Current TX stats BP state 7801232812Sjmallett When the TX stats machine cannot update the stats 7802232812Sjmallett registers quickly enough, the machine has the 7803232812Sjmallett ability to BP TX datapath. This is a rare event 7804232812Sjmallett and will not occur in normal operation. 7805232812Sjmallett 0 = no backpressure is applied 7806232812Sjmallett 1 = backpressure is applied to TX datapath to 7807232812Sjmallett allow stat update operations to complete */ 7808215976Sjmallett uint64_t cnt : 16; /**< Number of cycles that BP has been asserted 7809215976Sjmallett Saturating counter */ 7810215976Sjmallett#else 7811215976Sjmallett uint64_t cnt : 16; 7812215976Sjmallett uint64_t bp : 1; 7813215976Sjmallett uint64_t reserved_17_63 : 47; 7814215976Sjmallett#endif 7815215976Sjmallett } s; 7816215976Sjmallett struct cvmx_gmxx_stat_bp_s cn30xx; 7817215976Sjmallett struct cvmx_gmxx_stat_bp_s cn31xx; 7818215976Sjmallett struct cvmx_gmxx_stat_bp_s cn38xx; 7819215976Sjmallett struct cvmx_gmxx_stat_bp_s cn38xxp2; 7820215976Sjmallett struct cvmx_gmxx_stat_bp_s cn50xx; 7821215976Sjmallett struct cvmx_gmxx_stat_bp_s cn52xx; 7822215976Sjmallett struct cvmx_gmxx_stat_bp_s cn52xxp1; 7823215976Sjmallett struct cvmx_gmxx_stat_bp_s cn56xx; 7824215976Sjmallett struct cvmx_gmxx_stat_bp_s cn56xxp1; 7825215976Sjmallett struct cvmx_gmxx_stat_bp_s cn58xx; 7826215976Sjmallett struct cvmx_gmxx_stat_bp_s cn58xxp1; 7827232812Sjmallett struct cvmx_gmxx_stat_bp_s cn61xx; 7828215976Sjmallett struct cvmx_gmxx_stat_bp_s cn63xx; 7829215976Sjmallett struct cvmx_gmxx_stat_bp_s cn63xxp1; 7830232812Sjmallett struct cvmx_gmxx_stat_bp_s cn66xx; 7831232812Sjmallett struct cvmx_gmxx_stat_bp_s cn68xx; 7832232812Sjmallett struct cvmx_gmxx_stat_bp_s cn68xxp1; 7833232812Sjmallett struct cvmx_gmxx_stat_bp_s cnf71xx; 7834215976Sjmallett}; 7835215976Sjmalletttypedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t; 7836215976Sjmallett 7837215976Sjmallett/** 7838232812Sjmallett * cvmx_gmx#_tb_reg 7839232812Sjmallett * 7840232812Sjmallett * DON'T PUT IN HRM* 7841232812Sjmallett * 7842232812Sjmallett */ 7843232812Sjmallettunion cvmx_gmxx_tb_reg { 7844232812Sjmallett uint64_t u64; 7845232812Sjmallett struct cvmx_gmxx_tb_reg_s { 7846232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7847232812Sjmallett uint64_t reserved_1_63 : 63; 7848232812Sjmallett uint64_t wr_magic : 1; /**< Enter stats model magic mode */ 7849232812Sjmallett#else 7850232812Sjmallett uint64_t wr_magic : 1; 7851232812Sjmallett uint64_t reserved_1_63 : 63; 7852232812Sjmallett#endif 7853232812Sjmallett } s; 7854232812Sjmallett struct cvmx_gmxx_tb_reg_s cn61xx; 7855232812Sjmallett struct cvmx_gmxx_tb_reg_s cn66xx; 7856232812Sjmallett struct cvmx_gmxx_tb_reg_s cn68xx; 7857232812Sjmallett struct cvmx_gmxx_tb_reg_s cnf71xx; 7858232812Sjmallett}; 7859232812Sjmalletttypedef union cvmx_gmxx_tb_reg cvmx_gmxx_tb_reg_t; 7860232812Sjmallett 7861232812Sjmallett/** 7862215976Sjmallett * cvmx_gmx#_tx#_append 7863215976Sjmallett * 7864215976Sjmallett * GMX_TX_APPEND = Packet TX Append Control 7865215976Sjmallett * 7866215976Sjmallett */ 7867232812Sjmallettunion cvmx_gmxx_txx_append { 7868215976Sjmallett uint64_t u64; 7869232812Sjmallett struct cvmx_gmxx_txx_append_s { 7870232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7871215976Sjmallett uint64_t reserved_4_63 : 60; 7872215976Sjmallett uint64_t force_fcs : 1; /**< Append the Ethernet FCS on each pause packet 7873215976Sjmallett when FCS is clear. Pause packets are normally 7874215976Sjmallett padded to 60 bytes. If GMX_TX_MIN_PKT[MIN_SIZE] 7875215976Sjmallett exceeds 59, then FORCE_FCS will not be used. */ 7876215976Sjmallett uint64_t fcs : 1; /**< Append the Ethernet FCS on each packet */ 7877215976Sjmallett uint64_t pad : 1; /**< Append PAD bytes such that min sized */ 7878215976Sjmallett uint64_t preamble : 1; /**< Prepend the Ethernet preamble on each transfer 7879215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, PREAMBLE 7880215976Sjmallett must be zero. */ 7881215976Sjmallett#else 7882215976Sjmallett uint64_t preamble : 1; 7883215976Sjmallett uint64_t pad : 1; 7884215976Sjmallett uint64_t fcs : 1; 7885215976Sjmallett uint64_t force_fcs : 1; 7886215976Sjmallett uint64_t reserved_4_63 : 60; 7887215976Sjmallett#endif 7888215976Sjmallett } s; 7889215976Sjmallett struct cvmx_gmxx_txx_append_s cn30xx; 7890215976Sjmallett struct cvmx_gmxx_txx_append_s cn31xx; 7891215976Sjmallett struct cvmx_gmxx_txx_append_s cn38xx; 7892215976Sjmallett struct cvmx_gmxx_txx_append_s cn38xxp2; 7893215976Sjmallett struct cvmx_gmxx_txx_append_s cn50xx; 7894215976Sjmallett struct cvmx_gmxx_txx_append_s cn52xx; 7895215976Sjmallett struct cvmx_gmxx_txx_append_s cn52xxp1; 7896215976Sjmallett struct cvmx_gmxx_txx_append_s cn56xx; 7897215976Sjmallett struct cvmx_gmxx_txx_append_s cn56xxp1; 7898215976Sjmallett struct cvmx_gmxx_txx_append_s cn58xx; 7899215976Sjmallett struct cvmx_gmxx_txx_append_s cn58xxp1; 7900232812Sjmallett struct cvmx_gmxx_txx_append_s cn61xx; 7901215976Sjmallett struct cvmx_gmxx_txx_append_s cn63xx; 7902215976Sjmallett struct cvmx_gmxx_txx_append_s cn63xxp1; 7903232812Sjmallett struct cvmx_gmxx_txx_append_s cn66xx; 7904232812Sjmallett struct cvmx_gmxx_txx_append_s cn68xx; 7905232812Sjmallett struct cvmx_gmxx_txx_append_s cn68xxp1; 7906232812Sjmallett struct cvmx_gmxx_txx_append_s cnf71xx; 7907215976Sjmallett}; 7908215976Sjmalletttypedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t; 7909215976Sjmallett 7910215976Sjmallett/** 7911215976Sjmallett * cvmx_gmx#_tx#_burst 7912215976Sjmallett * 7913215976Sjmallett * GMX_TX_BURST = Packet TX Burst Counter 7914215976Sjmallett * 7915215976Sjmallett */ 7916232812Sjmallettunion cvmx_gmxx_txx_burst { 7917215976Sjmallett uint64_t u64; 7918232812Sjmallett struct cvmx_gmxx_txx_burst_s { 7919232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7920215976Sjmallett uint64_t reserved_16_63 : 48; 7921215976Sjmallett uint64_t burst : 16; /**< Burst (refer to 802.3 to set correctly) 7922215976Sjmallett Only valid for 1000Mbs half-duplex operation 7923215976Sjmallett halfdup / 1000Mbs: 0x2000 7924215976Sjmallett all other modes: 0x0 7925215976Sjmallett (SGMII/1000Base-X only) */ 7926215976Sjmallett#else 7927215976Sjmallett uint64_t burst : 16; 7928215976Sjmallett uint64_t reserved_16_63 : 48; 7929215976Sjmallett#endif 7930215976Sjmallett } s; 7931215976Sjmallett struct cvmx_gmxx_txx_burst_s cn30xx; 7932215976Sjmallett struct cvmx_gmxx_txx_burst_s cn31xx; 7933215976Sjmallett struct cvmx_gmxx_txx_burst_s cn38xx; 7934215976Sjmallett struct cvmx_gmxx_txx_burst_s cn38xxp2; 7935215976Sjmallett struct cvmx_gmxx_txx_burst_s cn50xx; 7936215976Sjmallett struct cvmx_gmxx_txx_burst_s cn52xx; 7937215976Sjmallett struct cvmx_gmxx_txx_burst_s cn52xxp1; 7938215976Sjmallett struct cvmx_gmxx_txx_burst_s cn56xx; 7939215976Sjmallett struct cvmx_gmxx_txx_burst_s cn56xxp1; 7940215976Sjmallett struct cvmx_gmxx_txx_burst_s cn58xx; 7941215976Sjmallett struct cvmx_gmxx_txx_burst_s cn58xxp1; 7942232812Sjmallett struct cvmx_gmxx_txx_burst_s cn61xx; 7943215976Sjmallett struct cvmx_gmxx_txx_burst_s cn63xx; 7944215976Sjmallett struct cvmx_gmxx_txx_burst_s cn63xxp1; 7945232812Sjmallett struct cvmx_gmxx_txx_burst_s cn66xx; 7946232812Sjmallett struct cvmx_gmxx_txx_burst_s cn68xx; 7947232812Sjmallett struct cvmx_gmxx_txx_burst_s cn68xxp1; 7948232812Sjmallett struct cvmx_gmxx_txx_burst_s cnf71xx; 7949215976Sjmallett}; 7950215976Sjmalletttypedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t; 7951215976Sjmallett 7952215976Sjmallett/** 7953215976Sjmallett * cvmx_gmx#_tx#_cbfc_xoff 7954215976Sjmallett */ 7955232812Sjmallettunion cvmx_gmxx_txx_cbfc_xoff { 7956215976Sjmallett uint64_t u64; 7957232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s { 7958232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7959215976Sjmallett uint64_t reserved_16_63 : 48; 7960215976Sjmallett uint64_t xoff : 16; /**< Which ports to backpressure 7961215976Sjmallett Do not write in HiGig2 mode i.e. when 7962215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 7963215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 7964215976Sjmallett#else 7965215976Sjmallett uint64_t xoff : 16; 7966215976Sjmallett uint64_t reserved_16_63 : 48; 7967215976Sjmallett#endif 7968215976Sjmallett } s; 7969215976Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; 7970215976Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; 7971232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx; 7972215976Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx; 7973215976Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1; 7974232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx; 7975232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx; 7976232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1; 7977232812Sjmallett struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx; 7978215976Sjmallett}; 7979215976Sjmalletttypedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t; 7980215976Sjmallett 7981215976Sjmallett/** 7982215976Sjmallett * cvmx_gmx#_tx#_cbfc_xon 7983215976Sjmallett */ 7984232812Sjmallettunion cvmx_gmxx_txx_cbfc_xon { 7985215976Sjmallett uint64_t u64; 7986232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s { 7987232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7988215976Sjmallett uint64_t reserved_16_63 : 48; 7989215976Sjmallett uint64_t xon : 16; /**< Which ports to stop backpressure 7990215976Sjmallett Do not write in HiGig2 mode i.e. when 7991215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 7992215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 7993215976Sjmallett#else 7994215976Sjmallett uint64_t xon : 16; 7995215976Sjmallett uint64_t reserved_16_63 : 48; 7996215976Sjmallett#endif 7997215976Sjmallett } s; 7998215976Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; 7999215976Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; 8000232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn61xx; 8001215976Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn63xx; 8002215976Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1; 8003232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn66xx; 8004232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn68xx; 8005232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1; 8006232812Sjmallett struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx; 8007215976Sjmallett}; 8008215976Sjmalletttypedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t; 8009215976Sjmallett 8010215976Sjmallett/** 8011215976Sjmallett * cvmx_gmx#_tx#_clk 8012215976Sjmallett * 8013215976Sjmallett * Per Port 8014215976Sjmallett * 8015215976Sjmallett * 8016215976Sjmallett * GMX_TX_CLK = RGMII TX Clock Generation Register 8017215976Sjmallett * 8018215976Sjmallett * Notes: 8019215976Sjmallett * Programming Restrictions: 8020215976Sjmallett * (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1. 8021215976Sjmallett * (2) In MII mode, CLK_CNT == 1 8022215976Sjmallett * (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock. 8023215976Sjmallett * 8024215976Sjmallett * RGMII Example: 8025215976Sjmallett * Given a 125MHz PLL reference clock... 8026215976Sjmallett * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1) 8027215976Sjmallett * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5) 8028215976Sjmallett * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50) 8029215976Sjmallett */ 8030232812Sjmallettunion cvmx_gmxx_txx_clk { 8031215976Sjmallett uint64_t u64; 8032232812Sjmallett struct cvmx_gmxx_txx_clk_s { 8033232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8034215976Sjmallett uint64_t reserved_6_63 : 58; 8035215976Sjmallett uint64_t clk_cnt : 6; /**< Controls the RGMII TXC frequency 8036215976Sjmallett When PLL is used, TXC(phase) = 8037215976Sjmallett spi4_tx_pll_ref_clk(period)/2*CLK_CNT 8038215976Sjmallett When PLL bypass is used, TXC(phase) = 8039215976Sjmallett spi4_tx_pll_ref_clk(period)*2*CLK_CNT 8040215976Sjmallett NOTE: CLK_CNT==0 will not generate any clock 8041215976Sjmallett if CLK_CNT > 1 if GMX_PRT_CFG[SPEED]==0 */ 8042215976Sjmallett#else 8043215976Sjmallett uint64_t clk_cnt : 6; 8044215976Sjmallett uint64_t reserved_6_63 : 58; 8045215976Sjmallett#endif 8046215976Sjmallett } s; 8047215976Sjmallett struct cvmx_gmxx_txx_clk_s cn30xx; 8048215976Sjmallett struct cvmx_gmxx_txx_clk_s cn31xx; 8049215976Sjmallett struct cvmx_gmxx_txx_clk_s cn38xx; 8050215976Sjmallett struct cvmx_gmxx_txx_clk_s cn38xxp2; 8051215976Sjmallett struct cvmx_gmxx_txx_clk_s cn50xx; 8052215976Sjmallett struct cvmx_gmxx_txx_clk_s cn58xx; 8053215976Sjmallett struct cvmx_gmxx_txx_clk_s cn58xxp1; 8054215976Sjmallett}; 8055215976Sjmalletttypedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t; 8056215976Sjmallett 8057215976Sjmallett/** 8058215976Sjmallett * cvmx_gmx#_tx#_ctl 8059215976Sjmallett * 8060215976Sjmallett * GMX_TX_CTL = TX Control register 8061215976Sjmallett * 8062215976Sjmallett */ 8063232812Sjmallettunion cvmx_gmxx_txx_ctl { 8064215976Sjmallett uint64_t u64; 8065232812Sjmallett struct cvmx_gmxx_txx_ctl_s { 8066232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8067215976Sjmallett uint64_t reserved_2_63 : 62; 8068215976Sjmallett uint64_t xsdef_en : 1; /**< Enables the excessive deferral check for stats 8069215976Sjmallett and interrupts 8070215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8071215976Sjmallett uint64_t xscol_en : 1; /**< Enables the excessive collision check for stats 8072215976Sjmallett and interrupts 8073215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8074215976Sjmallett#else 8075215976Sjmallett uint64_t xscol_en : 1; 8076215976Sjmallett uint64_t xsdef_en : 1; 8077215976Sjmallett uint64_t reserved_2_63 : 62; 8078215976Sjmallett#endif 8079215976Sjmallett } s; 8080215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn30xx; 8081215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn31xx; 8082215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn38xx; 8083215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn38xxp2; 8084215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn50xx; 8085215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn52xx; 8086215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn52xxp1; 8087215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn56xx; 8088215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn56xxp1; 8089215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn58xx; 8090215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn58xxp1; 8091232812Sjmallett struct cvmx_gmxx_txx_ctl_s cn61xx; 8092215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn63xx; 8093215976Sjmallett struct cvmx_gmxx_txx_ctl_s cn63xxp1; 8094232812Sjmallett struct cvmx_gmxx_txx_ctl_s cn66xx; 8095232812Sjmallett struct cvmx_gmxx_txx_ctl_s cn68xx; 8096232812Sjmallett struct cvmx_gmxx_txx_ctl_s cn68xxp1; 8097232812Sjmallett struct cvmx_gmxx_txx_ctl_s cnf71xx; 8098215976Sjmallett}; 8099215976Sjmalletttypedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t; 8100215976Sjmallett 8101215976Sjmallett/** 8102215976Sjmallett * cvmx_gmx#_tx#_min_pkt 8103215976Sjmallett * 8104215976Sjmallett * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size) 8105215976Sjmallett * 8106215976Sjmallett */ 8107232812Sjmallettunion cvmx_gmxx_txx_min_pkt { 8108215976Sjmallett uint64_t u64; 8109232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s { 8110232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8111215976Sjmallett uint64_t reserved_8_63 : 56; 8112215976Sjmallett uint64_t min_size : 8; /**< Min frame in bytes before the FCS is applied 8113215976Sjmallett Padding is only appened when GMX_TX_APPEND[PAD] 8114215976Sjmallett for the coresponding port is set. 8115215976Sjmallett In SGMII mode, packets will be padded to 8116215976Sjmallett MIN_SIZE+1. The reset value will pad to 60 bytes. 8117215976Sjmallett In XAUI mode, packets will be padded to 8118215976Sjmallett MIN(252,(MIN_SIZE+1 & ~0x3)) 8119215976Sjmallett When GMX_TX_XAUI_CTL[HG_EN] is set, the HiGig 8120215976Sjmallett header (12B or 16B) is normally added to the 8121215976Sjmallett packet, so MIN_SIZE should be 59+12=71B for 8122215976Sjmallett HiGig or 59+16=75B for HiGig2. */ 8123215976Sjmallett#else 8124215976Sjmallett uint64_t min_size : 8; 8125215976Sjmallett uint64_t reserved_8_63 : 56; 8126215976Sjmallett#endif 8127215976Sjmallett } s; 8128215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn30xx; 8129215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn31xx; 8130215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn38xx; 8131215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; 8132215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn50xx; 8133215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn52xx; 8134215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; 8135215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn56xx; 8136215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; 8137215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn58xx; 8138215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; 8139232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn61xx; 8140215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn63xx; 8141215976Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn63xxp1; 8142232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn66xx; 8143232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn68xx; 8144232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s cn68xxp1; 8145232812Sjmallett struct cvmx_gmxx_txx_min_pkt_s cnf71xx; 8146215976Sjmallett}; 8147215976Sjmalletttypedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t; 8148215976Sjmallett 8149215976Sjmallett/** 8150215976Sjmallett * cvmx_gmx#_tx#_pause_pkt_interval 8151215976Sjmallett * 8152215976Sjmallett * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent 8153215976Sjmallett * 8154215976Sjmallett * 8155215976Sjmallett * Notes: 8156215976Sjmallett * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and 8157215976Sjmallett * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 8158215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 8159215976Sjmallett * GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 8160215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 8161215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 8162215976Sjmallett * data. 8163215976Sjmallett * 8164215976Sjmallett * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is 8165215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 8166215976Sjmallett * following rule... 8167215976Sjmallett * 8168215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 8169215976Sjmallett * 8170215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 8171215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 8172215976Sjmallett * of the PAUSE packet (normally 64B). 8173215976Sjmallett */ 8174232812Sjmallettunion cvmx_gmxx_txx_pause_pkt_interval { 8175215976Sjmallett uint64_t u64; 8176232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s { 8177232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8178215976Sjmallett uint64_t reserved_16_63 : 48; 8179215976Sjmallett uint64_t interval : 16; /**< Arbitrate for a 802.3 pause packet, HiGig2 message, 8180215976Sjmallett or CBFC pause packet every (INTERVAL*512) 8181215976Sjmallett bit-times. 8182215976Sjmallett Normally, 0 < INTERVAL < GMX_TX_PAUSE_PKT_TIME 8183215976Sjmallett INTERVAL=0, will only send a single PAUSE packet 8184215976Sjmallett for each backpressure event */ 8185215976Sjmallett#else 8186215976Sjmallett uint64_t interval : 16; 8187215976Sjmallett uint64_t reserved_16_63 : 48; 8188215976Sjmallett#endif 8189215976Sjmallett } s; 8190215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; 8191215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; 8192215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; 8193215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; 8194215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; 8195215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; 8196215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; 8197215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; 8198215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; 8199215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; 8200215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; 8201232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx; 8202215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx; 8203215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1; 8204232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx; 8205232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx; 8206232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1; 8207232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx; 8208215976Sjmallett}; 8209215976Sjmalletttypedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t; 8210215976Sjmallett 8211215976Sjmallett/** 8212215976Sjmallett * cvmx_gmx#_tx#_pause_pkt_time 8213215976Sjmallett * 8214215976Sjmallett * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field 8215215976Sjmallett * 8216215976Sjmallett * 8217215976Sjmallett * Notes: 8218215976Sjmallett * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and 8219215976Sjmallett * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 8220215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 8221215976Sjmallett * GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 8222215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 8223215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 8224215976Sjmallett * data. 8225215976Sjmallett * 8226215976Sjmallett * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is 8227215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 8228215976Sjmallett * following rule... 8229215976Sjmallett * 8230215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 8231215976Sjmallett * 8232215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 8233215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 8234215976Sjmallett * of the PAUSE packet (normally 64B). 8235215976Sjmallett */ 8236232812Sjmallettunion cvmx_gmxx_txx_pause_pkt_time { 8237215976Sjmallett uint64_t u64; 8238232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s { 8239232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8240215976Sjmallett uint64_t reserved_16_63 : 48; 8241215976Sjmallett uint64_t time : 16; /**< The pause_time field placed in outbnd 802.3 pause 8242215976Sjmallett packets, HiGig2 messages, or CBFC pause packets. 8243215976Sjmallett pause_time is in 512 bit-times 8244215976Sjmallett Normally, TIME > GMX_TX_PAUSE_PKT_INTERVAL */ 8245215976Sjmallett#else 8246215976Sjmallett uint64_t time : 16; 8247215976Sjmallett uint64_t reserved_16_63 : 48; 8248215976Sjmallett#endif 8249215976Sjmallett } s; 8250215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; 8251215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; 8252215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; 8253215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; 8254215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; 8255215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; 8256215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; 8257215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; 8258215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; 8259215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; 8260215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; 8261232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx; 8262215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx; 8263215976Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1; 8264232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx; 8265232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx; 8266232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1; 8267232812Sjmallett struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx; 8268215976Sjmallett}; 8269215976Sjmalletttypedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t; 8270215976Sjmallett 8271215976Sjmallett/** 8272215976Sjmallett * cvmx_gmx#_tx#_pause_togo 8273215976Sjmallett * 8274215976Sjmallett * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure 8275215976Sjmallett * 8276215976Sjmallett */ 8277232812Sjmallettunion cvmx_gmxx_txx_pause_togo { 8278215976Sjmallett uint64_t u64; 8279232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s { 8280232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8281215976Sjmallett uint64_t reserved_32_63 : 32; 8282215976Sjmallett uint64_t msg_time : 16; /**< Amount of time remaining to backpressure 8283215976Sjmallett From the higig2 physical message pause timer 8284215976Sjmallett (only valid on port0) */ 8285215976Sjmallett uint64_t time : 16; /**< Amount of time remaining to backpressure 8286215976Sjmallett From the standard 802.3 pause timer */ 8287215976Sjmallett#else 8288215976Sjmallett uint64_t time : 16; 8289215976Sjmallett uint64_t msg_time : 16; 8290215976Sjmallett uint64_t reserved_32_63 : 32; 8291215976Sjmallett#endif 8292215976Sjmallett } s; 8293232812Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx { 8294232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8295215976Sjmallett uint64_t reserved_16_63 : 48; 8296215976Sjmallett uint64_t time : 16; /**< Amount of time remaining to backpressure */ 8297215976Sjmallett#else 8298215976Sjmallett uint64_t time : 16; 8299215976Sjmallett uint64_t reserved_16_63 : 48; 8300215976Sjmallett#endif 8301215976Sjmallett } cn30xx; 8302215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; 8303215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; 8304215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; 8305215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; 8306215976Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn52xx; 8307215976Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; 8308215976Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn56xx; 8309215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; 8310215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; 8311215976Sjmallett struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; 8312232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn61xx; 8313215976Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn63xx; 8314215976Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn63xxp1; 8315232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn66xx; 8316232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn68xx; 8317232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s cn68xxp1; 8318232812Sjmallett struct cvmx_gmxx_txx_pause_togo_s cnf71xx; 8319215976Sjmallett}; 8320215976Sjmalletttypedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t; 8321215976Sjmallett 8322215976Sjmallett/** 8323215976Sjmallett * cvmx_gmx#_tx#_pause_zero 8324215976Sjmallett * 8325215976Sjmallett * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure 8326215976Sjmallett * 8327215976Sjmallett */ 8328232812Sjmallettunion cvmx_gmxx_txx_pause_zero { 8329215976Sjmallett uint64_t u64; 8330232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s { 8331232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8332215976Sjmallett uint64_t reserved_1_63 : 63; 8333215976Sjmallett uint64_t send : 1; /**< When backpressure condition clear, send PAUSE 8334215976Sjmallett packet with pause_time of zero to enable the 8335215976Sjmallett channel */ 8336215976Sjmallett#else 8337215976Sjmallett uint64_t send : 1; 8338215976Sjmallett uint64_t reserved_1_63 : 63; 8339215976Sjmallett#endif 8340215976Sjmallett } s; 8341215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn30xx; 8342215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn31xx; 8343215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn38xx; 8344215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; 8345215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn50xx; 8346215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn52xx; 8347215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; 8348215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn56xx; 8349215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; 8350215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn58xx; 8351215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; 8352232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn61xx; 8353215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn63xx; 8354215976Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn63xxp1; 8355232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn66xx; 8356232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn68xx; 8357232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s cn68xxp1; 8358232812Sjmallett struct cvmx_gmxx_txx_pause_zero_s cnf71xx; 8359215976Sjmallett}; 8360215976Sjmalletttypedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t; 8361215976Sjmallett 8362215976Sjmallett/** 8363232812Sjmallett * cvmx_gmx#_tx#_pipe 8364232812Sjmallett */ 8365232812Sjmallettunion cvmx_gmxx_txx_pipe { 8366232812Sjmallett uint64_t u64; 8367232812Sjmallett struct cvmx_gmxx_txx_pipe_s { 8368232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8369232812Sjmallett uint64_t reserved_33_63 : 31; 8370232812Sjmallett uint64_t ign_bp : 1; /**< When set, GMX will not throttle the TX machines 8371232812Sjmallett if the PIPE return FIFO fills up. 8372232812Sjmallett IGN_BP should be clear in normal operation. */ 8373232812Sjmallett uint64_t reserved_21_31 : 11; 8374232812Sjmallett uint64_t nump : 5; /**< Number of pipes this port|channel supports. 8375232812Sjmallett In SGMII mode, each port binds to one pipe. 8376232812Sjmallett In XAUI/RXAUI mode, the port can bind upto 16 8377232812Sjmallett consecutive pipes. 8378232812Sjmallett SGMII mode, NUMP = 0 or 1. 8379232812Sjmallett XAUI/RXAUI mode, NUMP = 0 or 1-16. 8380232812Sjmallett 0 = Disabled */ 8381232812Sjmallett uint64_t reserved_7_15 : 9; 8382232812Sjmallett uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe 8383232812Sjmallett number this port|channel will accept. 8384232812Sjmallett This port will accept pko packets from pipes in 8385232812Sjmallett the range of: 8386232812Sjmallett BASE .. (BASE+(NUMP-1)) 8387232812Sjmallett BASE and NUMP must be constrained such that 8388232812Sjmallett 1) BASE+(NUMP-1) < 127 8389232812Sjmallett 2) Each used PKO pipe must map to exactly 8390232812Sjmallett one port|channel 8391232812Sjmallett 3) The pipe ranges must be consistent with 8392232812Sjmallett the PKO configuration. */ 8393232812Sjmallett#else 8394232812Sjmallett uint64_t base : 7; 8395232812Sjmallett uint64_t reserved_7_15 : 9; 8396232812Sjmallett uint64_t nump : 5; 8397232812Sjmallett uint64_t reserved_21_31 : 11; 8398232812Sjmallett uint64_t ign_bp : 1; 8399232812Sjmallett uint64_t reserved_33_63 : 31; 8400232812Sjmallett#endif 8401232812Sjmallett } s; 8402232812Sjmallett struct cvmx_gmxx_txx_pipe_s cn68xx; 8403232812Sjmallett struct cvmx_gmxx_txx_pipe_s cn68xxp1; 8404232812Sjmallett}; 8405232812Sjmalletttypedef union cvmx_gmxx_txx_pipe cvmx_gmxx_txx_pipe_t; 8406232812Sjmallett 8407232812Sjmallett/** 8408215976Sjmallett * cvmx_gmx#_tx#_sgmii_ctl 8409215976Sjmallett */ 8410232812Sjmallettunion cvmx_gmxx_txx_sgmii_ctl { 8411215976Sjmallett uint64_t u64; 8412232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s { 8413232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8414215976Sjmallett uint64_t reserved_1_63 : 63; 8415215976Sjmallett uint64_t align : 1; /**< Align the transmission to even cycles 8416232812Sjmallett 8417232812Sjmallett Recommended value is: 8418232812Sjmallett ALIGN = !GMX_TX_APPEND[PREAMBLE] 8419232812Sjmallett 8420232812Sjmallett (See the Transmit Conversion to Code groups 8421232812Sjmallett section in the SGMII Interface chapter of the 8422232812Sjmallett HRM for a complete discussion) 8423232812Sjmallett 8424215976Sjmallett 0 = Data can be sent on any cycle 8425232812Sjmallett In this mode, the interface will function at 8426232812Sjmallett maximum bandwidth. It is possible to for the 8427232812Sjmallett TX PCS machine to drop first byte of the TX 8428232812Sjmallett frame. When GMX_TX_APPEND[PREAMBLE] is set, 8429232812Sjmallett the first byte will be a preamble byte which 8430232812Sjmallett can be dropped to compensate for an extended 8431232812Sjmallett IPG. 8432232812Sjmallett 8433232812Sjmallett 1 = Data will only be sent on even cycles. 8434232812Sjmallett In this mode, there can be bandwidth 8435232812Sjmallett implications when sending odd-byte packets as 8436232812Sjmallett the IPG can extend an extra cycle. 8437232812Sjmallett There will be no loss of data. 8438232812Sjmallett 8439215976Sjmallett (SGMII/1000Base-X only) */ 8440215976Sjmallett#else 8441215976Sjmallett uint64_t align : 1; 8442215976Sjmallett uint64_t reserved_1_63 : 63; 8443215976Sjmallett#endif 8444215976Sjmallett } s; 8445215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; 8446215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; 8447215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; 8448215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; 8449232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx; 8450215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx; 8451215976Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1; 8452232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx; 8453232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx; 8454232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1; 8455232812Sjmallett struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx; 8456215976Sjmallett}; 8457215976Sjmalletttypedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t; 8458215976Sjmallett 8459215976Sjmallett/** 8460215976Sjmallett * cvmx_gmx#_tx#_slot 8461215976Sjmallett * 8462215976Sjmallett * GMX_TX_SLOT = Packet TX Slottime Counter 8463215976Sjmallett * 8464215976Sjmallett */ 8465232812Sjmallettunion cvmx_gmxx_txx_slot { 8466215976Sjmallett uint64_t u64; 8467232812Sjmallett struct cvmx_gmxx_txx_slot_s { 8468232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8469215976Sjmallett uint64_t reserved_10_63 : 54; 8470215976Sjmallett uint64_t slot : 10; /**< Slottime (refer to 802.3 to set correctly) 8471215976Sjmallett 10/100Mbs: 0x40 8472215976Sjmallett 1000Mbs: 0x200 8473215976Sjmallett (SGMII/1000Base-X only) */ 8474215976Sjmallett#else 8475215976Sjmallett uint64_t slot : 10; 8476215976Sjmallett uint64_t reserved_10_63 : 54; 8477215976Sjmallett#endif 8478215976Sjmallett } s; 8479215976Sjmallett struct cvmx_gmxx_txx_slot_s cn30xx; 8480215976Sjmallett struct cvmx_gmxx_txx_slot_s cn31xx; 8481215976Sjmallett struct cvmx_gmxx_txx_slot_s cn38xx; 8482215976Sjmallett struct cvmx_gmxx_txx_slot_s cn38xxp2; 8483215976Sjmallett struct cvmx_gmxx_txx_slot_s cn50xx; 8484215976Sjmallett struct cvmx_gmxx_txx_slot_s cn52xx; 8485215976Sjmallett struct cvmx_gmxx_txx_slot_s cn52xxp1; 8486215976Sjmallett struct cvmx_gmxx_txx_slot_s cn56xx; 8487215976Sjmallett struct cvmx_gmxx_txx_slot_s cn56xxp1; 8488215976Sjmallett struct cvmx_gmxx_txx_slot_s cn58xx; 8489215976Sjmallett struct cvmx_gmxx_txx_slot_s cn58xxp1; 8490232812Sjmallett struct cvmx_gmxx_txx_slot_s cn61xx; 8491215976Sjmallett struct cvmx_gmxx_txx_slot_s cn63xx; 8492215976Sjmallett struct cvmx_gmxx_txx_slot_s cn63xxp1; 8493232812Sjmallett struct cvmx_gmxx_txx_slot_s cn66xx; 8494232812Sjmallett struct cvmx_gmxx_txx_slot_s cn68xx; 8495232812Sjmallett struct cvmx_gmxx_txx_slot_s cn68xxp1; 8496232812Sjmallett struct cvmx_gmxx_txx_slot_s cnf71xx; 8497215976Sjmallett}; 8498215976Sjmalletttypedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t; 8499215976Sjmallett 8500215976Sjmallett/** 8501215976Sjmallett * cvmx_gmx#_tx#_soft_pause 8502215976Sjmallett * 8503215976Sjmallett * GMX_TX_SOFT_PAUSE = Packet TX Software Pause 8504215976Sjmallett * 8505215976Sjmallett */ 8506232812Sjmallettunion cvmx_gmxx_txx_soft_pause { 8507215976Sjmallett uint64_t u64; 8508232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s { 8509232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8510215976Sjmallett uint64_t reserved_16_63 : 48; 8511215976Sjmallett uint64_t time : 16; /**< Back off the TX bus for (TIME*512) bit-times */ 8512215976Sjmallett#else 8513215976Sjmallett uint64_t time : 16; 8514215976Sjmallett uint64_t reserved_16_63 : 48; 8515215976Sjmallett#endif 8516215976Sjmallett } s; 8517215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn30xx; 8518215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn31xx; 8519215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn38xx; 8520215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; 8521215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn50xx; 8522215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn52xx; 8523215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; 8524215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn56xx; 8525215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; 8526215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn58xx; 8527215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; 8528232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn61xx; 8529215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn63xx; 8530215976Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn63xxp1; 8531232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn66xx; 8532232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn68xx; 8533232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s cn68xxp1; 8534232812Sjmallett struct cvmx_gmxx_txx_soft_pause_s cnf71xx; 8535215976Sjmallett}; 8536215976Sjmalletttypedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t; 8537215976Sjmallett 8538215976Sjmallett/** 8539215976Sjmallett * cvmx_gmx#_tx#_stat0 8540215976Sjmallett * 8541215976Sjmallett * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL 8542215976Sjmallett * 8543215976Sjmallett * 8544215976Sjmallett * Notes: 8545215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8546215976Sjmallett * - Counters will wrap 8547215976Sjmallett */ 8548232812Sjmallettunion cvmx_gmxx_txx_stat0 { 8549215976Sjmallett uint64_t u64; 8550232812Sjmallett struct cvmx_gmxx_txx_stat0_s { 8551232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8552215976Sjmallett uint64_t xsdef : 32; /**< Number of packets dropped (never successfully 8553215976Sjmallett sent) due to excessive deferal 8554215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8555215976Sjmallett uint64_t xscol : 32; /**< Number of packets dropped (never successfully 8556215976Sjmallett sent) due to excessive collision. Defined by 8557215976Sjmallett GMX_TX_COL_ATTEMPT[LIMIT]. 8558215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8559215976Sjmallett#else 8560215976Sjmallett uint64_t xscol : 32; 8561215976Sjmallett uint64_t xsdef : 32; 8562215976Sjmallett#endif 8563215976Sjmallett } s; 8564215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn30xx; 8565215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn31xx; 8566215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn38xx; 8567215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn38xxp2; 8568215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn50xx; 8569215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn52xx; 8570215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn52xxp1; 8571215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn56xx; 8572215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn56xxp1; 8573215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn58xx; 8574215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn58xxp1; 8575232812Sjmallett struct cvmx_gmxx_txx_stat0_s cn61xx; 8576215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn63xx; 8577215976Sjmallett struct cvmx_gmxx_txx_stat0_s cn63xxp1; 8578232812Sjmallett struct cvmx_gmxx_txx_stat0_s cn66xx; 8579232812Sjmallett struct cvmx_gmxx_txx_stat0_s cn68xx; 8580232812Sjmallett struct cvmx_gmxx_txx_stat0_s cn68xxp1; 8581232812Sjmallett struct cvmx_gmxx_txx_stat0_s cnf71xx; 8582215976Sjmallett}; 8583215976Sjmalletttypedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t; 8584215976Sjmallett 8585215976Sjmallett/** 8586215976Sjmallett * cvmx_gmx#_tx#_stat1 8587215976Sjmallett * 8588215976Sjmallett * GMX_TX_STAT1 = GMX_TX_STATS_SCOL / GMX_TX_STATS_MCOL 8589215976Sjmallett * 8590215976Sjmallett * 8591215976Sjmallett * Notes: 8592215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8593215976Sjmallett * - Counters will wrap 8594215976Sjmallett */ 8595232812Sjmallettunion cvmx_gmxx_txx_stat1 { 8596215976Sjmallett uint64_t u64; 8597232812Sjmallett struct cvmx_gmxx_txx_stat1_s { 8598232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8599215976Sjmallett uint64_t scol : 32; /**< Number of packets sent with a single collision 8600215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8601215976Sjmallett uint64_t mcol : 32; /**< Number of packets sent with multiple collisions 8602215976Sjmallett but < GMX_TX_COL_ATTEMPT[LIMIT]. 8603215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 8604215976Sjmallett#else 8605215976Sjmallett uint64_t mcol : 32; 8606215976Sjmallett uint64_t scol : 32; 8607215976Sjmallett#endif 8608215976Sjmallett } s; 8609215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn30xx; 8610215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn31xx; 8611215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn38xx; 8612215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn38xxp2; 8613215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn50xx; 8614215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn52xx; 8615215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn52xxp1; 8616215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn56xx; 8617215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn56xxp1; 8618215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn58xx; 8619215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn58xxp1; 8620232812Sjmallett struct cvmx_gmxx_txx_stat1_s cn61xx; 8621215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn63xx; 8622215976Sjmallett struct cvmx_gmxx_txx_stat1_s cn63xxp1; 8623232812Sjmallett struct cvmx_gmxx_txx_stat1_s cn66xx; 8624232812Sjmallett struct cvmx_gmxx_txx_stat1_s cn68xx; 8625232812Sjmallett struct cvmx_gmxx_txx_stat1_s cn68xxp1; 8626232812Sjmallett struct cvmx_gmxx_txx_stat1_s cnf71xx; 8627215976Sjmallett}; 8628215976Sjmalletttypedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t; 8629215976Sjmallett 8630215976Sjmallett/** 8631215976Sjmallett * cvmx_gmx#_tx#_stat2 8632215976Sjmallett * 8633215976Sjmallett * GMX_TX_STAT2 = GMX_TX_STATS_OCTS 8634215976Sjmallett * 8635215976Sjmallett * 8636215976Sjmallett * Notes: 8637215976Sjmallett * - Octect counts are the sum of all data transmitted on the wire including 8638215976Sjmallett * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect 8639215976Sjmallett * counts do not include PREAMBLE byte or EXTEND cycles. 8640215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8641215976Sjmallett * - Counters will wrap 8642215976Sjmallett */ 8643232812Sjmallettunion cvmx_gmxx_txx_stat2 { 8644215976Sjmallett uint64_t u64; 8645232812Sjmallett struct cvmx_gmxx_txx_stat2_s { 8646232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8647215976Sjmallett uint64_t reserved_48_63 : 16; 8648215976Sjmallett uint64_t octs : 48; /**< Number of total octets sent on the interface. 8649215976Sjmallett Does not count octets from frames that were 8650215976Sjmallett truncated due to collisions in halfdup mode. */ 8651215976Sjmallett#else 8652215976Sjmallett uint64_t octs : 48; 8653215976Sjmallett uint64_t reserved_48_63 : 16; 8654215976Sjmallett#endif 8655215976Sjmallett } s; 8656215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn30xx; 8657215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn31xx; 8658215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn38xx; 8659215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn38xxp2; 8660215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn50xx; 8661215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn52xx; 8662215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn52xxp1; 8663215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn56xx; 8664215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn56xxp1; 8665215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn58xx; 8666215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn58xxp1; 8667232812Sjmallett struct cvmx_gmxx_txx_stat2_s cn61xx; 8668215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn63xx; 8669215976Sjmallett struct cvmx_gmxx_txx_stat2_s cn63xxp1; 8670232812Sjmallett struct cvmx_gmxx_txx_stat2_s cn66xx; 8671232812Sjmallett struct cvmx_gmxx_txx_stat2_s cn68xx; 8672232812Sjmallett struct cvmx_gmxx_txx_stat2_s cn68xxp1; 8673232812Sjmallett struct cvmx_gmxx_txx_stat2_s cnf71xx; 8674215976Sjmallett}; 8675215976Sjmalletttypedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t; 8676215976Sjmallett 8677215976Sjmallett/** 8678215976Sjmallett * cvmx_gmx#_tx#_stat3 8679215976Sjmallett * 8680215976Sjmallett * GMX_TX_STAT3 = GMX_TX_STATS_PKTS 8681215976Sjmallett * 8682215976Sjmallett * 8683215976Sjmallett * Notes: 8684215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8685215976Sjmallett * - Counters will wrap 8686215976Sjmallett */ 8687232812Sjmallettunion cvmx_gmxx_txx_stat3 { 8688215976Sjmallett uint64_t u64; 8689232812Sjmallett struct cvmx_gmxx_txx_stat3_s { 8690232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8691215976Sjmallett uint64_t reserved_32_63 : 32; 8692215976Sjmallett uint64_t pkts : 32; /**< Number of total frames sent on the interface. 8693215976Sjmallett Does not count frames that were truncated due to 8694215976Sjmallett collisions in halfdup mode. */ 8695215976Sjmallett#else 8696215976Sjmallett uint64_t pkts : 32; 8697215976Sjmallett uint64_t reserved_32_63 : 32; 8698215976Sjmallett#endif 8699215976Sjmallett } s; 8700215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn30xx; 8701215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn31xx; 8702215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn38xx; 8703215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn38xxp2; 8704215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn50xx; 8705215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn52xx; 8706215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn52xxp1; 8707215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn56xx; 8708215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn56xxp1; 8709215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn58xx; 8710215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn58xxp1; 8711232812Sjmallett struct cvmx_gmxx_txx_stat3_s cn61xx; 8712215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn63xx; 8713215976Sjmallett struct cvmx_gmxx_txx_stat3_s cn63xxp1; 8714232812Sjmallett struct cvmx_gmxx_txx_stat3_s cn66xx; 8715232812Sjmallett struct cvmx_gmxx_txx_stat3_s cn68xx; 8716232812Sjmallett struct cvmx_gmxx_txx_stat3_s cn68xxp1; 8717232812Sjmallett struct cvmx_gmxx_txx_stat3_s cnf71xx; 8718215976Sjmallett}; 8719215976Sjmalletttypedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t; 8720215976Sjmallett 8721215976Sjmallett/** 8722215976Sjmallett * cvmx_gmx#_tx#_stat4 8723215976Sjmallett * 8724215976Sjmallett * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64) 8725215976Sjmallett * 8726215976Sjmallett * 8727215976Sjmallett * Notes: 8728215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 8729215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 8730215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 8731215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8732215976Sjmallett * - Counters will wrap 8733215976Sjmallett */ 8734232812Sjmallettunion cvmx_gmxx_txx_stat4 { 8735215976Sjmallett uint64_t u64; 8736232812Sjmallett struct cvmx_gmxx_txx_stat4_s { 8737232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8738215976Sjmallett uint64_t hist1 : 32; /**< Number of packets sent with an octet count of 64. */ 8739215976Sjmallett uint64_t hist0 : 32; /**< Number of packets sent with an octet count 8740215976Sjmallett of < 64. */ 8741215976Sjmallett#else 8742215976Sjmallett uint64_t hist0 : 32; 8743215976Sjmallett uint64_t hist1 : 32; 8744215976Sjmallett#endif 8745215976Sjmallett } s; 8746215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn30xx; 8747215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn31xx; 8748215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn38xx; 8749215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn38xxp2; 8750215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn50xx; 8751215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn52xx; 8752215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn52xxp1; 8753215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn56xx; 8754215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn56xxp1; 8755215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn58xx; 8756215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn58xxp1; 8757232812Sjmallett struct cvmx_gmxx_txx_stat4_s cn61xx; 8758215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn63xx; 8759215976Sjmallett struct cvmx_gmxx_txx_stat4_s cn63xxp1; 8760232812Sjmallett struct cvmx_gmxx_txx_stat4_s cn66xx; 8761232812Sjmallett struct cvmx_gmxx_txx_stat4_s cn68xx; 8762232812Sjmallett struct cvmx_gmxx_txx_stat4_s cn68xxp1; 8763232812Sjmallett struct cvmx_gmxx_txx_stat4_s cnf71xx; 8764215976Sjmallett}; 8765215976Sjmalletttypedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t; 8766215976Sjmallett 8767215976Sjmallett/** 8768215976Sjmallett * cvmx_gmx#_tx#_stat5 8769215976Sjmallett * 8770215976Sjmallett * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127) 8771215976Sjmallett * 8772215976Sjmallett * 8773215976Sjmallett * Notes: 8774215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 8775215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 8776215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 8777215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8778215976Sjmallett * - Counters will wrap 8779215976Sjmallett */ 8780232812Sjmallettunion cvmx_gmxx_txx_stat5 { 8781215976Sjmallett uint64_t u64; 8782232812Sjmallett struct cvmx_gmxx_txx_stat5_s { 8783232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8784215976Sjmallett uint64_t hist3 : 32; /**< Number of packets sent with an octet count of 8785215976Sjmallett 128 - 255. */ 8786215976Sjmallett uint64_t hist2 : 32; /**< Number of packets sent with an octet count of 8787215976Sjmallett 65 - 127. */ 8788215976Sjmallett#else 8789215976Sjmallett uint64_t hist2 : 32; 8790215976Sjmallett uint64_t hist3 : 32; 8791215976Sjmallett#endif 8792215976Sjmallett } s; 8793215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn30xx; 8794215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn31xx; 8795215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn38xx; 8796215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn38xxp2; 8797215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn50xx; 8798215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn52xx; 8799215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn52xxp1; 8800215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn56xx; 8801215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn56xxp1; 8802215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn58xx; 8803215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn58xxp1; 8804232812Sjmallett struct cvmx_gmxx_txx_stat5_s cn61xx; 8805215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn63xx; 8806215976Sjmallett struct cvmx_gmxx_txx_stat5_s cn63xxp1; 8807232812Sjmallett struct cvmx_gmxx_txx_stat5_s cn66xx; 8808232812Sjmallett struct cvmx_gmxx_txx_stat5_s cn68xx; 8809232812Sjmallett struct cvmx_gmxx_txx_stat5_s cn68xxp1; 8810232812Sjmallett struct cvmx_gmxx_txx_stat5_s cnf71xx; 8811215976Sjmallett}; 8812215976Sjmalletttypedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t; 8813215976Sjmallett 8814215976Sjmallett/** 8815215976Sjmallett * cvmx_gmx#_tx#_stat6 8816215976Sjmallett * 8817215976Sjmallett * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511) 8818215976Sjmallett * 8819215976Sjmallett * 8820215976Sjmallett * Notes: 8821215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 8822215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 8823215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 8824215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8825215976Sjmallett * - Counters will wrap 8826215976Sjmallett */ 8827232812Sjmallettunion cvmx_gmxx_txx_stat6 { 8828215976Sjmallett uint64_t u64; 8829232812Sjmallett struct cvmx_gmxx_txx_stat6_s { 8830232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8831215976Sjmallett uint64_t hist5 : 32; /**< Number of packets sent with an octet count of 8832215976Sjmallett 512 - 1023. */ 8833215976Sjmallett uint64_t hist4 : 32; /**< Number of packets sent with an octet count of 8834215976Sjmallett 256 - 511. */ 8835215976Sjmallett#else 8836215976Sjmallett uint64_t hist4 : 32; 8837215976Sjmallett uint64_t hist5 : 32; 8838215976Sjmallett#endif 8839215976Sjmallett } s; 8840215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn30xx; 8841215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn31xx; 8842215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn38xx; 8843215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn38xxp2; 8844215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn50xx; 8845215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn52xx; 8846215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn52xxp1; 8847215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn56xx; 8848215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn56xxp1; 8849215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn58xx; 8850215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn58xxp1; 8851232812Sjmallett struct cvmx_gmxx_txx_stat6_s cn61xx; 8852215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn63xx; 8853215976Sjmallett struct cvmx_gmxx_txx_stat6_s cn63xxp1; 8854232812Sjmallett struct cvmx_gmxx_txx_stat6_s cn66xx; 8855232812Sjmallett struct cvmx_gmxx_txx_stat6_s cn68xx; 8856232812Sjmallett struct cvmx_gmxx_txx_stat6_s cn68xxp1; 8857232812Sjmallett struct cvmx_gmxx_txx_stat6_s cnf71xx; 8858215976Sjmallett}; 8859215976Sjmalletttypedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t; 8860215976Sjmallett 8861215976Sjmallett/** 8862215976Sjmallett * cvmx_gmx#_tx#_stat7 8863215976Sjmallett * 8864215976Sjmallett * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518) 8865215976Sjmallett * 8866215976Sjmallett * 8867215976Sjmallett * Notes: 8868215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 8869215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 8870215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 8871215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8872215976Sjmallett * - Counters will wrap 8873215976Sjmallett */ 8874232812Sjmallettunion cvmx_gmxx_txx_stat7 { 8875215976Sjmallett uint64_t u64; 8876232812Sjmallett struct cvmx_gmxx_txx_stat7_s { 8877232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8878215976Sjmallett uint64_t hist7 : 32; /**< Number of packets sent with an octet count 8879215976Sjmallett of > 1518. */ 8880215976Sjmallett uint64_t hist6 : 32; /**< Number of packets sent with an octet count of 8881215976Sjmallett 1024 - 1518. */ 8882215976Sjmallett#else 8883215976Sjmallett uint64_t hist6 : 32; 8884215976Sjmallett uint64_t hist7 : 32; 8885215976Sjmallett#endif 8886215976Sjmallett } s; 8887215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn30xx; 8888215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn31xx; 8889215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn38xx; 8890215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn38xxp2; 8891215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn50xx; 8892215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn52xx; 8893215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn52xxp1; 8894215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn56xx; 8895215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn56xxp1; 8896215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn58xx; 8897215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn58xxp1; 8898232812Sjmallett struct cvmx_gmxx_txx_stat7_s cn61xx; 8899215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn63xx; 8900215976Sjmallett struct cvmx_gmxx_txx_stat7_s cn63xxp1; 8901232812Sjmallett struct cvmx_gmxx_txx_stat7_s cn66xx; 8902232812Sjmallett struct cvmx_gmxx_txx_stat7_s cn68xx; 8903232812Sjmallett struct cvmx_gmxx_txx_stat7_s cn68xxp1; 8904232812Sjmallett struct cvmx_gmxx_txx_stat7_s cnf71xx; 8905215976Sjmallett}; 8906215976Sjmalletttypedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t; 8907215976Sjmallett 8908215976Sjmallett/** 8909215976Sjmallett * cvmx_gmx#_tx#_stat8 8910215976Sjmallett * 8911215976Sjmallett * GMX_TX_STAT8 = GMX_TX_STATS_MCST / GMX_TX_STATS_BCST 8912215976Sjmallett * 8913215976Sjmallett * 8914215976Sjmallett * Notes: 8915215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8916215976Sjmallett * - Counters will wrap 8917215976Sjmallett * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the 8918215976Sjmallett * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet 8919215976Sjmallett * as per the 802.3 frame definition. If the system requires additional data 8920215976Sjmallett * before the L2 header, then the MCST and BCST counters may not reflect 8921215976Sjmallett * reality and should be ignored by software. 8922215976Sjmallett */ 8923232812Sjmallettunion cvmx_gmxx_txx_stat8 { 8924215976Sjmallett uint64_t u64; 8925232812Sjmallett struct cvmx_gmxx_txx_stat8_s { 8926232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8927215976Sjmallett uint64_t mcst : 32; /**< Number of packets sent to multicast DMAC. 8928215976Sjmallett Does not include BCST packets. */ 8929215976Sjmallett uint64_t bcst : 32; /**< Number of packets sent to broadcast DMAC. 8930215976Sjmallett Does not include MCST packets. */ 8931215976Sjmallett#else 8932215976Sjmallett uint64_t bcst : 32; 8933215976Sjmallett uint64_t mcst : 32; 8934215976Sjmallett#endif 8935215976Sjmallett } s; 8936215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn30xx; 8937215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn31xx; 8938215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn38xx; 8939215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn38xxp2; 8940215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn50xx; 8941215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn52xx; 8942215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn52xxp1; 8943215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn56xx; 8944215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn56xxp1; 8945215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn58xx; 8946215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn58xxp1; 8947232812Sjmallett struct cvmx_gmxx_txx_stat8_s cn61xx; 8948215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn63xx; 8949215976Sjmallett struct cvmx_gmxx_txx_stat8_s cn63xxp1; 8950232812Sjmallett struct cvmx_gmxx_txx_stat8_s cn66xx; 8951232812Sjmallett struct cvmx_gmxx_txx_stat8_s cn68xx; 8952232812Sjmallett struct cvmx_gmxx_txx_stat8_s cn68xxp1; 8953232812Sjmallett struct cvmx_gmxx_txx_stat8_s cnf71xx; 8954215976Sjmallett}; 8955215976Sjmalletttypedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t; 8956215976Sjmallett 8957215976Sjmallett/** 8958215976Sjmallett * cvmx_gmx#_tx#_stat9 8959215976Sjmallett * 8960215976Sjmallett * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL 8961215976Sjmallett * 8962215976Sjmallett * 8963215976Sjmallett * Notes: 8964215976Sjmallett * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set 8965215976Sjmallett * - Counters will wrap 8966215976Sjmallett */ 8967232812Sjmallettunion cvmx_gmxx_txx_stat9 { 8968215976Sjmallett uint64_t u64; 8969232812Sjmallett struct cvmx_gmxx_txx_stat9_s { 8970232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8971215976Sjmallett uint64_t undflw : 32; /**< Number of underflow packets */ 8972215976Sjmallett uint64_t ctl : 32; /**< Number of Control packets (PAUSE flow control) 8973215976Sjmallett generated by GMX. It does not include control 8974232812Sjmallett packets forwarded or generated by the PP's. 8975232812Sjmallett CTL will count the number of generated PFC frames. 8976232812Sjmallett CTL will not track the number of generated HG2 8977232812Sjmallett messages. */ 8978215976Sjmallett#else 8979215976Sjmallett uint64_t ctl : 32; 8980215976Sjmallett uint64_t undflw : 32; 8981215976Sjmallett#endif 8982215976Sjmallett } s; 8983215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn30xx; 8984215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn31xx; 8985215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn38xx; 8986215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn38xxp2; 8987215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn50xx; 8988215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn52xx; 8989215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn52xxp1; 8990215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn56xx; 8991215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn56xxp1; 8992215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn58xx; 8993215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn58xxp1; 8994232812Sjmallett struct cvmx_gmxx_txx_stat9_s cn61xx; 8995215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn63xx; 8996215976Sjmallett struct cvmx_gmxx_txx_stat9_s cn63xxp1; 8997232812Sjmallett struct cvmx_gmxx_txx_stat9_s cn66xx; 8998232812Sjmallett struct cvmx_gmxx_txx_stat9_s cn68xx; 8999232812Sjmallett struct cvmx_gmxx_txx_stat9_s cn68xxp1; 9000232812Sjmallett struct cvmx_gmxx_txx_stat9_s cnf71xx; 9001215976Sjmallett}; 9002215976Sjmalletttypedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t; 9003215976Sjmallett 9004215976Sjmallett/** 9005215976Sjmallett * cvmx_gmx#_tx#_stats_ctl 9006215976Sjmallett * 9007215976Sjmallett * GMX_TX_STATS_CTL = TX Stats Control register 9008215976Sjmallett * 9009215976Sjmallett */ 9010232812Sjmallettunion cvmx_gmxx_txx_stats_ctl { 9011215976Sjmallett uint64_t u64; 9012232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s { 9013232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9014215976Sjmallett uint64_t reserved_1_63 : 63; 9015215976Sjmallett uint64_t rd_clr : 1; /**< Stats registers will clear on reads */ 9016215976Sjmallett#else 9017215976Sjmallett uint64_t rd_clr : 1; 9018215976Sjmallett uint64_t reserved_1_63 : 63; 9019215976Sjmallett#endif 9020215976Sjmallett } s; 9021215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn30xx; 9022215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn31xx; 9023215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn38xx; 9024215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; 9025215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn50xx; 9026215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn52xx; 9027215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; 9028215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn56xx; 9029215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; 9030215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn58xx; 9031215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; 9032232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn61xx; 9033215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn63xx; 9034215976Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1; 9035232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn66xx; 9036232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn68xx; 9037232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1; 9038232812Sjmallett struct cvmx_gmxx_txx_stats_ctl_s cnf71xx; 9039215976Sjmallett}; 9040215976Sjmalletttypedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t; 9041215976Sjmallett 9042215976Sjmallett/** 9043215976Sjmallett * cvmx_gmx#_tx#_thresh 9044215976Sjmallett * 9045215976Sjmallett * Per Port 9046215976Sjmallett * 9047215976Sjmallett * 9048215976Sjmallett * GMX_TX_THRESH = Packet TX Threshold 9049215976Sjmallett * 9050215976Sjmallett * Notes: 9051215976Sjmallett * In XAUI mode, prt0 is used for checking. Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x100. 9052215976Sjmallett * 9053215976Sjmallett */ 9054232812Sjmallettunion cvmx_gmxx_txx_thresh { 9055215976Sjmallett uint64_t u64; 9056232812Sjmallett struct cvmx_gmxx_txx_thresh_s { 9057232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9058232812Sjmallett uint64_t reserved_10_63 : 54; 9059232812Sjmallett uint64_t cnt : 10; /**< Number of 16B ticks to accumulate in the TX FIFO 9060215976Sjmallett before sending on the packet interface 9061215976Sjmallett This register should be large enough to prevent 9062215976Sjmallett underflow on the packet interface and must never 9063215976Sjmallett be set to zero. This register cannot exceed the 9064215976Sjmallett the TX FIFO depth which is... 9065215976Sjmallett GMX_TX_PRTS==0,1: CNT MAX = 0x100 9066215976Sjmallett GMX_TX_PRTS==2 : CNT MAX = 0x080 9067215976Sjmallett GMX_TX_PRTS==3,4: CNT MAX = 0x040 */ 9068215976Sjmallett#else 9069232812Sjmallett uint64_t cnt : 10; 9070232812Sjmallett uint64_t reserved_10_63 : 54; 9071215976Sjmallett#endif 9072215976Sjmallett } s; 9073232812Sjmallett struct cvmx_gmxx_txx_thresh_cn30xx { 9074232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9075215976Sjmallett uint64_t reserved_7_63 : 57; 9076215976Sjmallett uint64_t cnt : 7; /**< Number of 16B ticks to accumulate in the TX FIFO 9077215976Sjmallett before sending on the RGMII interface 9078215976Sjmallett This register should be large enough to prevent 9079215976Sjmallett underflow on the RGMII interface and must never 9080215976Sjmallett be set below 4. This register cannot exceed the 9081215976Sjmallett the TX FIFO depth which is 64 16B entries. */ 9082215976Sjmallett#else 9083215976Sjmallett uint64_t cnt : 7; 9084215976Sjmallett uint64_t reserved_7_63 : 57; 9085215976Sjmallett#endif 9086215976Sjmallett } cn30xx; 9087215976Sjmallett struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; 9088232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx { 9089232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9090232812Sjmallett uint64_t reserved_9_63 : 55; 9091232812Sjmallett uint64_t cnt : 9; /**< Number of 16B ticks to accumulate in the TX FIFO 9092232812Sjmallett before sending on the RGMII interface 9093232812Sjmallett This register should be large enough to prevent 9094232812Sjmallett underflow on the RGMII interface and must never 9095232812Sjmallett be set to zero. This register cannot exceed the 9096232812Sjmallett the TX FIFO depth which is... 9097232812Sjmallett GMX_TX_PRTS==0,1: CNT MAX = 0x100 9098232812Sjmallett GMX_TX_PRTS==2 : CNT MAX = 0x080 9099232812Sjmallett GMX_TX_PRTS==3,4: CNT MAX = 0x040 9100232812Sjmallett (PASS2 expands from 6 to 9 bits) */ 9101232812Sjmallett#else 9102232812Sjmallett uint64_t cnt : 9; 9103232812Sjmallett uint64_t reserved_9_63 : 55; 9104232812Sjmallett#endif 9105232812Sjmallett } cn38xx; 9106232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2; 9107215976Sjmallett struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; 9108232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn52xx; 9109232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1; 9110232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn56xx; 9111232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1; 9112232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn58xx; 9113232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1; 9114232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn61xx; 9115232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn63xx; 9116232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1; 9117232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cn66xx; 9118232812Sjmallett struct cvmx_gmxx_txx_thresh_s cn68xx; 9119232812Sjmallett struct cvmx_gmxx_txx_thresh_s cn68xxp1; 9120232812Sjmallett struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx; 9121215976Sjmallett}; 9122215976Sjmalletttypedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t; 9123215976Sjmallett 9124215976Sjmallett/** 9125215976Sjmallett * cvmx_gmx#_tx_bp 9126215976Sjmallett * 9127215976Sjmallett * GMX_TX_BP = Packet Interface TX BackPressure Register 9128215976Sjmallett * 9129215976Sjmallett * 9130215976Sjmallett * Notes: 9131215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of BP is used. 9132215976Sjmallett * 9133215976Sjmallett */ 9134232812Sjmallettunion cvmx_gmxx_tx_bp { 9135215976Sjmallett uint64_t u64; 9136232812Sjmallett struct cvmx_gmxx_tx_bp_s { 9137232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9138215976Sjmallett uint64_t reserved_4_63 : 60; 9139215976Sjmallett uint64_t bp : 4; /**< Per port BackPressure status 9140215976Sjmallett 0=Port is available 9141215976Sjmallett 1=Port should be back pressured */ 9142215976Sjmallett#else 9143215976Sjmallett uint64_t bp : 4; 9144215976Sjmallett uint64_t reserved_4_63 : 60; 9145215976Sjmallett#endif 9146215976Sjmallett } s; 9147232812Sjmallett struct cvmx_gmxx_tx_bp_cn30xx { 9148232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9149215976Sjmallett uint64_t reserved_3_63 : 61; 9150215976Sjmallett uint64_t bp : 3; /**< Per port BackPressure status 9151215976Sjmallett 0=Port is available 9152215976Sjmallett 1=Port should be back pressured */ 9153215976Sjmallett#else 9154215976Sjmallett uint64_t bp : 3; 9155215976Sjmallett uint64_t reserved_3_63 : 61; 9156215976Sjmallett#endif 9157215976Sjmallett } cn30xx; 9158215976Sjmallett struct cvmx_gmxx_tx_bp_cn30xx cn31xx; 9159215976Sjmallett struct cvmx_gmxx_tx_bp_s cn38xx; 9160215976Sjmallett struct cvmx_gmxx_tx_bp_s cn38xxp2; 9161215976Sjmallett struct cvmx_gmxx_tx_bp_cn30xx cn50xx; 9162215976Sjmallett struct cvmx_gmxx_tx_bp_s cn52xx; 9163215976Sjmallett struct cvmx_gmxx_tx_bp_s cn52xxp1; 9164215976Sjmallett struct cvmx_gmxx_tx_bp_s cn56xx; 9165215976Sjmallett struct cvmx_gmxx_tx_bp_s cn56xxp1; 9166215976Sjmallett struct cvmx_gmxx_tx_bp_s cn58xx; 9167215976Sjmallett struct cvmx_gmxx_tx_bp_s cn58xxp1; 9168232812Sjmallett struct cvmx_gmxx_tx_bp_s cn61xx; 9169215976Sjmallett struct cvmx_gmxx_tx_bp_s cn63xx; 9170215976Sjmallett struct cvmx_gmxx_tx_bp_s cn63xxp1; 9171232812Sjmallett struct cvmx_gmxx_tx_bp_s cn66xx; 9172232812Sjmallett struct cvmx_gmxx_tx_bp_s cn68xx; 9173232812Sjmallett struct cvmx_gmxx_tx_bp_s cn68xxp1; 9174232812Sjmallett struct cvmx_gmxx_tx_bp_cnf71xx { 9175232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9176232812Sjmallett uint64_t reserved_2_63 : 62; 9177232812Sjmallett uint64_t bp : 2; /**< Per port BackPressure status 9178232812Sjmallett 0=Port is available 9179232812Sjmallett 1=Port should be back pressured */ 9180232812Sjmallett#else 9181232812Sjmallett uint64_t bp : 2; 9182232812Sjmallett uint64_t reserved_2_63 : 62; 9183232812Sjmallett#endif 9184232812Sjmallett } cnf71xx; 9185215976Sjmallett}; 9186215976Sjmalletttypedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t; 9187215976Sjmallett 9188215976Sjmallett/** 9189215976Sjmallett * cvmx_gmx#_tx_clk_msk# 9190215976Sjmallett * 9191215976Sjmallett * GMX_TX_CLK_MSK = GMX Clock Select 9192215976Sjmallett * 9193215976Sjmallett */ 9194232812Sjmallettunion cvmx_gmxx_tx_clk_mskx { 9195215976Sjmallett uint64_t u64; 9196232812Sjmallett struct cvmx_gmxx_tx_clk_mskx_s { 9197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9198215976Sjmallett uint64_t reserved_1_63 : 63; 9199215976Sjmallett uint64_t msk : 1; /**< Write this bit to a 1 when switching clks */ 9200215976Sjmallett#else 9201215976Sjmallett uint64_t msk : 1; 9202215976Sjmallett uint64_t reserved_1_63 : 63; 9203215976Sjmallett#endif 9204215976Sjmallett } s; 9205215976Sjmallett struct cvmx_gmxx_tx_clk_mskx_s cn30xx; 9206215976Sjmallett struct cvmx_gmxx_tx_clk_mskx_s cn50xx; 9207215976Sjmallett}; 9208215976Sjmalletttypedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t; 9209215976Sjmallett 9210215976Sjmallett/** 9211215976Sjmallett * cvmx_gmx#_tx_col_attempt 9212215976Sjmallett * 9213215976Sjmallett * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame 9214215976Sjmallett * 9215215976Sjmallett */ 9216232812Sjmallettunion cvmx_gmxx_tx_col_attempt { 9217215976Sjmallett uint64_t u64; 9218232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s { 9219232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9220215976Sjmallett uint64_t reserved_5_63 : 59; 9221215976Sjmallett uint64_t limit : 5; /**< Collision Attempts 9222215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9223215976Sjmallett#else 9224215976Sjmallett uint64_t limit : 5; 9225215976Sjmallett uint64_t reserved_5_63 : 59; 9226215976Sjmallett#endif 9227215976Sjmallett } s; 9228215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn30xx; 9229215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn31xx; 9230215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn38xx; 9231215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; 9232215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn50xx; 9233215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn52xx; 9234215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; 9235215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn56xx; 9236215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; 9237215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn58xx; 9238215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; 9239232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn61xx; 9240215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn63xx; 9241215976Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn63xxp1; 9242232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn66xx; 9243232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn68xx; 9244232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s cn68xxp1; 9245232812Sjmallett struct cvmx_gmxx_tx_col_attempt_s cnf71xx; 9246215976Sjmallett}; 9247215976Sjmalletttypedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t; 9248215976Sjmallett 9249215976Sjmallett/** 9250215976Sjmallett * cvmx_gmx#_tx_corrupt 9251215976Sjmallett * 9252215976Sjmallett * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set 9253215976Sjmallett * 9254215976Sjmallett * 9255215976Sjmallett * Notes: 9256215976Sjmallett * Packets sent from PKO with the ERR wire asserted will be corrupted by 9257215976Sjmallett * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0). 9258215976Sjmallett * 9259215976Sjmallett * Corruption means that GMX will send a bad FCS value. If GMX_TX_APPEND[FCS] 9260215976Sjmallett * is clear then no FCS is sent and the GMX cannot corrupt it. The corrupt FCS 9261215976Sjmallett * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error 9262215976Sjmallett * propagation code in XAUI mode. 9263215976Sjmallett */ 9264232812Sjmallettunion cvmx_gmxx_tx_corrupt { 9265215976Sjmallett uint64_t u64; 9266232812Sjmallett struct cvmx_gmxx_tx_corrupt_s { 9267232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9268215976Sjmallett uint64_t reserved_4_63 : 60; 9269215976Sjmallett uint64_t corrupt : 4; /**< Per port error propagation 9270215976Sjmallett 0=Never corrupt packets 9271215976Sjmallett 1=Corrupt packets with ERR */ 9272215976Sjmallett#else 9273215976Sjmallett uint64_t corrupt : 4; 9274215976Sjmallett uint64_t reserved_4_63 : 60; 9275215976Sjmallett#endif 9276215976Sjmallett } s; 9277232812Sjmallett struct cvmx_gmxx_tx_corrupt_cn30xx { 9278232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9279215976Sjmallett uint64_t reserved_3_63 : 61; 9280215976Sjmallett uint64_t corrupt : 3; /**< Per port error propagation 9281215976Sjmallett 0=Never corrupt packets 9282215976Sjmallett 1=Corrupt packets with ERR */ 9283215976Sjmallett#else 9284215976Sjmallett uint64_t corrupt : 3; 9285215976Sjmallett uint64_t reserved_3_63 : 61; 9286215976Sjmallett#endif 9287215976Sjmallett } cn30xx; 9288215976Sjmallett struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; 9289215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn38xx; 9290215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn38xxp2; 9291215976Sjmallett struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; 9292215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn52xx; 9293215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn52xxp1; 9294215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn56xx; 9295215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn56xxp1; 9296215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn58xx; 9297215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn58xxp1; 9298232812Sjmallett struct cvmx_gmxx_tx_corrupt_s cn61xx; 9299215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn63xx; 9300215976Sjmallett struct cvmx_gmxx_tx_corrupt_s cn63xxp1; 9301232812Sjmallett struct cvmx_gmxx_tx_corrupt_s cn66xx; 9302232812Sjmallett struct cvmx_gmxx_tx_corrupt_s cn68xx; 9303232812Sjmallett struct cvmx_gmxx_tx_corrupt_s cn68xxp1; 9304232812Sjmallett struct cvmx_gmxx_tx_corrupt_cnf71xx { 9305232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9306232812Sjmallett uint64_t reserved_2_63 : 62; 9307232812Sjmallett uint64_t corrupt : 2; /**< Per port error propagation 9308232812Sjmallett 0=Never corrupt packets 9309232812Sjmallett 1=Corrupt packets with ERR */ 9310232812Sjmallett#else 9311232812Sjmallett uint64_t corrupt : 2; 9312232812Sjmallett uint64_t reserved_2_63 : 62; 9313232812Sjmallett#endif 9314232812Sjmallett } cnf71xx; 9315215976Sjmallett}; 9316215976Sjmalletttypedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t; 9317215976Sjmallett 9318215976Sjmallett/** 9319215976Sjmallett * cvmx_gmx#_tx_hg2_reg1 9320215976Sjmallett * 9321215976Sjmallett * Notes: 9322215976Sjmallett * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in 9323215976Sjmallett * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of 9324215976Sjmallett * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of 9325215976Sjmallett * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior. 9326215976Sjmallett * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values. 9327215976Sjmallett */ 9328232812Sjmallettunion cvmx_gmxx_tx_hg2_reg1 { 9329215976Sjmallett uint64_t u64; 9330232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s { 9331232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9332215976Sjmallett uint64_t reserved_16_63 : 48; 9333215976Sjmallett uint64_t tx_xof : 16; /**< TX HiGig2 message for logical link pause when any 9334215976Sjmallett bit value changes 9335215976Sjmallett Only write in HiGig2 mode i.e. when 9336215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 9337215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 9338215976Sjmallett#else 9339215976Sjmallett uint64_t tx_xof : 16; 9340215976Sjmallett uint64_t reserved_16_63 : 48; 9341215976Sjmallett#endif 9342215976Sjmallett } s; 9343215976Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; 9344215976Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; 9345215976Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; 9346232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn61xx; 9347215976Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn63xx; 9348215976Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1; 9349232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn66xx; 9350232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn68xx; 9351232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1; 9352232812Sjmallett struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx; 9353215976Sjmallett}; 9354215976Sjmalletttypedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t; 9355215976Sjmallett 9356215976Sjmallett/** 9357215976Sjmallett * cvmx_gmx#_tx_hg2_reg2 9358215976Sjmallett * 9359215976Sjmallett * Notes: 9360215976Sjmallett * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in 9361215976Sjmallett * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of 9362215976Sjmallett * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of 9363215976Sjmallett * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior. 9364215976Sjmallett * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values. 9365215976Sjmallett */ 9366232812Sjmallettunion cvmx_gmxx_tx_hg2_reg2 { 9367215976Sjmallett uint64_t u64; 9368232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s { 9369232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9370215976Sjmallett uint64_t reserved_16_63 : 48; 9371215976Sjmallett uint64_t tx_xon : 16; /**< TX HiGig2 message for logical link pause when any 9372215976Sjmallett bit value changes 9373215976Sjmallett Only write in HiGig2 mode i.e. when 9374215976Sjmallett GMX_TX_XAUI_CTL[HG_EN]=1 and 9375215976Sjmallett GMX_RX_UDD_SKP[SKIP]=16. */ 9376215976Sjmallett#else 9377215976Sjmallett uint64_t tx_xon : 16; 9378215976Sjmallett uint64_t reserved_16_63 : 48; 9379215976Sjmallett#endif 9380215976Sjmallett } s; 9381215976Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; 9382215976Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; 9383215976Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; 9384232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn61xx; 9385215976Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn63xx; 9386215976Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1; 9387232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn66xx; 9388232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn68xx; 9389232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1; 9390232812Sjmallett struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx; 9391215976Sjmallett}; 9392215976Sjmalletttypedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t; 9393215976Sjmallett 9394215976Sjmallett/** 9395215976Sjmallett * cvmx_gmx#_tx_ifg 9396215976Sjmallett * 9397215976Sjmallett * GMX_TX_IFG = Packet TX Interframe Gap 9398215976Sjmallett * 9399215976Sjmallett * 9400215976Sjmallett * Notes: 9401215976Sjmallett * * Programming IFG1 and IFG2. 9402215976Sjmallett * 9403215976Sjmallett * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3 9404215976Sjmallett * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range 9405215976Sjmallett * of 4-12, and the IFG1+IFG2 sum must be 12. 9406215976Sjmallett * 9407215976Sjmallett * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3 9408215976Sjmallett * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range 9409215976Sjmallett * of 1-11, and the IFG1+IFG2 sum must be 12. 9410215976Sjmallett * 9411215976Sjmallett * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the 9412215976Sjmallett * IFG1+IFG2 sum must be 12. IFG1[1:0] and IFG2[1:0] must be zero. 9413215976Sjmallett * 9414215976Sjmallett * For all other systems, IFG1 and IFG2 can be any value in the range of 9415215976Sjmallett * 1-15. Allowing for a total possible IFG sum of 2-30. 9416215976Sjmallett */ 9417232812Sjmallettunion cvmx_gmxx_tx_ifg { 9418215976Sjmallett uint64_t u64; 9419232812Sjmallett struct cvmx_gmxx_tx_ifg_s { 9420232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9421215976Sjmallett uint64_t reserved_8_63 : 56; 9422215976Sjmallett uint64_t ifg2 : 4; /**< 1/3 of the interframe gap timing (in IFG2*8 bits) 9423215976Sjmallett If CRS is detected during IFG2, then the 9424215976Sjmallett interFrameSpacing timer is not reset and a frame 9425215976Sjmallett is transmited once the timer expires. */ 9426215976Sjmallett uint64_t ifg1 : 4; /**< 2/3 of the interframe gap timing (in IFG1*8 bits) 9427215976Sjmallett If CRS is detected during IFG1, then the 9428215976Sjmallett interFrameSpacing timer is reset and a frame is 9429215976Sjmallett not transmited. */ 9430215976Sjmallett#else 9431215976Sjmallett uint64_t ifg1 : 4; 9432215976Sjmallett uint64_t ifg2 : 4; 9433215976Sjmallett uint64_t reserved_8_63 : 56; 9434215976Sjmallett#endif 9435215976Sjmallett } s; 9436215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn30xx; 9437215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn31xx; 9438215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn38xx; 9439215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn38xxp2; 9440215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn50xx; 9441215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn52xx; 9442215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn52xxp1; 9443215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn56xx; 9444215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn56xxp1; 9445215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn58xx; 9446215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn58xxp1; 9447232812Sjmallett struct cvmx_gmxx_tx_ifg_s cn61xx; 9448215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn63xx; 9449215976Sjmallett struct cvmx_gmxx_tx_ifg_s cn63xxp1; 9450232812Sjmallett struct cvmx_gmxx_tx_ifg_s cn66xx; 9451232812Sjmallett struct cvmx_gmxx_tx_ifg_s cn68xx; 9452232812Sjmallett struct cvmx_gmxx_tx_ifg_s cn68xxp1; 9453232812Sjmallett struct cvmx_gmxx_tx_ifg_s cnf71xx; 9454215976Sjmallett}; 9455215976Sjmalletttypedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t; 9456215976Sjmallett 9457215976Sjmallett/** 9458215976Sjmallett * cvmx_gmx#_tx_int_en 9459215976Sjmallett * 9460215976Sjmallett * GMX_TX_INT_EN = Interrupt Enable 9461215976Sjmallett * 9462215976Sjmallett * 9463215976Sjmallett * Notes: 9464215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used. 9465215976Sjmallett * 9466215976Sjmallett */ 9467232812Sjmallettunion cvmx_gmxx_tx_int_en { 9468215976Sjmallett uint64_t u64; 9469232812Sjmallett struct cvmx_gmxx_tx_int_en_s { 9470232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9471232812Sjmallett uint64_t reserved_25_63 : 39; 9472232812Sjmallett uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change 9473232812Sjmallett to GMX_RX_XAUI_CTL[STATUS] 9474232812Sjmallett (XAUI mode only) */ 9475215976Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9476215976Sjmallett sent due to XSCOL */ 9477215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9478215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9479215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9480215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9481215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9482215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9483215976Sjmallett uint64_t reserved_6_7 : 2; 9484215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9485232812Sjmallett uint64_t reserved_1_1 : 1; 9486215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9487215976Sjmallett#else 9488215976Sjmallett uint64_t pko_nxa : 1; 9489232812Sjmallett uint64_t reserved_1_1 : 1; 9490215976Sjmallett uint64_t undflw : 4; 9491215976Sjmallett uint64_t reserved_6_7 : 2; 9492215976Sjmallett uint64_t xscol : 4; 9493215976Sjmallett uint64_t xsdef : 4; 9494215976Sjmallett uint64_t late_col : 4; 9495215976Sjmallett uint64_t ptp_lost : 4; 9496232812Sjmallett uint64_t xchange : 1; 9497232812Sjmallett uint64_t reserved_25_63 : 39; 9498215976Sjmallett#endif 9499215976Sjmallett } s; 9500232812Sjmallett struct cvmx_gmxx_tx_int_en_cn30xx { 9501232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9502215976Sjmallett uint64_t reserved_19_63 : 45; 9503215976Sjmallett uint64_t late_col : 3; /**< TX Late Collision */ 9504215976Sjmallett uint64_t reserved_15_15 : 1; 9505215976Sjmallett uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9506215976Sjmallett uint64_t reserved_11_11 : 1; 9507215976Sjmallett uint64_t xscol : 3; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9508215976Sjmallett uint64_t reserved_5_7 : 3; 9509215976Sjmallett uint64_t undflw : 3; /**< TX Underflow (RGMII mode only) */ 9510215976Sjmallett uint64_t reserved_1_1 : 1; 9511215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9512215976Sjmallett#else 9513215976Sjmallett uint64_t pko_nxa : 1; 9514215976Sjmallett uint64_t reserved_1_1 : 1; 9515215976Sjmallett uint64_t undflw : 3; 9516215976Sjmallett uint64_t reserved_5_7 : 3; 9517215976Sjmallett uint64_t xscol : 3; 9518215976Sjmallett uint64_t reserved_11_11 : 1; 9519215976Sjmallett uint64_t xsdef : 3; 9520215976Sjmallett uint64_t reserved_15_15 : 1; 9521215976Sjmallett uint64_t late_col : 3; 9522215976Sjmallett uint64_t reserved_19_63 : 45; 9523215976Sjmallett#endif 9524215976Sjmallett } cn30xx; 9525232812Sjmallett struct cvmx_gmxx_tx_int_en_cn31xx { 9526232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9527215976Sjmallett uint64_t reserved_15_63 : 49; 9528215976Sjmallett uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9529215976Sjmallett uint64_t reserved_11_11 : 1; 9530215976Sjmallett uint64_t xscol : 3; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9531215976Sjmallett uint64_t reserved_5_7 : 3; 9532215976Sjmallett uint64_t undflw : 3; /**< TX Underflow (RGMII mode only) */ 9533215976Sjmallett uint64_t reserved_1_1 : 1; 9534215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9535215976Sjmallett#else 9536215976Sjmallett uint64_t pko_nxa : 1; 9537215976Sjmallett uint64_t reserved_1_1 : 1; 9538215976Sjmallett uint64_t undflw : 3; 9539215976Sjmallett uint64_t reserved_5_7 : 3; 9540215976Sjmallett uint64_t xscol : 3; 9541215976Sjmallett uint64_t reserved_11_11 : 1; 9542215976Sjmallett uint64_t xsdef : 3; 9543215976Sjmallett uint64_t reserved_15_63 : 49; 9544215976Sjmallett#endif 9545215976Sjmallett } cn31xx; 9546232812Sjmallett struct cvmx_gmxx_tx_int_en_cn38xx { 9547232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9548215976Sjmallett uint64_t reserved_20_63 : 44; 9549215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9550215976Sjmallett (PASS3 only) */ 9551215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9552215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9553215976Sjmallett uint64_t reserved_6_7 : 2; 9554215976Sjmallett uint64_t undflw : 4; /**< TX Underflow (RGMII mode only) */ 9555215976Sjmallett uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */ 9556215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9557215976Sjmallett#else 9558215976Sjmallett uint64_t pko_nxa : 1; 9559215976Sjmallett uint64_t ncb_nxa : 1; 9560215976Sjmallett uint64_t undflw : 4; 9561215976Sjmallett uint64_t reserved_6_7 : 2; 9562215976Sjmallett uint64_t xscol : 4; 9563215976Sjmallett uint64_t xsdef : 4; 9564215976Sjmallett uint64_t late_col : 4; 9565215976Sjmallett uint64_t reserved_20_63 : 44; 9566215976Sjmallett#endif 9567215976Sjmallett } cn38xx; 9568232812Sjmallett struct cvmx_gmxx_tx_int_en_cn38xxp2 { 9569232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9570215976Sjmallett uint64_t reserved_16_63 : 48; 9571215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9572215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9573215976Sjmallett uint64_t reserved_6_7 : 2; 9574215976Sjmallett uint64_t undflw : 4; /**< TX Underflow (RGMII mode only) */ 9575215976Sjmallett uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */ 9576215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9577215976Sjmallett#else 9578215976Sjmallett uint64_t pko_nxa : 1; 9579215976Sjmallett uint64_t ncb_nxa : 1; 9580215976Sjmallett uint64_t undflw : 4; 9581215976Sjmallett uint64_t reserved_6_7 : 2; 9582215976Sjmallett uint64_t xscol : 4; 9583215976Sjmallett uint64_t xsdef : 4; 9584215976Sjmallett uint64_t reserved_16_63 : 48; 9585215976Sjmallett#endif 9586215976Sjmallett } cn38xxp2; 9587215976Sjmallett struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; 9588232812Sjmallett struct cvmx_gmxx_tx_int_en_cn52xx { 9589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9590215976Sjmallett uint64_t reserved_20_63 : 44; 9591215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9592215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9593215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9594215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9595215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9596215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9597215976Sjmallett uint64_t reserved_6_7 : 2; 9598215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9599215976Sjmallett uint64_t reserved_1_1 : 1; 9600215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9601215976Sjmallett#else 9602215976Sjmallett uint64_t pko_nxa : 1; 9603215976Sjmallett uint64_t reserved_1_1 : 1; 9604215976Sjmallett uint64_t undflw : 4; 9605215976Sjmallett uint64_t reserved_6_7 : 2; 9606215976Sjmallett uint64_t xscol : 4; 9607215976Sjmallett uint64_t xsdef : 4; 9608215976Sjmallett uint64_t late_col : 4; 9609215976Sjmallett uint64_t reserved_20_63 : 44; 9610215976Sjmallett#endif 9611215976Sjmallett } cn52xx; 9612215976Sjmallett struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; 9613215976Sjmallett struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; 9614215976Sjmallett struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; 9615215976Sjmallett struct cvmx_gmxx_tx_int_en_cn38xx cn58xx; 9616215976Sjmallett struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1; 9617232812Sjmallett struct cvmx_gmxx_tx_int_en_s cn61xx; 9618232812Sjmallett struct cvmx_gmxx_tx_int_en_cn63xx { 9619232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9620215976Sjmallett uint64_t reserved_24_63 : 40; 9621215976Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9622215976Sjmallett sent due to XSCOL */ 9623215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9624215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9625215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9626215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9627215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9628215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9629215976Sjmallett uint64_t reserved_6_7 : 2; 9630215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9631215976Sjmallett uint64_t reserved_1_1 : 1; 9632215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9633215976Sjmallett#else 9634215976Sjmallett uint64_t pko_nxa : 1; 9635215976Sjmallett uint64_t reserved_1_1 : 1; 9636215976Sjmallett uint64_t undflw : 4; 9637215976Sjmallett uint64_t reserved_6_7 : 2; 9638215976Sjmallett uint64_t xscol : 4; 9639215976Sjmallett uint64_t xsdef : 4; 9640215976Sjmallett uint64_t late_col : 4; 9641215976Sjmallett uint64_t ptp_lost : 4; 9642215976Sjmallett uint64_t reserved_24_63 : 40; 9643215976Sjmallett#endif 9644215976Sjmallett } cn63xx; 9645215976Sjmallett struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1; 9646232812Sjmallett struct cvmx_gmxx_tx_int_en_s cn66xx; 9647232812Sjmallett struct cvmx_gmxx_tx_int_en_cn68xx { 9648232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9649232812Sjmallett uint64_t reserved_25_63 : 39; 9650232812Sjmallett uint64_t xchange : 1; /**< XAUI/RXAUI link status changed - this denotes a 9651232812Sjmallett change to GMX_RX_XAUI_CTL[STATUS] 9652232812Sjmallett (XAUI/RXAUI mode only) */ 9653232812Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9654232812Sjmallett sent due to XSCOL */ 9655232812Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9656232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9657232812Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9658232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9659232812Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9660232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9661232812Sjmallett uint64_t reserved_6_7 : 2; 9662232812Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9663232812Sjmallett uint64_t pko_nxp : 1; /**< Port pipe out-of-range from PKO Interface */ 9664232812Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9665232812Sjmallett#else 9666232812Sjmallett uint64_t pko_nxa : 1; 9667232812Sjmallett uint64_t pko_nxp : 1; 9668232812Sjmallett uint64_t undflw : 4; 9669232812Sjmallett uint64_t reserved_6_7 : 2; 9670232812Sjmallett uint64_t xscol : 4; 9671232812Sjmallett uint64_t xsdef : 4; 9672232812Sjmallett uint64_t late_col : 4; 9673232812Sjmallett uint64_t ptp_lost : 4; 9674232812Sjmallett uint64_t xchange : 1; 9675232812Sjmallett uint64_t reserved_25_63 : 39; 9676232812Sjmallett#endif 9677232812Sjmallett } cn68xx; 9678232812Sjmallett struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1; 9679232812Sjmallett struct cvmx_gmxx_tx_int_en_cnf71xx { 9680232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9681232812Sjmallett uint64_t reserved_25_63 : 39; 9682232812Sjmallett uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change 9683232812Sjmallett to GMX_RX_XAUI_CTL[STATUS] 9684232812Sjmallett (XAUI mode only) */ 9685232812Sjmallett uint64_t reserved_22_23 : 2; 9686232812Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 9687232812Sjmallett sent due to XSCOL */ 9688232812Sjmallett uint64_t reserved_18_19 : 2; 9689232812Sjmallett uint64_t late_col : 2; /**< TX Late Collision 9690232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9691232812Sjmallett uint64_t reserved_14_15 : 2; 9692232812Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral 9693232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9694232812Sjmallett uint64_t reserved_10_11 : 2; 9695232812Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions 9696232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9697232812Sjmallett uint64_t reserved_4_7 : 4; 9698232812Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 9699232812Sjmallett uint64_t reserved_1_1 : 1; 9700232812Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9701232812Sjmallett#else 9702232812Sjmallett uint64_t pko_nxa : 1; 9703232812Sjmallett uint64_t reserved_1_1 : 1; 9704232812Sjmallett uint64_t undflw : 2; 9705232812Sjmallett uint64_t reserved_4_7 : 4; 9706232812Sjmallett uint64_t xscol : 2; 9707232812Sjmallett uint64_t reserved_10_11 : 2; 9708232812Sjmallett uint64_t xsdef : 2; 9709232812Sjmallett uint64_t reserved_14_15 : 2; 9710232812Sjmallett uint64_t late_col : 2; 9711232812Sjmallett uint64_t reserved_18_19 : 2; 9712232812Sjmallett uint64_t ptp_lost : 2; 9713232812Sjmallett uint64_t reserved_22_23 : 2; 9714232812Sjmallett uint64_t xchange : 1; 9715232812Sjmallett uint64_t reserved_25_63 : 39; 9716232812Sjmallett#endif 9717232812Sjmallett } cnf71xx; 9718215976Sjmallett}; 9719215976Sjmalletttypedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t; 9720215976Sjmallett 9721215976Sjmallett/** 9722215976Sjmallett * cvmx_gmx#_tx_int_reg 9723215976Sjmallett * 9724215976Sjmallett * GMX_TX_INT_REG = Interrupt Register 9725215976Sjmallett * 9726215976Sjmallett * 9727215976Sjmallett * Notes: 9728215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used. 9729215976Sjmallett * 9730215976Sjmallett */ 9731232812Sjmallettunion cvmx_gmxx_tx_int_reg { 9732215976Sjmallett uint64_t u64; 9733232812Sjmallett struct cvmx_gmxx_tx_int_reg_s { 9734232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9735232812Sjmallett uint64_t reserved_25_63 : 39; 9736232812Sjmallett uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change 9737232812Sjmallett to GMX_RX_XAUI_CTL[STATUS] 9738232812Sjmallett (XAUI mode only) */ 9739215976Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9740215976Sjmallett sent due to XSCOL */ 9741215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9742215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9743215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9744215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9745215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9746215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9747215976Sjmallett uint64_t reserved_6_7 : 2; 9748215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9749232812Sjmallett uint64_t reserved_1_1 : 1; 9750215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9751215976Sjmallett#else 9752215976Sjmallett uint64_t pko_nxa : 1; 9753232812Sjmallett uint64_t reserved_1_1 : 1; 9754215976Sjmallett uint64_t undflw : 4; 9755215976Sjmallett uint64_t reserved_6_7 : 2; 9756215976Sjmallett uint64_t xscol : 4; 9757215976Sjmallett uint64_t xsdef : 4; 9758215976Sjmallett uint64_t late_col : 4; 9759215976Sjmallett uint64_t ptp_lost : 4; 9760232812Sjmallett uint64_t xchange : 1; 9761232812Sjmallett uint64_t reserved_25_63 : 39; 9762215976Sjmallett#endif 9763215976Sjmallett } s; 9764232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn30xx { 9765232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9766215976Sjmallett uint64_t reserved_19_63 : 45; 9767215976Sjmallett uint64_t late_col : 3; /**< TX Late Collision */ 9768215976Sjmallett uint64_t reserved_15_15 : 1; 9769215976Sjmallett uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9770215976Sjmallett uint64_t reserved_11_11 : 1; 9771215976Sjmallett uint64_t xscol : 3; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9772215976Sjmallett uint64_t reserved_5_7 : 3; 9773215976Sjmallett uint64_t undflw : 3; /**< TX Underflow (RGMII mode only) */ 9774215976Sjmallett uint64_t reserved_1_1 : 1; 9775215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9776215976Sjmallett#else 9777215976Sjmallett uint64_t pko_nxa : 1; 9778215976Sjmallett uint64_t reserved_1_1 : 1; 9779215976Sjmallett uint64_t undflw : 3; 9780215976Sjmallett uint64_t reserved_5_7 : 3; 9781215976Sjmallett uint64_t xscol : 3; 9782215976Sjmallett uint64_t reserved_11_11 : 1; 9783215976Sjmallett uint64_t xsdef : 3; 9784215976Sjmallett uint64_t reserved_15_15 : 1; 9785215976Sjmallett uint64_t late_col : 3; 9786215976Sjmallett uint64_t reserved_19_63 : 45; 9787215976Sjmallett#endif 9788215976Sjmallett } cn30xx; 9789232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn31xx { 9790232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9791215976Sjmallett uint64_t reserved_15_63 : 49; 9792215976Sjmallett uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9793215976Sjmallett uint64_t reserved_11_11 : 1; 9794215976Sjmallett uint64_t xscol : 3; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9795215976Sjmallett uint64_t reserved_5_7 : 3; 9796215976Sjmallett uint64_t undflw : 3; /**< TX Underflow (RGMII mode only) */ 9797215976Sjmallett uint64_t reserved_1_1 : 1; 9798215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9799215976Sjmallett#else 9800215976Sjmallett uint64_t pko_nxa : 1; 9801215976Sjmallett uint64_t reserved_1_1 : 1; 9802215976Sjmallett uint64_t undflw : 3; 9803215976Sjmallett uint64_t reserved_5_7 : 3; 9804215976Sjmallett uint64_t xscol : 3; 9805215976Sjmallett uint64_t reserved_11_11 : 1; 9806215976Sjmallett uint64_t xsdef : 3; 9807215976Sjmallett uint64_t reserved_15_63 : 49; 9808215976Sjmallett#endif 9809215976Sjmallett } cn31xx; 9810232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn38xx { 9811232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9812215976Sjmallett uint64_t reserved_20_63 : 44; 9813215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9814215976Sjmallett (PASS3 only) */ 9815215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9816215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9817215976Sjmallett uint64_t reserved_6_7 : 2; 9818215976Sjmallett uint64_t undflw : 4; /**< TX Underflow (RGMII mode only) */ 9819215976Sjmallett uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */ 9820215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9821215976Sjmallett#else 9822215976Sjmallett uint64_t pko_nxa : 1; 9823215976Sjmallett uint64_t ncb_nxa : 1; 9824215976Sjmallett uint64_t undflw : 4; 9825215976Sjmallett uint64_t reserved_6_7 : 2; 9826215976Sjmallett uint64_t xscol : 4; 9827215976Sjmallett uint64_t xsdef : 4; 9828215976Sjmallett uint64_t late_col : 4; 9829215976Sjmallett uint64_t reserved_20_63 : 44; 9830215976Sjmallett#endif 9831215976Sjmallett } cn38xx; 9832232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn38xxp2 { 9833232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9834215976Sjmallett uint64_t reserved_16_63 : 48; 9835215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */ 9836215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */ 9837215976Sjmallett uint64_t reserved_6_7 : 2; 9838215976Sjmallett uint64_t undflw : 4; /**< TX Underflow (RGMII mode only) */ 9839215976Sjmallett uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */ 9840215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9841215976Sjmallett#else 9842215976Sjmallett uint64_t pko_nxa : 1; 9843215976Sjmallett uint64_t ncb_nxa : 1; 9844215976Sjmallett uint64_t undflw : 4; 9845215976Sjmallett uint64_t reserved_6_7 : 2; 9846215976Sjmallett uint64_t xscol : 4; 9847215976Sjmallett uint64_t xsdef : 4; 9848215976Sjmallett uint64_t reserved_16_63 : 48; 9849215976Sjmallett#endif 9850215976Sjmallett } cn38xxp2; 9851215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; 9852232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn52xx { 9853232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9854215976Sjmallett uint64_t reserved_20_63 : 44; 9855215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9856215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9857215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9858215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9859215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9860215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9861215976Sjmallett uint64_t reserved_6_7 : 2; 9862215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9863215976Sjmallett uint64_t reserved_1_1 : 1; 9864215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9865215976Sjmallett#else 9866215976Sjmallett uint64_t pko_nxa : 1; 9867215976Sjmallett uint64_t reserved_1_1 : 1; 9868215976Sjmallett uint64_t undflw : 4; 9869215976Sjmallett uint64_t reserved_6_7 : 2; 9870215976Sjmallett uint64_t xscol : 4; 9871215976Sjmallett uint64_t xsdef : 4; 9872215976Sjmallett uint64_t late_col : 4; 9873215976Sjmallett uint64_t reserved_20_63 : 44; 9874215976Sjmallett#endif 9875215976Sjmallett } cn52xx; 9876215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; 9877215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; 9878215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; 9879215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx; 9880215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1; 9881232812Sjmallett struct cvmx_gmxx_tx_int_reg_s cn61xx; 9882232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn63xx { 9883232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9884215976Sjmallett uint64_t reserved_24_63 : 40; 9885215976Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9886215976Sjmallett sent due to XSCOL */ 9887215976Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9888215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9889215976Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9890215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9891215976Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9892215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9893215976Sjmallett uint64_t reserved_6_7 : 2; 9894215976Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9895215976Sjmallett uint64_t reserved_1_1 : 1; 9896215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9897215976Sjmallett#else 9898215976Sjmallett uint64_t pko_nxa : 1; 9899215976Sjmallett uint64_t reserved_1_1 : 1; 9900215976Sjmallett uint64_t undflw : 4; 9901215976Sjmallett uint64_t reserved_6_7 : 2; 9902215976Sjmallett uint64_t xscol : 4; 9903215976Sjmallett uint64_t xsdef : 4; 9904215976Sjmallett uint64_t late_col : 4; 9905215976Sjmallett uint64_t ptp_lost : 4; 9906215976Sjmallett uint64_t reserved_24_63 : 40; 9907215976Sjmallett#endif 9908215976Sjmallett } cn63xx; 9909215976Sjmallett struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1; 9910232812Sjmallett struct cvmx_gmxx_tx_int_reg_s cn66xx; 9911232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn68xx { 9912232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9913232812Sjmallett uint64_t reserved_25_63 : 39; 9914232812Sjmallett uint64_t xchange : 1; /**< XAUI/RXAUI link status changed - this denotes ae 9915232812Sjmallett change to GMX_RX_XAUI_CTL[STATUS] 9916232812Sjmallett (XAUI/RXAUI mode only) */ 9917232812Sjmallett uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be 9918232812Sjmallett sent due to XSCOL */ 9919232812Sjmallett uint64_t late_col : 4; /**< TX Late Collision 9920232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9921232812Sjmallett uint64_t xsdef : 4; /**< TX Excessive deferral 9922232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9923232812Sjmallett uint64_t xscol : 4; /**< TX Excessive collisions 9924232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9925232812Sjmallett uint64_t reserved_6_7 : 2; 9926232812Sjmallett uint64_t undflw : 4; /**< TX Underflow */ 9927232812Sjmallett uint64_t pko_nxp : 1; /**< Port pipe out-of-range from PKO Interface */ 9928232812Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9929232812Sjmallett#else 9930232812Sjmallett uint64_t pko_nxa : 1; 9931232812Sjmallett uint64_t pko_nxp : 1; 9932232812Sjmallett uint64_t undflw : 4; 9933232812Sjmallett uint64_t reserved_6_7 : 2; 9934232812Sjmallett uint64_t xscol : 4; 9935232812Sjmallett uint64_t xsdef : 4; 9936232812Sjmallett uint64_t late_col : 4; 9937232812Sjmallett uint64_t ptp_lost : 4; 9938232812Sjmallett uint64_t xchange : 1; 9939232812Sjmallett uint64_t reserved_25_63 : 39; 9940232812Sjmallett#endif 9941232812Sjmallett } cn68xx; 9942232812Sjmallett struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1; 9943232812Sjmallett struct cvmx_gmxx_tx_int_reg_cnf71xx { 9944232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9945232812Sjmallett uint64_t reserved_25_63 : 39; 9946232812Sjmallett uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change 9947232812Sjmallett to GMX_RX_XAUI_CTL[STATUS] 9948232812Sjmallett (XAUI mode only) */ 9949232812Sjmallett uint64_t reserved_22_23 : 2; 9950232812Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 9951232812Sjmallett sent due to XSCOL */ 9952232812Sjmallett uint64_t reserved_18_19 : 2; 9953232812Sjmallett uint64_t late_col : 2; /**< TX Late Collision 9954232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9955232812Sjmallett uint64_t reserved_14_15 : 2; 9956232812Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral 9957232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9958232812Sjmallett uint64_t reserved_10_11 : 2; 9959232812Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions 9960232812Sjmallett (SGMII/1000Base-X half-duplex only) */ 9961232812Sjmallett uint64_t reserved_4_7 : 4; 9962232812Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 9963232812Sjmallett uint64_t reserved_1_1 : 1; 9964232812Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 9965232812Sjmallett#else 9966232812Sjmallett uint64_t pko_nxa : 1; 9967232812Sjmallett uint64_t reserved_1_1 : 1; 9968232812Sjmallett uint64_t undflw : 2; 9969232812Sjmallett uint64_t reserved_4_7 : 4; 9970232812Sjmallett uint64_t xscol : 2; 9971232812Sjmallett uint64_t reserved_10_11 : 2; 9972232812Sjmallett uint64_t xsdef : 2; 9973232812Sjmallett uint64_t reserved_14_15 : 2; 9974232812Sjmallett uint64_t late_col : 2; 9975232812Sjmallett uint64_t reserved_18_19 : 2; 9976232812Sjmallett uint64_t ptp_lost : 2; 9977232812Sjmallett uint64_t reserved_22_23 : 2; 9978232812Sjmallett uint64_t xchange : 1; 9979232812Sjmallett uint64_t reserved_25_63 : 39; 9980232812Sjmallett#endif 9981232812Sjmallett } cnf71xx; 9982215976Sjmallett}; 9983215976Sjmalletttypedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t; 9984215976Sjmallett 9985215976Sjmallett/** 9986215976Sjmallett * cvmx_gmx#_tx_jam 9987215976Sjmallett * 9988215976Sjmallett * GMX_TX_JAM = Packet TX Jam Pattern 9989215976Sjmallett * 9990215976Sjmallett */ 9991232812Sjmallettunion cvmx_gmxx_tx_jam { 9992215976Sjmallett uint64_t u64; 9993232812Sjmallett struct cvmx_gmxx_tx_jam_s { 9994232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9995215976Sjmallett uint64_t reserved_8_63 : 56; 9996215976Sjmallett uint64_t jam : 8; /**< Jam pattern 9997215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 9998215976Sjmallett#else 9999215976Sjmallett uint64_t jam : 8; 10000215976Sjmallett uint64_t reserved_8_63 : 56; 10001215976Sjmallett#endif 10002215976Sjmallett } s; 10003215976Sjmallett struct cvmx_gmxx_tx_jam_s cn30xx; 10004215976Sjmallett struct cvmx_gmxx_tx_jam_s cn31xx; 10005215976Sjmallett struct cvmx_gmxx_tx_jam_s cn38xx; 10006215976Sjmallett struct cvmx_gmxx_tx_jam_s cn38xxp2; 10007215976Sjmallett struct cvmx_gmxx_tx_jam_s cn50xx; 10008215976Sjmallett struct cvmx_gmxx_tx_jam_s cn52xx; 10009215976Sjmallett struct cvmx_gmxx_tx_jam_s cn52xxp1; 10010215976Sjmallett struct cvmx_gmxx_tx_jam_s cn56xx; 10011215976Sjmallett struct cvmx_gmxx_tx_jam_s cn56xxp1; 10012215976Sjmallett struct cvmx_gmxx_tx_jam_s cn58xx; 10013215976Sjmallett struct cvmx_gmxx_tx_jam_s cn58xxp1; 10014232812Sjmallett struct cvmx_gmxx_tx_jam_s cn61xx; 10015215976Sjmallett struct cvmx_gmxx_tx_jam_s cn63xx; 10016215976Sjmallett struct cvmx_gmxx_tx_jam_s cn63xxp1; 10017232812Sjmallett struct cvmx_gmxx_tx_jam_s cn66xx; 10018232812Sjmallett struct cvmx_gmxx_tx_jam_s cn68xx; 10019232812Sjmallett struct cvmx_gmxx_tx_jam_s cn68xxp1; 10020232812Sjmallett struct cvmx_gmxx_tx_jam_s cnf71xx; 10021215976Sjmallett}; 10022215976Sjmalletttypedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t; 10023215976Sjmallett 10024215976Sjmallett/** 10025215976Sjmallett * cvmx_gmx#_tx_lfsr 10026215976Sjmallett * 10027215976Sjmallett * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff 10028215976Sjmallett * 10029215976Sjmallett */ 10030232812Sjmallettunion cvmx_gmxx_tx_lfsr { 10031215976Sjmallett uint64_t u64; 10032232812Sjmallett struct cvmx_gmxx_tx_lfsr_s { 10033232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10034215976Sjmallett uint64_t reserved_16_63 : 48; 10035215976Sjmallett uint64_t lfsr : 16; /**< The current state of the LFSR used to feed random 10036215976Sjmallett numbers to compute truncated binary exponential 10037215976Sjmallett backoff. 10038215976Sjmallett (SGMII/1000Base-X half-duplex only) */ 10039215976Sjmallett#else 10040215976Sjmallett uint64_t lfsr : 16; 10041215976Sjmallett uint64_t reserved_16_63 : 48; 10042215976Sjmallett#endif 10043215976Sjmallett } s; 10044215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn30xx; 10045215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn31xx; 10046215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn38xx; 10047215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn38xxp2; 10048215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn50xx; 10049215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn52xx; 10050215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn52xxp1; 10051215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn56xx; 10052215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn56xxp1; 10053215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn58xx; 10054215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn58xxp1; 10055232812Sjmallett struct cvmx_gmxx_tx_lfsr_s cn61xx; 10056215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn63xx; 10057215976Sjmallett struct cvmx_gmxx_tx_lfsr_s cn63xxp1; 10058232812Sjmallett struct cvmx_gmxx_tx_lfsr_s cn66xx; 10059232812Sjmallett struct cvmx_gmxx_tx_lfsr_s cn68xx; 10060232812Sjmallett struct cvmx_gmxx_tx_lfsr_s cn68xxp1; 10061232812Sjmallett struct cvmx_gmxx_tx_lfsr_s cnf71xx; 10062215976Sjmallett}; 10063215976Sjmalletttypedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t; 10064215976Sjmallett 10065215976Sjmallett/** 10066215976Sjmallett * cvmx_gmx#_tx_ovr_bp 10067215976Sjmallett * 10068215976Sjmallett * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure 10069215976Sjmallett * 10070215976Sjmallett * 10071215976Sjmallett * Notes: 10072215976Sjmallett * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used. 10073215976Sjmallett * 10074215976Sjmallett * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero 10075215976Sjmallett * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol 10076215976Sjmallett * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by 10077215976Sjmallett * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure 10078215976Sjmallett * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2 10079215976Sjmallett * protocol. 10080215976Sjmallett */ 10081232812Sjmallettunion cvmx_gmxx_tx_ovr_bp { 10082215976Sjmallett uint64_t u64; 10083232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_s { 10084232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10085215976Sjmallett uint64_t reserved_48_63 : 16; 10086215976Sjmallett uint64_t tx_prt_bp : 16; /**< Per port BP sent to PKO 10087215976Sjmallett 0=Port is available 10088215976Sjmallett 1=Port should be back pressured 10089215976Sjmallett TX_PRT_BP should not be set until 10090215976Sjmallett GMX_INF_MODE[EN] has been enabled */ 10091215976Sjmallett uint64_t reserved_12_31 : 20; 10092215976Sjmallett uint64_t en : 4; /**< Per port Enable back pressure override */ 10093215976Sjmallett uint64_t bp : 4; /**< Per port BackPressure status to use 10094215976Sjmallett 0=Port is available 10095215976Sjmallett 1=Port should be back pressured */ 10096215976Sjmallett uint64_t ign_full : 4; /**< Ignore the RX FIFO full when computing BP */ 10097215976Sjmallett#else 10098215976Sjmallett uint64_t ign_full : 4; 10099215976Sjmallett uint64_t bp : 4; 10100215976Sjmallett uint64_t en : 4; 10101215976Sjmallett uint64_t reserved_12_31 : 20; 10102215976Sjmallett uint64_t tx_prt_bp : 16; 10103215976Sjmallett uint64_t reserved_48_63 : 16; 10104215976Sjmallett#endif 10105215976Sjmallett } s; 10106232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn30xx { 10107232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10108215976Sjmallett uint64_t reserved_11_63 : 53; 10109215976Sjmallett uint64_t en : 3; /**< Per port Enable back pressure override */ 10110215976Sjmallett uint64_t reserved_7_7 : 1; 10111215976Sjmallett uint64_t bp : 3; /**< Per port BackPressure status to use 10112215976Sjmallett 0=Port is available 10113215976Sjmallett 1=Port should be back pressured */ 10114215976Sjmallett uint64_t reserved_3_3 : 1; 10115215976Sjmallett uint64_t ign_full : 3; /**< Ignore the RX FIFO full when computing BP */ 10116215976Sjmallett#else 10117215976Sjmallett uint64_t ign_full : 3; 10118215976Sjmallett uint64_t reserved_3_3 : 1; 10119215976Sjmallett uint64_t bp : 3; 10120215976Sjmallett uint64_t reserved_7_7 : 1; 10121215976Sjmallett uint64_t en : 3; 10122215976Sjmallett uint64_t reserved_11_63 : 53; 10123215976Sjmallett#endif 10124215976Sjmallett } cn30xx; 10125215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; 10126232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn38xx { 10127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10128215976Sjmallett uint64_t reserved_12_63 : 52; 10129215976Sjmallett uint64_t en : 4; /**< Per port Enable back pressure override */ 10130215976Sjmallett uint64_t bp : 4; /**< Per port BackPressure status to use 10131215976Sjmallett 0=Port is available 10132215976Sjmallett 1=Port should be back pressured */ 10133215976Sjmallett uint64_t ign_full : 4; /**< Ignore the RX FIFO full when computing BP */ 10134215976Sjmallett#else 10135215976Sjmallett uint64_t ign_full : 4; 10136215976Sjmallett uint64_t bp : 4; 10137215976Sjmallett uint64_t en : 4; 10138215976Sjmallett uint64_t reserved_12_63 : 52; 10139215976Sjmallett#endif 10140215976Sjmallett } cn38xx; 10141215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; 10142215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; 10143215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn52xx; 10144215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; 10145215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn56xx; 10146215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; 10147215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; 10148215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; 10149232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn61xx; 10150215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn63xx; 10151215976Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1; 10152232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn66xx; 10153232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn68xx; 10154232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1; 10155232812Sjmallett struct cvmx_gmxx_tx_ovr_bp_cnf71xx { 10156232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10157232812Sjmallett uint64_t reserved_48_63 : 16; 10158232812Sjmallett uint64_t tx_prt_bp : 16; /**< Per port BP sent to PKO 10159232812Sjmallett 0=Port is available 10160232812Sjmallett 1=Port should be back pressured 10161232812Sjmallett TX_PRT_BP should not be set until 10162232812Sjmallett GMX_INF_MODE[EN] has been enabled */ 10163232812Sjmallett uint64_t reserved_10_31 : 22; 10164232812Sjmallett uint64_t en : 2; /**< Per port Enable back pressure override */ 10165232812Sjmallett uint64_t reserved_6_7 : 2; 10166232812Sjmallett uint64_t bp : 2; /**< Per port BackPressure status to use 10167232812Sjmallett 0=Port is available 10168232812Sjmallett 1=Port should be back pressured */ 10169232812Sjmallett uint64_t reserved_2_3 : 2; 10170232812Sjmallett uint64_t ign_full : 2; /**< Ignore the RX FIFO full when computing BP */ 10171232812Sjmallett#else 10172232812Sjmallett uint64_t ign_full : 2; 10173232812Sjmallett uint64_t reserved_2_3 : 2; 10174232812Sjmallett uint64_t bp : 2; 10175232812Sjmallett uint64_t reserved_6_7 : 2; 10176232812Sjmallett uint64_t en : 2; 10177232812Sjmallett uint64_t reserved_10_31 : 22; 10178232812Sjmallett uint64_t tx_prt_bp : 16; 10179232812Sjmallett uint64_t reserved_48_63 : 16; 10180232812Sjmallett#endif 10181232812Sjmallett } cnf71xx; 10182215976Sjmallett}; 10183215976Sjmalletttypedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t; 10184215976Sjmallett 10185215976Sjmallett/** 10186215976Sjmallett * cvmx_gmx#_tx_pause_pkt_dmac 10187215976Sjmallett * 10188215976Sjmallett * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field 10189215976Sjmallett * 10190215976Sjmallett */ 10191232812Sjmallettunion cvmx_gmxx_tx_pause_pkt_dmac { 10192215976Sjmallett uint64_t u64; 10193232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s { 10194232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10195215976Sjmallett uint64_t reserved_48_63 : 16; 10196215976Sjmallett uint64_t dmac : 48; /**< The DMAC field placed is outbnd pause pkts */ 10197215976Sjmallett#else 10198215976Sjmallett uint64_t dmac : 48; 10199215976Sjmallett uint64_t reserved_48_63 : 16; 10200215976Sjmallett#endif 10201215976Sjmallett } s; 10202215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; 10203215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; 10204215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; 10205215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; 10206215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; 10207215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; 10208215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; 10209215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; 10210215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; 10211215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; 10212215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; 10213232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx; 10214215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx; 10215215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1; 10216232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx; 10217232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx; 10218232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1; 10219232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx; 10220215976Sjmallett}; 10221215976Sjmalletttypedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t; 10222215976Sjmallett 10223215976Sjmallett/** 10224215976Sjmallett * cvmx_gmx#_tx_pause_pkt_type 10225215976Sjmallett * 10226215976Sjmallett * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field 10227215976Sjmallett * 10228215976Sjmallett */ 10229232812Sjmallettunion cvmx_gmxx_tx_pause_pkt_type { 10230215976Sjmallett uint64_t u64; 10231232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s { 10232232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10233215976Sjmallett uint64_t reserved_16_63 : 48; 10234215976Sjmallett uint64_t type : 16; /**< The TYPE field placed is outbnd pause pkts */ 10235215976Sjmallett#else 10236215976Sjmallett uint64_t type : 16; 10237215976Sjmallett uint64_t reserved_16_63 : 48; 10238215976Sjmallett#endif 10239215976Sjmallett } s; 10240215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; 10241215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; 10242215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; 10243215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; 10244215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; 10245215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; 10246215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; 10247215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; 10248215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; 10249215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; 10250215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; 10251232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx; 10252215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx; 10253215976Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1; 10254232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx; 10255232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx; 10256232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1; 10257232812Sjmallett struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx; 10258215976Sjmallett}; 10259215976Sjmalletttypedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t; 10260215976Sjmallett 10261215976Sjmallett/** 10262215976Sjmallett * cvmx_gmx#_tx_prts 10263215976Sjmallett * 10264215976Sjmallett * Common 10265215976Sjmallett * 10266215976Sjmallett * 10267215976Sjmallett * GMX_TX_PRTS = TX Ports 10268215976Sjmallett * 10269215976Sjmallett * Notes: 10270215976Sjmallett * * The value programmed for PRTS is the number of the highest architected 10271215976Sjmallett * port number on the interface, plus 1. For example, if port 2 is the 10272215976Sjmallett * highest architected port, then the programmed value should be 3 since 10273215976Sjmallett * there are 3 ports in the system - 0, 1, and 2. 10274215976Sjmallett */ 10275232812Sjmallettunion cvmx_gmxx_tx_prts { 10276215976Sjmallett uint64_t u64; 10277232812Sjmallett struct cvmx_gmxx_tx_prts_s { 10278232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10279215976Sjmallett uint64_t reserved_5_63 : 59; 10280215976Sjmallett uint64_t prts : 5; /**< Number of ports allowed on the interface 10281215976Sjmallett (SGMII/1000Base-X only) */ 10282215976Sjmallett#else 10283215976Sjmallett uint64_t prts : 5; 10284215976Sjmallett uint64_t reserved_5_63 : 59; 10285215976Sjmallett#endif 10286215976Sjmallett } s; 10287215976Sjmallett struct cvmx_gmxx_tx_prts_s cn30xx; 10288215976Sjmallett struct cvmx_gmxx_tx_prts_s cn31xx; 10289215976Sjmallett struct cvmx_gmxx_tx_prts_s cn38xx; 10290215976Sjmallett struct cvmx_gmxx_tx_prts_s cn38xxp2; 10291215976Sjmallett struct cvmx_gmxx_tx_prts_s cn50xx; 10292215976Sjmallett struct cvmx_gmxx_tx_prts_s cn52xx; 10293215976Sjmallett struct cvmx_gmxx_tx_prts_s cn52xxp1; 10294215976Sjmallett struct cvmx_gmxx_tx_prts_s cn56xx; 10295215976Sjmallett struct cvmx_gmxx_tx_prts_s cn56xxp1; 10296215976Sjmallett struct cvmx_gmxx_tx_prts_s cn58xx; 10297215976Sjmallett struct cvmx_gmxx_tx_prts_s cn58xxp1; 10298232812Sjmallett struct cvmx_gmxx_tx_prts_s cn61xx; 10299215976Sjmallett struct cvmx_gmxx_tx_prts_s cn63xx; 10300215976Sjmallett struct cvmx_gmxx_tx_prts_s cn63xxp1; 10301232812Sjmallett struct cvmx_gmxx_tx_prts_s cn66xx; 10302232812Sjmallett struct cvmx_gmxx_tx_prts_s cn68xx; 10303232812Sjmallett struct cvmx_gmxx_tx_prts_s cn68xxp1; 10304232812Sjmallett struct cvmx_gmxx_tx_prts_s cnf71xx; 10305215976Sjmallett}; 10306215976Sjmalletttypedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t; 10307215976Sjmallett 10308215976Sjmallett/** 10309215976Sjmallett * cvmx_gmx#_tx_spi_ctl 10310215976Sjmallett * 10311215976Sjmallett * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4 10312215976Sjmallett * 10313215976Sjmallett */ 10314232812Sjmallettunion cvmx_gmxx_tx_spi_ctl { 10315215976Sjmallett uint64_t u64; 10316232812Sjmallett struct cvmx_gmxx_tx_spi_ctl_s { 10317232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10318215976Sjmallett uint64_t reserved_2_63 : 62; 10319215976Sjmallett uint64_t tpa_clr : 1; /**< TPA Clear Mode 10320215976Sjmallett Clear credit counter when satisifed status */ 10321215976Sjmallett uint64_t cont_pkt : 1; /**< Contiguous Packet Mode 10322215976Sjmallett Finish one packet before switching to another 10323215976Sjmallett Cannot be set in Spi4 pass-through mode */ 10324215976Sjmallett#else 10325215976Sjmallett uint64_t cont_pkt : 1; 10326215976Sjmallett uint64_t tpa_clr : 1; 10327215976Sjmallett uint64_t reserved_2_63 : 62; 10328215976Sjmallett#endif 10329215976Sjmallett } s; 10330215976Sjmallett struct cvmx_gmxx_tx_spi_ctl_s cn38xx; 10331215976Sjmallett struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; 10332215976Sjmallett struct cvmx_gmxx_tx_spi_ctl_s cn58xx; 10333215976Sjmallett struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; 10334215976Sjmallett}; 10335215976Sjmalletttypedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t; 10336215976Sjmallett 10337215976Sjmallett/** 10338215976Sjmallett * cvmx_gmx#_tx_spi_drain 10339215976Sjmallett * 10340215976Sjmallett * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO 10341215976Sjmallett * 10342215976Sjmallett */ 10343232812Sjmallettunion cvmx_gmxx_tx_spi_drain { 10344215976Sjmallett uint64_t u64; 10345232812Sjmallett struct cvmx_gmxx_tx_spi_drain_s { 10346232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10347215976Sjmallett uint64_t reserved_16_63 : 48; 10348215976Sjmallett uint64_t drain : 16; /**< Per port drain control 10349215976Sjmallett 0=Normal operation 10350215976Sjmallett 1=GMX TX will be popped, but no valid data will 10351215976Sjmallett be sent to SPX. Credits are correctly returned 10352215976Sjmallett to PKO. STX_IGN_CAL should be set to ignore 10353215976Sjmallett TPA and not stall due to back-pressure. 10354215976Sjmallett (PASS3 only) */ 10355215976Sjmallett#else 10356215976Sjmallett uint64_t drain : 16; 10357215976Sjmallett uint64_t reserved_16_63 : 48; 10358215976Sjmallett#endif 10359215976Sjmallett } s; 10360215976Sjmallett struct cvmx_gmxx_tx_spi_drain_s cn38xx; 10361215976Sjmallett struct cvmx_gmxx_tx_spi_drain_s cn58xx; 10362215976Sjmallett struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; 10363215976Sjmallett}; 10364215976Sjmalletttypedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t; 10365215976Sjmallett 10366215976Sjmallett/** 10367215976Sjmallett * cvmx_gmx#_tx_spi_max 10368215976Sjmallett * 10369215976Sjmallett * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX 10370215976Sjmallett * 10371215976Sjmallett */ 10372232812Sjmallettunion cvmx_gmxx_tx_spi_max { 10373215976Sjmallett uint64_t u64; 10374232812Sjmallett struct cvmx_gmxx_tx_spi_max_s { 10375232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10376215976Sjmallett uint64_t reserved_23_63 : 41; 10377215976Sjmallett uint64_t slice : 7; /**< Number of 16B blocks to transmit in a burst before 10378215976Sjmallett switching to the next port. SLICE does not always 10379215976Sjmallett limit the burst length transmitted by OCTEON. 10380215976Sjmallett Depending on the traffic pattern and 10381215976Sjmallett GMX_TX_SPI_ROUND programming, the next port could 10382215976Sjmallett be the same as the current port. In this case, 10383215976Sjmallett OCTEON may merge multiple sub-SLICE bursts into 10384215976Sjmallett one contiguous burst that is longer than SLICE 10385215976Sjmallett (as long as the burst does not cross a packet 10386215976Sjmallett boundary). 10387215976Sjmallett SLICE must be programmed to be >= 10388215976Sjmallett GMX_TX_SPI_THRESH[THRESH] 10389215976Sjmallett If SLICE==0, then the transmitter will tend to 10390215976Sjmallett send the complete packet. The port will only 10391215976Sjmallett switch if credits are exhausted or PKO cannot 10392215976Sjmallett keep up. 10393215976Sjmallett (90nm ONLY) */ 10394215976Sjmallett uint64_t max2 : 8; /**< MAX2 (per Spi4.2 spec) */ 10395215976Sjmallett uint64_t max1 : 8; /**< MAX1 (per Spi4.2 spec) 10396215976Sjmallett MAX1 >= GMX_TX_SPI_THRESH[THRESH] */ 10397215976Sjmallett#else 10398215976Sjmallett uint64_t max1 : 8; 10399215976Sjmallett uint64_t max2 : 8; 10400215976Sjmallett uint64_t slice : 7; 10401215976Sjmallett uint64_t reserved_23_63 : 41; 10402215976Sjmallett#endif 10403215976Sjmallett } s; 10404232812Sjmallett struct cvmx_gmxx_tx_spi_max_cn38xx { 10405232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10406215976Sjmallett uint64_t reserved_16_63 : 48; 10407215976Sjmallett uint64_t max2 : 8; /**< MAX2 (per Spi4.2 spec) */ 10408215976Sjmallett uint64_t max1 : 8; /**< MAX1 (per Spi4.2 spec) 10409215976Sjmallett MAX1 >= GMX_TX_SPI_THRESH[THRESH] */ 10410215976Sjmallett#else 10411215976Sjmallett uint64_t max1 : 8; 10412215976Sjmallett uint64_t max2 : 8; 10413215976Sjmallett uint64_t reserved_16_63 : 48; 10414215976Sjmallett#endif 10415215976Sjmallett } cn38xx; 10416215976Sjmallett struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; 10417215976Sjmallett struct cvmx_gmxx_tx_spi_max_s cn58xx; 10418215976Sjmallett struct cvmx_gmxx_tx_spi_max_s cn58xxp1; 10419215976Sjmallett}; 10420215976Sjmalletttypedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t; 10421215976Sjmallett 10422215976Sjmallett/** 10423215976Sjmallett * cvmx_gmx#_tx_spi_round# 10424215976Sjmallett * 10425215976Sjmallett * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration 10426215976Sjmallett * 10427215976Sjmallett */ 10428232812Sjmallettunion cvmx_gmxx_tx_spi_roundx { 10429215976Sjmallett uint64_t u64; 10430232812Sjmallett struct cvmx_gmxx_tx_spi_roundx_s { 10431232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10432215976Sjmallett uint64_t reserved_16_63 : 48; 10433215976Sjmallett uint64_t round : 16; /**< Which Spi ports participate in each arbitration 10434215976Sjmallett round. Each bit corresponds to a spi port 10435215976Sjmallett - 0: this port will arb in this round 10436215976Sjmallett - 1: this port will not arb in this round 10437215976Sjmallett (90nm ONLY) */ 10438215976Sjmallett#else 10439215976Sjmallett uint64_t round : 16; 10440215976Sjmallett uint64_t reserved_16_63 : 48; 10441215976Sjmallett#endif 10442215976Sjmallett } s; 10443215976Sjmallett struct cvmx_gmxx_tx_spi_roundx_s cn58xx; 10444215976Sjmallett struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; 10445215976Sjmallett}; 10446215976Sjmalletttypedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t; 10447215976Sjmallett 10448215976Sjmallett/** 10449215976Sjmallett * cvmx_gmx#_tx_spi_thresh 10450215976Sjmallett * 10451215976Sjmallett * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold 10452215976Sjmallett * 10453215976Sjmallett * 10454215976Sjmallett * Notes: 10455215976Sjmallett * Note: zero will map to 0x20 10456215976Sjmallett * 10457215976Sjmallett * This will normally creates Spi4 traffic bursts at least THRESH in length. 10458215976Sjmallett * If dclk > eclk, then this rule may not always hold and Octeon may split 10459215976Sjmallett * transfers into smaller bursts - some of which could be as short as 16B. 10460215976Sjmallett * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is 10461215976Sjmallett * not a multiple of 16B. 10462215976Sjmallett */ 10463232812Sjmallettunion cvmx_gmxx_tx_spi_thresh { 10464215976Sjmallett uint64_t u64; 10465232812Sjmallett struct cvmx_gmxx_tx_spi_thresh_s { 10466232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10467215976Sjmallett uint64_t reserved_6_63 : 58; 10468215976Sjmallett uint64_t thresh : 6; /**< Transmit threshold in 16B blocks - cannot be zero 10469215976Sjmallett THRESH <= TX_FIFO size (in non-passthrough mode) 10470215976Sjmallett THRESH <= TX_FIFO size-2 (in passthrough mode) 10471215976Sjmallett THRESH <= GMX_TX_SPI_MAX[MAX1] 10472215976Sjmallett THRESH <= GMX_TX_SPI_MAX[MAX2], if not then is it 10473215976Sjmallett possible for Octeon to send a Spi4 data burst of 10474215976Sjmallett MAX2 <= burst <= THRESH 16B ticks 10475215976Sjmallett GMX_TX_SPI_MAX[SLICE] must be programmed to be >= 10476215976Sjmallett THRESH */ 10477215976Sjmallett#else 10478215976Sjmallett uint64_t thresh : 6; 10479215976Sjmallett uint64_t reserved_6_63 : 58; 10480215976Sjmallett#endif 10481215976Sjmallett } s; 10482215976Sjmallett struct cvmx_gmxx_tx_spi_thresh_s cn38xx; 10483215976Sjmallett struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; 10484215976Sjmallett struct cvmx_gmxx_tx_spi_thresh_s cn58xx; 10485215976Sjmallett struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; 10486215976Sjmallett}; 10487215976Sjmalletttypedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t; 10488215976Sjmallett 10489215976Sjmallett/** 10490215976Sjmallett * cvmx_gmx#_tx_xaui_ctl 10491215976Sjmallett */ 10492232812Sjmallettunion cvmx_gmxx_tx_xaui_ctl { 10493215976Sjmallett uint64_t u64; 10494232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s { 10495232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10496215976Sjmallett uint64_t reserved_11_63 : 53; 10497215976Sjmallett uint64_t hg_pause_hgi : 2; /**< HGI Field for HW generated HiGig pause packets 10498215976Sjmallett (XAUI mode only) */ 10499215976Sjmallett uint64_t hg_en : 1; /**< Enable HiGig Mode 10500215976Sjmallett When HG_EN is set and GMX_RX_UDD_SKP[SKIP]=12 10501215976Sjmallett the interface is in HiGig/HiGig+ mode and the 10502215976Sjmallett following must be set: 10503215976Sjmallett GMX_RX_FRM_CTL[PRE_CHK] == 0 10504215976Sjmallett GMX_RX_UDD_SKP[FCSSEL] == 0 10505215976Sjmallett GMX_RX_UDD_SKP[SKIP] == 12 10506215976Sjmallett GMX_TX_APPEND[PREAMBLE] == 0 10507215976Sjmallett When HG_EN is set and GMX_RX_UDD_SKP[SKIP]=16 10508215976Sjmallett the interface is in HiGig2 mode and the 10509215976Sjmallett following must be set: 10510215976Sjmallett GMX_RX_FRM_CTL[PRE_CHK] == 0 10511215976Sjmallett GMX_RX_UDD_SKP[FCSSEL] == 0 10512215976Sjmallett GMX_RX_UDD_SKP[SKIP] == 16 10513215976Sjmallett GMX_TX_APPEND[PREAMBLE] == 0 10514215976Sjmallett GMX_PRT0_CBFC_CTL[RX_EN] == 0 10515215976Sjmallett GMX_PRT0_CBFC_CTL[TX_EN] == 0 10516215976Sjmallett (XAUI mode only) */ 10517215976Sjmallett uint64_t reserved_7_7 : 1; 10518215976Sjmallett uint64_t ls_byp : 1; /**< Bypass the link status as determined by the XGMII 10519215976Sjmallett receiver and set the link status of the 10520215976Sjmallett transmitter to LS. 10521215976Sjmallett (XAUI mode only) */ 10522215976Sjmallett uint64_t ls : 2; /**< Link Status 10523215976Sjmallett 0 = Link Ok 10524215976Sjmallett Link runs normally. RS passes MAC data to PCS 10525215976Sjmallett 1 = Local Fault 10526215976Sjmallett RS layer sends continuous remote fault 10527215976Sjmallett sequences. 10528215976Sjmallett 2 = Remote Fault 10529215976Sjmallett RS layer sends continuous idles sequences 10530215976Sjmallett 3 = Link Drain 10531215976Sjmallett RS layer drops full packets to allow GMX and 10532215976Sjmallett PKO to drain their FIFOs 10533215976Sjmallett (XAUI mode only) */ 10534215976Sjmallett uint64_t reserved_2_3 : 2; 10535215976Sjmallett uint64_t uni_en : 1; /**< Enable Unidirectional Mode (IEEE Clause 66) 10536215976Sjmallett (XAUI mode only) */ 10537215976Sjmallett uint64_t dic_en : 1; /**< Enable the deficit idle counter for IFG averaging 10538215976Sjmallett (XAUI mode only) */ 10539215976Sjmallett#else 10540215976Sjmallett uint64_t dic_en : 1; 10541215976Sjmallett uint64_t uni_en : 1; 10542215976Sjmallett uint64_t reserved_2_3 : 2; 10543215976Sjmallett uint64_t ls : 2; 10544215976Sjmallett uint64_t ls_byp : 1; 10545215976Sjmallett uint64_t reserved_7_7 : 1; 10546215976Sjmallett uint64_t hg_en : 1; 10547215976Sjmallett uint64_t hg_pause_hgi : 2; 10548215976Sjmallett uint64_t reserved_11_63 : 53; 10549215976Sjmallett#endif 10550215976Sjmallett } s; 10551215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; 10552215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; 10553215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; 10554215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; 10555232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn61xx; 10556215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn63xx; 10557215976Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1; 10558232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn66xx; 10559232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn68xx; 10560232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1; 10561232812Sjmallett struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx; 10562215976Sjmallett}; 10563215976Sjmalletttypedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t; 10564215976Sjmallett 10565215976Sjmallett/** 10566215976Sjmallett * cvmx_gmx#_xaui_ext_loopback 10567215976Sjmallett */ 10568232812Sjmallettunion cvmx_gmxx_xaui_ext_loopback { 10569215976Sjmallett uint64_t u64; 10570232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s { 10571232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 10572215976Sjmallett uint64_t reserved_5_63 : 59; 10573215976Sjmallett uint64_t en : 1; /**< Loopback enable 10574215976Sjmallett Puts the packet interface in external loopback 10575215976Sjmallett mode on the XAUI bus in which the RX lines are 10576215976Sjmallett reflected on the TX lines. 10577215976Sjmallett (XAUI mode only) */ 10578215976Sjmallett uint64_t thresh : 4; /**< Threshhold on the TX FIFO 10579215976Sjmallett SW must only write the typical value. Any other 10580215976Sjmallett value will cause loopback mode not to function 10581215976Sjmallett correctly. 10582215976Sjmallett (XAUI mode only) */ 10583215976Sjmallett#else 10584215976Sjmallett uint64_t thresh : 4; 10585215976Sjmallett uint64_t en : 1; 10586215976Sjmallett uint64_t reserved_5_63 : 59; 10587215976Sjmallett#endif 10588215976Sjmallett } s; 10589215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; 10590215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; 10591215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; 10592215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; 10593232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn61xx; 10594215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn63xx; 10595215976Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1; 10596232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn66xx; 10597232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn68xx; 10598232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1; 10599232812Sjmallett struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx; 10600215976Sjmallett}; 10601215976Sjmalletttypedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t; 10602215976Sjmallett 10603215976Sjmallett#endif 10604