1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-dpi-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon dpi. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_DPI_DEFS_H__ 53232812Sjmallett#define __CVMX_DPI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60215976Sjmallett cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000000ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_DPI_CTL_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71215976Sjmallett cvmx_warn("CVMX_DPI_CTL not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000040ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset) 79215976Sjmallett{ 80215976Sjmallett if (!( 81232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 82232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 83232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 84232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 85232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 86215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 87215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8; 88215976Sjmallett} 89215976Sjmallett#else 90215976Sjmallett#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) 91215976Sjmallett#endif 92215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset) 94215976Sjmallett{ 95215976Sjmallett if (!( 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 97232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 98232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 99232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 100232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 101215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 102215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8; 103215976Sjmallett} 104215976Sjmallett#else 105215976Sjmallett#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) 106215976Sjmallett#endif 107215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108232812Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_ERR_RSP_STATUS(unsigned long offset) 109232812Sjmallett{ 110232812Sjmallett if (!( 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 114232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 115232812Sjmallett cvmx_warn("CVMX_DPI_DMAX_ERR_RSP_STATUS(%lu) is invalid on this chip\n", offset); 116232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8; 117232812Sjmallett} 118232812Sjmallett#else 119232812Sjmallett#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8) 120232812Sjmallett#endif 121232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset) 123215976Sjmallett{ 124215976Sjmallett if (!( 125232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 126232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 127232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 128232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 130215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 131215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8; 132215976Sjmallett} 133215976Sjmallett#else 134215976Sjmallett#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) 135215976Sjmallett#endif 136215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137232812Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_IFLIGHT(unsigned long offset) 138232812Sjmallett{ 139232812Sjmallett if (!( 140232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 141232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 142232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 143232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 144232812Sjmallett cvmx_warn("CVMX_DPI_DMAX_IFLIGHT(%lu) is invalid on this chip\n", offset); 145232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8; 146232812Sjmallett} 147232812Sjmallett#else 148232812Sjmallett#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8) 149232812Sjmallett#endif 150232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 151215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset) 152215976Sjmallett{ 153215976Sjmallett if (!( 154232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 155232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 156232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 157232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 158232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 159215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8; 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset) 167215976Sjmallett{ 168215976Sjmallett if (!( 169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 171232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 172232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 173232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 174215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset); 175215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8; 176215976Sjmallett} 177215976Sjmallett#else 178215976Sjmallett#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) 179215976Sjmallett#endif 180215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181215976Sjmallettstatic inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset) 182215976Sjmallett{ 183215976Sjmallett if (!( 184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 188232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 189215976Sjmallett cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset); 190215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8; 191215976Sjmallett} 192215976Sjmallett#else 193215976Sjmallett#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) 194215976Sjmallett#endif 195215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 196215976Sjmallett#define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC() 197215976Sjmallettstatic inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void) 198215976Sjmallett{ 199232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 200215976Sjmallett cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n"); 201215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000048ull); 202215976Sjmallett} 203215976Sjmallett#else 204215976Sjmallett#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) 205215976Sjmallett#endif 206215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 207215976Sjmallettstatic inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset) 208215976Sjmallett{ 209215976Sjmallett if (!( 210232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) || 211232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 212232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) || 213232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) || 214232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5))))) 215215976Sjmallett cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset); 216215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8; 217215976Sjmallett} 218215976Sjmallett#else 219215976Sjmallett#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) 220215976Sjmallett#endif 221215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222232812Sjmallettstatic inline uint64_t CVMX_DPI_DMA_PPX_CNT(unsigned long offset) 223232812Sjmallett{ 224232812Sjmallett if (!( 225232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 228232812Sjmallett cvmx_warn("CVMX_DPI_DMA_PPX_CNT(%lu) is invalid on this chip\n", offset); 229232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8; 230232812Sjmallett} 231232812Sjmallett#else 232232812Sjmallett#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8) 233232812Sjmallett#endif 234232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 235215976Sjmallettstatic inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset) 236215976Sjmallett{ 237215976Sjmallett if (!( 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) || 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) || 242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5))))) 243215976Sjmallett cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset); 244215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8; 245215976Sjmallett} 246215976Sjmallett#else 247215976Sjmallett#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) 248215976Sjmallett#endif 249215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 250215976Sjmallett#define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC() 251215976Sjmallettstatic inline uint64_t CVMX_DPI_INFO_REG_FUNC(void) 252215976Sjmallett{ 253232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 254215976Sjmallett cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n"); 255215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000980ull); 256215976Sjmallett} 257215976Sjmallett#else 258215976Sjmallett#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) 259215976Sjmallett#endif 260215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 261215976Sjmallett#define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC() 262215976Sjmallettstatic inline uint64_t CVMX_DPI_INT_EN_FUNC(void) 263215976Sjmallett{ 264232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 265215976Sjmallett cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n"); 266215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000010ull); 267215976Sjmallett} 268215976Sjmallett#else 269215976Sjmallett#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) 270215976Sjmallett#endif 271215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 272215976Sjmallett#define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC() 273215976Sjmallettstatic inline uint64_t CVMX_DPI_INT_REG_FUNC(void) 274215976Sjmallett{ 275232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 276215976Sjmallett cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n"); 277215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000008ull); 278215976Sjmallett} 279215976Sjmallett#else 280215976Sjmallett#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) 281215976Sjmallett#endif 282215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 283232812Sjmallettstatic inline uint64_t CVMX_DPI_NCBX_CFG(unsigned long block_id) 284232812Sjmallett{ 285232812Sjmallett if (!( 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 289232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 290232812Sjmallett cvmx_warn("CVMX_DPI_NCBX_CFG(%lu) is invalid on this chip\n", block_id); 291232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000800ull); 292232812Sjmallett} 293232812Sjmallett#else 294232812Sjmallett#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull)) 295232812Sjmallett#endif 296232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297215976Sjmallett#define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC() 298215976Sjmallettstatic inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void) 299215976Sjmallett{ 300232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 301215976Sjmallett cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n"); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000830ull); 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallett#define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC() 309215976Sjmallettstatic inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void) 310215976Sjmallett{ 311232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 312215976Sjmallett cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n"); 313215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000078ull); 314215976Sjmallett} 315215976Sjmallett#else 316215976Sjmallett#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) 317215976Sjmallett#endif 318215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319215976Sjmallett#define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC() 320215976Sjmallettstatic inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void) 321215976Sjmallett{ 322232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 323215976Sjmallett cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n"); 324215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000058ull); 325215976Sjmallett} 326215976Sjmallett#else 327215976Sjmallett#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) 328215976Sjmallett#endif 329215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330215976Sjmallett#define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC() 331215976Sjmallettstatic inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void) 332215976Sjmallett{ 333232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 334215976Sjmallett cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n"); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000068ull); 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallett#define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC() 342215976Sjmallettstatic inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void) 343215976Sjmallett{ 344232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 345215976Sjmallett cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n"); 346215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000060ull); 347215976Sjmallett} 348215976Sjmallett#else 349215976Sjmallett#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) 350215976Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallett#define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC() 353215976Sjmallettstatic inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void) 354215976Sjmallett{ 355232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 356215976Sjmallett cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n"); 357215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000070ull); 358215976Sjmallett} 359215976Sjmallett#else 360215976Sjmallett#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) 361215976Sjmallett#endif 362215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 363232812Sjmallett#define CVMX_DPI_REQ_ERR_SKIP_COMP CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC() 364232812Sjmallettstatic inline uint64_t CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC(void) 365232812Sjmallett{ 366232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 367232812Sjmallett cvmx_warn("CVMX_DPI_REQ_ERR_SKIP_COMP not supported on this chip\n"); 368232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000838ull); 369232812Sjmallett} 370232812Sjmallett#else 371232812Sjmallett#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) 372232812Sjmallett#endif 373232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 374215976Sjmallett#define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC() 375215976Sjmallettstatic inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void) 376215976Sjmallett{ 377232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 378215976Sjmallett cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n"); 379215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000050ull); 380215976Sjmallett} 381215976Sjmallett#else 382215976Sjmallett#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) 383215976Sjmallett#endif 384215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 385215976Sjmallettstatic inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset) 386215976Sjmallett{ 387215976Sjmallett if (!( 388232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 389232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 390232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 391232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 392232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 393215976Sjmallett cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset); 394232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8; 395215976Sjmallett} 396215976Sjmallett#else 397232812Sjmallett#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) 398215976Sjmallett#endif 399215976Sjmallettstatic inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) 400215976Sjmallett{ 401232812Sjmallett switch(cvmx_get_octeon_family()) { 402232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 403232812Sjmallett if ((offset <= 3)) 404232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 3) * 8; 405232812Sjmallett break; 406232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 407232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 408232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 409232812Sjmallett 410232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) 411232812Sjmallett if ((offset <= 1)) 412232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8; 413232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) 414232812Sjmallett if ((offset <= 1)) 415232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; if ((offset <= 1)) 416232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; 417232812Sjmallett break; 418232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 419232812Sjmallett if ((offset <= 1)) 420232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8; 421232812Sjmallett break; 422232812Sjmallett } 423232812Sjmallett cvmx_warn("CVMX_DPI_SLI_PRTX_ERR (offset = %lu) not supported on this chip\n", offset); 424215976Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; 425215976Sjmallett} 426215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427215976Sjmallettstatic inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset) 428215976Sjmallett{ 429215976Sjmallett if (!( 430232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 431232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 432232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 433232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 434232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 435215976Sjmallett cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset); 436232812Sjmallett return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8; 437215976Sjmallett} 438215976Sjmallett#else 439232812Sjmallett#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) 440215976Sjmallett#endif 441215976Sjmallett 442215976Sjmallett/** 443215976Sjmallett * cvmx_dpi_bist_status 444215976Sjmallett */ 445232812Sjmallettunion cvmx_dpi_bist_status { 446215976Sjmallett uint64_t u64; 447232812Sjmallett struct cvmx_dpi_bist_status_s { 448232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 449232812Sjmallett uint64_t reserved_47_63 : 17; 450232812Sjmallett uint64_t bist : 47; /**< BIST Results. 451232812Sjmallett HW sets a bit in BIST for for memory that fails 452232812Sjmallett BIST. */ 453232812Sjmallett#else 454232812Sjmallett uint64_t bist : 47; 455232812Sjmallett uint64_t reserved_47_63 : 17; 456232812Sjmallett#endif 457232812Sjmallett } s; 458232812Sjmallett struct cvmx_dpi_bist_status_s cn61xx; 459232812Sjmallett struct cvmx_dpi_bist_status_cn63xx { 460232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 461232812Sjmallett uint64_t reserved_45_63 : 19; 462232812Sjmallett uint64_t bist : 45; /**< BIST Results. 463232812Sjmallett HW sets a bit in BIST for for memory that fails 464232812Sjmallett BIST. */ 465232812Sjmallett#else 466232812Sjmallett uint64_t bist : 45; 467232812Sjmallett uint64_t reserved_45_63 : 19; 468232812Sjmallett#endif 469232812Sjmallett } cn63xx; 470232812Sjmallett struct cvmx_dpi_bist_status_cn63xxp1 { 471232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 472215976Sjmallett uint64_t reserved_37_63 : 27; 473215976Sjmallett uint64_t bist : 37; /**< BIST Results. 474215976Sjmallett HW sets a bit in BIST for for memory that fails 475215976Sjmallett BIST. */ 476215976Sjmallett#else 477215976Sjmallett uint64_t bist : 37; 478215976Sjmallett uint64_t reserved_37_63 : 27; 479215976Sjmallett#endif 480232812Sjmallett } cn63xxp1; 481232812Sjmallett struct cvmx_dpi_bist_status_s cn66xx; 482232812Sjmallett struct cvmx_dpi_bist_status_cn63xx cn68xx; 483232812Sjmallett struct cvmx_dpi_bist_status_cn63xx cn68xxp1; 484232812Sjmallett struct cvmx_dpi_bist_status_s cnf71xx; 485215976Sjmallett}; 486215976Sjmalletttypedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t; 487215976Sjmallett 488215976Sjmallett/** 489215976Sjmallett * cvmx_dpi_ctl 490215976Sjmallett */ 491232812Sjmallettunion cvmx_dpi_ctl { 492215976Sjmallett uint64_t u64; 493232812Sjmallett struct cvmx_dpi_ctl_s { 494232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 495215976Sjmallett uint64_t reserved_2_63 : 62; 496215976Sjmallett uint64_t clk : 1; /**< Status bit that indicates that the clks are running */ 497215976Sjmallett uint64_t en : 1; /**< Turns on the DMA and Packet state machines */ 498215976Sjmallett#else 499215976Sjmallett uint64_t en : 1; 500215976Sjmallett uint64_t clk : 1; 501215976Sjmallett uint64_t reserved_2_63 : 62; 502215976Sjmallett#endif 503215976Sjmallett } s; 504232812Sjmallett struct cvmx_dpi_ctl_cn61xx { 505232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 506232812Sjmallett uint64_t reserved_1_63 : 63; 507232812Sjmallett uint64_t en : 1; /**< Turns on the DMA and Packet state machines */ 508232812Sjmallett#else 509232812Sjmallett uint64_t en : 1; 510232812Sjmallett uint64_t reserved_1_63 : 63; 511232812Sjmallett#endif 512232812Sjmallett } cn61xx; 513215976Sjmallett struct cvmx_dpi_ctl_s cn63xx; 514215976Sjmallett struct cvmx_dpi_ctl_s cn63xxp1; 515232812Sjmallett struct cvmx_dpi_ctl_s cn66xx; 516232812Sjmallett struct cvmx_dpi_ctl_s cn68xx; 517232812Sjmallett struct cvmx_dpi_ctl_s cn68xxp1; 518232812Sjmallett struct cvmx_dpi_ctl_cn61xx cnf71xx; 519215976Sjmallett}; 520215976Sjmalletttypedef union cvmx_dpi_ctl cvmx_dpi_ctl_t; 521215976Sjmallett 522215976Sjmallett/** 523215976Sjmallett * cvmx_dpi_dma#_counts 524215976Sjmallett * 525215976Sjmallett * DPI_DMA[0..7]_COUNTS = DMA Instruction Counts 526215976Sjmallett * 527215976Sjmallett * Values for determing the number of instructions for DMA[0..7] in the DPI. 528215976Sjmallett */ 529232812Sjmallettunion cvmx_dpi_dmax_counts { 530215976Sjmallett uint64_t u64; 531232812Sjmallett struct cvmx_dpi_dmax_counts_s { 532232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 533215976Sjmallett uint64_t reserved_39_63 : 25; 534215976Sjmallett uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO locally 535215976Sjmallett cached within DPI. */ 536215976Sjmallett uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 537215976Sjmallett#else 538215976Sjmallett uint64_t dbell : 32; 539215976Sjmallett uint64_t fcnt : 7; 540215976Sjmallett uint64_t reserved_39_63 : 25; 541215976Sjmallett#endif 542215976Sjmallett } s; 543232812Sjmallett struct cvmx_dpi_dmax_counts_s cn61xx; 544215976Sjmallett struct cvmx_dpi_dmax_counts_s cn63xx; 545215976Sjmallett struct cvmx_dpi_dmax_counts_s cn63xxp1; 546232812Sjmallett struct cvmx_dpi_dmax_counts_s cn66xx; 547232812Sjmallett struct cvmx_dpi_dmax_counts_s cn68xx; 548232812Sjmallett struct cvmx_dpi_dmax_counts_s cn68xxp1; 549232812Sjmallett struct cvmx_dpi_dmax_counts_s cnf71xx; 550215976Sjmallett}; 551215976Sjmalletttypedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t; 552215976Sjmallett 553215976Sjmallett/** 554215976Sjmallett * cvmx_dpi_dma#_dbell 555215976Sjmallett * 556215976Sjmallett * DPI_DMA_DBELL[0..7] = DMA Door Bell 557215976Sjmallett * 558215976Sjmallett * The door bell register for DMA[0..7] queue. 559215976Sjmallett */ 560232812Sjmallettunion cvmx_dpi_dmax_dbell { 561215976Sjmallett uint64_t u64; 562232812Sjmallett struct cvmx_dpi_dmax_dbell_s { 563232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 564215976Sjmallett uint64_t reserved_16_63 : 48; 565215976Sjmallett uint64_t dbell : 16; /**< The value written to this register is added to the 566215976Sjmallett number of 8byte words to be read and processes for 567215976Sjmallett the low priority dma queue. */ 568215976Sjmallett#else 569215976Sjmallett uint64_t dbell : 16; 570215976Sjmallett uint64_t reserved_16_63 : 48; 571215976Sjmallett#endif 572215976Sjmallett } s; 573232812Sjmallett struct cvmx_dpi_dmax_dbell_s cn61xx; 574215976Sjmallett struct cvmx_dpi_dmax_dbell_s cn63xx; 575215976Sjmallett struct cvmx_dpi_dmax_dbell_s cn63xxp1; 576232812Sjmallett struct cvmx_dpi_dmax_dbell_s cn66xx; 577232812Sjmallett struct cvmx_dpi_dmax_dbell_s cn68xx; 578232812Sjmallett struct cvmx_dpi_dmax_dbell_s cn68xxp1; 579232812Sjmallett struct cvmx_dpi_dmax_dbell_s cnf71xx; 580215976Sjmallett}; 581215976Sjmalletttypedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t; 582215976Sjmallett 583215976Sjmallett/** 584232812Sjmallett * cvmx_dpi_dma#_err_rsp_status 585232812Sjmallett */ 586232812Sjmallettunion cvmx_dpi_dmax_err_rsp_status { 587232812Sjmallett uint64_t u64; 588232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s { 589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 590232812Sjmallett uint64_t reserved_6_63 : 58; 591232812Sjmallett uint64_t status : 6; /**< QUE captures the ErrorResponse status of the last 592232812Sjmallett 6 instructions for each instruction queue. 593232812Sjmallett STATUS<5> represents the status for first 594232812Sjmallett instruction in instruction order while STATUS<0> 595232812Sjmallett represents the last or most recent instruction. 596232812Sjmallett If STATUS<n> is set, then the nth instruction in 597232812Sjmallett the given queue experienced an ErrorResponse. 598232812Sjmallett Otherwise, it completed normally. */ 599232812Sjmallett#else 600232812Sjmallett uint64_t status : 6; 601232812Sjmallett uint64_t reserved_6_63 : 58; 602232812Sjmallett#endif 603232812Sjmallett } s; 604232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; 605232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; 606232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; 607232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; 608232812Sjmallett struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; 609232812Sjmallett}; 610232812Sjmalletttypedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t; 611232812Sjmallett 612232812Sjmallett/** 613215976Sjmallett * cvmx_dpi_dma#_ibuff_saddr 614215976Sjmallett * 615215976Sjmallett * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 616215976Sjmallett * 617215976Sjmallett * The address to start reading Instructions from for DMA[0..7]. 618215976Sjmallett */ 619232812Sjmallettunion cvmx_dpi_dmax_ibuff_saddr { 620215976Sjmallett uint64_t u64; 621232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_s { 622232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 623215976Sjmallett uint64_t reserved_62_63 : 2; 624215976Sjmallett uint64_t csize : 14; /**< The size in 8B words of the DMA Instruction Chunk. 625215976Sjmallett This value should only be written at known times 626215976Sjmallett in order to prevent corruption of the instruction 627215976Sjmallett queue. The minimum CSIZE is 16 (one cacheblock). */ 628215976Sjmallett uint64_t reserved_41_47 : 7; 629215976Sjmallett uint64_t idle : 1; /**< DMA Request Queue is IDLE */ 630232812Sjmallett uint64_t saddr : 33; /**< The 128 byte aligned starting or chunk address. 631232812Sjmallett SADDR is address bit 35:7 of the starting 632232812Sjmallett instructions address. When new chunks are fetched 633232812Sjmallett by the HW, SADDR will be updated to reflect the 634232812Sjmallett address of the current chunk. 635232812Sjmallett A write to SADDR resets both the queue's doorbell 636232812Sjmallett (DPI_DMAx_COUNTS[DBELL) and its tail pointer 637232812Sjmallett (DPI_DMAx_NADDR[ADDR]). */ 638232812Sjmallett uint64_t reserved_0_6 : 7; 639232812Sjmallett#else 640232812Sjmallett uint64_t reserved_0_6 : 7; 641232812Sjmallett uint64_t saddr : 33; 642232812Sjmallett uint64_t idle : 1; 643232812Sjmallett uint64_t reserved_41_47 : 7; 644232812Sjmallett uint64_t csize : 14; 645232812Sjmallett uint64_t reserved_62_63 : 2; 646232812Sjmallett#endif 647232812Sjmallett } s; 648232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { 649232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 650232812Sjmallett uint64_t reserved_62_63 : 2; 651232812Sjmallett uint64_t csize : 14; /**< The size in 8B words of the DMA Instruction Chunk. 652232812Sjmallett This value should only be written at known times 653232812Sjmallett in order to prevent corruption of the instruction 654232812Sjmallett queue. The minimum CSIZE is 16 (one cacheblock). */ 655232812Sjmallett uint64_t reserved_41_47 : 7; 656232812Sjmallett uint64_t idle : 1; /**< DMA Request Queue is IDLE */ 657215976Sjmallett uint64_t reserved_36_39 : 4; 658215976Sjmallett uint64_t saddr : 29; /**< The 128 byte aligned starting or chunk address. 659215976Sjmallett SADDR is address bit 35:7 of the starting 660215976Sjmallett instructions address. When new chunks are fetched 661215976Sjmallett by the HW, SADDR will be updated to reflect the 662215976Sjmallett address of the current chunk. 663215976Sjmallett A write to SADDR resets both the queue's doorbell 664215976Sjmallett (DPI_DMAx_COUNTS[DBELL) and its tail pointer 665215976Sjmallett (DPI_DMAx_NADDR[ADDR]). */ 666215976Sjmallett uint64_t reserved_0_6 : 7; 667215976Sjmallett#else 668215976Sjmallett uint64_t reserved_0_6 : 7; 669215976Sjmallett uint64_t saddr : 29; 670215976Sjmallett uint64_t reserved_36_39 : 4; 671215976Sjmallett uint64_t idle : 1; 672215976Sjmallett uint64_t reserved_41_47 : 7; 673215976Sjmallett uint64_t csize : 14; 674215976Sjmallett uint64_t reserved_62_63 : 2; 675215976Sjmallett#endif 676232812Sjmallett } cn61xx; 677232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; 678232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; 679232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; 680232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; 681232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; 682232812Sjmallett struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; 683215976Sjmallett}; 684215976Sjmalletttypedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t; 685215976Sjmallett 686215976Sjmallett/** 687232812Sjmallett * cvmx_dpi_dma#_iflight 688232812Sjmallett */ 689232812Sjmallettunion cvmx_dpi_dmax_iflight { 690232812Sjmallett uint64_t u64; 691232812Sjmallett struct cvmx_dpi_dmax_iflight_s { 692232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 693232812Sjmallett uint64_t reserved_3_63 : 61; 694232812Sjmallett uint64_t cnt : 3; /**< The number of instructions from a given queue that 695232812Sjmallett can be inflight to the DMA engines at a time. 696232812Sjmallett Reset value matches the number of DMA engines. */ 697232812Sjmallett#else 698232812Sjmallett uint64_t cnt : 3; 699232812Sjmallett uint64_t reserved_3_63 : 61; 700232812Sjmallett#endif 701232812Sjmallett } s; 702232812Sjmallett struct cvmx_dpi_dmax_iflight_s cn61xx; 703232812Sjmallett struct cvmx_dpi_dmax_iflight_s cn66xx; 704232812Sjmallett struct cvmx_dpi_dmax_iflight_s cn68xx; 705232812Sjmallett struct cvmx_dpi_dmax_iflight_s cn68xxp1; 706232812Sjmallett struct cvmx_dpi_dmax_iflight_s cnf71xx; 707232812Sjmallett}; 708232812Sjmalletttypedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t; 709232812Sjmallett 710232812Sjmallett/** 711215976Sjmallett * cvmx_dpi_dma#_naddr 712215976Sjmallett * 713215976Sjmallett * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address 714215976Sjmallett * 715215976Sjmallett * Place DPI will read the next Ichunk data from. 716215976Sjmallett */ 717232812Sjmallettunion cvmx_dpi_dmax_naddr { 718215976Sjmallett uint64_t u64; 719232812Sjmallett struct cvmx_dpi_dmax_naddr_s { 720232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 721232812Sjmallett uint64_t reserved_40_63 : 24; 722232812Sjmallett uint64_t addr : 40; /**< The next L2C address to read DMA# instructions 723232812Sjmallett from. */ 724232812Sjmallett#else 725232812Sjmallett uint64_t addr : 40; 726232812Sjmallett uint64_t reserved_40_63 : 24; 727232812Sjmallett#endif 728232812Sjmallett } s; 729232812Sjmallett struct cvmx_dpi_dmax_naddr_cn61xx { 730232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 731215976Sjmallett uint64_t reserved_36_63 : 28; 732215976Sjmallett uint64_t addr : 36; /**< The next L2C address to read DMA# instructions 733215976Sjmallett from. */ 734215976Sjmallett#else 735215976Sjmallett uint64_t addr : 36; 736215976Sjmallett uint64_t reserved_36_63 : 28; 737215976Sjmallett#endif 738232812Sjmallett } cn61xx; 739232812Sjmallett struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; 740232812Sjmallett struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; 741232812Sjmallett struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; 742232812Sjmallett struct cvmx_dpi_dmax_naddr_s cn68xx; 743232812Sjmallett struct cvmx_dpi_dmax_naddr_s cn68xxp1; 744232812Sjmallett struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; 745215976Sjmallett}; 746215976Sjmalletttypedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t; 747215976Sjmallett 748215976Sjmallett/** 749215976Sjmallett * cvmx_dpi_dma#_reqbnk0 750215976Sjmallett * 751215976Sjmallett * DPI_DMA[0..7]_REQBNK0 = DMA Request State Bank0 752215976Sjmallett * 753215976Sjmallett * Current contents of the request state machine - bank0 754215976Sjmallett */ 755232812Sjmallettunion cvmx_dpi_dmax_reqbnk0 { 756215976Sjmallett uint64_t u64; 757232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s { 758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 759215976Sjmallett uint64_t state : 64; /**< State */ 760215976Sjmallett#else 761215976Sjmallett uint64_t state : 64; 762215976Sjmallett#endif 763215976Sjmallett } s; 764232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn61xx; 765215976Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn63xx; 766215976Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; 767232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn66xx; 768232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn68xx; 769232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; 770232812Sjmallett struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; 771215976Sjmallett}; 772215976Sjmalletttypedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t; 773215976Sjmallett 774215976Sjmallett/** 775215976Sjmallett * cvmx_dpi_dma#_reqbnk1 776215976Sjmallett * 777215976Sjmallett * DPI_DMA[0..7]_REQBNK1 = DMA Request State Bank1 778215976Sjmallett * 779215976Sjmallett * Current contents of the request state machine - bank1 780215976Sjmallett */ 781232812Sjmallettunion cvmx_dpi_dmax_reqbnk1 { 782215976Sjmallett uint64_t u64; 783232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s { 784232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 785215976Sjmallett uint64_t state : 64; /**< State */ 786215976Sjmallett#else 787215976Sjmallett uint64_t state : 64; 788215976Sjmallett#endif 789215976Sjmallett } s; 790232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn61xx; 791215976Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn63xx; 792215976Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; 793232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn66xx; 794232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn68xx; 795232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; 796232812Sjmallett struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; 797215976Sjmallett}; 798215976Sjmalletttypedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t; 799215976Sjmallett 800215976Sjmallett/** 801215976Sjmallett * cvmx_dpi_dma_control 802215976Sjmallett * 803215976Sjmallett * DPI_DMA_CONTROL = DMA Control Register 804215976Sjmallett * 805215976Sjmallett * Controls operation of the DMA IN/OUT. 806215976Sjmallett */ 807232812Sjmallettunion cvmx_dpi_dma_control { 808215976Sjmallett uint64_t u64; 809232812Sjmallett struct cvmx_dpi_dma_control_s { 810232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 811232812Sjmallett uint64_t reserved_62_63 : 2; 812232812Sjmallett uint64_t dici_mode : 1; /**< DMA Instruction Completion Interrupt Mode 813232812Sjmallett turns on mode to increment DPI_DMA_PPx_CNT 814232812Sjmallett counters. */ 815232812Sjmallett uint64_t pkt_en1 : 1; /**< Enables the 2nd packet interface. 816232812Sjmallett When the packet interface is enabled, engine 4 817232812Sjmallett is used for packets and is not available for DMA. 818232812Sjmallett The packet interfaces must be enabled in order. 819232812Sjmallett When PKT_EN1=1, then PKT_EN=1. 820232812Sjmallett When PKT_EN1=1, then DMA_ENB<4>=0. */ 821232812Sjmallett uint64_t ffp_dis : 1; /**< Force forward progress disable 822232812Sjmallett The DMA engines will compete for shared resources. 823232812Sjmallett If the HW detects that particular engines are not 824232812Sjmallett able to make requests to an interface, the HW 825232812Sjmallett will periodically trade-off throughput for 826232812Sjmallett fairness. */ 827232812Sjmallett uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 828232812Sjmallett 829232812Sjmallett When COMMIT_MODE=0, DPI considers an instruction 830232812Sjmallett complete when the HW internally generates the 831232812Sjmallett final write for the current instruction. 832232812Sjmallett 833232812Sjmallett When COMMIT_MODE=1, DPI additionally waits for 834232812Sjmallett the final write to reach the interface coherency 835232812Sjmallett point to declare the instructions complete. 836232812Sjmallett 837232812Sjmallett Please note: when COMMIT_MODE == 0, DPI may not 838232812Sjmallett follow the HRM ordering rules. 839232812Sjmallett 840232812Sjmallett DPI hardware performance may be better with 841232812Sjmallett COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 842232812Sjmallett to the relaxed ordering rules. 843232812Sjmallett 844232812Sjmallett If the HRM ordering rules are required, set 845232812Sjmallett COMMIT_MODE == 1. */ 846232812Sjmallett uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 847232812Sjmallett This mode has been deprecated. */ 848232812Sjmallett uint64_t pkt_en : 1; /**< Enables 1st the packet interface. 849232812Sjmallett When the packet interface is enabled, engine 5 850232812Sjmallett is used for packets and is not available for DMA. 851232812Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. 852232812Sjmallett When PKT_EN1=1, then PKT_EN=1. */ 853232812Sjmallett uint64_t reserved_54_55 : 2; 854232812Sjmallett uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 855232812Sjmallett DMA engine. After being enabled an engine should 856232812Sjmallett not be disabled while processing instructions. 857232812Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. 858232812Sjmallett When PKT_EN1=1, then DMA_ENB<4>=0. */ 859232812Sjmallett uint64_t reserved_34_47 : 14; 860232812Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 861232812Sjmallett 0 to L2C memory when a DMA is done, the address 862232812Sjmallett to be written to will be treated as a Little 863232812Sjmallett Endian address. */ 864232812Sjmallett uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 865232812Sjmallett field for a free page operation for the memory 866232812Sjmallett that contained the data. */ 867232812Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 868232812Sjmallett freed this value is used for the DWB field of the 869232812Sjmallett operation. */ 870232812Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 871232812Sjmallett be returned to when used. */ 872232812Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the SLI_DMAX_CNT 873232812Sjmallett DMA counters, if '0' then the number of bytes 874232812Sjmallett in the dma transfer will be added to the 875232812Sjmallett SLI_DMAX_CNT count register. */ 876232812Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 877232812Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 878232812Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 879232812Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 880232812Sjmallett 0=DPTR format 1 is used 881232812Sjmallett use register values for address and pointer 882232812Sjmallett values for ES, NS, RO 883232812Sjmallett 1=DPTR format 0 is used 884232812Sjmallett use pointer values for address and register 885232812Sjmallett values for ES, NS, RO */ 886232812Sjmallett uint64_t reserved_0_13 : 14; 887232812Sjmallett#else 888232812Sjmallett uint64_t reserved_0_13 : 14; 889232812Sjmallett uint64_t o_mode : 1; 890232812Sjmallett uint64_t o_es : 2; 891232812Sjmallett uint64_t o_ns : 1; 892232812Sjmallett uint64_t o_ro : 1; 893232812Sjmallett uint64_t o_add1 : 1; 894232812Sjmallett uint64_t fpa_que : 3; 895232812Sjmallett uint64_t dwb_ichk : 9; 896232812Sjmallett uint64_t dwb_denb : 1; 897232812Sjmallett uint64_t b0_lend : 1; 898232812Sjmallett uint64_t reserved_34_47 : 14; 899232812Sjmallett uint64_t dma_enb : 6; 900232812Sjmallett uint64_t reserved_54_55 : 2; 901232812Sjmallett uint64_t pkt_en : 1; 902232812Sjmallett uint64_t pkt_hp : 1; 903232812Sjmallett uint64_t commit_mode : 1; 904232812Sjmallett uint64_t ffp_dis : 1; 905232812Sjmallett uint64_t pkt_en1 : 1; 906232812Sjmallett uint64_t dici_mode : 1; 907232812Sjmallett uint64_t reserved_62_63 : 2; 908232812Sjmallett#endif 909232812Sjmallett } s; 910232812Sjmallett struct cvmx_dpi_dma_control_s cn61xx; 911232812Sjmallett struct cvmx_dpi_dma_control_cn63xx { 912232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 913215976Sjmallett uint64_t reserved_61_63 : 3; 914215976Sjmallett uint64_t pkt_en1 : 1; /**< Enables the 2nd packet interface. 915215976Sjmallett When the packet interface is enabled, engine 4 916215976Sjmallett is used for packets and is not available for DMA. 917215976Sjmallett The packet interfaces must be enabled in order. 918215976Sjmallett When PKT_EN1=1, then PKT_EN=1. 919215976Sjmallett When PKT_EN1=1, then DMA_ENB<4>=0. */ 920215976Sjmallett uint64_t ffp_dis : 1; /**< Force forward progress disable 921215976Sjmallett The DMA engines will compete for shared resources. 922215976Sjmallett If the HW detects that particular engines are not 923215976Sjmallett able to make requests to an interface, the HW 924215976Sjmallett will periodically trade-off throughput for 925215976Sjmallett fairness. */ 926215976Sjmallett uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 927215976Sjmallett 928215976Sjmallett When COMMIT_MODE=0, DPI considers an instruction 929215976Sjmallett complete when the HW internally generates the 930215976Sjmallett final write for the current instruction. 931215976Sjmallett 932215976Sjmallett When COMMIT_MODE=1, DPI additionally waits for 933215976Sjmallett the final write to reach the interface coherency 934215976Sjmallett point to declare the instructions complete. 935215976Sjmallett 936215976Sjmallett Please note: when COMMIT_MODE == 0, DPI may not 937215976Sjmallett follow the HRM ordering rules. 938215976Sjmallett 939215976Sjmallett DPI hardware performance may be better with 940215976Sjmallett COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 941215976Sjmallett to the relaxed ordering rules. 942215976Sjmallett 943215976Sjmallett If the HRM ordering rules are required, set 944215976Sjmallett COMMIT_MODE == 1. */ 945215976Sjmallett uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 946232812Sjmallett This mode has been deprecated. */ 947232812Sjmallett uint64_t pkt_en : 1; /**< Enables 1st the packet interface. 948215976Sjmallett When the packet interface is enabled, engine 5 949215976Sjmallett is used for packets and is not available for DMA. 950215976Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. 951232812Sjmallett When PKT_EN1=1, then PKT_EN=1. */ 952215976Sjmallett uint64_t reserved_54_55 : 2; 953215976Sjmallett uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 954215976Sjmallett DMA engine. After being enabled an engine should 955215976Sjmallett not be disabled while processing instructions. 956232812Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. 957232812Sjmallett When PKT_EN1=1, then DMA_ENB<4>=0. */ 958215976Sjmallett uint64_t reserved_34_47 : 14; 959215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 960215976Sjmallett 0 to L2C memory when a DMA is done, the address 961215976Sjmallett to be written to will be treated as a Little 962215976Sjmallett Endian address. */ 963215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 964215976Sjmallett field for a free page operation for the memory 965215976Sjmallett that contained the data. */ 966215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 967215976Sjmallett freed this value is used for the DWB field of the 968215976Sjmallett operation. */ 969215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 970215976Sjmallett be returned to when used. */ 971215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 972215976Sjmallett if '0' then the number of bytes in the dma 973215976Sjmallett transfer will be added to the count register. */ 974215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 975215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 976215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 977215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 978215976Sjmallett 0=DPTR format 1 is used 979215976Sjmallett use register values for address and pointer 980215976Sjmallett values for ES, NS, RO 981215976Sjmallett 1=DPTR format 0 is used 982215976Sjmallett use pointer values for address and register 983215976Sjmallett values for ES, NS, RO */ 984215976Sjmallett uint64_t reserved_0_13 : 14; 985215976Sjmallett#else 986215976Sjmallett uint64_t reserved_0_13 : 14; 987215976Sjmallett uint64_t o_mode : 1; 988215976Sjmallett uint64_t o_es : 2; 989215976Sjmallett uint64_t o_ns : 1; 990215976Sjmallett uint64_t o_ro : 1; 991215976Sjmallett uint64_t o_add1 : 1; 992215976Sjmallett uint64_t fpa_que : 3; 993215976Sjmallett uint64_t dwb_ichk : 9; 994215976Sjmallett uint64_t dwb_denb : 1; 995215976Sjmallett uint64_t b0_lend : 1; 996215976Sjmallett uint64_t reserved_34_47 : 14; 997215976Sjmallett uint64_t dma_enb : 6; 998215976Sjmallett uint64_t reserved_54_55 : 2; 999215976Sjmallett uint64_t pkt_en : 1; 1000215976Sjmallett uint64_t pkt_hp : 1; 1001215976Sjmallett uint64_t commit_mode : 1; 1002215976Sjmallett uint64_t ffp_dis : 1; 1003215976Sjmallett uint64_t pkt_en1 : 1; 1004215976Sjmallett uint64_t reserved_61_63 : 3; 1005215976Sjmallett#endif 1006232812Sjmallett } cn63xx; 1007232812Sjmallett struct cvmx_dpi_dma_control_cn63xxp1 { 1008232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1009215976Sjmallett uint64_t reserved_59_63 : 5; 1010215976Sjmallett uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 1011215976Sjmallett 1012215976Sjmallett When COMMIT_MODE=0, DPI considers an instruction 1013215976Sjmallett complete when the HW internally generates the 1014215976Sjmallett final write for the current instruction. 1015215976Sjmallett 1016215976Sjmallett When COMMIT_MODE=1, DPI additionally waits for 1017215976Sjmallett the final write to reach the interface coherency 1018215976Sjmallett point to declare the instructions complete. 1019215976Sjmallett 1020215976Sjmallett Please note: when COMMIT_MODE == 0, DPI may not 1021215976Sjmallett follow the HRM ordering rules. 1022215976Sjmallett 1023215976Sjmallett DPI hardware performance may be better with 1024215976Sjmallett COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 1025215976Sjmallett to the relaxed ordering rules. 1026215976Sjmallett 1027215976Sjmallett If the HRM ordering rules are required, set 1028215976Sjmallett COMMIT_MODE == 1. */ 1029215976Sjmallett uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 1030215976Sjmallett Engine 5 will be serviced more frequently to 1031215976Sjmallett deliver more bandwidth to packet interface. 1032215976Sjmallett When PKT_EN=0, then PKT_HP=0. */ 1033215976Sjmallett uint64_t pkt_en : 1; /**< Enables the packet interface. 1034215976Sjmallett When the packet interface is enabled, engine 5 1035215976Sjmallett is used for packets and is not available for DMA. 1036215976Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. 1037215976Sjmallett When PKT_EN=0, then PKT_HP=0. */ 1038215976Sjmallett uint64_t reserved_54_55 : 2; 1039215976Sjmallett uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 1040215976Sjmallett DMA engine. After being enabled an engine should 1041215976Sjmallett not be disabled while processing instructions. 1042215976Sjmallett When PKT_EN=1, then DMA_ENB<5>=0. */ 1043215976Sjmallett uint64_t reserved_34_47 : 14; 1044215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 1045215976Sjmallett 0 to L2C memory when a DMA is done, the address 1046215976Sjmallett to be written to will be treated as a Little 1047215976Sjmallett Endian address. */ 1048215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 1049215976Sjmallett field for a free page operation for the memory 1050215976Sjmallett that contained the data. */ 1051215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 1052215976Sjmallett freed this value is used for the DWB field of the 1053215976Sjmallett operation. */ 1054215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 1055215976Sjmallett be returned to when used. */ 1056215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 1057215976Sjmallett if '0' then the number of bytes in the dma 1058215976Sjmallett transfer will be added to the count register. */ 1059215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 1060215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 1061215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 1062215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 1063215976Sjmallett 0=DPTR format 1 is used 1064215976Sjmallett use register values for address and pointer 1065215976Sjmallett values for ES, NS, RO 1066215976Sjmallett 1=DPTR format 0 is used 1067215976Sjmallett use pointer values for address and register 1068215976Sjmallett values for ES, NS, RO */ 1069215976Sjmallett uint64_t reserved_0_13 : 14; 1070215976Sjmallett#else 1071215976Sjmallett uint64_t reserved_0_13 : 14; 1072215976Sjmallett uint64_t o_mode : 1; 1073215976Sjmallett uint64_t o_es : 2; 1074215976Sjmallett uint64_t o_ns : 1; 1075215976Sjmallett uint64_t o_ro : 1; 1076215976Sjmallett uint64_t o_add1 : 1; 1077215976Sjmallett uint64_t fpa_que : 3; 1078215976Sjmallett uint64_t dwb_ichk : 9; 1079215976Sjmallett uint64_t dwb_denb : 1; 1080215976Sjmallett uint64_t b0_lend : 1; 1081215976Sjmallett uint64_t reserved_34_47 : 14; 1082215976Sjmallett uint64_t dma_enb : 6; 1083215976Sjmallett uint64_t reserved_54_55 : 2; 1084215976Sjmallett uint64_t pkt_en : 1; 1085215976Sjmallett uint64_t pkt_hp : 1; 1086215976Sjmallett uint64_t commit_mode : 1; 1087215976Sjmallett uint64_t reserved_59_63 : 5; 1088215976Sjmallett#endif 1089215976Sjmallett } cn63xxp1; 1090232812Sjmallett struct cvmx_dpi_dma_control_cn63xx cn66xx; 1091232812Sjmallett struct cvmx_dpi_dma_control_s cn68xx; 1092232812Sjmallett struct cvmx_dpi_dma_control_cn63xx cn68xxp1; 1093232812Sjmallett struct cvmx_dpi_dma_control_s cnf71xx; 1094215976Sjmallett}; 1095215976Sjmalletttypedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t; 1096215976Sjmallett 1097215976Sjmallett/** 1098215976Sjmallett * cvmx_dpi_dma_eng#_en 1099215976Sjmallett */ 1100232812Sjmallettunion cvmx_dpi_dma_engx_en { 1101215976Sjmallett uint64_t u64; 1102232812Sjmallett struct cvmx_dpi_dma_engx_en_s { 1103232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1104215976Sjmallett uint64_t reserved_8_63 : 56; 1105215976Sjmallett uint64_t qen : 8; /**< Controls which logical instruction queues can be 1106215976Sjmallett serviced by the DMA engine. Setting QEN==0 1107215976Sjmallett effectively disables the engine. 1108215976Sjmallett When DPI_DMA_CONTROL[PKT_EN] = 1, then 1109232812Sjmallett DPI_DMA_ENG5_EN[QEN] must be zero. 1110232812Sjmallett When DPI_DMA_CONTROL[PKT_EN1] = 1, then 1111232812Sjmallett DPI_DMA_ENG4_EN[QEN] must be zero. */ 1112215976Sjmallett#else 1113215976Sjmallett uint64_t qen : 8; 1114215976Sjmallett uint64_t reserved_8_63 : 56; 1115215976Sjmallett#endif 1116215976Sjmallett } s; 1117232812Sjmallett struct cvmx_dpi_dma_engx_en_s cn61xx; 1118215976Sjmallett struct cvmx_dpi_dma_engx_en_s cn63xx; 1119215976Sjmallett struct cvmx_dpi_dma_engx_en_s cn63xxp1; 1120232812Sjmallett struct cvmx_dpi_dma_engx_en_s cn66xx; 1121232812Sjmallett struct cvmx_dpi_dma_engx_en_s cn68xx; 1122232812Sjmallett struct cvmx_dpi_dma_engx_en_s cn68xxp1; 1123232812Sjmallett struct cvmx_dpi_dma_engx_en_s cnf71xx; 1124215976Sjmallett}; 1125215976Sjmalletttypedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t; 1126215976Sjmallett 1127215976Sjmallett/** 1128232812Sjmallett * cvmx_dpi_dma_pp#_cnt 1129232812Sjmallett * 1130232812Sjmallett * DPI_DMA_PP[0..3]_CNT = DMA per PP Instr Done Counter 1131232812Sjmallett * 1132232812Sjmallett * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma instruction 1133232812Sjmallett * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter. 1134232812Sjmallett * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write. 1135232812Sjmallett * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do nothing. 1136232812Sjmallett */ 1137232812Sjmallettunion cvmx_dpi_dma_ppx_cnt { 1138232812Sjmallett uint64_t u64; 1139232812Sjmallett struct cvmx_dpi_dma_ppx_cnt_s { 1140232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1141232812Sjmallett uint64_t reserved_16_63 : 48; 1142232812Sjmallett uint64_t cnt : 16; /**< Counter incremented according to conditions 1143232812Sjmallett described above and decremented by values written 1144232812Sjmallett to this field. A CNT of non zero, will cause 1145232812Sjmallett an interrupt in the CIU_SUM1_PPX_IPX register */ 1146232812Sjmallett#else 1147232812Sjmallett uint64_t cnt : 16; 1148232812Sjmallett uint64_t reserved_16_63 : 48; 1149232812Sjmallett#endif 1150232812Sjmallett } s; 1151232812Sjmallett struct cvmx_dpi_dma_ppx_cnt_s cn61xx; 1152232812Sjmallett struct cvmx_dpi_dma_ppx_cnt_s cn68xx; 1153232812Sjmallett struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; 1154232812Sjmallett}; 1155232812Sjmalletttypedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t; 1156232812Sjmallett 1157232812Sjmallett/** 1158215976Sjmallett * cvmx_dpi_eng#_buf 1159215976Sjmallett * 1160215976Sjmallett * Notes: 1161215976Sjmallett * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB. 1162215976Sjmallett * 1163215976Sjmallett */ 1164232812Sjmallettunion cvmx_dpi_engx_buf { 1165215976Sjmallett uint64_t u64; 1166232812Sjmallett struct cvmx_dpi_engx_buf_s { 1167232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1168232812Sjmallett uint64_t reserved_37_63 : 27; 1169232812Sjmallett uint64_t compblks : 5; /**< Computed engine block size */ 1170232812Sjmallett uint64_t reserved_9_31 : 23; 1171232812Sjmallett uint64_t base : 5; /**< The base address in 512B blocks of the engine fifo */ 1172232812Sjmallett uint64_t blks : 4; /**< The size of the engine fifo 1173232812Sjmallett Legal values are 0-10. 1174232812Sjmallett 0 = Engine is disabled 1175232812Sjmallett 1 = 0.5KB buffer 1176232812Sjmallett 2 = 1.0KB buffer 1177232812Sjmallett 3 = 1.5KB buffer 1178232812Sjmallett 4 = 2.0KB buffer 1179232812Sjmallett 5 = 2.5KB buffer 1180232812Sjmallett 6 = 3.0KB buffer 1181232812Sjmallett 7 = 3.5KB buffer 1182232812Sjmallett 8 = 4.0KB buffer 1183232812Sjmallett 9 = 6.0KB buffer 1184232812Sjmallett 10 = 8.0KB buffer */ 1185232812Sjmallett#else 1186232812Sjmallett uint64_t blks : 4; 1187232812Sjmallett uint64_t base : 5; 1188232812Sjmallett uint64_t reserved_9_31 : 23; 1189232812Sjmallett uint64_t compblks : 5; 1190232812Sjmallett uint64_t reserved_37_63 : 27; 1191232812Sjmallett#endif 1192232812Sjmallett } s; 1193232812Sjmallett struct cvmx_dpi_engx_buf_s cn61xx; 1194232812Sjmallett struct cvmx_dpi_engx_buf_cn63xx { 1195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1196215976Sjmallett uint64_t reserved_8_63 : 56; 1197215976Sjmallett uint64_t base : 4; /**< The base address in 512B blocks of the engine fifo */ 1198215976Sjmallett uint64_t blks : 4; /**< The size in 512B blocks of the engine fifo 1199215976Sjmallett Legal values are 0-8. 1200215976Sjmallett 0 = Engine is disabled 1201215976Sjmallett 1 = 0.5KB buffer 1202215976Sjmallett 2 = 1.0KB buffer 1203215976Sjmallett 3 = 1.5KB buffer 1204215976Sjmallett 4 = 2.0KB buffer 1205215976Sjmallett 5 = 2.5KB buffer 1206215976Sjmallett 6 = 3.0KB buffer 1207215976Sjmallett 7 = 3.5KB buffer 1208215976Sjmallett 8 = 4.0KB buffer */ 1209215976Sjmallett#else 1210215976Sjmallett uint64_t blks : 4; 1211215976Sjmallett uint64_t base : 4; 1212215976Sjmallett uint64_t reserved_8_63 : 56; 1213215976Sjmallett#endif 1214232812Sjmallett } cn63xx; 1215232812Sjmallett struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; 1216232812Sjmallett struct cvmx_dpi_engx_buf_s cn66xx; 1217232812Sjmallett struct cvmx_dpi_engx_buf_s cn68xx; 1218232812Sjmallett struct cvmx_dpi_engx_buf_s cn68xxp1; 1219232812Sjmallett struct cvmx_dpi_engx_buf_s cnf71xx; 1220215976Sjmallett}; 1221215976Sjmalletttypedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t; 1222215976Sjmallett 1223215976Sjmallett/** 1224215976Sjmallett * cvmx_dpi_info_reg 1225215976Sjmallett */ 1226232812Sjmallettunion cvmx_dpi_info_reg { 1227215976Sjmallett uint64_t u64; 1228232812Sjmallett struct cvmx_dpi_info_reg_s { 1229232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1230215976Sjmallett uint64_t reserved_8_63 : 56; 1231215976Sjmallett uint64_t ffp : 4; /**< Force Forward Progress Indicator */ 1232215976Sjmallett uint64_t reserved_2_3 : 2; 1233215976Sjmallett uint64_t ncb : 1; /**< NCB Register Access 1234215976Sjmallett This interrupt will fire in normal operation 1235215976Sjmallett when SW reads a DPI register through the NCB 1236215976Sjmallett interface. */ 1237215976Sjmallett uint64_t rsl : 1; /**< RSL Register Access 1238215976Sjmallett This interrupt will fire in normal operation 1239215976Sjmallett when SW reads a DPI register through the RSL 1240215976Sjmallett interface. */ 1241215976Sjmallett#else 1242215976Sjmallett uint64_t rsl : 1; 1243215976Sjmallett uint64_t ncb : 1; 1244215976Sjmallett uint64_t reserved_2_3 : 2; 1245215976Sjmallett uint64_t ffp : 4; 1246215976Sjmallett uint64_t reserved_8_63 : 56; 1247215976Sjmallett#endif 1248215976Sjmallett } s; 1249232812Sjmallett struct cvmx_dpi_info_reg_s cn61xx; 1250215976Sjmallett struct cvmx_dpi_info_reg_s cn63xx; 1251232812Sjmallett struct cvmx_dpi_info_reg_cn63xxp1 { 1252232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1253215976Sjmallett uint64_t reserved_2_63 : 62; 1254215976Sjmallett uint64_t ncb : 1; /**< NCB Register Access 1255215976Sjmallett This interrupt will fire in normal operation 1256215976Sjmallett when SW reads a DPI register through the NCB 1257215976Sjmallett interface. */ 1258215976Sjmallett uint64_t rsl : 1; /**< RSL Register Access 1259215976Sjmallett This interrupt will fire in normal operation 1260215976Sjmallett when SW reads a DPI register through the RSL 1261215976Sjmallett interface. */ 1262215976Sjmallett#else 1263215976Sjmallett uint64_t rsl : 1; 1264215976Sjmallett uint64_t ncb : 1; 1265215976Sjmallett uint64_t reserved_2_63 : 62; 1266215976Sjmallett#endif 1267215976Sjmallett } cn63xxp1; 1268232812Sjmallett struct cvmx_dpi_info_reg_s cn66xx; 1269232812Sjmallett struct cvmx_dpi_info_reg_s cn68xx; 1270232812Sjmallett struct cvmx_dpi_info_reg_s cn68xxp1; 1271232812Sjmallett struct cvmx_dpi_info_reg_s cnf71xx; 1272215976Sjmallett}; 1273215976Sjmalletttypedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t; 1274215976Sjmallett 1275215976Sjmallett/** 1276215976Sjmallett * cvmx_dpi_int_en 1277215976Sjmallett */ 1278232812Sjmallettunion cvmx_dpi_int_en { 1279215976Sjmallett uint64_t u64; 1280232812Sjmallett struct cvmx_dpi_int_en_s { 1281232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1282232812Sjmallett uint64_t reserved_28_63 : 36; 1283232812Sjmallett uint64_t sprt3_rst : 1; /**< DMA instruction was dropped because the source or 1284232812Sjmallett destination port was in reset. 1285232812Sjmallett this bit is set. */ 1286232812Sjmallett uint64_t sprt2_rst : 1; /**< DMA instruction was dropped because the source or 1287232812Sjmallett destination port was in reset. 1288232812Sjmallett this bit is set. */ 1289232812Sjmallett uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1290232812Sjmallett destination port was in reset. 1291232812Sjmallett this bit is set. */ 1292232812Sjmallett uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1293232812Sjmallett destination port was in reset. 1294232812Sjmallett this bit is set. */ 1295232812Sjmallett uint64_t reserved_23_23 : 1; 1296232812Sjmallett uint64_t req_badfil : 1; /**< DMA instruction unexpected fill */ 1297232812Sjmallett uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer */ 1298232812Sjmallett uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction */ 1299232812Sjmallett uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow */ 1300232812Sjmallett uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow */ 1301232812Sjmallett uint64_t req_badlen : 1; /**< DMA instruction fetch with length */ 1302232812Sjmallett uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer */ 1303232812Sjmallett uint64_t dmadbo : 8; /**< DMAx doorbell overflow. */ 1304232812Sjmallett uint64_t reserved_2_7 : 6; 1305232812Sjmallett uint64_t nfovr : 1; /**< CSR Fifo Overflow */ 1306232812Sjmallett uint64_t nderr : 1; /**< NCB Decode Error */ 1307232812Sjmallett#else 1308232812Sjmallett uint64_t nderr : 1; 1309232812Sjmallett uint64_t nfovr : 1; 1310232812Sjmallett uint64_t reserved_2_7 : 6; 1311232812Sjmallett uint64_t dmadbo : 8; 1312232812Sjmallett uint64_t req_badadr : 1; 1313232812Sjmallett uint64_t req_badlen : 1; 1314232812Sjmallett uint64_t req_ovrflw : 1; 1315232812Sjmallett uint64_t req_undflw : 1; 1316232812Sjmallett uint64_t req_anull : 1; 1317232812Sjmallett uint64_t req_inull : 1; 1318232812Sjmallett uint64_t req_badfil : 1; 1319232812Sjmallett uint64_t reserved_23_23 : 1; 1320232812Sjmallett uint64_t sprt0_rst : 1; 1321232812Sjmallett uint64_t sprt1_rst : 1; 1322232812Sjmallett uint64_t sprt2_rst : 1; 1323232812Sjmallett uint64_t sprt3_rst : 1; 1324232812Sjmallett uint64_t reserved_28_63 : 36; 1325232812Sjmallett#endif 1326232812Sjmallett } s; 1327232812Sjmallett struct cvmx_dpi_int_en_s cn61xx; 1328232812Sjmallett struct cvmx_dpi_int_en_cn63xx { 1329232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1330215976Sjmallett uint64_t reserved_26_63 : 38; 1331215976Sjmallett uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1332215976Sjmallett destination port was in reset. 1333215976Sjmallett this bit is set. */ 1334215976Sjmallett uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1335215976Sjmallett destination port was in reset. 1336215976Sjmallett this bit is set. */ 1337215976Sjmallett uint64_t reserved_23_23 : 1; 1338215976Sjmallett uint64_t req_badfil : 1; /**< DMA instruction unexpected fill */ 1339215976Sjmallett uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer */ 1340215976Sjmallett uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction */ 1341215976Sjmallett uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow */ 1342215976Sjmallett uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow */ 1343215976Sjmallett uint64_t req_badlen : 1; /**< DMA instruction fetch with length */ 1344215976Sjmallett uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer */ 1345215976Sjmallett uint64_t dmadbo : 8; /**< DMAx doorbell overflow. */ 1346215976Sjmallett uint64_t reserved_2_7 : 6; 1347215976Sjmallett uint64_t nfovr : 1; /**< CSR Fifo Overflow */ 1348215976Sjmallett uint64_t nderr : 1; /**< NCB Decode Error */ 1349215976Sjmallett#else 1350215976Sjmallett uint64_t nderr : 1; 1351215976Sjmallett uint64_t nfovr : 1; 1352215976Sjmallett uint64_t reserved_2_7 : 6; 1353215976Sjmallett uint64_t dmadbo : 8; 1354215976Sjmallett uint64_t req_badadr : 1; 1355215976Sjmallett uint64_t req_badlen : 1; 1356215976Sjmallett uint64_t req_ovrflw : 1; 1357215976Sjmallett uint64_t req_undflw : 1; 1358215976Sjmallett uint64_t req_anull : 1; 1359215976Sjmallett uint64_t req_inull : 1; 1360215976Sjmallett uint64_t req_badfil : 1; 1361215976Sjmallett uint64_t reserved_23_23 : 1; 1362215976Sjmallett uint64_t sprt0_rst : 1; 1363215976Sjmallett uint64_t sprt1_rst : 1; 1364215976Sjmallett uint64_t reserved_26_63 : 38; 1365215976Sjmallett#endif 1366232812Sjmallett } cn63xx; 1367232812Sjmallett struct cvmx_dpi_int_en_cn63xx cn63xxp1; 1368232812Sjmallett struct cvmx_dpi_int_en_s cn66xx; 1369232812Sjmallett struct cvmx_dpi_int_en_cn63xx cn68xx; 1370232812Sjmallett struct cvmx_dpi_int_en_cn63xx cn68xxp1; 1371232812Sjmallett struct cvmx_dpi_int_en_s cnf71xx; 1372215976Sjmallett}; 1373215976Sjmalletttypedef union cvmx_dpi_int_en cvmx_dpi_int_en_t; 1374215976Sjmallett 1375215976Sjmallett/** 1376215976Sjmallett * cvmx_dpi_int_reg 1377215976Sjmallett */ 1378232812Sjmallettunion cvmx_dpi_int_reg { 1379215976Sjmallett uint64_t u64; 1380232812Sjmallett struct cvmx_dpi_int_reg_s { 1381232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1382232812Sjmallett uint64_t reserved_28_63 : 36; 1383232812Sjmallett uint64_t sprt3_rst : 1; /**< DMA instruction was dropped because the source or 1384232812Sjmallett destination port was in reset. 1385232812Sjmallett this bit is set. */ 1386232812Sjmallett uint64_t sprt2_rst : 1; /**< DMA instruction was dropped because the source or 1387232812Sjmallett destination port was in reset. 1388232812Sjmallett this bit is set. */ 1389232812Sjmallett uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1390232812Sjmallett destination port was in reset. 1391232812Sjmallett this bit is set. */ 1392232812Sjmallett uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1393232812Sjmallett destination port was in reset. 1394232812Sjmallett this bit is set. */ 1395232812Sjmallett uint64_t reserved_23_23 : 1; 1396232812Sjmallett uint64_t req_badfil : 1; /**< DMA instruction unexpected fill 1397232812Sjmallett Instruction fill when none outstanding. */ 1398232812Sjmallett uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer 1399232812Sjmallett Next pointer was NULL. */ 1400232812Sjmallett uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction 1401232812Sjmallett Fetched instruction word was 0. */ 1402232812Sjmallett uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow 1403232812Sjmallett DPI tracks outstanding instructions fetches. 1404232812Sjmallett Interrupt will fire when FIFO underflows. */ 1405232812Sjmallett uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow 1406232812Sjmallett DPI tracks outstanding instructions fetches. 1407232812Sjmallett Interrupt will fire when FIFO overflows. */ 1408232812Sjmallett uint64_t req_badlen : 1; /**< DMA instruction fetch with length 1409232812Sjmallett Interrupt will fire if DPI forms an instruction 1410232812Sjmallett fetch with length of zero. */ 1411232812Sjmallett uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer 1412232812Sjmallett Interrupt will fire if DPI forms an instruction 1413232812Sjmallett fetch to the NULL pointer. */ 1414232812Sjmallett uint64_t dmadbo : 8; /**< DMAx doorbell overflow. 1415232812Sjmallett DPI has a 32-bit counter for each request's queue 1416232812Sjmallett outstanding doorbell counts. Interrupt will fire 1417232812Sjmallett if the count overflows. */ 1418232812Sjmallett uint64_t reserved_2_7 : 6; 1419232812Sjmallett uint64_t nfovr : 1; /**< CSR Fifo Overflow 1420232812Sjmallett DPI can store upto 16 CSR request. The FIFO will 1421232812Sjmallett overflow if that number is exceeded. */ 1422232812Sjmallett uint64_t nderr : 1; /**< NCB Decode Error 1423232812Sjmallett DPI received a NCB transaction on the outbound 1424232812Sjmallett bus to the DPI deviceID, but the command was not 1425232812Sjmallett recognized. */ 1426232812Sjmallett#else 1427232812Sjmallett uint64_t nderr : 1; 1428232812Sjmallett uint64_t nfovr : 1; 1429232812Sjmallett uint64_t reserved_2_7 : 6; 1430232812Sjmallett uint64_t dmadbo : 8; 1431232812Sjmallett uint64_t req_badadr : 1; 1432232812Sjmallett uint64_t req_badlen : 1; 1433232812Sjmallett uint64_t req_ovrflw : 1; 1434232812Sjmallett uint64_t req_undflw : 1; 1435232812Sjmallett uint64_t req_anull : 1; 1436232812Sjmallett uint64_t req_inull : 1; 1437232812Sjmallett uint64_t req_badfil : 1; 1438232812Sjmallett uint64_t reserved_23_23 : 1; 1439232812Sjmallett uint64_t sprt0_rst : 1; 1440232812Sjmallett uint64_t sprt1_rst : 1; 1441232812Sjmallett uint64_t sprt2_rst : 1; 1442232812Sjmallett uint64_t sprt3_rst : 1; 1443232812Sjmallett uint64_t reserved_28_63 : 36; 1444232812Sjmallett#endif 1445232812Sjmallett } s; 1446232812Sjmallett struct cvmx_dpi_int_reg_s cn61xx; 1447232812Sjmallett struct cvmx_dpi_int_reg_cn63xx { 1448232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1449215976Sjmallett uint64_t reserved_26_63 : 38; 1450215976Sjmallett uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1451215976Sjmallett destination port was in reset. 1452215976Sjmallett this bit is set. */ 1453215976Sjmallett uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1454215976Sjmallett destination port was in reset. 1455215976Sjmallett this bit is set. */ 1456215976Sjmallett uint64_t reserved_23_23 : 1; 1457215976Sjmallett uint64_t req_badfil : 1; /**< DMA instruction unexpected fill 1458215976Sjmallett Instruction fill when none outstanding. */ 1459215976Sjmallett uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer 1460215976Sjmallett Next pointer was NULL. */ 1461215976Sjmallett uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction 1462215976Sjmallett Fetched instruction word was 0. */ 1463215976Sjmallett uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow 1464215976Sjmallett DPI tracks outstanding instructions fetches. 1465215976Sjmallett Interrupt will fire when FIFO underflows. */ 1466215976Sjmallett uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow 1467215976Sjmallett DPI tracks outstanding instructions fetches. 1468215976Sjmallett Interrupt will fire when FIFO overflows. */ 1469215976Sjmallett uint64_t req_badlen : 1; /**< DMA instruction fetch with length 1470215976Sjmallett Interrupt will fire if DPI forms an instruction 1471215976Sjmallett fetch with length of zero. */ 1472215976Sjmallett uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer 1473215976Sjmallett Interrupt will fire if DPI forms an instruction 1474215976Sjmallett fetch to the NULL pointer. */ 1475215976Sjmallett uint64_t dmadbo : 8; /**< DMAx doorbell overflow. 1476215976Sjmallett DPI has a 32-bit counter for each request's queue 1477215976Sjmallett outstanding doorbell counts. Interrupt will fire 1478215976Sjmallett if the count overflows. */ 1479215976Sjmallett uint64_t reserved_2_7 : 6; 1480215976Sjmallett uint64_t nfovr : 1; /**< CSR Fifo Overflow 1481215976Sjmallett DPI can store upto 16 CSR request. The FIFO will 1482215976Sjmallett overflow if that number is exceeded. */ 1483215976Sjmallett uint64_t nderr : 1; /**< NCB Decode Error 1484215976Sjmallett DPI received a NCB transaction on the outbound 1485215976Sjmallett bus to the DPI deviceID, but the command was not 1486215976Sjmallett recognized. */ 1487215976Sjmallett#else 1488215976Sjmallett uint64_t nderr : 1; 1489215976Sjmallett uint64_t nfovr : 1; 1490215976Sjmallett uint64_t reserved_2_7 : 6; 1491215976Sjmallett uint64_t dmadbo : 8; 1492215976Sjmallett uint64_t req_badadr : 1; 1493215976Sjmallett uint64_t req_badlen : 1; 1494215976Sjmallett uint64_t req_ovrflw : 1; 1495215976Sjmallett uint64_t req_undflw : 1; 1496215976Sjmallett uint64_t req_anull : 1; 1497215976Sjmallett uint64_t req_inull : 1; 1498215976Sjmallett uint64_t req_badfil : 1; 1499215976Sjmallett uint64_t reserved_23_23 : 1; 1500215976Sjmallett uint64_t sprt0_rst : 1; 1501215976Sjmallett uint64_t sprt1_rst : 1; 1502215976Sjmallett uint64_t reserved_26_63 : 38; 1503215976Sjmallett#endif 1504232812Sjmallett } cn63xx; 1505232812Sjmallett struct cvmx_dpi_int_reg_cn63xx cn63xxp1; 1506232812Sjmallett struct cvmx_dpi_int_reg_s cn66xx; 1507232812Sjmallett struct cvmx_dpi_int_reg_cn63xx cn68xx; 1508232812Sjmallett struct cvmx_dpi_int_reg_cn63xx cn68xxp1; 1509232812Sjmallett struct cvmx_dpi_int_reg_s cnf71xx; 1510215976Sjmallett}; 1511215976Sjmalletttypedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t; 1512215976Sjmallett 1513215976Sjmallett/** 1514232812Sjmallett * cvmx_dpi_ncb#_cfg 1515232812Sjmallett */ 1516232812Sjmallettunion cvmx_dpi_ncbx_cfg { 1517232812Sjmallett uint64_t u64; 1518232812Sjmallett struct cvmx_dpi_ncbx_cfg_s { 1519232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1520232812Sjmallett uint64_t reserved_6_63 : 58; 1521232812Sjmallett uint64_t molr : 6; /**< Max Outstanding Load Requests 1522232812Sjmallett Limits the number of oustanding load requests on 1523232812Sjmallett the NCB interface. This value can range from 1 1524232812Sjmallett to 32. Setting a value of 0 will halt all read 1525232812Sjmallett traffic to the NCB interface. There are no 1526232812Sjmallett restrictions on when this value can be changed. */ 1527232812Sjmallett#else 1528232812Sjmallett uint64_t molr : 6; 1529232812Sjmallett uint64_t reserved_6_63 : 58; 1530232812Sjmallett#endif 1531232812Sjmallett } s; 1532232812Sjmallett struct cvmx_dpi_ncbx_cfg_s cn61xx; 1533232812Sjmallett struct cvmx_dpi_ncbx_cfg_s cn66xx; 1534232812Sjmallett struct cvmx_dpi_ncbx_cfg_s cn68xx; 1535232812Sjmallett struct cvmx_dpi_ncbx_cfg_s cnf71xx; 1536232812Sjmallett}; 1537232812Sjmalletttypedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t; 1538232812Sjmallett 1539232812Sjmallett/** 1540215976Sjmallett * cvmx_dpi_pint_info 1541215976Sjmallett * 1542215976Sjmallett * DPI_PINT_INFO = DPI Packet Interrupt Info 1543215976Sjmallett * 1544215976Sjmallett * DPI Packet Interrupt Info. 1545215976Sjmallett */ 1546232812Sjmallettunion cvmx_dpi_pint_info { 1547215976Sjmallett uint64_t u64; 1548232812Sjmallett struct cvmx_dpi_pint_info_s { 1549232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1550215976Sjmallett uint64_t reserved_14_63 : 50; 1551215976Sjmallett uint64_t iinfo : 6; /**< Packet Instruction Doorbell count overflow info */ 1552215976Sjmallett uint64_t reserved_6_7 : 2; 1553215976Sjmallett uint64_t sinfo : 6; /**< Packet Scatterlist Doorbell count overflow info */ 1554215976Sjmallett#else 1555215976Sjmallett uint64_t sinfo : 6; 1556215976Sjmallett uint64_t reserved_6_7 : 2; 1557215976Sjmallett uint64_t iinfo : 6; 1558215976Sjmallett uint64_t reserved_14_63 : 50; 1559215976Sjmallett#endif 1560215976Sjmallett } s; 1561232812Sjmallett struct cvmx_dpi_pint_info_s cn61xx; 1562215976Sjmallett struct cvmx_dpi_pint_info_s cn63xx; 1563215976Sjmallett struct cvmx_dpi_pint_info_s cn63xxp1; 1564232812Sjmallett struct cvmx_dpi_pint_info_s cn66xx; 1565232812Sjmallett struct cvmx_dpi_pint_info_s cn68xx; 1566232812Sjmallett struct cvmx_dpi_pint_info_s cn68xxp1; 1567232812Sjmallett struct cvmx_dpi_pint_info_s cnf71xx; 1568215976Sjmallett}; 1569215976Sjmalletttypedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t; 1570215976Sjmallett 1571215976Sjmallett/** 1572215976Sjmallett * cvmx_dpi_pkt_err_rsp 1573215976Sjmallett */ 1574232812Sjmallettunion cvmx_dpi_pkt_err_rsp { 1575215976Sjmallett uint64_t u64; 1576232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s { 1577232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1578215976Sjmallett uint64_t reserved_1_63 : 63; 1579215976Sjmallett uint64_t pkterr : 1; /**< Indicates that an ErrorResponse was received from 1580215976Sjmallett the I/O subsystem. */ 1581215976Sjmallett#else 1582215976Sjmallett uint64_t pkterr : 1; 1583215976Sjmallett uint64_t reserved_1_63 : 63; 1584215976Sjmallett#endif 1585215976Sjmallett } s; 1586232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn61xx; 1587215976Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn63xx; 1588215976Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; 1589232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn66xx; 1590232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn68xx; 1591232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; 1592232812Sjmallett struct cvmx_dpi_pkt_err_rsp_s cnf71xx; 1593215976Sjmallett}; 1594215976Sjmalletttypedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t; 1595215976Sjmallett 1596215976Sjmallett/** 1597215976Sjmallett * cvmx_dpi_req_err_rsp 1598215976Sjmallett */ 1599232812Sjmallettunion cvmx_dpi_req_err_rsp { 1600215976Sjmallett uint64_t u64; 1601232812Sjmallett struct cvmx_dpi_req_err_rsp_s { 1602232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1603215976Sjmallett uint64_t reserved_8_63 : 56; 1604215976Sjmallett uint64_t qerr : 8; /**< Indicates which instruction queue received an 1605215976Sjmallett ErrorResponse from the I/O subsystem. 1606215976Sjmallett SW must clear the bit before the the cooresponding 1607215976Sjmallett instruction queue will continue processing 1608215976Sjmallett instructions if DPI_REQ_ERR_RSP_EN[EN] is set. */ 1609215976Sjmallett#else 1610215976Sjmallett uint64_t qerr : 8; 1611215976Sjmallett uint64_t reserved_8_63 : 56; 1612215976Sjmallett#endif 1613215976Sjmallett } s; 1614232812Sjmallett struct cvmx_dpi_req_err_rsp_s cn61xx; 1615215976Sjmallett struct cvmx_dpi_req_err_rsp_s cn63xx; 1616215976Sjmallett struct cvmx_dpi_req_err_rsp_s cn63xxp1; 1617232812Sjmallett struct cvmx_dpi_req_err_rsp_s cn66xx; 1618232812Sjmallett struct cvmx_dpi_req_err_rsp_s cn68xx; 1619232812Sjmallett struct cvmx_dpi_req_err_rsp_s cn68xxp1; 1620232812Sjmallett struct cvmx_dpi_req_err_rsp_s cnf71xx; 1621215976Sjmallett}; 1622215976Sjmalletttypedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t; 1623215976Sjmallett 1624215976Sjmallett/** 1625215976Sjmallett * cvmx_dpi_req_err_rsp_en 1626215976Sjmallett */ 1627232812Sjmallettunion cvmx_dpi_req_err_rsp_en { 1628215976Sjmallett uint64_t u64; 1629232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s { 1630232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1631215976Sjmallett uint64_t reserved_8_63 : 56; 1632215976Sjmallett uint64_t en : 8; /**< Indicates which instruction queues should stop 1633215976Sjmallett dispatching instructions when an ErrorResponse 1634215976Sjmallett is received from the I/O subsystem. */ 1635215976Sjmallett#else 1636215976Sjmallett uint64_t en : 8; 1637215976Sjmallett uint64_t reserved_8_63 : 56; 1638215976Sjmallett#endif 1639215976Sjmallett } s; 1640232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn61xx; 1641215976Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn63xx; 1642215976Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; 1643232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn66xx; 1644232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn68xx; 1645232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; 1646232812Sjmallett struct cvmx_dpi_req_err_rsp_en_s cnf71xx; 1647215976Sjmallett}; 1648215976Sjmalletttypedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t; 1649215976Sjmallett 1650215976Sjmallett/** 1651215976Sjmallett * cvmx_dpi_req_err_rst 1652215976Sjmallett */ 1653232812Sjmallettunion cvmx_dpi_req_err_rst { 1654215976Sjmallett uint64_t u64; 1655232812Sjmallett struct cvmx_dpi_req_err_rst_s { 1656232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1657215976Sjmallett uint64_t reserved_8_63 : 56; 1658215976Sjmallett uint64_t qerr : 8; /**< Indicates which instruction queue dropped an 1659215976Sjmallett instruction because the source or destination 1660215976Sjmallett was in reset. 1661215976Sjmallett SW must clear the bit before the the cooresponding 1662215976Sjmallett instruction queue will continue processing 1663215976Sjmallett instructions if DPI_REQ_ERR_RST_EN[EN] is set. */ 1664215976Sjmallett#else 1665215976Sjmallett uint64_t qerr : 8; 1666215976Sjmallett uint64_t reserved_8_63 : 56; 1667215976Sjmallett#endif 1668215976Sjmallett } s; 1669232812Sjmallett struct cvmx_dpi_req_err_rst_s cn61xx; 1670215976Sjmallett struct cvmx_dpi_req_err_rst_s cn63xx; 1671215976Sjmallett struct cvmx_dpi_req_err_rst_s cn63xxp1; 1672232812Sjmallett struct cvmx_dpi_req_err_rst_s cn66xx; 1673232812Sjmallett struct cvmx_dpi_req_err_rst_s cn68xx; 1674232812Sjmallett struct cvmx_dpi_req_err_rst_s cn68xxp1; 1675232812Sjmallett struct cvmx_dpi_req_err_rst_s cnf71xx; 1676215976Sjmallett}; 1677215976Sjmalletttypedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t; 1678215976Sjmallett 1679215976Sjmallett/** 1680215976Sjmallett * cvmx_dpi_req_err_rst_en 1681215976Sjmallett */ 1682232812Sjmallettunion cvmx_dpi_req_err_rst_en { 1683215976Sjmallett uint64_t u64; 1684232812Sjmallett struct cvmx_dpi_req_err_rst_en_s { 1685232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1686215976Sjmallett uint64_t reserved_8_63 : 56; 1687215976Sjmallett uint64_t en : 8; /**< Indicates which instruction queues should stop 1688215976Sjmallett dispatching instructions when an instruction 1689215976Sjmallett is dropped because the source or destination port 1690215976Sjmallett is in reset. */ 1691215976Sjmallett#else 1692215976Sjmallett uint64_t en : 8; 1693215976Sjmallett uint64_t reserved_8_63 : 56; 1694215976Sjmallett#endif 1695215976Sjmallett } s; 1696232812Sjmallett struct cvmx_dpi_req_err_rst_en_s cn61xx; 1697215976Sjmallett struct cvmx_dpi_req_err_rst_en_s cn63xx; 1698215976Sjmallett struct cvmx_dpi_req_err_rst_en_s cn63xxp1; 1699232812Sjmallett struct cvmx_dpi_req_err_rst_en_s cn66xx; 1700232812Sjmallett struct cvmx_dpi_req_err_rst_en_s cn68xx; 1701232812Sjmallett struct cvmx_dpi_req_err_rst_en_s cn68xxp1; 1702232812Sjmallett struct cvmx_dpi_req_err_rst_en_s cnf71xx; 1703215976Sjmallett}; 1704215976Sjmalletttypedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t; 1705215976Sjmallett 1706215976Sjmallett/** 1707232812Sjmallett * cvmx_dpi_req_err_skip_comp 1708232812Sjmallett */ 1709232812Sjmallettunion cvmx_dpi_req_err_skip_comp { 1710232812Sjmallett uint64_t u64; 1711232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s { 1712232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1713232812Sjmallett uint64_t reserved_24_63 : 40; 1714232812Sjmallett uint64_t en_rst : 8; /**< Indicates which instruction queue should skip the 1715232812Sjmallett completion phase once an port reset is 1716232812Sjmallett detected as indicated by DPI_REQ_ERR_RST. All 1717232812Sjmallett completions to the effected instruction queue 1718232812Sjmallett will be skipped as long as 1719232812Sjmallett DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or 1720232812Sjmallett DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are 1721232812Sjmallett set. */ 1722232812Sjmallett uint64_t reserved_8_15 : 8; 1723232812Sjmallett uint64_t en_rsp : 8; /**< Indicates which instruction queue should skip the 1724232812Sjmallett completion phase once an ErrorResponse is 1725232812Sjmallett detected as indicated by DPI_REQ_ERR_RSP. All 1726232812Sjmallett completions to the effected instruction queue 1727232812Sjmallett will be skipped as long as 1728232812Sjmallett DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or 1729232812Sjmallett DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are 1730232812Sjmallett set. */ 1731232812Sjmallett#else 1732232812Sjmallett uint64_t en_rsp : 8; 1733232812Sjmallett uint64_t reserved_8_15 : 8; 1734232812Sjmallett uint64_t en_rst : 8; 1735232812Sjmallett uint64_t reserved_24_63 : 40; 1736232812Sjmallett#endif 1737232812Sjmallett } s; 1738232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s cn61xx; 1739232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s cn66xx; 1740232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s cn68xx; 1741232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; 1742232812Sjmallett struct cvmx_dpi_req_err_skip_comp_s cnf71xx; 1743232812Sjmallett}; 1744232812Sjmalletttypedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t; 1745232812Sjmallett 1746232812Sjmallett/** 1747215976Sjmallett * cvmx_dpi_req_gbl_en 1748215976Sjmallett */ 1749232812Sjmallettunion cvmx_dpi_req_gbl_en { 1750215976Sjmallett uint64_t u64; 1751232812Sjmallett struct cvmx_dpi_req_gbl_en_s { 1752232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1753215976Sjmallett uint64_t reserved_8_63 : 56; 1754215976Sjmallett uint64_t qen : 8; /**< Indicates which instruction queues are enabled and 1755215976Sjmallett can dispatch instructions to a requesting engine. */ 1756215976Sjmallett#else 1757215976Sjmallett uint64_t qen : 8; 1758215976Sjmallett uint64_t reserved_8_63 : 56; 1759215976Sjmallett#endif 1760215976Sjmallett } s; 1761232812Sjmallett struct cvmx_dpi_req_gbl_en_s cn61xx; 1762215976Sjmallett struct cvmx_dpi_req_gbl_en_s cn63xx; 1763215976Sjmallett struct cvmx_dpi_req_gbl_en_s cn63xxp1; 1764232812Sjmallett struct cvmx_dpi_req_gbl_en_s cn66xx; 1765232812Sjmallett struct cvmx_dpi_req_gbl_en_s cn68xx; 1766232812Sjmallett struct cvmx_dpi_req_gbl_en_s cn68xxp1; 1767232812Sjmallett struct cvmx_dpi_req_gbl_en_s cnf71xx; 1768215976Sjmallett}; 1769215976Sjmalletttypedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t; 1770215976Sjmallett 1771215976Sjmallett/** 1772215976Sjmallett * cvmx_dpi_sli_prt#_cfg 1773215976Sjmallett * 1774215976Sjmallett * DPI_SLI_PRTx_CFG = DPI SLI Port Configuration 1775215976Sjmallett * 1776215976Sjmallett * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use 1777215976Sjmallett */ 1778232812Sjmallettunion cvmx_dpi_sli_prtx_cfg { 1779215976Sjmallett uint64_t u64; 1780232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_s { 1781232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1782215976Sjmallett uint64_t reserved_25_63 : 39; 1783215976Sjmallett uint64_t halt : 1; /**< When set, HALT indicates that the MAC has detected 1784215976Sjmallett a reset condition. No further instructions that 1785215976Sjmallett reference the MAC from any instruction Q will be 1786215976Sjmallett issued until the MAC comes out of reset and HALT 1787215976Sjmallett is cleared in SLI_CTL_PORTx[DIS_PORT]. */ 1788232812Sjmallett uint64_t qlm_cfg : 4; /**< QLM_CFG is a function of MIO_QLMx_CFG[QLM_CFG] 1789232812Sjmallett QLM_CFG may contain values that are not normally 1790232812Sjmallett used for DMA and/or packet operations. 1791232812Sjmallett QLM_CFG does not indicate if a port is disabled. 1792232812Sjmallett MIO_QLMx_CFG can be used for more complete QLM 1793232812Sjmallett configuration information. 1794232812Sjmallett 0000 = MAC is PCIe 1x4 (QLM) or 1x2 (DLM) 1795232812Sjmallett 0001 = MAC is PCIe 2x1 (DLM only) 1796232812Sjmallett 0010 = MAC is SGMII 1797232812Sjmallett 0011 = MAC is XAUI 1798232812Sjmallett all other encodings are RESERVED */ 1799232812Sjmallett uint64_t reserved_17_19 : 3; 1800232812Sjmallett uint64_t rd_mode : 1; /**< Read Mode 1801232812Sjmallett 0=Exact Read Mode 1802232812Sjmallett If the port is a PCIe port, the HW reads on a 1803232812Sjmallett 4B granularity. In this mode, the HW may break 1804232812Sjmallett a given read into 3 operations to satisify 1805232812Sjmallett PCIe rules. 1806232812Sjmallett If the port is a SRIO port, the HW follows the 1807232812Sjmallett SRIO read rules from the SRIO specification and 1808232812Sjmallett only issues 32*n, 16, and 8 byte operations 1809232812Sjmallett on the SRIO bus. 1810232812Sjmallett 1=Block Mode 1811232812Sjmallett The HW will read more data than requested in 1812232812Sjmallett order to minimize the number of operations 1813232812Sjmallett necessary to complete the operation. 1814232812Sjmallett The memory region must be memory like. */ 1815232812Sjmallett uint64_t reserved_14_15 : 2; 1816232812Sjmallett uint64_t molr : 6; /**< Max Outstanding Load Requests 1817232812Sjmallett Limits the number of oustanding load requests on 1818232812Sjmallett the port by restricting the number of tags 1819232812Sjmallett used by the SLI to track load responses. This 1820232812Sjmallett value can range from 1 to 32 depending on the MAC 1821232812Sjmallett type and number of lanes. 1822232812Sjmallett MAC == PCIe: Max is 32 1823232812Sjmallett MAC == sRio / 4 lanes: Max is 32 1824232812Sjmallett MAC == sRio / 2 lanes: Max is 16 1825232812Sjmallett MAC == sRio / 1 lane: Max is 8 1826232812Sjmallett Reset value is computed based on the MAC config. 1827232812Sjmallett Setting MOLR to a value of 0 will halt all read 1828232812Sjmallett traffic to the port. There are no restrictions 1829232812Sjmallett on when this value can be changed. */ 1830232812Sjmallett uint64_t mps_lim : 1; /**< MAC memory space write requests cannot cross the 1831232812Sjmallett (naturally-aligned) MPS boundary. 1832232812Sjmallett When clear, DPI is allowed to issue a MAC memory 1833232812Sjmallett space read that crosses the naturally-aligned 1834232812Sjmallett boundary of size defined by MPS. (DPI will still 1835232812Sjmallett only cross the boundary when it would eliminate a 1836232812Sjmallett write by doing so.) 1837232812Sjmallett When set, DPI will never issue a MAC memory space 1838232812Sjmallett write that crosses the naturally-aligned boundary 1839232812Sjmallett of size defined by MPS. */ 1840232812Sjmallett uint64_t reserved_5_6 : 2; 1841232812Sjmallett uint64_t mps : 1; /**< Max Payload Size 1842232812Sjmallett 0 = 128B 1843232812Sjmallett 1 = 256B 1844232812Sjmallett For PCIe MACs, this MPS size must not exceed 1845232812Sjmallett the size selected by PCIE*_CFG030[MPS]. 1846232812Sjmallett For sRIO MACs, all MPS values are allowed. */ 1847232812Sjmallett uint64_t mrrs_lim : 1; /**< MAC memory space read requests cannot cross the 1848232812Sjmallett (naturally-aligned) MRRS boundary. 1849232812Sjmallett When clear, DPI is allowed to issue a MAC memory 1850232812Sjmallett space read that crosses the naturally-aligned 1851232812Sjmallett boundary of size defined by MRRS. (DPI will still 1852232812Sjmallett only cross the boundary when it would eliminate a 1853232812Sjmallett read by doing so.) 1854232812Sjmallett When set, DPI will never issue a MAC memory space 1855232812Sjmallett read that crosses the naturally-aligned boundary 1856232812Sjmallett of size defined by MRRS. */ 1857232812Sjmallett uint64_t reserved_2_2 : 1; 1858232812Sjmallett uint64_t mrrs : 2; /**< Max Read Request Size 1859232812Sjmallett 0 = 128B 1860232812Sjmallett 1 = 256B 1861232812Sjmallett 2 = 512B 1862232812Sjmallett 3 = 1024B 1863232812Sjmallett For PCIe MACs, this MRRS size must not exceed 1864232812Sjmallett the size selected by PCIE*_CFG030[MRRS]. 1865232812Sjmallett For sRIO MACs, this MRRS size must be <= 256B. */ 1866232812Sjmallett#else 1867232812Sjmallett uint64_t mrrs : 2; 1868232812Sjmallett uint64_t reserved_2_2 : 1; 1869232812Sjmallett uint64_t mrrs_lim : 1; 1870232812Sjmallett uint64_t mps : 1; 1871232812Sjmallett uint64_t reserved_5_6 : 2; 1872232812Sjmallett uint64_t mps_lim : 1; 1873232812Sjmallett uint64_t molr : 6; 1874232812Sjmallett uint64_t reserved_14_15 : 2; 1875232812Sjmallett uint64_t rd_mode : 1; 1876232812Sjmallett uint64_t reserved_17_19 : 3; 1877232812Sjmallett uint64_t qlm_cfg : 4; 1878232812Sjmallett uint64_t halt : 1; 1879232812Sjmallett uint64_t reserved_25_63 : 39; 1880232812Sjmallett#endif 1881232812Sjmallett } s; 1882232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_s cn61xx; 1883232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_cn63xx { 1884232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1885232812Sjmallett uint64_t reserved_25_63 : 39; 1886232812Sjmallett uint64_t halt : 1; /**< When set, HALT indicates that the MAC has detected 1887232812Sjmallett a reset condition. No further instructions that 1888232812Sjmallett reference the MAC from any instruction Q will be 1889232812Sjmallett issued until the MAC comes out of reset and HALT 1890232812Sjmallett is cleared in SLI_CTL_PORTx[DIS_PORT]. */ 1891215976Sjmallett uint64_t reserved_21_23 : 3; 1892215976Sjmallett uint64_t qlm_cfg : 1; /**< Read only copy of the QLM CFG pin 1893232812Sjmallett Since QLM_CFG is simply a copy of the QLM CFG 1894232812Sjmallett pins, it may reflect values that are not normal 1895232812Sjmallett for DMA or packet operations. QLM_CFG does not 1896232812Sjmallett indicate if a port is disabled. 1897215976Sjmallett 0= MAC is PCIe 1898215976Sjmallett 1= MAC is SRIO */ 1899215976Sjmallett uint64_t reserved_17_19 : 3; 1900215976Sjmallett uint64_t rd_mode : 1; /**< Read Mode 1901215976Sjmallett 0=Exact Read Mode 1902215976Sjmallett If the port is a PCIe port, the HW reads on a 1903215976Sjmallett 4B granularity. In this mode, the HW may break 1904215976Sjmallett a given read into 3 operations to satisify 1905215976Sjmallett PCIe rules. 1906215976Sjmallett If the port is a SRIO port, the HW follows the 1907215976Sjmallett SRIO read rules from the SRIO specification and 1908215976Sjmallett only issues 32*n, 16, and 8 byte operations 1909215976Sjmallett on the SRIO bus. 1910215976Sjmallett 1=Block Mode 1911215976Sjmallett The HW will read more data than requested in 1912215976Sjmallett order to minimize the number of operations 1913215976Sjmallett necessary to complete the operation. 1914215976Sjmallett The memory region must be memory like. */ 1915215976Sjmallett uint64_t reserved_14_15 : 2; 1916215976Sjmallett uint64_t molr : 6; /**< Max Outstanding Load Requests 1917215976Sjmallett Limits the number of oustanding load requests on 1918215976Sjmallett the port by restricting the number of tags 1919215976Sjmallett used by the SLI to track load responses. This 1920215976Sjmallett value can range from 1 to 32. Setting a value of 1921215976Sjmallett 0 will halt all read traffic to the port. There 1922215976Sjmallett are no restrictions on when this value 1923215976Sjmallett can be changed. */ 1924215976Sjmallett uint64_t mps_lim : 1; /**< MAC memory space write requests cannot cross the 1925215976Sjmallett (naturally-aligned) MPS boundary. 1926215976Sjmallett When clear, DPI is allowed to issue a MAC memory 1927215976Sjmallett space read that crosses the naturally-aligned 1928215976Sjmallett boundary of size defined by MPS. (DPI will still 1929215976Sjmallett only cross the boundary when it would eliminate a 1930215976Sjmallett write by doing so.) 1931215976Sjmallett When set, DPI will never issue a MAC memory space 1932215976Sjmallett write that crosses the naturally-aligned boundary 1933215976Sjmallett of size defined by MPS. */ 1934215976Sjmallett uint64_t reserved_5_6 : 2; 1935215976Sjmallett uint64_t mps : 1; /**< Max Payload Size 1936215976Sjmallett 0 = 128B 1937215976Sjmallett 1 = 256B 1938215976Sjmallett For PCIe MACs, this MPS size must not exceed 1939215976Sjmallett the size selected by PCIE*_CFG030[MPS]. 1940215976Sjmallett For sRIO MACs, all MPS values are allowed. */ 1941215976Sjmallett uint64_t mrrs_lim : 1; /**< MAC memory space read requests cannot cross the 1942215976Sjmallett (naturally-aligned) MRRS boundary. 1943215976Sjmallett When clear, DPI is allowed to issue a MAC memory 1944215976Sjmallett space read that crosses the naturally-aligned 1945215976Sjmallett boundary of size defined by MRRS. (DPI will still 1946215976Sjmallett only cross the boundary when it would eliminate a 1947215976Sjmallett read by doing so.) 1948215976Sjmallett When set, DPI will never issue a MAC memory space 1949215976Sjmallett read that crosses the naturally-aligned boundary 1950215976Sjmallett of size defined by MRRS. */ 1951215976Sjmallett uint64_t reserved_2_2 : 1; 1952215976Sjmallett uint64_t mrrs : 2; /**< Max Read Request Size 1953215976Sjmallett 0 = 128B 1954215976Sjmallett 1 = 256B 1955215976Sjmallett 2 = 512B 1956215976Sjmallett 3 = 1024B 1957215976Sjmallett For PCIe MACs, this MRRS size must not exceed 1958215976Sjmallett the size selected by PCIE*_CFG030[MRRS]. 1959215976Sjmallett For sRIO MACs, this MRRS size must be <= 256B. */ 1960215976Sjmallett#else 1961215976Sjmallett uint64_t mrrs : 2; 1962215976Sjmallett uint64_t reserved_2_2 : 1; 1963215976Sjmallett uint64_t mrrs_lim : 1; 1964215976Sjmallett uint64_t mps : 1; 1965215976Sjmallett uint64_t reserved_5_6 : 2; 1966215976Sjmallett uint64_t mps_lim : 1; 1967215976Sjmallett uint64_t molr : 6; 1968215976Sjmallett uint64_t reserved_14_15 : 2; 1969215976Sjmallett uint64_t rd_mode : 1; 1970215976Sjmallett uint64_t reserved_17_19 : 3; 1971215976Sjmallett uint64_t qlm_cfg : 1; 1972215976Sjmallett uint64_t reserved_21_23 : 3; 1973215976Sjmallett uint64_t halt : 1; 1974215976Sjmallett uint64_t reserved_25_63 : 39; 1975215976Sjmallett#endif 1976232812Sjmallett } cn63xx; 1977232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; 1978232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_s cn66xx; 1979232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; 1980232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; 1981232812Sjmallett struct cvmx_dpi_sli_prtx_cfg_s cnf71xx; 1982215976Sjmallett}; 1983215976Sjmalletttypedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t; 1984215976Sjmallett 1985215976Sjmallett/** 1986215976Sjmallett * cvmx_dpi_sli_prt#_err 1987215976Sjmallett * 1988215976Sjmallett * DPI_SLI_PRTx_ERR = DPI SLI Port Error Info 1989215976Sjmallett * 1990215976Sjmallett * Logs the Address and Request Queue associated with the reported SLI error response 1991215976Sjmallett */ 1992232812Sjmallettunion cvmx_dpi_sli_prtx_err { 1993215976Sjmallett uint64_t u64; 1994232812Sjmallett struct cvmx_dpi_sli_prtx_err_s { 1995232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1996232812Sjmallett uint64_t addr : 61; /**< Address of the failed load request. 1997232812Sjmallett Address is locked along with the 1998232812Sjmallett DPI_SLI_PRTx_ERR_INFO register. 1999232812Sjmallett See the DPI_SLI_PRTx_ERR_INFO[LOCK] description 2000232812Sjmallett for further information. */ 2001215976Sjmallett uint64_t reserved_0_2 : 3; 2002215976Sjmallett#else 2003215976Sjmallett uint64_t reserved_0_2 : 3; 2004215976Sjmallett uint64_t addr : 61; 2005215976Sjmallett#endif 2006215976Sjmallett } s; 2007232812Sjmallett struct cvmx_dpi_sli_prtx_err_s cn61xx; 2008215976Sjmallett struct cvmx_dpi_sli_prtx_err_s cn63xx; 2009215976Sjmallett struct cvmx_dpi_sli_prtx_err_s cn63xxp1; 2010232812Sjmallett struct cvmx_dpi_sli_prtx_err_s cn66xx; 2011232812Sjmallett struct cvmx_dpi_sli_prtx_err_s cn68xx; 2012232812Sjmallett struct cvmx_dpi_sli_prtx_err_s cn68xxp1; 2013232812Sjmallett struct cvmx_dpi_sli_prtx_err_s cnf71xx; 2014215976Sjmallett}; 2015215976Sjmalletttypedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t; 2016215976Sjmallett 2017215976Sjmallett/** 2018215976Sjmallett * cvmx_dpi_sli_prt#_err_info 2019215976Sjmallett * 2020215976Sjmallett * DPI_SLI_PRTx_ERR_INFO = DPI SLI Port Error Info 2021215976Sjmallett * 2022215976Sjmallett * Logs the Address and Request Queue associated with the reported SLI error response 2023215976Sjmallett */ 2024232812Sjmallettunion cvmx_dpi_sli_prtx_err_info { 2025215976Sjmallett uint64_t u64; 2026232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s { 2027232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2028215976Sjmallett uint64_t reserved_9_63 : 55; 2029215976Sjmallett uint64_t lock : 1; /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have 2030232812Sjmallett captured and locked contents. 2031232812Sjmallett When Octeon first detects an ErrorResponse, the 2032232812Sjmallett TYPE, REQQ, and ADDR of the error is saved and an 2033232812Sjmallett internal lock state is set so the data associated 2034232812Sjmallett with the initial error is perserved. 2035232812Sjmallett Subsequent ErrorResponses will optionally raise 2036232812Sjmallett an interrupt, but will not modify the TYPE, REQQ, 2037232812Sjmallett or ADDR fields until the internal lock state is 2038232812Sjmallett cleared. 2039232812Sjmallett SW can clear the internal lock state by writting 2040232812Sjmallett a '1' to the appropriate bit in either 2041232812Sjmallett DPI_REQ_ERR_RSP or DPI_PKT_ERR_RSP depending on 2042232812Sjmallett the TYPE field. 2043232812Sjmallett Once the internal lock state is cleared, 2044232812Sjmallett the next ErrorResponse will set the TYPE, REQQ, 2045232812Sjmallett and ADDR for the new transaction. */ 2046215976Sjmallett uint64_t reserved_5_7 : 3; 2047215976Sjmallett uint64_t type : 1; /**< Type of transaction that caused the ErrorResponse. 2048215976Sjmallett 0=DMA Instruction 2049215976Sjmallett 1=PKT Instruction */ 2050215976Sjmallett uint64_t reserved_3_3 : 1; 2051215976Sjmallett uint64_t reqq : 3; /**< Request queue that made the failed load request. */ 2052215976Sjmallett#else 2053215976Sjmallett uint64_t reqq : 3; 2054215976Sjmallett uint64_t reserved_3_3 : 1; 2055215976Sjmallett uint64_t type : 1; 2056215976Sjmallett uint64_t reserved_5_7 : 3; 2057215976Sjmallett uint64_t lock : 1; 2058215976Sjmallett uint64_t reserved_9_63 : 55; 2059215976Sjmallett#endif 2060215976Sjmallett } s; 2061232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn61xx; 2062215976Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn63xx; 2063215976Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; 2064232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn66xx; 2065232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn68xx; 2066232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; 2067232812Sjmallett struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; 2068215976Sjmallett}; 2069215976Sjmalletttypedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t; 2070215976Sjmallett 2071215976Sjmallett#endif 2072