1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-dfa-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon dfa. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_DFA_DEFS_H__ 53232812Sjmallett#define __CVMX_DFA_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_DFA_BIST0_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60215976Sjmallett cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370007F0ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_DFA_BIST1_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71215976Sjmallett cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370007F8ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_DFA_BST0_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 82215976Sjmallett cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800300007F0ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_DFA_BST1_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 93215976Sjmallett cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800300007F8ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_DFA_CFG_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 104215976Sjmallett cvmx_warn("CVMX_DFA_CFG not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000000ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(0x0001180030000000ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_DFA_CONFIG_FUNC(void) 113215976Sjmallett{ 114232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 115215976Sjmallett cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000000ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_DFA_CONFIG (CVMX_ADD_IO_SEG(0x0001180037000000ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_DFA_CONTROL_FUNC(void) 124215976Sjmallett{ 125232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 126215976Sjmallett cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000020ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_DFA_CONTROL (CVMX_ADD_IO_SEG(0x0001180037000020ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_DFA_DBELL_FUNC(void) 135215976Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 137215976Sjmallett cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370000000000ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_DFA_DBELL (CVMX_ADD_IO_SEG(0x0001370000000000ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void) 146215976Sjmallett{ 147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 148215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000210ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_DFA_DDR2_ADDR (CVMX_ADD_IO_SEG(0x0001180030000210ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void) 157215976Sjmallett{ 158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 159215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000080ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_DFA_DDR2_BUS (CVMX_ADD_IO_SEG(0x0001180030000080ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void) 168215976Sjmallett{ 169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 170215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000208ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_DFA_DDR2_CFG (CVMX_ADD_IO_SEG(0x0001180030000208ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void) 179215976Sjmallett{ 180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 181215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000090ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_DFA_DDR2_COMP (CVMX_ADD_IO_SEG(0x0001180030000090ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallett#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC() 189215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void) 190215976Sjmallett{ 191215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 192215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n"); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000268ull); 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_DFA_DDR2_EMRS (CVMX_ADD_IO_SEG(0x0001180030000268ull)) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallett#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC() 200215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void) 201215976Sjmallett{ 202215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 203215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n"); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000078ull); 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_DFA_DDR2_FCNT (CVMX_ADD_IO_SEG(0x0001180030000078ull)) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallett#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC() 211215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void) 212215976Sjmallett{ 213215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 214215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n"); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000260ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_DFA_DDR2_MRS (CVMX_ADD_IO_SEG(0x0001180030000260ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallett#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC() 222215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void) 223215976Sjmallett{ 224215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 225215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n"); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000070ull); 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_DFA_DDR2_OPT (CVMX_ADD_IO_SEG(0x0001180030000070ull)) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallett#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC() 233215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void) 234215976Sjmallett{ 235215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 236215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n"); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000088ull); 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_DFA_DDR2_PLL (CVMX_ADD_IO_SEG(0x0001180030000088ull)) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallett#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC() 244215976Sjmallettstatic inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void) 245215976Sjmallett{ 246215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 247215976Sjmallett cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n"); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000218ull); 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_DFA_DDR2_TMG (CVMX_ADD_IO_SEG(0x0001180030000218ull)) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallett#define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC() 255215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG0_FUNC(void) 256215976Sjmallett{ 257232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 258215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n"); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000040ull); 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_DFA_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180037000040ull)) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallett#define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC() 266215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG1_FUNC(void) 267215976Sjmallett{ 268232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 269215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n"); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000048ull); 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_DFA_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180037000048ull)) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallett#define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC() 277215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG2_FUNC(void) 278215976Sjmallett{ 279232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 280215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n"); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000050ull); 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_DFA_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180037000050ull)) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallett#define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC() 288215976Sjmallettstatic inline uint64_t CVMX_DFA_DEBUG3_FUNC(void) 289215976Sjmallett{ 290232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 291215976Sjmallett cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n"); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000058ull); 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_DFA_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180037000058ull)) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallett#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC() 299215976Sjmallettstatic inline uint64_t CVMX_DFA_DIFCTL_FUNC(void) 300215976Sjmallett{ 301232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 302215976Sjmallett cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n"); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370600000000ull); 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_DFA_DIFCTL (CVMX_ADD_IO_SEG(0x0001370600000000ull)) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallett#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC() 310215976Sjmallettstatic inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void) 311215976Sjmallett{ 312232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 313215976Sjmallett cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n"); 314215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370200000000ull); 315215976Sjmallett} 316215976Sjmallett#else 317215976Sjmallett#define CVMX_DFA_DIFRDPTR (CVMX_ADD_IO_SEG(0x0001370200000000ull)) 318215976Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallett#define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC() 321215976Sjmallettstatic inline uint64_t CVMX_DFA_DTCFADR_FUNC(void) 322215976Sjmallett{ 323232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 324215976Sjmallett cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n"); 325215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000060ull); 326215976Sjmallett} 327215976Sjmallett#else 328215976Sjmallett#define CVMX_DFA_DTCFADR (CVMX_ADD_IO_SEG(0x0001180037000060ull)) 329215976Sjmallett#endif 330215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331215976Sjmallett#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC() 332215976Sjmallettstatic inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void) 333215976Sjmallett{ 334215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 335215976Sjmallett cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n"); 336215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000200ull); 337215976Sjmallett} 338215976Sjmallett#else 339215976Sjmallett#define CVMX_DFA_ECLKCFG (CVMX_ADD_IO_SEG(0x0001180030000200ull)) 340215976Sjmallett#endif 341215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342215976Sjmallett#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC() 343215976Sjmallettstatic inline uint64_t CVMX_DFA_ERR_FUNC(void) 344215976Sjmallett{ 345215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 346215976Sjmallett cvmx_warn("CVMX_DFA_ERR not supported on this chip\n"); 347215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000028ull); 348215976Sjmallett} 349215976Sjmallett#else 350215976Sjmallett#define CVMX_DFA_ERR (CVMX_ADD_IO_SEG(0x0001180030000028ull)) 351215976Sjmallett#endif 352215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353215976Sjmallett#define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC() 354215976Sjmallettstatic inline uint64_t CVMX_DFA_ERROR_FUNC(void) 355215976Sjmallett{ 356232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 357215976Sjmallett cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n"); 358215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000028ull); 359215976Sjmallett} 360215976Sjmallett#else 361215976Sjmallett#define CVMX_DFA_ERROR (CVMX_ADD_IO_SEG(0x0001180037000028ull)) 362215976Sjmallett#endif 363215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364215976Sjmallett#define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC() 365215976Sjmallettstatic inline uint64_t CVMX_DFA_INTMSK_FUNC(void) 366215976Sjmallett{ 367232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 368215976Sjmallett cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n"); 369215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000030ull); 370215976Sjmallett} 371215976Sjmallett#else 372215976Sjmallett#define CVMX_DFA_INTMSK (CVMX_ADD_IO_SEG(0x0001180037000030ull)) 373215976Sjmallett#endif 374215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375215976Sjmallett#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC() 376215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void) 377215976Sjmallett{ 378215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 379215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n"); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000008ull); 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_DFA_MEMCFG0 (CVMX_ADD_IO_SEG(0x0001180030000008ull)) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallett#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC() 387215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void) 388215976Sjmallett{ 389215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 390215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n"); 391215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000010ull); 392215976Sjmallett} 393215976Sjmallett#else 394215976Sjmallett#define CVMX_DFA_MEMCFG1 (CVMX_ADD_IO_SEG(0x0001180030000010ull)) 395215976Sjmallett#endif 396215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397215976Sjmallett#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC() 398215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void) 399215976Sjmallett{ 400215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 401215976Sjmallett cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n"); 402215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000060ull); 403215976Sjmallett} 404215976Sjmallett#else 405215976Sjmallett#define CVMX_DFA_MEMCFG2 (CVMX_ADD_IO_SEG(0x0001180030000060ull)) 406215976Sjmallett#endif 407215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408215976Sjmallett#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC() 409215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMFADR_FUNC(void) 410215976Sjmallett{ 411215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 412215976Sjmallett cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n"); 413215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000030ull); 414215976Sjmallett} 415215976Sjmallett#else 416215976Sjmallett#define CVMX_DFA_MEMFADR (CVMX_ADD_IO_SEG(0x0001180030000030ull)) 417215976Sjmallett#endif 418215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419215976Sjmallett#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC() 420215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMFCR_FUNC(void) 421215976Sjmallett{ 422215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 423215976Sjmallett cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n"); 424215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000038ull); 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_DFA_MEMFCR (CVMX_ADD_IO_SEG(0x0001180030000038ull)) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallett#define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC() 431215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void) 432215976Sjmallett{ 433232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 434215976Sjmallett cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n"); 435215976Sjmallett return CVMX_ADD_IO_SEG(0x0001370700000000ull); 436215976Sjmallett} 437215976Sjmallett#else 438215976Sjmallett#define CVMX_DFA_MEMHIDAT (CVMX_ADD_IO_SEG(0x0001370700000000ull)) 439215976Sjmallett#endif 440215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441215976Sjmallett#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC() 442215976Sjmallettstatic inline uint64_t CVMX_DFA_MEMRLD_FUNC(void) 443215976Sjmallett{ 444215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 445215976Sjmallett cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n"); 446215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000018ull); 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_DFA_MEMRLD (CVMX_ADD_IO_SEG(0x0001180030000018ull)) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallett#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC() 453215976Sjmallettstatic inline uint64_t CVMX_DFA_NCBCTL_FUNC(void) 454215976Sjmallett{ 455215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 456215976Sjmallett cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n"); 457215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000020ull); 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_DFA_NCBCTL (CVMX_ADD_IO_SEG(0x0001180030000020ull)) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallett#define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC() 464215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void) 465215976Sjmallett{ 466232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 467215976Sjmallett cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n"); 468215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000090ull); 469215976Sjmallett} 470215976Sjmallett#else 471215976Sjmallett#define CVMX_DFA_PFC0_CNT (CVMX_ADD_IO_SEG(0x0001180037000090ull)) 472215976Sjmallett#endif 473215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474215976Sjmallett#define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC() 475215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void) 476215976Sjmallett{ 477232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 478215976Sjmallett cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n"); 479215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000088ull); 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_DFA_PFC0_CTL (CVMX_ADD_IO_SEG(0x0001180037000088ull)) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallett#define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC() 486215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void) 487215976Sjmallett{ 488232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 489215976Sjmallett cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n"); 490215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000A0ull); 491215976Sjmallett} 492215976Sjmallett#else 493215976Sjmallett#define CVMX_DFA_PFC1_CNT (CVMX_ADD_IO_SEG(0x00011800370000A0ull)) 494215976Sjmallett#endif 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallett#define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC() 497215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void) 498215976Sjmallett{ 499232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 500215976Sjmallett cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n"); 501215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000098ull); 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_DFA_PFC1_CTL (CVMX_ADD_IO_SEG(0x0001180037000098ull)) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallett#define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC() 508215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void) 509215976Sjmallett{ 510232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 511215976Sjmallett cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n"); 512215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000B0ull); 513215976Sjmallett} 514215976Sjmallett#else 515215976Sjmallett#define CVMX_DFA_PFC2_CNT (CVMX_ADD_IO_SEG(0x00011800370000B0ull)) 516215976Sjmallett#endif 517215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518215976Sjmallett#define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC() 519215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void) 520215976Sjmallett{ 521232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 522215976Sjmallett cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n"); 523215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000A8ull); 524215976Sjmallett} 525215976Sjmallett#else 526215976Sjmallett#define CVMX_DFA_PFC2_CTL (CVMX_ADD_IO_SEG(0x00011800370000A8ull)) 527215976Sjmallett#endif 528215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529215976Sjmallett#define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC() 530215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void) 531215976Sjmallett{ 532232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 533215976Sjmallett cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n"); 534215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000C0ull); 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_DFA_PFC3_CNT (CVMX_ADD_IO_SEG(0x00011800370000C0ull)) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallett#define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC() 541215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void) 542215976Sjmallett{ 543232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 544215976Sjmallett cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n"); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800370000B8ull); 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_DFA_PFC3_CTL (CVMX_ADD_IO_SEG(0x00011800370000B8ull)) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallett#define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC() 552215976Sjmallettstatic inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void) 553215976Sjmallett{ 554232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 555215976Sjmallett cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n"); 556215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180037000080ull); 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_DFA_PFC_GCTL (CVMX_ADD_IO_SEG(0x0001180037000080ull)) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallett#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC() 563215976Sjmallettstatic inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void) 564215976Sjmallett{ 565215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN58XX))) 566215976Sjmallett cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n"); 567215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000068ull); 568215976Sjmallett} 569215976Sjmallett#else 570215976Sjmallett#define CVMX_DFA_RODT_COMP_CTL (CVMX_ADD_IO_SEG(0x0001180030000068ull)) 571215976Sjmallett#endif 572215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573215976Sjmallett#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC() 574215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void) 575215976Sjmallett{ 576215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 577215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n"); 578215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000040ull); 579215976Sjmallett} 580215976Sjmallett#else 581215976Sjmallett#define CVMX_DFA_SBD_DBG0 (CVMX_ADD_IO_SEG(0x0001180030000040ull)) 582215976Sjmallett#endif 583215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584215976Sjmallett#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC() 585215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void) 586215976Sjmallett{ 587215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 588215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n"); 589215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000048ull); 590215976Sjmallett} 591215976Sjmallett#else 592215976Sjmallett#define CVMX_DFA_SBD_DBG1 (CVMX_ADD_IO_SEG(0x0001180030000048ull)) 593215976Sjmallett#endif 594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595215976Sjmallett#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC() 596215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void) 597215976Sjmallett{ 598215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 599215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n"); 600215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000050ull); 601215976Sjmallett} 602215976Sjmallett#else 603215976Sjmallett#define CVMX_DFA_SBD_DBG2 (CVMX_ADD_IO_SEG(0x0001180030000050ull)) 604215976Sjmallett#endif 605215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606215976Sjmallett#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC() 607215976Sjmallettstatic inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void) 608215976Sjmallett{ 609215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 610215976Sjmallett cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n"); 611215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180030000058ull); 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_DFA_SBD_DBG3 (CVMX_ADD_IO_SEG(0x0001180030000058ull)) 615215976Sjmallett#endif 616215976Sjmallett 617215976Sjmallett/** 618215976Sjmallett * cvmx_dfa_bist0 619215976Sjmallett * 620215976Sjmallett * DFA_BIST0 = DFA Bist Status (per-DTC) 621215976Sjmallett * 622215976Sjmallett * Description: 623215976Sjmallett */ 624232812Sjmallettunion cvmx_dfa_bist0 { 625215976Sjmallett uint64_t u64; 626232812Sjmallett struct cvmx_dfa_bist0_s { 627232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 628232812Sjmallett uint64_t reserved_27_63 : 37; 629232812Sjmallett uint64_t gfb : 3; /**< Bist Results for GFB RAM(s) (per-cluster) 630232812Sjmallett - 0: GOOD (or bist in progress/never run) 631232812Sjmallett - 1: BAD */ 632232812Sjmallett uint64_t reserved_22_23 : 2; 633232812Sjmallett uint64_t stx2 : 2; /**< Bist Results for STX2 RAM(s) 634232812Sjmallett - 0: GOOD (or bist in progress/never run) 635232812Sjmallett - 1: BAD */ 636232812Sjmallett uint64_t stx1 : 2; /**< Bist Results for STX1 RAM(s) 637232812Sjmallett - 0: GOOD (or bist in progress/never run) 638232812Sjmallett - 1: BAD */ 639232812Sjmallett uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 640232812Sjmallett - 0: GOOD (or bist in progress/never run) 641232812Sjmallett - 1: BAD */ 642232812Sjmallett uint64_t reserved_14_15 : 2; 643232812Sjmallett uint64_t dtx2 : 2; /**< Bist Results for DTX2 RAM(s) 644232812Sjmallett - 0: GOOD (or bist in progress/never run) 645232812Sjmallett - 1: BAD */ 646232812Sjmallett uint64_t dtx1 : 2; /**< Bist Results for DTX1 RAM(s) 647232812Sjmallett - 0: GOOD (or bist in progress/never run) 648232812Sjmallett - 1: BAD */ 649232812Sjmallett uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 650232812Sjmallett - 0: GOOD (or bist in progress/never run) 651232812Sjmallett - 1: BAD */ 652232812Sjmallett uint64_t reserved_7_7 : 1; 653232812Sjmallett uint64_t rdf : 3; /**< Bist Results for RWB RAM(s) (per-cluster) 654232812Sjmallett - 0: GOOD (or bist in progress/never run) 655232812Sjmallett - 1: BAD */ 656232812Sjmallett uint64_t reserved_3_3 : 1; 657232812Sjmallett uint64_t pdb : 3; /**< Bist Results for PDB RAM(s) (per-cluster) 658232812Sjmallett - 0: GOOD (or bist in progress/never run) 659232812Sjmallett - 1: BAD */ 660232812Sjmallett#else 661232812Sjmallett uint64_t pdb : 3; 662232812Sjmallett uint64_t reserved_3_3 : 1; 663232812Sjmallett uint64_t rdf : 3; 664232812Sjmallett uint64_t reserved_7_7 : 1; 665232812Sjmallett uint64_t dtx : 2; 666232812Sjmallett uint64_t dtx1 : 2; 667232812Sjmallett uint64_t dtx2 : 2; 668232812Sjmallett uint64_t reserved_14_15 : 2; 669232812Sjmallett uint64_t stx : 2; 670232812Sjmallett uint64_t stx1 : 2; 671232812Sjmallett uint64_t stx2 : 2; 672232812Sjmallett uint64_t reserved_22_23 : 2; 673232812Sjmallett uint64_t gfb : 3; 674232812Sjmallett uint64_t reserved_27_63 : 37; 675232812Sjmallett#endif 676232812Sjmallett } s; 677232812Sjmallett struct cvmx_dfa_bist0_cn61xx { 678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 679232812Sjmallett uint64_t reserved_25_63 : 39; 680232812Sjmallett uint64_t gfb : 1; /**< Bist Results for GFB RAM(s) (per-cluster) 681232812Sjmallett - 0: GOOD (or bist in progress/never run) 682232812Sjmallett - 1: BAD */ 683232812Sjmallett uint64_t reserved_18_23 : 6; 684232812Sjmallett uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 685232812Sjmallett - 0: GOOD (or bist in progress/never run) 686232812Sjmallett - 1: BAD */ 687232812Sjmallett uint64_t reserved_10_15 : 6; 688232812Sjmallett uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 689232812Sjmallett - 0: GOOD (or bist in progress/never run) 690232812Sjmallett - 1: BAD */ 691232812Sjmallett uint64_t reserved_5_7 : 3; 692232812Sjmallett uint64_t rdf : 1; /**< Bist Results for RWB RAM(s) (per-cluster) 693232812Sjmallett - 0: GOOD (or bist in progress/never run) 694232812Sjmallett - 1: BAD */ 695232812Sjmallett uint64_t reserved_1_3 : 3; 696232812Sjmallett uint64_t pdb : 1; /**< Bist Results for PDB RAM(s) (per-cluster) 697232812Sjmallett - 0: GOOD (or bist in progress/never run) 698232812Sjmallett - 1: BAD */ 699232812Sjmallett#else 700232812Sjmallett uint64_t pdb : 1; 701232812Sjmallett uint64_t reserved_1_3 : 3; 702232812Sjmallett uint64_t rdf : 1; 703232812Sjmallett uint64_t reserved_5_7 : 3; 704232812Sjmallett uint64_t dtx : 2; 705232812Sjmallett uint64_t reserved_10_15 : 6; 706232812Sjmallett uint64_t stx : 2; 707232812Sjmallett uint64_t reserved_18_23 : 6; 708232812Sjmallett uint64_t gfb : 1; 709232812Sjmallett uint64_t reserved_25_63 : 39; 710232812Sjmallett#endif 711232812Sjmallett } cn61xx; 712232812Sjmallett struct cvmx_dfa_bist0_cn63xx { 713232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 714215976Sjmallett uint64_t reserved_29_63 : 35; 715215976Sjmallett uint64_t mwb : 1; /**< Bist Results for MWB RAM(s) 716215976Sjmallett - 0: GOOD (or bist in progress/never run) 717215976Sjmallett - 1: BAD */ 718215976Sjmallett uint64_t reserved_25_27 : 3; 719215976Sjmallett uint64_t gfb : 1; /**< Bist Results for GFB RAM(s) 720215976Sjmallett - 0: GOOD (or bist in progress/never run) 721215976Sjmallett - 1: BAD */ 722215976Sjmallett uint64_t reserved_18_23 : 6; 723215976Sjmallett uint64_t stx : 2; /**< Bist Results for STX RAM(s) 724215976Sjmallett - 0: GOOD (or bist in progress/never run) 725215976Sjmallett - 1: BAD */ 726215976Sjmallett uint64_t reserved_10_15 : 6; 727215976Sjmallett uint64_t dtx : 2; /**< Bist Results for DTX RAM(s) 728215976Sjmallett - 0: GOOD (or bist in progress/never run) 729215976Sjmallett - 1: BAD */ 730215976Sjmallett uint64_t reserved_5_7 : 3; 731215976Sjmallett uint64_t rdf : 1; /**< Bist Results for RWB[3:0] RAM(s) 732215976Sjmallett - 0: GOOD (or bist in progress/never run) 733215976Sjmallett - 1: BAD */ 734215976Sjmallett uint64_t reserved_1_3 : 3; 735215976Sjmallett uint64_t pdb : 1; /**< Bist Results for PDB RAM(s) 736215976Sjmallett - 0: GOOD (or bist in progress/never run) 737215976Sjmallett - 1: BAD */ 738215976Sjmallett#else 739215976Sjmallett uint64_t pdb : 1; 740215976Sjmallett uint64_t reserved_1_3 : 3; 741215976Sjmallett uint64_t rdf : 1; 742215976Sjmallett uint64_t reserved_5_7 : 3; 743215976Sjmallett uint64_t dtx : 2; 744215976Sjmallett uint64_t reserved_10_15 : 6; 745215976Sjmallett uint64_t stx : 2; 746215976Sjmallett uint64_t reserved_18_23 : 6; 747215976Sjmallett uint64_t gfb : 1; 748215976Sjmallett uint64_t reserved_25_27 : 3; 749215976Sjmallett uint64_t mwb : 1; 750215976Sjmallett uint64_t reserved_29_63 : 35; 751215976Sjmallett#endif 752232812Sjmallett } cn63xx; 753232812Sjmallett struct cvmx_dfa_bist0_cn63xx cn63xxp1; 754232812Sjmallett struct cvmx_dfa_bist0_cn63xx cn66xx; 755232812Sjmallett struct cvmx_dfa_bist0_cn68xx { 756232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 757232812Sjmallett uint64_t reserved_30_63 : 34; 758232812Sjmallett uint64_t mrp : 2; /**< Bist Results for MRP RAM(s) (per-DLC) 759232812Sjmallett - 0: GOOD (or bist in progress/never run) 760232812Sjmallett - 1: BAD */ 761232812Sjmallett uint64_t reserved_27_27 : 1; 762232812Sjmallett uint64_t gfb : 3; /**< Bist Results for GFB RAM(s) (per-cluster) 763232812Sjmallett - 0: GOOD (or bist in progress/never run) 764232812Sjmallett - 1: BAD */ 765232812Sjmallett uint64_t reserved_22_23 : 2; 766232812Sjmallett uint64_t stx2 : 2; /**< Bist Results for STX2 RAM(s) 767232812Sjmallett - 0: GOOD (or bist in progress/never run) 768232812Sjmallett - 1: BAD */ 769232812Sjmallett uint64_t stx1 : 2; /**< Bist Results for STX1 RAM(s) 770232812Sjmallett - 0: GOOD (or bist in progress/never run) 771232812Sjmallett - 1: BAD */ 772232812Sjmallett uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 773232812Sjmallett - 0: GOOD (or bist in progress/never run) 774232812Sjmallett - 1: BAD */ 775232812Sjmallett uint64_t reserved_14_15 : 2; 776232812Sjmallett uint64_t dtx2 : 2; /**< Bist Results for DTX2 RAM(s) 777232812Sjmallett - 0: GOOD (or bist in progress/never run) 778232812Sjmallett - 1: BAD */ 779232812Sjmallett uint64_t dtx1 : 2; /**< Bist Results for DTX1 RAM(s) 780232812Sjmallett - 0: GOOD (or bist in progress/never run) 781232812Sjmallett - 1: BAD */ 782232812Sjmallett uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 783232812Sjmallett - 0: GOOD (or bist in progress/never run) 784232812Sjmallett - 1: BAD */ 785232812Sjmallett uint64_t reserved_7_7 : 1; 786232812Sjmallett uint64_t rdf : 3; /**< Bist Results for RWB RAM(s) (per-cluster) 787232812Sjmallett - 0: GOOD (or bist in progress/never run) 788232812Sjmallett - 1: BAD */ 789232812Sjmallett uint64_t reserved_3_3 : 1; 790232812Sjmallett uint64_t pdb : 3; /**< Bist Results for PDB RAM(s) (per-cluster) 791232812Sjmallett - 0: GOOD (or bist in progress/never run) 792232812Sjmallett - 1: BAD */ 793232812Sjmallett#else 794232812Sjmallett uint64_t pdb : 3; 795232812Sjmallett uint64_t reserved_3_3 : 1; 796232812Sjmallett uint64_t rdf : 3; 797232812Sjmallett uint64_t reserved_7_7 : 1; 798232812Sjmallett uint64_t dtx : 2; 799232812Sjmallett uint64_t dtx1 : 2; 800232812Sjmallett uint64_t dtx2 : 2; 801232812Sjmallett uint64_t reserved_14_15 : 2; 802232812Sjmallett uint64_t stx : 2; 803232812Sjmallett uint64_t stx1 : 2; 804232812Sjmallett uint64_t stx2 : 2; 805232812Sjmallett uint64_t reserved_22_23 : 2; 806232812Sjmallett uint64_t gfb : 3; 807232812Sjmallett uint64_t reserved_27_27 : 1; 808232812Sjmallett uint64_t mrp : 2; 809232812Sjmallett uint64_t reserved_30_63 : 34; 810232812Sjmallett#endif 811232812Sjmallett } cn68xx; 812232812Sjmallett struct cvmx_dfa_bist0_cn68xx cn68xxp1; 813215976Sjmallett}; 814215976Sjmalletttypedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t; 815215976Sjmallett 816215976Sjmallett/** 817215976Sjmallett * cvmx_dfa_bist1 818215976Sjmallett * 819215976Sjmallett * DFA_BIST1 = DFA Bist Status (Globals) 820215976Sjmallett * 821215976Sjmallett * Description: 822215976Sjmallett */ 823232812Sjmallettunion cvmx_dfa_bist1 { 824215976Sjmallett uint64_t u64; 825232812Sjmallett struct cvmx_dfa_bist1_s { 826232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 827232812Sjmallett uint64_t reserved_21_63 : 43; 828232812Sjmallett uint64_t dlc1ram : 1; /**< DLC1 Bist Results 829232812Sjmallett - 0: GOOD (or bist in progress/never run) 830232812Sjmallett - 1: BAD */ 831232812Sjmallett uint64_t dlc0ram : 1; /**< DLC0 Bist Results 832232812Sjmallett - 0: GOOD (or bist in progress/never run) 833232812Sjmallett - 1: BAD */ 834232812Sjmallett uint64_t dc2ram3 : 1; /**< Cluster#2 Bist Results for RAM3 RAM 835232812Sjmallett - 0: GOOD (or bist in progress/never run) 836232812Sjmallett - 1: BAD */ 837232812Sjmallett uint64_t dc2ram2 : 1; /**< Cluster#2 Bist Results for RAM2 RAM 838232812Sjmallett - 0: GOOD (or bist in progress/never run) 839232812Sjmallett - 1: BAD */ 840232812Sjmallett uint64_t dc2ram1 : 1; /**< Cluster#2 Bist Results for RAM1 RAM 841232812Sjmallett - 0: GOOD (or bist in progress/never run) 842232812Sjmallett - 1: BAD */ 843232812Sjmallett uint64_t dc1ram3 : 1; /**< Cluster#1 Bist Results for RAM3 RAM 844232812Sjmallett - 0: GOOD (or bist in progress/never run) 845232812Sjmallett - 1: BAD */ 846232812Sjmallett uint64_t dc1ram2 : 1; /**< Cluster#1 Bist Results for RAM2 RAM 847232812Sjmallett - 0: GOOD (or bist in progress/never run) 848232812Sjmallett - 1: BAD */ 849232812Sjmallett uint64_t dc1ram1 : 1; /**< Cluster#1 Bist Results for RAM1 RAM 850232812Sjmallett - 0: GOOD (or bist in progress/never run) 851232812Sjmallett - 1: BAD */ 852232812Sjmallett uint64_t ram3 : 1; /**< Cluster#0 Bist Results for RAM3 RAM 853232812Sjmallett - 0: GOOD (or bist in progress/never run) 854232812Sjmallett - 1: BAD */ 855232812Sjmallett uint64_t ram2 : 1; /**< Cluster#0 Bist Results for RAM2 RAM 856232812Sjmallett - 0: GOOD (or bist in progress/never run) 857232812Sjmallett - 1: BAD */ 858232812Sjmallett uint64_t ram1 : 1; /**< Cluster#0 Bist Results for RAM1 RAM 859232812Sjmallett - 0: GOOD (or bist in progress/never run) 860232812Sjmallett - 1: BAD */ 861232812Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 862232812Sjmallett - 0: GOOD (or bist in progress/never run) 863232812Sjmallett - 1: BAD */ 864232812Sjmallett uint64_t gutv : 1; /**< Bist Results for GUTV RAM 865232812Sjmallett - 0: GOOD (or bist in progress/never run) 866232812Sjmallett - 1: BAD */ 867232812Sjmallett uint64_t reserved_7_7 : 1; 868232812Sjmallett uint64_t gutp : 3; /**< Bist Results for GUTP RAMs (per-cluster) 869232812Sjmallett - 0: GOOD (or bist in progress/never run) 870232812Sjmallett - 1: BAD */ 871232812Sjmallett uint64_t ncd : 1; /**< Bist Results for NCD RAM 872232812Sjmallett - 0: GOOD (or bist in progress/never run) 873232812Sjmallett - 1: BAD */ 874232812Sjmallett uint64_t gif : 1; /**< Bist Results for GIF RAM 875232812Sjmallett - 0: GOOD (or bist in progress/never run) 876232812Sjmallett - 1: BAD */ 877232812Sjmallett uint64_t gib : 1; /**< Bist Results for GIB RAM 878232812Sjmallett - 0: GOOD (or bist in progress/never run) 879232812Sjmallett - 1: BAD */ 880232812Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 881232812Sjmallett - 0: GOOD (or bist in progress/never run) 882232812Sjmallett - 1: BAD */ 883232812Sjmallett#else 884232812Sjmallett uint64_t gfu : 1; 885232812Sjmallett uint64_t gib : 1; 886232812Sjmallett uint64_t gif : 1; 887232812Sjmallett uint64_t ncd : 1; 888232812Sjmallett uint64_t gutp : 3; 889232812Sjmallett uint64_t reserved_7_7 : 1; 890232812Sjmallett uint64_t gutv : 1; 891232812Sjmallett uint64_t crq : 1; 892232812Sjmallett uint64_t ram1 : 1; 893232812Sjmallett uint64_t ram2 : 1; 894232812Sjmallett uint64_t ram3 : 1; 895232812Sjmallett uint64_t dc1ram1 : 1; 896232812Sjmallett uint64_t dc1ram2 : 1; 897232812Sjmallett uint64_t dc1ram3 : 1; 898232812Sjmallett uint64_t dc2ram1 : 1; 899232812Sjmallett uint64_t dc2ram2 : 1; 900232812Sjmallett uint64_t dc2ram3 : 1; 901232812Sjmallett uint64_t dlc0ram : 1; 902232812Sjmallett uint64_t dlc1ram : 1; 903232812Sjmallett uint64_t reserved_21_63 : 43; 904232812Sjmallett#endif 905232812Sjmallett } s; 906232812Sjmallett struct cvmx_dfa_bist1_cn61xx { 907232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 908232812Sjmallett uint64_t reserved_20_63 : 44; 909232812Sjmallett uint64_t dlc0ram : 1; /**< DLC0 Bist Results 910232812Sjmallett - 0: GOOD (or bist in progress/never run) 911232812Sjmallett - 1: BAD */ 912232812Sjmallett uint64_t reserved_13_18 : 6; 913232812Sjmallett uint64_t ram3 : 1; /**< Cluster#0 Bist Results for RAM3 RAM 914232812Sjmallett - 0: GOOD (or bist in progress/never run) 915232812Sjmallett - 1: BAD */ 916232812Sjmallett uint64_t ram2 : 1; /**< Cluster#0 Bist Results for RAM2 RAM 917232812Sjmallett - 0: GOOD (or bist in progress/never run) 918232812Sjmallett - 1: BAD */ 919232812Sjmallett uint64_t ram1 : 1; /**< Cluster#0 Bist Results for RAM1 RAM 920232812Sjmallett - 0: GOOD (or bist in progress/never run) 921232812Sjmallett - 1: BAD */ 922232812Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 923232812Sjmallett - 0: GOOD (or bist in progress/never run) 924232812Sjmallett - 1: BAD */ 925232812Sjmallett uint64_t gutv : 1; /**< Bist Results for GUTV RAM 926232812Sjmallett - 0: GOOD (or bist in progress/never run) 927232812Sjmallett - 1: BAD */ 928232812Sjmallett uint64_t reserved_5_7 : 3; 929232812Sjmallett uint64_t gutp : 1; /**< Bist Results for GUTP RAMs 930232812Sjmallett - 0: GOOD (or bist in progress/never run) 931232812Sjmallett - 1: BAD */ 932232812Sjmallett uint64_t ncd : 1; /**< Bist Results for NCD RAM 933232812Sjmallett - 0: GOOD (or bist in progress/never run) 934232812Sjmallett - 1: BAD */ 935232812Sjmallett uint64_t gif : 1; /**< Bist Results for GIF RAM 936232812Sjmallett - 0: GOOD (or bist in progress/never run) 937232812Sjmallett - 1: BAD */ 938232812Sjmallett uint64_t gib : 1; /**< Bist Results for GIB RAM 939232812Sjmallett - 0: GOOD (or bist in progress/never run) 940232812Sjmallett - 1: BAD */ 941232812Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 942232812Sjmallett - 0: GOOD (or bist in progress/never run) 943232812Sjmallett - 1: BAD */ 944232812Sjmallett#else 945232812Sjmallett uint64_t gfu : 1; 946232812Sjmallett uint64_t gib : 1; 947232812Sjmallett uint64_t gif : 1; 948232812Sjmallett uint64_t ncd : 1; 949232812Sjmallett uint64_t gutp : 1; 950232812Sjmallett uint64_t reserved_5_7 : 3; 951232812Sjmallett uint64_t gutv : 1; 952232812Sjmallett uint64_t crq : 1; 953232812Sjmallett uint64_t ram1 : 1; 954232812Sjmallett uint64_t ram2 : 1; 955232812Sjmallett uint64_t ram3 : 1; 956232812Sjmallett uint64_t reserved_13_18 : 6; 957232812Sjmallett uint64_t dlc0ram : 1; 958232812Sjmallett uint64_t reserved_20_63 : 44; 959232812Sjmallett#endif 960232812Sjmallett } cn61xx; 961232812Sjmallett struct cvmx_dfa_bist1_cn63xx { 962232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 963215976Sjmallett uint64_t reserved_13_63 : 51; 964215976Sjmallett uint64_t ram3 : 1; /**< Bist Results for RAM3 RAM 965215976Sjmallett - 0: GOOD (or bist in progress/never run) 966215976Sjmallett - 1: BAD */ 967215976Sjmallett uint64_t ram2 : 1; /**< Bist Results for RAM2 RAM 968215976Sjmallett - 0: GOOD (or bist in progress/never run) 969215976Sjmallett - 1: BAD */ 970215976Sjmallett uint64_t ram1 : 1; /**< Bist Results for RAM1 RAM 971215976Sjmallett - 0: GOOD (or bist in progress/never run) 972215976Sjmallett - 1: BAD */ 973215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 974215976Sjmallett - 0: GOOD (or bist in progress/never run) 975215976Sjmallett - 1: BAD */ 976215976Sjmallett uint64_t gutv : 1; /**< Bist Results for GUTV RAM 977215976Sjmallett - 0: GOOD (or bist in progress/never run) 978215976Sjmallett - 1: BAD */ 979215976Sjmallett uint64_t reserved_5_7 : 3; 980215976Sjmallett uint64_t gutp : 1; /**< Bist Results for NCD RAM 981215976Sjmallett - 0: GOOD (or bist in progress/never run) 982215976Sjmallett - 1: BAD */ 983215976Sjmallett uint64_t ncd : 1; /**< Bist Results for NCD RAM 984215976Sjmallett - 0: GOOD (or bist in progress/never run) 985215976Sjmallett - 1: BAD */ 986215976Sjmallett uint64_t gif : 1; /**< Bist Results for GIF RAM 987215976Sjmallett - 0: GOOD (or bist in progress/never run) 988215976Sjmallett - 1: BAD */ 989215976Sjmallett uint64_t gib : 1; /**< Bist Results for GIB RAM 990215976Sjmallett - 0: GOOD (or bist in progress/never run) 991215976Sjmallett - 1: BAD */ 992215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 993215976Sjmallett - 0: GOOD (or bist in progress/never run) 994215976Sjmallett - 1: BAD */ 995215976Sjmallett#else 996215976Sjmallett uint64_t gfu : 1; 997215976Sjmallett uint64_t gib : 1; 998215976Sjmallett uint64_t gif : 1; 999215976Sjmallett uint64_t ncd : 1; 1000215976Sjmallett uint64_t gutp : 1; 1001215976Sjmallett uint64_t reserved_5_7 : 3; 1002215976Sjmallett uint64_t gutv : 1; 1003215976Sjmallett uint64_t crq : 1; 1004215976Sjmallett uint64_t ram1 : 1; 1005215976Sjmallett uint64_t ram2 : 1; 1006215976Sjmallett uint64_t ram3 : 1; 1007215976Sjmallett uint64_t reserved_13_63 : 51; 1008215976Sjmallett#endif 1009232812Sjmallett } cn63xx; 1010232812Sjmallett struct cvmx_dfa_bist1_cn63xx cn63xxp1; 1011232812Sjmallett struct cvmx_dfa_bist1_cn63xx cn66xx; 1012232812Sjmallett struct cvmx_dfa_bist1_s cn68xx; 1013232812Sjmallett struct cvmx_dfa_bist1_s cn68xxp1; 1014215976Sjmallett}; 1015215976Sjmalletttypedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t; 1016215976Sjmallett 1017215976Sjmallett/** 1018215976Sjmallett * cvmx_dfa_bst0 1019215976Sjmallett * 1020215976Sjmallett * DFA_BST0 = DFA Bist Status 1021215976Sjmallett * 1022215976Sjmallett * Description: 1023215976Sjmallett */ 1024232812Sjmallettunion cvmx_dfa_bst0 { 1025215976Sjmallett uint64_t u64; 1026232812Sjmallett struct cvmx_dfa_bst0_s { 1027232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1028215976Sjmallett uint64_t reserved_32_63 : 32; 1029215976Sjmallett uint64_t rdf : 16; /**< Bist Results for RDF[3:0] RAM(s) 1030215976Sjmallett - 0: GOOD (or bist in progress/never run) 1031215976Sjmallett - 1: BAD */ 1032215976Sjmallett uint64_t pdf : 16; /**< Bist Results for PDF[3:0] RAM(s) 1033215976Sjmallett - 0: GOOD (or bist in progress/never run) 1034215976Sjmallett - 1: BAD */ 1035215976Sjmallett#else 1036215976Sjmallett uint64_t pdf : 16; 1037215976Sjmallett uint64_t rdf : 16; 1038215976Sjmallett uint64_t reserved_32_63 : 32; 1039215976Sjmallett#endif 1040215976Sjmallett } s; 1041215976Sjmallett struct cvmx_dfa_bst0_s cn31xx; 1042215976Sjmallett struct cvmx_dfa_bst0_s cn38xx; 1043215976Sjmallett struct cvmx_dfa_bst0_s cn38xxp2; 1044232812Sjmallett struct cvmx_dfa_bst0_cn58xx { 1045232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1046215976Sjmallett uint64_t reserved_20_63 : 44; 1047215976Sjmallett uint64_t rdf : 4; /**< Bist Results for RDF[3:0] RAM(s) 1048215976Sjmallett - 0: GOOD (or bist in progress/never run) 1049215976Sjmallett - 1: BAD */ 1050215976Sjmallett uint64_t reserved_4_15 : 12; 1051215976Sjmallett uint64_t pdf : 4; /**< Bist Results for PDF[3:0] RAM(s) 1052215976Sjmallett - 0: GOOD (or bist in progress/never run) 1053215976Sjmallett - 1: BAD */ 1054215976Sjmallett#else 1055215976Sjmallett uint64_t pdf : 4; 1056215976Sjmallett uint64_t reserved_4_15 : 12; 1057215976Sjmallett uint64_t rdf : 4; 1058215976Sjmallett uint64_t reserved_20_63 : 44; 1059215976Sjmallett#endif 1060215976Sjmallett } cn58xx; 1061215976Sjmallett struct cvmx_dfa_bst0_cn58xx cn58xxp1; 1062215976Sjmallett}; 1063215976Sjmalletttypedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t; 1064215976Sjmallett 1065215976Sjmallett/** 1066215976Sjmallett * cvmx_dfa_bst1 1067215976Sjmallett * 1068215976Sjmallett * DFA_BST1 = DFA Bist Status 1069215976Sjmallett * 1070215976Sjmallett * Description: 1071215976Sjmallett */ 1072232812Sjmallettunion cvmx_dfa_bst1 { 1073215976Sjmallett uint64_t u64; 1074232812Sjmallett struct cvmx_dfa_bst1_s { 1075232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1076215976Sjmallett uint64_t reserved_23_63 : 41; 1077215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 1078215976Sjmallett - 0: GOOD (or bist in progress/never run) 1079215976Sjmallett - 1: BAD */ 1080215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 1081215976Sjmallett - 0: GOOD (or bist in progress/never run) 1082215976Sjmallett - 1: BAD */ 1083215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 1084215976Sjmallett - 0: GOOD (or bist in progress/never run) 1085215976Sjmallett - 1: BAD */ 1086215976Sjmallett uint64_t drf : 1; /**< Bist Results for DRF RAM 1087215976Sjmallett - 0: GOOD (or bist in progress/never run) 1088215976Sjmallett - 1: BAD */ 1089215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 1090215976Sjmallett - 0: GOOD (or bist in progress/never run) 1091215976Sjmallett - 1: BAD */ 1092215976Sjmallett uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 1093215976Sjmallett - 0: GOOD (or bist in progress/never run) 1094215976Sjmallett - 1: BAD */ 1095215976Sjmallett uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 1096215976Sjmallett - 0: GOOD (or bist in progress/never run) 1097215976Sjmallett - 1: BAD */ 1098215976Sjmallett uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 1099215976Sjmallett - 0: GOOD (or bist in progress/never run) 1100215976Sjmallett - 1: BAD */ 1101215976Sjmallett uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 1102215976Sjmallett - 0: GOOD (or bist in progress/never run) 1103215976Sjmallett - 1: BAD */ 1104215976Sjmallett#else 1105215976Sjmallett uint64_t p1_brf : 8; 1106215976Sjmallett uint64_t p0_brf : 8; 1107215976Sjmallett uint64_t p1_bwb : 1; 1108215976Sjmallett uint64_t p0_bwb : 1; 1109215976Sjmallett uint64_t crf : 1; 1110215976Sjmallett uint64_t drf : 1; 1111215976Sjmallett uint64_t gfu : 1; 1112215976Sjmallett uint64_t ifu : 1; 1113215976Sjmallett uint64_t crq : 1; 1114215976Sjmallett uint64_t reserved_23_63 : 41; 1115215976Sjmallett#endif 1116215976Sjmallett } s; 1117232812Sjmallett struct cvmx_dfa_bst1_cn31xx { 1118232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1119215976Sjmallett uint64_t reserved_23_63 : 41; 1120215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 1121215976Sjmallett - 0: GOOD (or bist in progress/never run) 1122215976Sjmallett - 1: BAD */ 1123215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 1124215976Sjmallett - 0: GOOD (or bist in progress/never run) 1125215976Sjmallett - 1: BAD */ 1126215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 1127215976Sjmallett - 0: GOOD (or bist in progress/never run) 1128215976Sjmallett - 1: BAD */ 1129215976Sjmallett uint64_t drf : 1; /**< Bist Results for DRF RAM 1130215976Sjmallett - 0: GOOD (or bist in progress/never run) 1131215976Sjmallett - 1: BAD */ 1132215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 1133215976Sjmallett - 0: GOOD (or bist in progress/never run) 1134215976Sjmallett - 1: BAD */ 1135215976Sjmallett uint64_t reserved_0_17 : 18; 1136215976Sjmallett#else 1137215976Sjmallett uint64_t reserved_0_17 : 18; 1138215976Sjmallett uint64_t crf : 1; 1139215976Sjmallett uint64_t drf : 1; 1140215976Sjmallett uint64_t gfu : 1; 1141215976Sjmallett uint64_t ifu : 1; 1142215976Sjmallett uint64_t crq : 1; 1143215976Sjmallett uint64_t reserved_23_63 : 41; 1144215976Sjmallett#endif 1145215976Sjmallett } cn31xx; 1146215976Sjmallett struct cvmx_dfa_bst1_s cn38xx; 1147215976Sjmallett struct cvmx_dfa_bst1_s cn38xxp2; 1148232812Sjmallett struct cvmx_dfa_bst1_cn58xx { 1149232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1150215976Sjmallett uint64_t reserved_23_63 : 41; 1151215976Sjmallett uint64_t crq : 1; /**< Bist Results for CRQ RAM 1152215976Sjmallett - 0: GOOD (or bist in progress/never run) 1153215976Sjmallett - 1: BAD */ 1154215976Sjmallett uint64_t ifu : 1; /**< Bist Results for IFU RAM 1155215976Sjmallett - 0: GOOD (or bist in progress/never run) 1156215976Sjmallett - 1: BAD */ 1157215976Sjmallett uint64_t gfu : 1; /**< Bist Results for GFU RAM 1158215976Sjmallett - 0: GOOD (or bist in progress/never run) 1159215976Sjmallett - 1: BAD */ 1160215976Sjmallett uint64_t reserved_19_19 : 1; 1161215976Sjmallett uint64_t crf : 1; /**< Bist Results for CRF RAM 1162215976Sjmallett - 0: GOOD (or bist in progress/never run) 1163215976Sjmallett - 1: BAD */ 1164215976Sjmallett uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 1165215976Sjmallett - 0: GOOD (or bist in progress/never run) 1166215976Sjmallett - 1: BAD */ 1167215976Sjmallett uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 1168215976Sjmallett - 0: GOOD (or bist in progress/never run) 1169215976Sjmallett - 1: BAD */ 1170215976Sjmallett uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 1171215976Sjmallett - 0: GOOD (or bist in progress/never run) 1172215976Sjmallett - 1: BAD */ 1173215976Sjmallett uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 1174215976Sjmallett - 0: GOOD (or bist in progress/never run) 1175215976Sjmallett - 1: BAD */ 1176215976Sjmallett#else 1177215976Sjmallett uint64_t p1_brf : 8; 1178215976Sjmallett uint64_t p0_brf : 8; 1179215976Sjmallett uint64_t p1_bwb : 1; 1180215976Sjmallett uint64_t p0_bwb : 1; 1181215976Sjmallett uint64_t crf : 1; 1182215976Sjmallett uint64_t reserved_19_19 : 1; 1183215976Sjmallett uint64_t gfu : 1; 1184215976Sjmallett uint64_t ifu : 1; 1185215976Sjmallett uint64_t crq : 1; 1186215976Sjmallett uint64_t reserved_23_63 : 41; 1187215976Sjmallett#endif 1188215976Sjmallett } cn58xx; 1189215976Sjmallett struct cvmx_dfa_bst1_cn58xx cn58xxp1; 1190215976Sjmallett}; 1191215976Sjmalletttypedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t; 1192215976Sjmallett 1193215976Sjmallett/** 1194215976Sjmallett * cvmx_dfa_cfg 1195215976Sjmallett * 1196215976Sjmallett * Specify the RSL base addresses for the block 1197215976Sjmallett * 1198215976Sjmallett * DFA_CFG = DFA Configuration 1199215976Sjmallett * 1200215976Sjmallett * Description: 1201215976Sjmallett */ 1202232812Sjmallettunion cvmx_dfa_cfg { 1203215976Sjmallett uint64_t u64; 1204232812Sjmallett struct cvmx_dfa_cfg_s { 1205232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1206215976Sjmallett uint64_t reserved_4_63 : 60; 1207215976Sjmallett uint64_t nrpl_ena : 1; /**< When set, allows the per-node replication feature to be 1208215976Sjmallett enabled. 1209215976Sjmallett In 36-bit mode: The IWORD0[31:30]=SNREPL field AND 1210215976Sjmallett bits [21:20] of the Next Node ptr are used in generating 1211215976Sjmallett the next node address (see OCTEON HRM - DFA Chapter for 1212215976Sjmallett psuedo-code of DTE next node address generation). 1213215976Sjmallett NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode), 1214215976Sjmallett (regardless of IWORD0[NRPLEN]), the Resultant Word1+ 1215215976Sjmallett [[47:44],[23:20]] = Next Node's [27:20] bits. This allows 1216215976Sjmallett SW to use the RESERVED bits of the final node for SW 1217215976Sjmallett caching. Also, if required, SW will use [22:21]=Node 1218215976Sjmallett Replication to re-start the same graph walk(if graph 1219215976Sjmallett walk prematurely terminated (ie: DATA_GONE). 1220215976Sjmallett In 18-bit mode: The IWORD0[31:30]=SNREPL field AND 1221215976Sjmallett bit [16:14] of the Next Node ptr are used in generating 1222215976Sjmallett the next node address (see OCTEON HRM - DFA Chapter for 1223215976Sjmallett psuedo-code of DTE next node address generation). 1224215976Sjmallett If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [ 1225215976Sjmallett If next node ptr[16] is set [ 1226215976Sjmallett next node ptr[15:14] indicates the next node repl 1227215976Sjmallett next node ptr[13:0] indicates the position of the 1228215976Sjmallett node relative to the first normal node (i.e. 1229215976Sjmallett IWORD3[Msize] must be added to get the final node) 1230215976Sjmallett ] 1231215976Sjmallett else If next node ptr[16] is not set [ 1232215976Sjmallett next node ptr[15:0] indicates the next node id 1233215976Sjmallett next node repl = 0 1234215976Sjmallett ] 1235215976Sjmallett ] 1236215976Sjmallett NOTE: For 18b node replication, MAX node space=64KB(2^16) 1237215976Sjmallett is used in detecting terminal node space(see HRM for full 1238215976Sjmallett description). 1239215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1240215976Sjmallett aware of the "per-node" replication. */ 1241215976Sjmallett uint64_t nxor_ena : 1; /**< When set, allows the DTE Instruction IWORD0[NXOREN] 1242215976Sjmallett to be used to enable/disable the per-node address 'scramble' 1243215976Sjmallett of the LLM address to lessen the effects of bank conflicts. 1244215976Sjmallett If IWORD0[NXOREN] is also set, then: 1245215976Sjmallett In 36-bit mode: The node_Id[7:0] 8-bit value is XORed 1246215976Sjmallett against the LLM address addr[9:2]. 1247215976Sjmallett In 18-bit mode: The node_id[6:0] 7-bit value is XORed 1248215976Sjmallett against the LLM address addr[8:2]. (note: we don't address 1249215976Sjmallett scramble outside the mode's node space). 1250215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1251215976Sjmallett aware of the "per-node" address scramble. 1252215976Sjmallett NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 1253215976Sjmallett read/write operations. */ 1254215976Sjmallett uint64_t gxor_ena : 1; /**< When set, the DTE Instruction IWORD0[GXOR] 1255215976Sjmallett field is used to 'scramble' the LLM address 1256215976Sjmallett to lessen the effects of bank conflicts. 1257215976Sjmallett In 36-bit mode: The GXOR[7:0] 8-bit value is XORed 1258215976Sjmallett against the LLM address addr[9:2]. 1259215976Sjmallett In 18-bit mode: GXOR[6:0] 7-bit value is XORed against 1260215976Sjmallett the LLM address addr[8:2]. (note: we don't address 1261215976Sjmallett scramble outside the mode's node space) 1262215976Sjmallett NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1263215976Sjmallett aware of the "per-graph" address scramble. 1264215976Sjmallett NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 1265215976Sjmallett read/write operations. */ 1266215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 1267215976Sjmallett Selects the arbitration mode used to select DFA 1268215976Sjmallett requests issued from either CP2 or the DTE (NCB-CSR 1269215976Sjmallett or DFA HW engine). 1270215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1271215976Sjmallett - 1: Round-Robin 1272215976Sjmallett NOTE: This should only be written to a different value 1273215976Sjmallett during power-on SW initialization. */ 1274215976Sjmallett#else 1275215976Sjmallett uint64_t sarb : 1; 1276215976Sjmallett uint64_t gxor_ena : 1; 1277215976Sjmallett uint64_t nxor_ena : 1; 1278215976Sjmallett uint64_t nrpl_ena : 1; 1279215976Sjmallett uint64_t reserved_4_63 : 60; 1280215976Sjmallett#endif 1281215976Sjmallett } s; 1282215976Sjmallett struct cvmx_dfa_cfg_s cn38xx; 1283232812Sjmallett struct cvmx_dfa_cfg_cn38xxp2 { 1284232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1285215976Sjmallett uint64_t reserved_1_63 : 63; 1286215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 1287215976Sjmallett Selects the arbitration mode used to select DFA 1288215976Sjmallett requests issued from either CP2 or the DTE (NCB-CSR 1289215976Sjmallett or DFA HW engine). 1290215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1291215976Sjmallett - 1: Round-Robin 1292215976Sjmallett NOTE: This should only be written to a different value 1293215976Sjmallett during power-on SW initialization. */ 1294215976Sjmallett#else 1295215976Sjmallett uint64_t sarb : 1; 1296215976Sjmallett uint64_t reserved_1_63 : 63; 1297215976Sjmallett#endif 1298215976Sjmallett } cn38xxp2; 1299215976Sjmallett struct cvmx_dfa_cfg_s cn58xx; 1300215976Sjmallett struct cvmx_dfa_cfg_s cn58xxp1; 1301215976Sjmallett}; 1302215976Sjmalletttypedef union cvmx_dfa_cfg cvmx_dfa_cfg_t; 1303215976Sjmallett 1304215976Sjmallett/** 1305215976Sjmallett * cvmx_dfa_config 1306215976Sjmallett * 1307215976Sjmallett * Specify the RSL base addresses for the block 1308215976Sjmallett * 1309215976Sjmallett * DFA_CONFIG = DFA Configuration Register 1310215976Sjmallett * 1311215976Sjmallett * Description: 1312215976Sjmallett */ 1313232812Sjmallettunion cvmx_dfa_config { 1314215976Sjmallett uint64_t u64; 1315232812Sjmallett struct cvmx_dfa_config_s { 1316232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1317232812Sjmallett uint64_t reserved_11_63 : 53; 1318232812Sjmallett uint64_t dlcclear_bist : 1; /**< When DLCSTART_BIST is written 0->1, if DLCCLEAR_BIST=1, all 1319232812Sjmallett previous DLC BiST state is cleared. 1320232812Sjmallett NOTES: 1321232812Sjmallett 1) DLCCLEAR_BIST must be written to 1 before DLCSTART_BIST 1322232812Sjmallett is written to 1 udsing a separate CSR write. 1323232812Sjmallett 2) DLCCLEAR_BIST must not be changed after writing DLCSTART_BIST 1324232812Sjmallett 0->1 until the BIST operation completes. */ 1325232812Sjmallett uint64_t dlcstart_bist : 1; /**< When software writes DLCSTART_BIST=0->1, a BiST is executed 1326232812Sjmallett for the DLC sub-block RAMs which contains DCLK domain 1327232812Sjmallett asynchronous RAMs. 1328232812Sjmallett NOTES: 1329232812Sjmallett 1) This bit should only be written after DCLK has been enabled 1330232812Sjmallett by software and is stable. 1331232812Sjmallett (see LMC initialization routine for details on how to enable 1332232812Sjmallett the DDR3 memory (DCLK) - which requires LMC PLL init, clock 1333232812Sjmallett divider and proper DLL initialization sequence). */ 1334232812Sjmallett uint64_t repl_ena : 1; /**< Replication Mode Enable 1335232812Sjmallett *** o63-P2 NEW *** 1336232812Sjmallett When set, enables replication mode performance enhancement 1337232812Sjmallett feature. This enables the DFA to communicate address 1338232812Sjmallett replication information during memory references to the 1339232812Sjmallett memory controller. 1340232812Sjmallett For o63-P2: This is used by the memory controller 1341232812Sjmallett to support graph data in multiple banks (or bank sets), so that 1342232812Sjmallett the least full bank can be selected to minimize the effects of 1343232812Sjmallett DDR3 bank conflicts (ie: tRC=row cycle time). 1344232812Sjmallett For o68: This is used by the memory controller to support graph 1345232812Sjmallett data in multiple ports (or port sets), so that the least full 1346232812Sjmallett port can be selected to minimize latency effects. 1347232812Sjmallett SWNOTE: Using this mode requires the DFA SW compiler and DFA 1348232812Sjmallett driver to be aware of the address replication changes. 1349232812Sjmallett This involves changes to the MLOAD/GWALK DFA instruction format 1350232812Sjmallett (see: IWORD2.SREPL), as well as changes to node arc and metadata 1351232812Sjmallett definitions which now support an additional REPL field. 1352232812Sjmallett When clear, replication mode is disabled, and DFA will interpret 1353232812Sjmallett DFA instructions and node-arc formats which DO NOT have 1354232812Sjmallett address replication information. */ 1355232812Sjmallett uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1356232812Sjmallett A one in each bit of the mask represents which DTE cluster to 1357232812Sjmallett cripple. 1358232812Sjmallett NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1359232812Sjmallett is the only bit used. 1360232812Sjmallett o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1361232812Sjmallett SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1362232812Sjmallett be forced into this register at reset. Any fuse bits that 1363232812Sjmallett contain '1' will be disallowed during a write and will always 1364232812Sjmallett be read as '1'. */ 1365232812Sjmallett uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1366232812Sjmallett cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1367232812Sjmallett within each cluster. However, when the DFA performance 1368232812Sjmallett counters are used, SW may want to limit the \#of DTEs 1369232812Sjmallett per cluster available, as there are only 4 parallel 1370232812Sjmallett performance counters. 1371232812Sjmallett DTE_CLCRIP | \#DTEs crippled(per cluster) 1372232812Sjmallett ------------+----------------------------- 1373232812Sjmallett 0 | 0 DTE[15:0]:ON 1374232812Sjmallett 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1375232812Sjmallett 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1376232812Sjmallett 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1377232812Sjmallett 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1378232812Sjmallett 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1379232812Sjmallett 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1380232812Sjmallett 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1381232812Sjmallett NOTE: Higher numbered DTEs are crippled first. For instance, 1382232812Sjmallett on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1383232812Sjmallett DTE#s [15:8] within the cluster are crippled and only 1384232812Sjmallett DTE#s [7:0] are available. 1385232812Sjmallett IMPNOTE: The encodings are done in such a way as to later 1386232812Sjmallett be used with fuses (for future o2 revisions which will disable 1387232812Sjmallett some \#of DTEs). Blowing a fuse has the effect that there will 1388232812Sjmallett always be fewer DTEs available. [ie: we never want a customer 1389232812Sjmallett to blow additional fuses to get more DTEs]. 1390232812Sjmallett SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1391232812Sjmallett be forced into this register at reset. Any fuse bits that 1392232812Sjmallett contain '1' will be disallowed during a write and will always 1393232812Sjmallett be read as '1'. */ 1394232812Sjmallett uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1395232812Sjmallett When SET, the DFA clocks for DTE(thread engine) 1396232812Sjmallett operation are disabled (to conserve overall chip clocking 1397232812Sjmallett power when the DFA function is not used). 1398232812Sjmallett NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1399232812Sjmallett operations to the DFA (will result in NCB Bus Timeout 1400232812Sjmallett errors). 1401232812Sjmallett NOTE: This should only be written to a different value 1402232812Sjmallett during power-on SW initialization. 1403232812Sjmallett SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1404232812Sjmallett be forced into this register at reset. If the fuse bit 1405232812Sjmallett contains '1', writes to DTECLKDIS are disallowed and 1406232812Sjmallett will always be read as '1'. */ 1407232812Sjmallett#else 1408232812Sjmallett uint64_t dteclkdis : 1; 1409232812Sjmallett uint64_t cldtecrip : 3; 1410232812Sjmallett uint64_t clmskcrip : 4; 1411232812Sjmallett uint64_t repl_ena : 1; 1412232812Sjmallett uint64_t dlcstart_bist : 1; 1413232812Sjmallett uint64_t dlcclear_bist : 1; 1414232812Sjmallett uint64_t reserved_11_63 : 53; 1415232812Sjmallett#endif 1416232812Sjmallett } s; 1417232812Sjmallett struct cvmx_dfa_config_s cn61xx; 1418232812Sjmallett struct cvmx_dfa_config_cn63xx { 1419232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1420215976Sjmallett uint64_t reserved_9_63 : 55; 1421215976Sjmallett uint64_t repl_ena : 1; /**< Replication Mode Enable 1422215976Sjmallett *** o63-P2 NEW *** 1423215976Sjmallett When set, enables replication mode performance enhancement 1424215976Sjmallett feature. This enables the DFA to communicate address 1425215976Sjmallett replication information during memory references to the DFM 1426215976Sjmallett (memory controller). This in turn is used by the DFM to support 1427215976Sjmallett graph data in multiple banks (or bank sets), so that the least 1428215976Sjmallett full bank can be selected to minimize the effects of DDR3 bank 1429215976Sjmallett conflicts (ie: tRC=row cycle time). 1430215976Sjmallett SWNOTE: Using this mode requires the DFA SW compiler and DFA 1431215976Sjmallett driver to be aware of the o63-P2 address replication changes. 1432215976Sjmallett This involves changes to the MLOAD/GWALK DFA instruction format 1433215976Sjmallett (see: IWORD2.SREPL), as well as changes to node arc and metadata 1434215976Sjmallett definitions which now support an additional REPL field. 1435215976Sjmallett When clear, replication mode is disabled, and DFA will interpret 1436215976Sjmallett o63-P1 DFA instructions and node-arc formats which DO NOT have 1437215976Sjmallett address replication information. */ 1438215976Sjmallett uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1439215976Sjmallett A one in each bit of the mask represents which DTE cluster to 1440215976Sjmallett cripple. 1441215976Sjmallett NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1442215976Sjmallett is the only bit used. 1443215976Sjmallett o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1444215976Sjmallett SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1445215976Sjmallett be forced into this register at reset. Any fuse bits that 1446215976Sjmallett contain '1' will be disallowed during a write and will always 1447215976Sjmallett be read as '1'. */ 1448215976Sjmallett uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1449215976Sjmallett cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1450215976Sjmallett within each cluster. However, when the DFA performance 1451215976Sjmallett counters are used, SW may want to limit the \#of DTEs 1452215976Sjmallett per cluster available, as there are only 4 parallel 1453215976Sjmallett performance counters. 1454215976Sjmallett DTE_CLCRIP | \#DTEs crippled(per cluster) 1455215976Sjmallett ------------+----------------------------- 1456215976Sjmallett 0 | 0 DTE[15:0]:ON 1457215976Sjmallett 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1458215976Sjmallett 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1459215976Sjmallett 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1460215976Sjmallett 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1461215976Sjmallett 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1462215976Sjmallett 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1463215976Sjmallett 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1464215976Sjmallett NOTE: Higher numbered DTEs are crippled first. For instance, 1465215976Sjmallett on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1466215976Sjmallett DTE#s [15:8] within the cluster are crippled and only 1467215976Sjmallett DTE#s [7:0] are available. 1468215976Sjmallett IMPNOTE: The encodings are done in such a way as to later 1469215976Sjmallett be used with fuses (for future o2 revisions which will disable 1470215976Sjmallett some \#of DTEs). Blowing a fuse has the effect that there will 1471215976Sjmallett always be fewer DTEs available. [ie: we never want a customer 1472215976Sjmallett to blow additional fuses to get more DTEs]. 1473215976Sjmallett SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1474215976Sjmallett be forced into this register at reset. Any fuse bits that 1475215976Sjmallett contain '1' will be disallowed during a write and will always 1476215976Sjmallett be read as '1'. */ 1477215976Sjmallett uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1478215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 1479215976Sjmallett operation are disabled (to conserve overall chip clocking 1480215976Sjmallett power when the DFA function is not used). 1481215976Sjmallett NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1482215976Sjmallett operations to the DFA (will result in NCB Bus Timeout 1483215976Sjmallett errors). 1484215976Sjmallett NOTE: This should only be written to a different value 1485215976Sjmallett during power-on SW initialization. 1486215976Sjmallett SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1487215976Sjmallett be forced into this register at reset. If the fuse bit 1488215976Sjmallett contains '1', writes to DTECLKDIS are disallowed and 1489215976Sjmallett will always be read as '1'. */ 1490215976Sjmallett#else 1491215976Sjmallett uint64_t dteclkdis : 1; 1492215976Sjmallett uint64_t cldtecrip : 3; 1493215976Sjmallett uint64_t clmskcrip : 4; 1494215976Sjmallett uint64_t repl_ena : 1; 1495215976Sjmallett uint64_t reserved_9_63 : 55; 1496215976Sjmallett#endif 1497232812Sjmallett } cn63xx; 1498232812Sjmallett struct cvmx_dfa_config_cn63xxp1 { 1499232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1500215976Sjmallett uint64_t reserved_8_63 : 56; 1501215976Sjmallett uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1502215976Sjmallett A one in each bit of the mask represents which DTE cluster to 1503215976Sjmallett cripple. 1504215976Sjmallett NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1505215976Sjmallett is the only bit used. 1506215976Sjmallett o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1507215976Sjmallett SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1508215976Sjmallett be forced into this register at reset. Any fuse bits that 1509215976Sjmallett contain '1' will be disallowed during a write and will always 1510215976Sjmallett be read as '1'. */ 1511215976Sjmallett uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1512215976Sjmallett cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1513215976Sjmallett within each cluster. However, when the DFA performance 1514215976Sjmallett counters are used, SW may want to limit the \#of DTEs 1515215976Sjmallett per cluster available, as there are only 4 parallel 1516215976Sjmallett performance counters. 1517215976Sjmallett DTE_CLCRIP | \#DTEs crippled(per cluster) 1518215976Sjmallett ------------+----------------------------- 1519215976Sjmallett 0 | 0 DTE[15:0]:ON 1520215976Sjmallett 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1521215976Sjmallett 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1522215976Sjmallett 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1523215976Sjmallett 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1524215976Sjmallett 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1525215976Sjmallett 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1526215976Sjmallett 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1527215976Sjmallett NOTE: Higher numbered DTEs are crippled first. For instance, 1528215976Sjmallett on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1529215976Sjmallett DTE#s [15:8] within the cluster are crippled and only 1530215976Sjmallett DTE#s [7:0] are available. 1531215976Sjmallett IMPNOTE: The encodings are done in such a way as to later 1532215976Sjmallett be used with fuses (for future o2 revisions which will disable 1533215976Sjmallett some \#of DTEs). Blowing a fuse has the effect that there will 1534215976Sjmallett always be fewer DTEs available. [ie: we never want a customer 1535215976Sjmallett to blow additional fuses to get more DTEs]. 1536215976Sjmallett SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1537215976Sjmallett be forced into this register at reset. Any fuse bits that 1538215976Sjmallett contain '1' will be disallowed during a write and will always 1539215976Sjmallett be read as '1'. */ 1540215976Sjmallett uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1541215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 1542215976Sjmallett operation are disabled (to conserve overall chip clocking 1543215976Sjmallett power when the DFA function is not used). 1544215976Sjmallett NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1545215976Sjmallett operations to the DFA (will result in NCB Bus Timeout 1546215976Sjmallett errors). 1547215976Sjmallett NOTE: This should only be written to a different value 1548215976Sjmallett during power-on SW initialization. 1549215976Sjmallett SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1550215976Sjmallett be forced into this register at reset. If the fuse bit 1551215976Sjmallett contains '1', writes to DTECLKDIS are disallowed and 1552215976Sjmallett will always be read as '1'. */ 1553215976Sjmallett#else 1554215976Sjmallett uint64_t dteclkdis : 1; 1555215976Sjmallett uint64_t cldtecrip : 3; 1556215976Sjmallett uint64_t clmskcrip : 4; 1557215976Sjmallett uint64_t reserved_8_63 : 56; 1558215976Sjmallett#endif 1559215976Sjmallett } cn63xxp1; 1560232812Sjmallett struct cvmx_dfa_config_cn63xx cn66xx; 1561232812Sjmallett struct cvmx_dfa_config_s cn68xx; 1562232812Sjmallett struct cvmx_dfa_config_s cn68xxp1; 1563215976Sjmallett}; 1564215976Sjmalletttypedef union cvmx_dfa_config cvmx_dfa_config_t; 1565215976Sjmallett 1566215976Sjmallett/** 1567215976Sjmallett * cvmx_dfa_control 1568215976Sjmallett * 1569215976Sjmallett * DFA_CONTROL = DFA Control Register 1570215976Sjmallett * 1571215976Sjmallett * Description: 1572215976Sjmallett */ 1573232812Sjmallettunion cvmx_dfa_control { 1574215976Sjmallett uint64_t u64; 1575232812Sjmallett struct cvmx_dfa_control_s { 1576232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1577232812Sjmallett uint64_t reserved_12_63 : 52; 1578232812Sjmallett uint64_t sbdnum : 6; /**< SBD Debug Entry# 1579232812Sjmallett *FOR INTERNAL USE ONLY* 1580232812Sjmallett DFA Scoreboard debug control 1581232812Sjmallett Selects which one of 48 DFA Scoreboard entries is 1582232812Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 1583232812Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 1584232812Sjmallett *FOR INTERNAL USE ONLY* 1585232812Sjmallett DFA Scoreboard debug control 1586232812Sjmallett When written with a '1', the DFA Scoreboard Debug 1587232812Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 1588232812Sjmallett This allows SW to lock down the contents of the entire 1589232812Sjmallett SBD for a single instant in time. All subsequent reads 1590232812Sjmallett of the DFA scoreboard registers will return the data 1591232812Sjmallett from that instant in time. */ 1592232812Sjmallett uint64_t reserved_3_4 : 2; 1593232812Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 1594232812Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 1595232812Sjmallett NOTE: This should only be written to a different value 1596232812Sjmallett during power-on SW initialization. */ 1597232812Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 1598232812Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 1599232812Sjmallett NOTE: This should only be written to a different value 1600232812Sjmallett during power-on SW initialization. */ 1601232812Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 1602232812Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 1603232812Sjmallett NOTE: This should only be written to a different value 1604232812Sjmallett during power-on SW initialization. */ 1605232812Sjmallett#else 1606232812Sjmallett uint64_t imode : 1; 1607232812Sjmallett uint64_t qmode : 1; 1608232812Sjmallett uint64_t pmode : 1; 1609232812Sjmallett uint64_t reserved_3_4 : 2; 1610232812Sjmallett uint64_t sbdlck : 1; 1611232812Sjmallett uint64_t sbdnum : 6; 1612232812Sjmallett uint64_t reserved_12_63 : 52; 1613232812Sjmallett#endif 1614232812Sjmallett } s; 1615232812Sjmallett struct cvmx_dfa_control_cn61xx { 1616232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1617215976Sjmallett uint64_t reserved_10_63 : 54; 1618215976Sjmallett uint64_t sbdnum : 4; /**< SBD Debug Entry# 1619215976Sjmallett *FOR INTERNAL USE ONLY* 1620215976Sjmallett DFA Scoreboard debug control 1621232812Sjmallett Selects which one of 16 DFA Scoreboard entries is 1622215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 1623215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 1624215976Sjmallett *FOR INTERNAL USE ONLY* 1625215976Sjmallett DFA Scoreboard debug control 1626215976Sjmallett When written with a '1', the DFA Scoreboard Debug 1627215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 1628215976Sjmallett This allows SW to lock down the contents of the entire 1629215976Sjmallett SBD for a single instant in time. All subsequent reads 1630215976Sjmallett of the DFA scoreboard registers will return the data 1631215976Sjmallett from that instant in time. */ 1632215976Sjmallett uint64_t reserved_3_4 : 2; 1633215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 1634215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 1635215976Sjmallett NOTE: This should only be written to a different value 1636215976Sjmallett during power-on SW initialization. */ 1637215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 1638215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 1639215976Sjmallett NOTE: This should only be written to a different value 1640215976Sjmallett during power-on SW initialization. */ 1641215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 1642215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 1643215976Sjmallett NOTE: This should only be written to a different value 1644215976Sjmallett during power-on SW initialization. */ 1645215976Sjmallett#else 1646215976Sjmallett uint64_t imode : 1; 1647215976Sjmallett uint64_t qmode : 1; 1648215976Sjmallett uint64_t pmode : 1; 1649215976Sjmallett uint64_t reserved_3_4 : 2; 1650215976Sjmallett uint64_t sbdlck : 1; 1651215976Sjmallett uint64_t sbdnum : 4; 1652215976Sjmallett uint64_t reserved_10_63 : 54; 1653215976Sjmallett#endif 1654232812Sjmallett } cn61xx; 1655232812Sjmallett struct cvmx_dfa_control_cn61xx cn63xx; 1656232812Sjmallett struct cvmx_dfa_control_cn61xx cn63xxp1; 1657232812Sjmallett struct cvmx_dfa_control_cn61xx cn66xx; 1658232812Sjmallett struct cvmx_dfa_control_s cn68xx; 1659232812Sjmallett struct cvmx_dfa_control_s cn68xxp1; 1660215976Sjmallett}; 1661215976Sjmalletttypedef union cvmx_dfa_control cvmx_dfa_control_t; 1662215976Sjmallett 1663215976Sjmallett/** 1664215976Sjmallett * cvmx_dfa_dbell 1665215976Sjmallett * 1666215976Sjmallett * DFA_DBELL = DFA Doorbell Register 1667215976Sjmallett * 1668215976Sjmallett * Description: 1669215976Sjmallett * NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00. 1670215976Sjmallett * To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00. 1671215976Sjmallett * 1672215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect. 1673215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect. 1674215976Sjmallett */ 1675232812Sjmallettunion cvmx_dfa_dbell { 1676215976Sjmallett uint64_t u64; 1677232812Sjmallett struct cvmx_dfa_dbell_s { 1678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1679215976Sjmallett uint64_t reserved_20_63 : 44; 1680215976Sjmallett uint64_t dbell : 20; /**< Represents the cumulative total of pending 1681215976Sjmallett DFA instructions which SW has previously written 1682215976Sjmallett into the DFA Instruction FIFO (DIF) in main memory. 1683215976Sjmallett Each DFA instruction contains a fixed size 32B 1684215976Sjmallett instruction word which is executed by the DFA HW. 1685215976Sjmallett The DBL register can hold up to 1M-1 (2^20-1) 1686215976Sjmallett pending DFA instruction requests. 1687215976Sjmallett During a read (by SW), the 'most recent' contents 1688215976Sjmallett of the DFA_DBELL register are returned at the time 1689215976Sjmallett the NCB-INB bus is driven. 1690215976Sjmallett NOTE: Since DFA HW updates this register, its 1691215976Sjmallett contents are unpredictable in SW. */ 1692215976Sjmallett#else 1693215976Sjmallett uint64_t dbell : 20; 1694215976Sjmallett uint64_t reserved_20_63 : 44; 1695215976Sjmallett#endif 1696215976Sjmallett } s; 1697215976Sjmallett struct cvmx_dfa_dbell_s cn31xx; 1698215976Sjmallett struct cvmx_dfa_dbell_s cn38xx; 1699215976Sjmallett struct cvmx_dfa_dbell_s cn38xxp2; 1700215976Sjmallett struct cvmx_dfa_dbell_s cn58xx; 1701215976Sjmallett struct cvmx_dfa_dbell_s cn58xxp1; 1702232812Sjmallett struct cvmx_dfa_dbell_s cn61xx; 1703215976Sjmallett struct cvmx_dfa_dbell_s cn63xx; 1704215976Sjmallett struct cvmx_dfa_dbell_s cn63xxp1; 1705232812Sjmallett struct cvmx_dfa_dbell_s cn66xx; 1706232812Sjmallett struct cvmx_dfa_dbell_s cn68xx; 1707232812Sjmallett struct cvmx_dfa_dbell_s cn68xxp1; 1708215976Sjmallett}; 1709215976Sjmalletttypedef union cvmx_dfa_dbell cvmx_dfa_dbell_t; 1710215976Sjmallett 1711215976Sjmallett/** 1712215976Sjmallett * cvmx_dfa_ddr2_addr 1713215976Sjmallett * 1714215976Sjmallett * DFA_DDR2_ADDR = DFA DDR2 fclk-domain Memory Address Config Register 1715215976Sjmallett * 1716215976Sjmallett * 1717215976Sjmallett * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK 1718215976Sjmallett * etc. 1719215976Sjmallett */ 1720232812Sjmallettunion cvmx_dfa_ddr2_addr { 1721215976Sjmallett uint64_t u64; 1722232812Sjmallett struct cvmx_dfa_ddr2_addr_s { 1723232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1724215976Sjmallett uint64_t reserved_9_63 : 55; 1725215976Sjmallett uint64_t rdimm_ena : 1; /**< If there is a need to insert a register chip on the 1726215976Sjmallett system (the equivalent of a registered DIMM) to 1727215976Sjmallett provide better setup for the command and control bits 1728215976Sjmallett turn this mode on. 1729215976Sjmallett RDIMM_ENA 1730215976Sjmallett 0 Registered Mode OFF 1731215976Sjmallett 1 Registered Mode ON */ 1732215976Sjmallett uint64_t num_rnks : 2; /**< NUM_RNKS is programmed based on how many ranks there 1733215976Sjmallett are in the system. This needs to be programmed correctly 1734215976Sjmallett regardless of whether we are in RNK_LO mode or not. 1735215976Sjmallett NUM_RNKS \# of Ranks 1736215976Sjmallett 0 1 1737215976Sjmallett 1 2 1738215976Sjmallett 2 4 1739215976Sjmallett 3 RESERVED */ 1740215976Sjmallett uint64_t rnk_lo : 1; /**< When this mode is turned on, consecutive addresses 1741215976Sjmallett outside the bank boundary 1742215976Sjmallett are programmed to go to different ranks in order to 1743215976Sjmallett minimize bank conflicts. It is useful in 4-bank DDR2 1744215976Sjmallett parts based memory to extend out the \#physical banks 1745215976Sjmallett available and minimize bank conflicts. 1746215976Sjmallett On 8 bank ddr2 parts, this mode is not very useful 1747215976Sjmallett because this mode does come with 1748215976Sjmallett a penalty which is that every successive reads that 1749215976Sjmallett cross rank boundary will need a 1 cycle bubble 1750215976Sjmallett inserted to prevent bus turnaround conflicts. 1751215976Sjmallett RNK_LO 1752215976Sjmallett 0 - OFF 1753215976Sjmallett 1 - ON */ 1754215976Sjmallett uint64_t num_colrows : 3; /**< NUM_COLROWS is used to set the MSB of the ROW_ADDR 1755215976Sjmallett and the LSB of RANK address when not in RNK_LO mode. 1756215976Sjmallett Calculate the sum of \#COL and \#ROW and program the 1757215976Sjmallett controller appropriately 1758215976Sjmallett RANK_LSB \#COLs + \#ROWs 1759215976Sjmallett ------------------------------ 1760215976Sjmallett - 000: 22 1761215976Sjmallett - 001: 23 1762215976Sjmallett - 010: 24 1763215976Sjmallett - 011: 25 1764215976Sjmallett - 100-111: RESERVED */ 1765215976Sjmallett uint64_t num_cols : 2; /**< The Long word address that the controller receives 1766215976Sjmallett needs to be converted to Row, Col, Rank and Bank 1767215976Sjmallett addresses depending on the memory part's micro arch. 1768215976Sjmallett NUM_COL tells the controller how many colum bits 1769215976Sjmallett there are and the controller uses this info to map 1770215976Sjmallett the LSB of the row address 1771215976Sjmallett - 00: num_cols = 9 1772215976Sjmallett - 01: num_cols = 10 1773215976Sjmallett - 10: num_cols = 11 1774215976Sjmallett - 11: RESERVED */ 1775215976Sjmallett#else 1776215976Sjmallett uint64_t num_cols : 2; 1777215976Sjmallett uint64_t num_colrows : 3; 1778215976Sjmallett uint64_t rnk_lo : 1; 1779215976Sjmallett uint64_t num_rnks : 2; 1780215976Sjmallett uint64_t rdimm_ena : 1; 1781215976Sjmallett uint64_t reserved_9_63 : 55; 1782215976Sjmallett#endif 1783215976Sjmallett } s; 1784215976Sjmallett struct cvmx_dfa_ddr2_addr_s cn31xx; 1785215976Sjmallett}; 1786215976Sjmalletttypedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t; 1787215976Sjmallett 1788215976Sjmallett/** 1789215976Sjmallett * cvmx_dfa_ddr2_bus 1790215976Sjmallett * 1791215976Sjmallett * DFA_DDR2_BUS = DFA DDR Bus Activity Counter 1792215976Sjmallett * 1793215976Sjmallett * 1794215976Sjmallett * Description: This counter counts \# cycles that the memory bus is doing a read/write/command 1795215976Sjmallett * Useful to benchmark the bus utilization as a ratio of 1796215976Sjmallett * \#Cycles of Data Transfer/\#Cycles since init or 1797215976Sjmallett * \#Cycles of Data Transfer/\#Cycles that memory controller is active 1798215976Sjmallett */ 1799232812Sjmallettunion cvmx_dfa_ddr2_bus { 1800215976Sjmallett uint64_t u64; 1801232812Sjmallett struct cvmx_dfa_ddr2_bus_s { 1802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1803215976Sjmallett uint64_t reserved_47_63 : 17; 1804215976Sjmallett uint64_t bus_cnt : 47; /**< Counter counts the \# cycles of Data transfer */ 1805215976Sjmallett#else 1806215976Sjmallett uint64_t bus_cnt : 47; 1807215976Sjmallett uint64_t reserved_47_63 : 17; 1808215976Sjmallett#endif 1809215976Sjmallett } s; 1810215976Sjmallett struct cvmx_dfa_ddr2_bus_s cn31xx; 1811215976Sjmallett}; 1812215976Sjmalletttypedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t; 1813215976Sjmallett 1814215976Sjmallett/** 1815215976Sjmallett * cvmx_dfa_ddr2_cfg 1816215976Sjmallett * 1817215976Sjmallett * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register 1818215976Sjmallett * 1819215976Sjmallett * Description: 1820215976Sjmallett */ 1821232812Sjmallettunion cvmx_dfa_ddr2_cfg { 1822215976Sjmallett uint64_t u64; 1823232812Sjmallett struct cvmx_dfa_ddr2_cfg_s { 1824232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1825215976Sjmallett uint64_t reserved_41_63 : 23; 1826215976Sjmallett uint64_t trfc : 5; /**< Establishes tRFC(from DDR2 data sheets) in \# of 1827215976Sjmallett 4 fclk intervals. 1828215976Sjmallett General Equation: 1829215976Sjmallett TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))] 1830215976Sjmallett Example: 1831215976Sjmallett tRFC(data-sheet-ns) = 127.5ns 1832215976Sjmallett Operational Frequency: 533MHz DDR rate 1833215976Sjmallett [fclk=266MHz(3.75ns)] 1834215976Sjmallett Then: 1835215976Sjmallett TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)] 1836215976Sjmallett = 9 */ 1837215976Sjmallett uint64_t mrs_pgm : 1; /**< When clear, the HW initialization sequence fixes 1838215976Sjmallett some of the *MRS register bit definitions. 1839215976Sjmallett EMRS: 1840215976Sjmallett A[14:13] = 0 RESERVED 1841215976Sjmallett A[12] = 0 Output Buffers Enabled (FIXED) 1842215976Sjmallett A[11] = 0 RDQS Disabled (FIXED) 1843215976Sjmallett A[10] = 0 DQSn Enabled (FIXED) 1844215976Sjmallett A[9:7] = 0 OCD Not supported (FIXED) 1845215976Sjmallett A[6] = 0 RTT Disabled (FIXED) 1846215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1) 1847215976Sjmallett Additive LATENCY (Programmable) 1848215976Sjmallett A[2]=0 RTT Disabled (FIXED) 1849215976Sjmallett A[1]=DFA_DDR2_TMG[DIC] (Programmable) 1850215976Sjmallett A[0] = 0 DLL Enabled (FIXED) 1851215976Sjmallett MRS: 1852215976Sjmallett A[14:13] = 0 RESERVED 1853215976Sjmallett A[12] = 0 Fast Active Power Down Mode (FIXED) 1854215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR](Programmable) 1855215976Sjmallett A[8] = 1 DLL Reset (FIXED) 1856215976Sjmallett A[7] = 0 Test Mode (FIXED) 1857215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable) 1858215976Sjmallett A[3] = 0 Burst Type(must be 0:Sequential) (FIXED) 1859215976Sjmallett A[2:0] = 2 Burst Length=4 (must be 0:Sequential) (FIXED) 1860215976Sjmallett When set, the HW initialization sequence sources 1861215976Sjmallett the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are 1862215976Sjmallett driven onto the DFA_A[] pins. (this allows the MRS/EMRS 1863215976Sjmallett fields to be completely programmable - however care 1864215976Sjmallett must be taken by software). 1865215976Sjmallett This mode is useful for customers who wish to: 1866215976Sjmallett 1) override the FIXED definitions(above), or 1867215976Sjmallett 2) Use a "clamshell mode" of operation where the 1868215976Sjmallett address bits(per rank) are swizzled on the 1869215976Sjmallett board to reduce stub lengths for optimal 1870215976Sjmallett frequency operation. 1871215976Sjmallett Use this in combination with DFA_DDR2_CFG[RNK_MSK] 1872215976Sjmallett to specify the INIT sequence for each of the 4 1873215976Sjmallett supported ranks. */ 1874215976Sjmallett uint64_t fpip : 3; /**< Early Fill Programmable Pipe [\#fclks] 1875215976Sjmallett This field dictates the \#fclks prior to the arrival 1876215976Sjmallett of fill data(in fclk domain), to start the 'early' fill 1877215976Sjmallett command pipe (in the eclk domain) so as to minimize the 1878215976Sjmallett overall fill latency. 1879215976Sjmallett The programmable early fill command signal is synchronized 1880215976Sjmallett into the eclk domain, where it is used to pull data out of 1881215976Sjmallett asynchronous RAM as fast as possible. 1882215976Sjmallett NOTE: A value of FPIP=0 is the 'safest' setting and will 1883215976Sjmallett result in the early fill command pipe starting in the 1884215976Sjmallett same cycle as the fill data. 1885215976Sjmallett General Equation: (for FPIP) 1886215976Sjmallett FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)] 1887215976Sjmallett where: 1888215976Sjmallett EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)] 1889215976Sjmallett Example: FCLK=200MHz/ECLK=600MHz 1890215976Sjmallett FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)] 1891215976Sjmallett FPIP <= 3 */ 1892215976Sjmallett uint64_t reserved_29_31 : 3; 1893215976Sjmallett uint64_t ref_int : 13; /**< Refresh Interval (represented in \#of fclk 1894215976Sjmallett increments). 1895215976Sjmallett Each refresh interval will generate a single 1896215976Sjmallett auto-refresh command sequence which implicitly targets 1897215976Sjmallett all banks within the device: 1898215976Sjmallett Example: For fclk=200MHz(5ns)/400MHz(DDR): 1899215976Sjmallett trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet] 1900215976Sjmallett REF_INT = ROUND_DOWN[(trefint/fclk)] 1901215976Sjmallett = ROUND_DOWN[(3900ns/5ns)] 1902215976Sjmallett = 780 fclks (0x30c) 1903215976Sjmallett NOTE: This should only be written to a different value 1904215976Sjmallett during power-on SW initialization. */ 1905215976Sjmallett uint64_t reserved_14_15 : 2; 1906215976Sjmallett uint64_t tskw : 2; /**< Board Skew (represented in \#fclks) 1907215976Sjmallett Represents additional board skew of DQ/DQS. 1908215976Sjmallett - 00: board-skew = 0 fclk 1909215976Sjmallett - 01: board-skew = 1 fclk 1910215976Sjmallett - 10: board-skew = 2 fclk 1911215976Sjmallett - 11: board-skew = 3 fclk 1912215976Sjmallett NOTE: This should only be written to a different value 1913215976Sjmallett during power-on SW initialization. */ 1914215976Sjmallett uint64_t rnk_msk : 4; /**< Controls the CS_N[3:0] during a) a HW Initialization 1915215976Sjmallett sequence (triggered by DFA_DDR2_CFG[INIT]) or 1916215976Sjmallett b) during a normal refresh sequence. If 1917215976Sjmallett the RNK_MSK[x]=1, the corresponding CS_N[x] is driven. 1918215976Sjmallett NOTE: This is required for DRAM used in a 1919215976Sjmallett clamshell configuration, since the address lines 1920215976Sjmallett carry Mode Register write data that is unique 1921215976Sjmallett per rank(or clam). In a clamshell configuration, 1922215976Sjmallett the N3K DFA_A[x] pin may be tied into Clam#0's A[x] 1923215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 1924215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 1925215976Sjmallett To support clamshell designs, SW must initiate 1926215976Sjmallett separate HW init sequences each unique rank address 1927215976Sjmallett mapping. Before each HW init sequence is triggered, 1928215976Sjmallett SW must preload the DFA_DDR2_MRS/EMRS registers with 1929215976Sjmallett the data that will be driven onto the A[14:0] wires 1930215976Sjmallett during the EMRS/MRS mode register write(s). 1931215976Sjmallett NOTE: After the final HW initialization sequence has 1932215976Sjmallett been triggered, SW must wait 64K eclks before writing 1933215976Sjmallett the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0] 1934215976Sjmallett is driven during refresh sequences in normal operation. 1935215976Sjmallett NOTE: This should only be written to a different value 1936215976Sjmallett during power-on SW initialization. */ 1937215976Sjmallett uint64_t silo_qc : 1; /**< Enables Quarter Cycle move of the Rd sampling window */ 1938215976Sjmallett uint64_t silo_hc : 1; /**< A combination of SILO_HC, SILO_QC and TSKW 1939215976Sjmallett specifies the positioning of the sampling strobe 1940215976Sjmallett when receiving read data back from DDR2. This is 1941215976Sjmallett done to offset any board trace induced delay on 1942215976Sjmallett the DQ and DQS which inherently makes these 1943215976Sjmallett asynchronous with respect to the internal clk of 1944215976Sjmallett controller. TSKW moves this sampling window by 1945215976Sjmallett integer cycles. SILO_QC and HC move this quarter 1946215976Sjmallett and half a cycle respectively. */ 1947215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#fclks): On reads, determines how many 1948215976Sjmallett additional fclks to wait (on top of CASLAT+1) before 1949215976Sjmallett pulling data out of the padring silos used for time 1950215976Sjmallett domain boundary crossing. 1951215976Sjmallett NOTE: This should only be written to a different value 1952215976Sjmallett during power-on SW initialization. */ 1953215976Sjmallett uint64_t bprch : 1; /**< Tristate Enable (back porch) (\#fclks) 1954215976Sjmallett On reads, allows user to control the shape of the 1955215976Sjmallett tristate disable back porch for the DQ data bus. 1956215976Sjmallett This parameter is also very dependent on the 1957215976Sjmallett RW_DLY and WR_DLY parameters and care must be 1958215976Sjmallett taken when programming these parameters to avoid 1959215976Sjmallett data bus contention. Valid range [0..2] 1960215976Sjmallett NOTE: This should only be written to a different value 1961215976Sjmallett during power-on SW initialization. */ 1962215976Sjmallett uint64_t fprch : 1; /**< Tristate Enable (front porch) (\#fclks) 1963215976Sjmallett On reads, allows user to control the shape of the 1964215976Sjmallett tristate disable front porch for the DQ data bus. 1965215976Sjmallett This parameter is also very dependent on the 1966215976Sjmallett RW_DLY and WR_DLY parameters and care must be 1967215976Sjmallett taken when programming these parameters to avoid 1968215976Sjmallett data bus contention. Valid range [0..2] 1969215976Sjmallett NOTE: This should only be written to a different value 1970215976Sjmallett during power-on SW initialization. */ 1971215976Sjmallett uint64_t init : 1; /**< When a '1' is written (and the previous value was '0'), 1972215976Sjmallett the HW init sequence(s) for the LLM Memory Port is 1973215976Sjmallett initiated. 1974215976Sjmallett NOTE: To initialize memory, SW must: 1975215976Sjmallett 1) Enable memory port 1976215976Sjmallett a) PRTENA=1 1977215976Sjmallett 2) Wait 200us (to ensure a stable clock 1978215976Sjmallett to the DDR2) - as per DDR2 spec. 1979215976Sjmallett 3) Write a '1' to the INIT which 1980215976Sjmallett will initiate a hardware initialization 1981215976Sjmallett sequence. 1982215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 1983215976Sjmallett cycles to ensure the HW init sequence has completed 1984215976Sjmallett before writing to ANY of the DFA_DDR2* registers. 1985215976Sjmallett NOTE: This should only be written to a different value 1986215976Sjmallett during power-on SW initialization. */ 1987215976Sjmallett uint64_t prtena : 1; /**< Enable DFA Memory 1988215976Sjmallett When enabled, this bit lets N3K be the default 1989215976Sjmallett driver for DFA-LLM memory port. */ 1990215976Sjmallett#else 1991215976Sjmallett uint64_t prtena : 1; 1992215976Sjmallett uint64_t init : 1; 1993215976Sjmallett uint64_t fprch : 1; 1994215976Sjmallett uint64_t bprch : 1; 1995215976Sjmallett uint64_t sil_lat : 2; 1996215976Sjmallett uint64_t silo_hc : 1; 1997215976Sjmallett uint64_t silo_qc : 1; 1998215976Sjmallett uint64_t rnk_msk : 4; 1999215976Sjmallett uint64_t tskw : 2; 2000215976Sjmallett uint64_t reserved_14_15 : 2; 2001215976Sjmallett uint64_t ref_int : 13; 2002215976Sjmallett uint64_t reserved_29_31 : 3; 2003215976Sjmallett uint64_t fpip : 3; 2004215976Sjmallett uint64_t mrs_pgm : 1; 2005215976Sjmallett uint64_t trfc : 5; 2006215976Sjmallett uint64_t reserved_41_63 : 23; 2007215976Sjmallett#endif 2008215976Sjmallett } s; 2009215976Sjmallett struct cvmx_dfa_ddr2_cfg_s cn31xx; 2010215976Sjmallett}; 2011215976Sjmalletttypedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t; 2012215976Sjmallett 2013215976Sjmallett/** 2014215976Sjmallett * cvmx_dfa_ddr2_comp 2015215976Sjmallett * 2016215976Sjmallett * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration 2017215976Sjmallett * 2018215976Sjmallett * 2019215976Sjmallett * Description: The following are registers to program the DDR2 PLL and DLL 2020215976Sjmallett */ 2021232812Sjmallettunion cvmx_dfa_ddr2_comp { 2022215976Sjmallett uint64_t u64; 2023232812Sjmallett struct cvmx_dfa_ddr2_comp_s { 2024232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2025215976Sjmallett uint64_t dfa__pctl : 4; /**< DFA DDR pctl from compensation circuit 2026215976Sjmallett Internal DBG only */ 2027215976Sjmallett uint64_t dfa__nctl : 4; /**< DFA DDR nctl from compensation circuit 2028215976Sjmallett Internal DBG only */ 2029215976Sjmallett uint64_t reserved_9_55 : 47; 2030215976Sjmallett uint64_t pctl_csr : 4; /**< Compensation control bits */ 2031215976Sjmallett uint64_t nctl_csr : 4; /**< Compensation control bits */ 2032215976Sjmallett uint64_t comp_bypass : 1; /**< Compensation Bypass */ 2033215976Sjmallett#else 2034215976Sjmallett uint64_t comp_bypass : 1; 2035215976Sjmallett uint64_t nctl_csr : 4; 2036215976Sjmallett uint64_t pctl_csr : 4; 2037215976Sjmallett uint64_t reserved_9_55 : 47; 2038215976Sjmallett uint64_t dfa__nctl : 4; 2039215976Sjmallett uint64_t dfa__pctl : 4; 2040215976Sjmallett#endif 2041215976Sjmallett } s; 2042215976Sjmallett struct cvmx_dfa_ddr2_comp_s cn31xx; 2043215976Sjmallett}; 2044215976Sjmalletttypedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t; 2045215976Sjmallett 2046215976Sjmallett/** 2047215976Sjmallett * cvmx_dfa_ddr2_emrs 2048215976Sjmallett * 2049215976Sjmallett * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0] 2050215976Sjmallett * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 2051215976Sjmallett * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 2052215976Sjmallett * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 2053215976Sjmallett * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 2054215976Sjmallett * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 2055215976Sjmallett * 2056215976Sjmallett * Notes: 2057215976Sjmallett * For DDR-II please consult your device's data sheet for further details: 2058215976Sjmallett * 2059215976Sjmallett */ 2060232812Sjmallettunion cvmx_dfa_ddr2_emrs { 2061215976Sjmallett uint64_t u64; 2062232812Sjmallett struct cvmx_dfa_ddr2_emrs_s { 2063232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2064215976Sjmallett uint64_t reserved_31_63 : 33; 2065215976Sjmallett uint64_t emrs1_ocd : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)" 2066215976Sjmallett step \#12a "EMRS OCD Default Command" A[9:7]=111 2067215976Sjmallett of DDR2 HW initialization sequence. 2068215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): 2069215976Sjmallett Power Up and initialization sequence). 2070215976Sjmallett A[14:13] = 0, RESERVED 2071215976Sjmallett A[12] = 0, Output Buffers Enabled 2072215976Sjmallett A[11] = 0, RDQS Disabled (we do not support RDQS) 2073215976Sjmallett A[10] = 0, DQSn Enabled 2074215976Sjmallett A[9:7] = 7, OCD Calibration Mode Default 2075215976Sjmallett A[6] = 0, ODT Disabled 2076215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 2077215976Sjmallett A[2]=0 Termination Res RTT (ODT off Default) 2078215976Sjmallett [A6,A2] = 0 -> ODT Disabled 2079215976Sjmallett 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 2080215976Sjmallett A[1]=0 Normal Output Driver Imp mode 2081215976Sjmallett (1 - weak ie., 60% of normal drive strength) 2082215976Sjmallett A[0] = 0 DLL Enabled */ 2083215976Sjmallett uint64_t reserved_15_15 : 1; 2084215976Sjmallett uint64_t emrs1 : 15; /**< Memory Address[14:0] during: 2085215976Sjmallett a) Step \#7 "EMRS1 to enable DLL (A[0]=0)" 2086215976Sjmallett b) Step \#12b "EMRS OCD Calibration Mode Exit" 2087215976Sjmallett steps of DDR2 HW initialization sequence. 2088215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up and 2089215976Sjmallett initialization sequence). 2090215976Sjmallett A[14:13] = 0, RESERVED 2091215976Sjmallett A[12] = 0, Output Buffers Enabled 2092215976Sjmallett A[11] = 0, RDQS Disabled (we do not support RDQS) 2093215976Sjmallett A[10] = 0, DQSn Enabled 2094215976Sjmallett A[9:7] = 0, OCD Calibration Mode exit/maintain 2095215976Sjmallett A[6] = 0, ODT Disabled 2096215976Sjmallett A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 2097215976Sjmallett A[2]=0 Termination Res RTT (ODT off Default) 2098215976Sjmallett [A6,A2] = 0 -> ODT Disabled 2099215976Sjmallett 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 2100215976Sjmallett A[1]=0 Normal Output Driver Imp mode 2101215976Sjmallett (1 - weak ie., 60% of normal drive strength) 2102215976Sjmallett A[0] = 0 DLL Enabled */ 2103215976Sjmallett#else 2104215976Sjmallett uint64_t emrs1 : 15; 2105215976Sjmallett uint64_t reserved_15_15 : 1; 2106215976Sjmallett uint64_t emrs1_ocd : 15; 2107215976Sjmallett uint64_t reserved_31_63 : 33; 2108215976Sjmallett#endif 2109215976Sjmallett } s; 2110215976Sjmallett struct cvmx_dfa_ddr2_emrs_s cn31xx; 2111215976Sjmallett}; 2112215976Sjmalletttypedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t; 2113215976Sjmallett 2114215976Sjmallett/** 2115215976Sjmallett * cvmx_dfa_ddr2_fcnt 2116215976Sjmallett * 2117215976Sjmallett * DFA_DDR2_FCNT = DFA FCLK Counter 2118215976Sjmallett * 2119215976Sjmallett * 2120215976Sjmallett * Description: This FCLK cycle counter gets going after memory has been initialized 2121215976Sjmallett */ 2122232812Sjmallettunion cvmx_dfa_ddr2_fcnt { 2123215976Sjmallett uint64_t u64; 2124232812Sjmallett struct cvmx_dfa_ddr2_fcnt_s { 2125232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2126215976Sjmallett uint64_t reserved_47_63 : 17; 2127215976Sjmallett uint64_t fcyc_cnt : 47; /**< Counter counts FCLK cycles or \# cycles that the memory 2128215976Sjmallett controller has requests queued up depending on FCNT_MODE 2129215976Sjmallett If FCNT_MODE = 0, this counter counts the \# FCLK cycles 2130215976Sjmallett If FCNT_MODE = 1, this counter counts the \# cycles the 2131215976Sjmallett controller is active with memory requests. */ 2132215976Sjmallett#else 2133215976Sjmallett uint64_t fcyc_cnt : 47; 2134215976Sjmallett uint64_t reserved_47_63 : 17; 2135215976Sjmallett#endif 2136215976Sjmallett } s; 2137215976Sjmallett struct cvmx_dfa_ddr2_fcnt_s cn31xx; 2138215976Sjmallett}; 2139215976Sjmalletttypedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t; 2140215976Sjmallett 2141215976Sjmallett/** 2142215976Sjmallett * cvmx_dfa_ddr2_mrs 2143215976Sjmallett * 2144215976Sjmallett * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0] 2145215976Sjmallett * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 2146215976Sjmallett * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 2147215976Sjmallett * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 2148215976Sjmallett * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 2149215976Sjmallett * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 2150215976Sjmallett * 2151215976Sjmallett * Notes: 2152215976Sjmallett * For DDR-II please consult your device's data sheet for further details: 2153215976Sjmallett * 2154215976Sjmallett */ 2155232812Sjmallettunion cvmx_dfa_ddr2_mrs { 2156215976Sjmallett uint64_t u64; 2157232812Sjmallett struct cvmx_dfa_ddr2_mrs_s { 2158232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2159215976Sjmallett uint64_t reserved_31_63 : 33; 2160215976Sjmallett uint64_t mrs : 15; /**< Memory Address[14:0] during "MRS without resetting 2161215976Sjmallett DLL A[8]=0" step of HW initialization sequence. 2162215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up 2163215976Sjmallett and initialization sequence - Step \#11). 2164215976Sjmallett A[14:13] = 0, RESERVED 2165215976Sjmallett A[12] = 0, Fast Active Power Down Mode 2166215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR] 2167215976Sjmallett A[8] = 0, for DLL Reset 2168215976Sjmallett A[7] =0 Test Mode (must be 0 for normal operation) 2169215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 2170215976Sjmallett A[3]=0 Burst Type(must be 0:Sequential) 2171215976Sjmallett A[2:0]=2 Burst Length=4(default) */ 2172215976Sjmallett uint64_t reserved_15_15 : 1; 2173215976Sjmallett uint64_t mrs_dll : 15; /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1" 2174215976Sjmallett step of HW initialization sequence. 2175215976Sjmallett (See JEDEC DDR2 specification (JESD79-2): Power Up 2176215976Sjmallett and initialization sequence - Step \#8). 2177215976Sjmallett A[14:13] = 0, RESERVED 2178215976Sjmallett A[12] = 0, Fast Active Power Down Mode 2179215976Sjmallett A[11:9] = DFA_DDR2_TMG[TWR] 2180215976Sjmallett A[8] = 1, for DLL Reset 2181215976Sjmallett A[7] = 0 Test Mode (must be 0 for normal operation) 2182215976Sjmallett A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 2183215976Sjmallett A[3] = 0 Burst Type(must be 0:Sequential) 2184215976Sjmallett A[2:0] = 2 Burst Length=4(default) */ 2185215976Sjmallett#else 2186215976Sjmallett uint64_t mrs_dll : 15; 2187215976Sjmallett uint64_t reserved_15_15 : 1; 2188215976Sjmallett uint64_t mrs : 15; 2189215976Sjmallett uint64_t reserved_31_63 : 33; 2190215976Sjmallett#endif 2191215976Sjmallett } s; 2192215976Sjmallett struct cvmx_dfa_ddr2_mrs_s cn31xx; 2193215976Sjmallett}; 2194215976Sjmalletttypedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t; 2195215976Sjmallett 2196215976Sjmallett/** 2197215976Sjmallett * cvmx_dfa_ddr2_opt 2198215976Sjmallett * 2199215976Sjmallett * DFA_DDR2_OPT = DFA DDR2 Optimization Registers 2200215976Sjmallett * 2201215976Sjmallett * 2202215976Sjmallett * Description: The following are registers to tweak certain parameters to boost performance 2203215976Sjmallett */ 2204232812Sjmallettunion cvmx_dfa_ddr2_opt { 2205215976Sjmallett uint64_t u64; 2206232812Sjmallett struct cvmx_dfa_ddr2_opt_s { 2207232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2208215976Sjmallett uint64_t reserved_10_63 : 54; 2209215976Sjmallett uint64_t max_read_batch : 5; /**< Maximum number of consecutive read to service before 2210215976Sjmallett allowing write to interrupt. */ 2211215976Sjmallett uint64_t max_write_batch : 5; /**< Maximum number of consecutive writes to service before 2212215976Sjmallett allowing reads to interrupt. */ 2213215976Sjmallett#else 2214215976Sjmallett uint64_t max_write_batch : 5; 2215215976Sjmallett uint64_t max_read_batch : 5; 2216215976Sjmallett uint64_t reserved_10_63 : 54; 2217215976Sjmallett#endif 2218215976Sjmallett } s; 2219215976Sjmallett struct cvmx_dfa_ddr2_opt_s cn31xx; 2220215976Sjmallett}; 2221215976Sjmalletttypedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t; 2222215976Sjmallett 2223215976Sjmallett/** 2224215976Sjmallett * cvmx_dfa_ddr2_pll 2225215976Sjmallett * 2226215976Sjmallett * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration 2227215976Sjmallett * 2228215976Sjmallett * 2229215976Sjmallett * Description: The following are registers to program the DDR2 PLL and DLL 2230215976Sjmallett */ 2231232812Sjmallettunion cvmx_dfa_ddr2_pll { 2232215976Sjmallett uint64_t u64; 2233232812Sjmallett struct cvmx_dfa_ddr2_pll_s { 2234232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2235215976Sjmallett uint64_t pll_setting : 17; /**< Internal Debug Use Only */ 2236215976Sjmallett uint64_t reserved_32_46 : 15; 2237215976Sjmallett uint64_t setting90 : 5; /**< Contains the setting of DDR DLL; Internal DBG only */ 2238215976Sjmallett uint64_t reserved_21_26 : 6; 2239215976Sjmallett uint64_t dll_setting : 5; /**< Contains the open loop setting value for the DDR90 delay 2240215976Sjmallett line. */ 2241215976Sjmallett uint64_t dll_byp : 1; /**< DLL Bypass. When set, the DDR90 DLL is bypassed and 2242215976Sjmallett the DLL behaves in Open Loop giving a fixed delay 2243215976Sjmallett set by DLL_SETTING */ 2244215976Sjmallett uint64_t qdll_ena : 1; /**< DDR Quad DLL Enable: A 0->1 transition on this bit after 2245215976Sjmallett erst deassertion will reset the DDR 90 DLL. Allow 2246215976Sjmallett 200 micro seconds for Lock before DDR Init. */ 2247215976Sjmallett uint64_t bw_ctl : 4; /**< Internal Use Only - for Debug */ 2248215976Sjmallett uint64_t bw_upd : 1; /**< Internal Use Only - for Debug */ 2249215976Sjmallett uint64_t pll_div2 : 1; /**< PLL Output is further divided by 2. Useful for slow 2250215976Sjmallett fclk frequencies where the PLL may be out of range. */ 2251215976Sjmallett uint64_t reserved_7_7 : 1; 2252215976Sjmallett uint64_t pll_ratio : 5; /**< Bits <6:2> sets the clk multiplication ratio 2253215976Sjmallett If the fclk frequency desired is less than 260MHz 2254215976Sjmallett (lower end saturation point of the pll), write 2x 2255215976Sjmallett the ratio desired in this register and set PLL_DIV2 */ 2256215976Sjmallett uint64_t pll_bypass : 1; /**< PLL Bypass. Uses the ref_clk without multiplication. */ 2257215976Sjmallett uint64_t pll_init : 1; /**< Need a 0 to 1 pulse on this CSR to get the DFA 2258215976Sjmallett Clk Generator Started. Write this register before 2259215976Sjmallett starting anything. Allow 200 uS for PLL Lock before 2260215976Sjmallett doing anything. */ 2261215976Sjmallett#else 2262215976Sjmallett uint64_t pll_init : 1; 2263215976Sjmallett uint64_t pll_bypass : 1; 2264215976Sjmallett uint64_t pll_ratio : 5; 2265215976Sjmallett uint64_t reserved_7_7 : 1; 2266215976Sjmallett uint64_t pll_div2 : 1; 2267215976Sjmallett uint64_t bw_upd : 1; 2268215976Sjmallett uint64_t bw_ctl : 4; 2269215976Sjmallett uint64_t qdll_ena : 1; 2270215976Sjmallett uint64_t dll_byp : 1; 2271215976Sjmallett uint64_t dll_setting : 5; 2272215976Sjmallett uint64_t reserved_21_26 : 6; 2273215976Sjmallett uint64_t setting90 : 5; 2274215976Sjmallett uint64_t reserved_32_46 : 15; 2275215976Sjmallett uint64_t pll_setting : 17; 2276215976Sjmallett#endif 2277215976Sjmallett } s; 2278215976Sjmallett struct cvmx_dfa_ddr2_pll_s cn31xx; 2279215976Sjmallett}; 2280215976Sjmalletttypedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t; 2281215976Sjmallett 2282215976Sjmallett/** 2283215976Sjmallett * cvmx_dfa_ddr2_tmg 2284215976Sjmallett * 2285215976Sjmallett * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register 2286215976Sjmallett * 2287215976Sjmallett * 2288215976Sjmallett * Description: The following are registers to program the DDR2 memory timing parameters. 2289215976Sjmallett */ 2290232812Sjmallettunion cvmx_dfa_ddr2_tmg { 2291215976Sjmallett uint64_t u64; 2292232812Sjmallett struct cvmx_dfa_ddr2_tmg_s { 2293232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2294215976Sjmallett uint64_t reserved_47_63 : 17; 2295215976Sjmallett uint64_t fcnt_mode : 1; /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles 2296215976Sjmallett If FCNT_MODE = 1, this counter counts the \# cycles the 2297215976Sjmallett controller is active with memory requests. */ 2298215976Sjmallett uint64_t cnt_clr : 1; /**< Clears the FCLK Cyc & Bus Util counter */ 2299215976Sjmallett uint64_t cavmipo : 1; /**< RESERVED */ 2300215976Sjmallett uint64_t ctr_rst : 1; /**< Reset oneshot pulse for refresh counter & Perf counters 2301215976Sjmallett SW should first write this field to a one to clear 2302215976Sjmallett & then write to a zero for normal operation */ 2303215976Sjmallett uint64_t odt_rtt : 2; /**< DDR2 Termination Resistor Setting 2304215976Sjmallett These two bits are loaded into the RTT 2305215976Sjmallett portion of the EMRS register bits A6 & A2. If DDR2's 2306215976Sjmallett termination (for the memory's DQ/DQS/DM pads) is not 2307215976Sjmallett desired, set it to 00. If it is, chose between 2308215976Sjmallett 01 for 75 ohm and 10 for 150 ohm termination. 2309215976Sjmallett 00 = ODT Disabled 2310215976Sjmallett 01 = 75 ohm Termination 2311215976Sjmallett 10 = 150 ohm Termination 2312215976Sjmallett 11 = 50 ohm Termination */ 2313215976Sjmallett uint64_t dqsn_ena : 1; /**< For DDR-II Mode, DIC[1] is used to load into EMRS 2314215976Sjmallett bit 10 - DQSN Enable/Disable field. By default, we 2315215976Sjmallett program the DDR's to drive the DQSN also. Set it to 2316215976Sjmallett 1 if DQSN should be Hi-Z. 2317215976Sjmallett 0 - DQSN Enable 2318215976Sjmallett 1 - DQSN Disable */ 2319215976Sjmallett uint64_t dic : 1; /**< Drive Strength Control: 2320215976Sjmallett For DDR-I/II Mode, DIC[0] is 2321215976Sjmallett loaded into the Extended Mode Register (EMRS) A1 bit 2322215976Sjmallett during initialization. (see DDR-I data sheet EMRS 2323215976Sjmallett description) 2324215976Sjmallett 0 = Normal 2325215976Sjmallett 1 = Reduced */ 2326215976Sjmallett uint64_t r2r_slot : 1; /**< A 1 on this register will force the controller to 2327215976Sjmallett slot a bubble between every reads */ 2328215976Sjmallett uint64_t tfaw : 5; /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1 2329215976Sjmallett Four Access Window time. Relevant only in 2330215976Sjmallett 8-bank parts. 2331215976Sjmallett TFAW = 5'b0 for DDR2-4bank 2332215976Sjmallett TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */ 2333215976Sjmallett uint64_t twtr : 4; /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)] 2334215976Sjmallett Last Wr Data to Rd Command time. 2335215976Sjmallett (Represented in fclk cycles) 2336215976Sjmallett TYP=15ns 2337215976Sjmallett - 0000: RESERVED 2338215976Sjmallett - 0001: 1 2339215976Sjmallett - ... 2340215976Sjmallett - 0111: 7 2341215976Sjmallett - 1000-1111: RESERVED */ 2342215976Sjmallett uint64_t twr : 3; /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech 2343215976Sjmallett This is not a direct encoding of the value. Its 2344215976Sjmallett programmed as below per DDR2 spec. The decimal number 2345215976Sjmallett on the right is RNDUP(tWR(ns) / clkFreq) 2346215976Sjmallett TYP=15ns 2347215976Sjmallett - 000: RESERVED 2348215976Sjmallett - 001: 2 2349215976Sjmallett - 010: 3 2350215976Sjmallett - 011: 4 2351215976Sjmallett - 100: 5 2352215976Sjmallett - 101: 6 2353215976Sjmallett - 110-111: RESERVED */ 2354215976Sjmallett uint64_t trp : 4; /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)] 2355215976Sjmallett (Represented in fclk cycles) 2356215976Sjmallett TYP=15ns 2357215976Sjmallett - 0000: RESERVED 2358215976Sjmallett - 0001: 1 2359215976Sjmallett - ... 2360215976Sjmallett - 0111: 7 2361215976Sjmallett - 1000-1111: RESERVED 2362215976Sjmallett When using parts with 8 banks (DFA_CFG->MAX_BNK 2363215976Sjmallett is 1), load tRP cycles + 1 into this register. */ 2364215976Sjmallett uint64_t tras : 5; /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)] 2365215976Sjmallett (Represented in fclk cycles) 2366215976Sjmallett TYP=45ns 2367215976Sjmallett - 00000-0001: RESERVED 2368215976Sjmallett - 00010: 2 2369215976Sjmallett - ... 2370215976Sjmallett - 10100: 20 2371215976Sjmallett - 10101-11111: RESERVED */ 2372215976Sjmallett uint64_t trrd : 3; /**< tRRD cycles: ACT-ACT timing parameter for different 2373215976Sjmallett banks. (Represented in fclk cycles) 2374215976Sjmallett For DDR2, TYP=7.5ns 2375215976Sjmallett - 000: RESERVED 2376215976Sjmallett - 001: 1 tCYC 2377215976Sjmallett - 010: 2 tCYC 2378215976Sjmallett - 011: 3 tCYC 2379215976Sjmallett - 100: 4 tCYC 2380215976Sjmallett - 101: 5 tCYC 2381215976Sjmallett - 110-111: RESERVED */ 2382215976Sjmallett uint64_t trcd : 4; /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)] 2383215976Sjmallett (Represented in fclk cycles) 2384215976Sjmallett TYP=15ns 2385215976Sjmallett - 0000: RESERVED 2386215976Sjmallett - 0001: 2 (2 is the smallest value allowed) 2387215976Sjmallett - 0002: 2 2388215976Sjmallett - ... 2389215976Sjmallett - 0111: 7 2390215976Sjmallett - 1110-1111: RESERVED */ 2391215976Sjmallett uint64_t addlat : 3; /**< When in Posted CAS mode ADDLAT needs to be programmed 2392215976Sjmallett to tRCD-1 2393215976Sjmallett ADDLAT \#additional latency cycles 2394215976Sjmallett 000 0 2395215976Sjmallett 001 1 (tRCD = 2 fclk's) 2396215976Sjmallett 010 2 (tRCD = 3 fclk's) 2397215976Sjmallett 011 3 (tRCD = 4 fclk's) 2398215976Sjmallett 100 4 (tRCD = 5 fclk's) 2399215976Sjmallett 101 5 (tRCD = 6 fclk's) 2400215976Sjmallett 110 6 (tRCD = 7 fclk's) 2401215976Sjmallett 111 7 (tRCD = 8 fclk's) */ 2402215976Sjmallett uint64_t pocas : 1; /**< Posted CAS mode. When 1, we use DDR2's Posted CAS 2403215976Sjmallett feature. When using this mode, ADDLAT needs to be 2404215976Sjmallett programmed as well */ 2405215976Sjmallett uint64_t caslat : 3; /**< CAS Latency in \# fclk Cycles 2406215976Sjmallett CASLAT \# CAS latency cycles 2407215976Sjmallett 000 - 010 RESERVED 2408215976Sjmallett 011 3 2409215976Sjmallett 100 4 2410215976Sjmallett 101 5 2411215976Sjmallett 110 6 2412215976Sjmallett 111 7 */ 2413215976Sjmallett uint64_t tmrd : 2; /**< tMRD Cycles 2414215976Sjmallett (Represented in fclk tCYC) 2415215976Sjmallett For DDR2, its TYP 2*tCYC) 2416215976Sjmallett - 000: RESERVED 2417215976Sjmallett - 001: 1 2418215976Sjmallett - 010: 2 2419215976Sjmallett - 011: 3 */ 2420215976Sjmallett uint64_t ddr2t : 1; /**< When 2T mode is turned on, command signals are 2421215976Sjmallett setup a cycle ahead of when the CS is enabled 2422215976Sjmallett and kept for a total of 2 cycles. This mode is 2423215976Sjmallett enabled in higher speeds when there is difficulty 2424215976Sjmallett meeting setup. Performance could 2425215976Sjmallett be negatively affected in 2T mode */ 2426215976Sjmallett#else 2427215976Sjmallett uint64_t ddr2t : 1; 2428215976Sjmallett uint64_t tmrd : 2; 2429215976Sjmallett uint64_t caslat : 3; 2430215976Sjmallett uint64_t pocas : 1; 2431215976Sjmallett uint64_t addlat : 3; 2432215976Sjmallett uint64_t trcd : 4; 2433215976Sjmallett uint64_t trrd : 3; 2434215976Sjmallett uint64_t tras : 5; 2435215976Sjmallett uint64_t trp : 4; 2436215976Sjmallett uint64_t twr : 3; 2437215976Sjmallett uint64_t twtr : 4; 2438215976Sjmallett uint64_t tfaw : 5; 2439215976Sjmallett uint64_t r2r_slot : 1; 2440215976Sjmallett uint64_t dic : 1; 2441215976Sjmallett uint64_t dqsn_ena : 1; 2442215976Sjmallett uint64_t odt_rtt : 2; 2443215976Sjmallett uint64_t ctr_rst : 1; 2444215976Sjmallett uint64_t cavmipo : 1; 2445215976Sjmallett uint64_t cnt_clr : 1; 2446215976Sjmallett uint64_t fcnt_mode : 1; 2447215976Sjmallett uint64_t reserved_47_63 : 17; 2448215976Sjmallett#endif 2449215976Sjmallett } s; 2450215976Sjmallett struct cvmx_dfa_ddr2_tmg_s cn31xx; 2451215976Sjmallett}; 2452215976Sjmalletttypedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t; 2453215976Sjmallett 2454215976Sjmallett/** 2455215976Sjmallett * cvmx_dfa_debug0 2456215976Sjmallett * 2457215976Sjmallett * DFA_DEBUG0 = DFA Scoreboard Debug \#0 Register 2458215976Sjmallett * *FOR INTERNAL USE ONLY* 2459215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2460215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2461215976Sjmallett * CSR read. 2462215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2463215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2464215976Sjmallett * instruction. 2465215976Sjmallett */ 2466232812Sjmallettunion cvmx_dfa_debug0 { 2467215976Sjmallett uint64_t u64; 2468232812Sjmallett struct cvmx_dfa_debug0_s { 2469232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2470215976Sjmallett uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 2471215976Sjmallett (DFA Scoreboard Debug) 2472215976Sjmallett [63:38] (26) rptr[28:3]: Result Base Pointer (QW-aligned) 2473215976Sjmallett [37:22] (16) Cumulative Result Write Counter (for HDR write) 2474215976Sjmallett [21] (1) Waiting for GRdRsp EOT 2475215976Sjmallett [20] (1) Waiting for GRdReq Issue (to NRQ) 2476215976Sjmallett [19] (1) GLPTR/GLCNT Valid 2477215976Sjmallett [18] (1) Completion Mark Detected 2478215976Sjmallett [17:15] (3) Completion Code [0=PDGONE/1=PERR/2=RFULL/3=TERM] 2479215976Sjmallett [14] (1) Completion Detected 2480215976Sjmallett [13] (1) Waiting for HDR RWrCmtRsp 2481215976Sjmallett [12] (1) Waiting for LAST RESULT RWrCmtRsp 2482215976Sjmallett [11] (1) Waiting for HDR RWrReq 2483215976Sjmallett [10] (1) Waiting for RWrReq 2484215976Sjmallett [9] (1) Waiting for WQWrReq issue 2485215976Sjmallett [8] (1) Waiting for PRdRsp EOT 2486215976Sjmallett [7] (1) Waiting for PRdReq Issue (to NRQ) 2487215976Sjmallett [6] (1) Packet Data Valid 2488215976Sjmallett [5] (1) WQVLD 2489215976Sjmallett [4] (1) WQ Done Point (either WQWrReq issued (for WQPTR<>0) OR HDR RWrCmtRsp) 2490215976Sjmallett [3] (1) Resultant write STF/P Mode 2491215976Sjmallett [2] (1) Packet Data LDT mode 2492215976Sjmallett [1] (1) Gather Mode 2493215976Sjmallett [0] (1) Valid */ 2494215976Sjmallett#else 2495215976Sjmallett uint64_t sbd0 : 64; 2496215976Sjmallett#endif 2497215976Sjmallett } s; 2498232812Sjmallett struct cvmx_dfa_debug0_s cn61xx; 2499215976Sjmallett struct cvmx_dfa_debug0_s cn63xx; 2500215976Sjmallett struct cvmx_dfa_debug0_s cn63xxp1; 2501232812Sjmallett struct cvmx_dfa_debug0_s cn66xx; 2502232812Sjmallett struct cvmx_dfa_debug0_s cn68xx; 2503232812Sjmallett struct cvmx_dfa_debug0_s cn68xxp1; 2504215976Sjmallett}; 2505215976Sjmalletttypedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t; 2506215976Sjmallett 2507215976Sjmallett/** 2508215976Sjmallett * cvmx_dfa_debug1 2509215976Sjmallett * 2510215976Sjmallett * DFA_DEBUG1 = DFA Scoreboard Debug \#1 Register 2511215976Sjmallett * *FOR INTERNAL USE ONLY* 2512215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2513215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2514215976Sjmallett * CSR read. 2515215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2516215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2517215976Sjmallett * instruction. 2518215976Sjmallett */ 2519232812Sjmallettunion cvmx_dfa_debug1 { 2520215976Sjmallett uint64_t u64; 2521232812Sjmallett struct cvmx_dfa_debug1_s { 2522232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2523215976Sjmallett uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 2524215976Sjmallett DFA Scoreboard Debug Data 2525215976Sjmallett [63:56] (8) UNUSED 2526215976Sjmallett [55:16] (40) Packet Data Pointer 2527215976Sjmallett [15:0] (16) Packet Data Counter */ 2528215976Sjmallett#else 2529215976Sjmallett uint64_t sbd1 : 64; 2530215976Sjmallett#endif 2531215976Sjmallett } s; 2532232812Sjmallett struct cvmx_dfa_debug1_s cn61xx; 2533215976Sjmallett struct cvmx_dfa_debug1_s cn63xx; 2534215976Sjmallett struct cvmx_dfa_debug1_s cn63xxp1; 2535232812Sjmallett struct cvmx_dfa_debug1_s cn66xx; 2536232812Sjmallett struct cvmx_dfa_debug1_s cn68xx; 2537232812Sjmallett struct cvmx_dfa_debug1_s cn68xxp1; 2538215976Sjmallett}; 2539215976Sjmalletttypedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t; 2540215976Sjmallett 2541215976Sjmallett/** 2542215976Sjmallett * cvmx_dfa_debug2 2543215976Sjmallett * 2544215976Sjmallett * DFA_DEBUG2 = DFA Scoreboard Debug \#2 Register 2545215976Sjmallett * 2546215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2547215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2548215976Sjmallett * CSR read. 2549215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2550215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2551215976Sjmallett * instruction. 2552215976Sjmallett */ 2553232812Sjmallettunion cvmx_dfa_debug2 { 2554215976Sjmallett uint64_t u64; 2555232812Sjmallett struct cvmx_dfa_debug2_s { 2556232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2557215976Sjmallett uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 2558215976Sjmallett [63:45] (19) UNUSED 2559215976Sjmallett [44:42] (3) Instruction Type 2560215976Sjmallett [41:5] (37) rwptr[39:3]: Result Write Pointer 2561215976Sjmallett [4:0] (5) prwcnt[4:0]: Pending Result Write Counter */ 2562215976Sjmallett#else 2563215976Sjmallett uint64_t sbd2 : 64; 2564215976Sjmallett#endif 2565215976Sjmallett } s; 2566232812Sjmallett struct cvmx_dfa_debug2_s cn61xx; 2567215976Sjmallett struct cvmx_dfa_debug2_s cn63xx; 2568215976Sjmallett struct cvmx_dfa_debug2_s cn63xxp1; 2569232812Sjmallett struct cvmx_dfa_debug2_s cn66xx; 2570232812Sjmallett struct cvmx_dfa_debug2_s cn68xx; 2571232812Sjmallett struct cvmx_dfa_debug2_s cn68xxp1; 2572215976Sjmallett}; 2573215976Sjmalletttypedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t; 2574215976Sjmallett 2575215976Sjmallett/** 2576215976Sjmallett * cvmx_dfa_debug3 2577215976Sjmallett * 2578215976Sjmallett * DFA_DEBUG3 = DFA Scoreboard Debug \#3 Register 2579215976Sjmallett * 2580215976Sjmallett * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2581215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2582215976Sjmallett * CSR read. 2583215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2584215976Sjmallett * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2585215976Sjmallett * instruction. 2586215976Sjmallett */ 2587232812Sjmallettunion cvmx_dfa_debug3 { 2588215976Sjmallett uint64_t u64; 2589232812Sjmallett struct cvmx_dfa_debug3_s { 2590232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2591215976Sjmallett uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 2592215976Sjmallett [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned) 2593215976Sjmallett [52:16] (37) glptr[39:3]: Gather List Pointer 2594215976Sjmallett [15:0] (16) glcnt Gather List Counter */ 2595215976Sjmallett#else 2596215976Sjmallett uint64_t sbd3 : 64; 2597215976Sjmallett#endif 2598215976Sjmallett } s; 2599232812Sjmallett struct cvmx_dfa_debug3_s cn61xx; 2600215976Sjmallett struct cvmx_dfa_debug3_s cn63xx; 2601215976Sjmallett struct cvmx_dfa_debug3_s cn63xxp1; 2602232812Sjmallett struct cvmx_dfa_debug3_s cn66xx; 2603232812Sjmallett struct cvmx_dfa_debug3_s cn68xx; 2604232812Sjmallett struct cvmx_dfa_debug3_s cn68xxp1; 2605215976Sjmallett}; 2606215976Sjmalletttypedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t; 2607215976Sjmallett 2608215976Sjmallett/** 2609215976Sjmallett * cvmx_dfa_difctl 2610215976Sjmallett * 2611215976Sjmallett * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register 2612215976Sjmallett * 2613215976Sjmallett * Description: 2614215976Sjmallett * NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b110. 2615215976Sjmallett * To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b110. 2616215976Sjmallett * 2617215976Sjmallett * NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could 2618215976Sjmallett * cause the DFA and FPA HW to become unpredictable. 2619215976Sjmallett * 2620215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect. 2621215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect. 2622215976Sjmallett */ 2623232812Sjmallettunion cvmx_dfa_difctl { 2624215976Sjmallett uint64_t u64; 2625232812Sjmallett struct cvmx_dfa_difctl_s { 2626232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2627232812Sjmallett uint64_t reserved_26_63 : 38; 2628232812Sjmallett uint64_t msegbase : 6; /**< Memory Segmentation Base Address 2629232812Sjmallett For debug purposes, backdoor accesses to the DFA 2630232812Sjmallett memory are supported via NCB-Direct CSR accesses to 2631232812Sjmallett the DFA Memory REGION(if addr[34:32]=5. However due 2632232812Sjmallett to the existing NCB address decoding scheme, the 2633232812Sjmallett address only offers a 4GB extent into the DFA memory 2634232812Sjmallett REGION. Therefore, the MSEGBASE CSR field provides 2635232812Sjmallett the additional upper memory address bits to allow access 2636232812Sjmallett to the full extent of memory (128GB MAX). 2637232812Sjmallett For DFA Memory REGION read NCB-Direct CSR accesses, the 2638232812Sjmallett 38bit L2/DRAM memory byte address is generated as follows: 2639232812Sjmallett memaddr[37:0] = [DFA_DIFCTL[MSEGBASE],ncb_addr[31:3],3'b0] 2640232812Sjmallett NOTE: See the upper 6bits of the memory address are sourced 2641232812Sjmallett from DFA_DIFCTL[MSEGBASE] CSR field. The lower 4GB address 2642232812Sjmallett offset is directly referenced using the NCB address bits during 2643232812Sjmallett the reference itself. 2644232812Sjmallett NOTE: The DFA_DIFCTL[MSEGBASE] is shared amongst all references. 2645232812Sjmallett As such, if multiple PPs are accessing different segments in memory, 2646232812Sjmallett their must be a SW mutual exclusive lock during each DFA Memory 2647232812Sjmallett REGION access to avoid collisions between PPs using the same MSEGBASE 2648232812Sjmallett CSR field. 2649232812Sjmallett NOTE: See also DFA_ERROR[DFANXM] programmable interrupt which is 2650232812Sjmallett flagged if SW tries to access non-existent memory space (address hole 2651232812Sjmallett or upper unused region of 38bit address space). */ 2652232812Sjmallett uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction 2653232812Sjmallett buffer that may be dirty and should not be 2654232812Sjmallett written-back to memory when the instruction 2655232812Sjmallett chunk is returned to the Free Page list. 2656232812Sjmallett NOTE: Typically SW will want to mark all DFA 2657232812Sjmallett Instruction memory returned to the Free Page list 2658232812Sjmallett as DWB (Don't WriteBack), therefore SW should 2659232812Sjmallett seed this register as: 2660232812Sjmallett DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */ 2661232812Sjmallett uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW 2662232812Sjmallett when the DFA instruction chunk is recycled back 2663232812Sjmallett to the Free Page List maintained by the FPA HW 2664232812Sjmallett (once the DFA instruction has been issued). */ 2665232812Sjmallett uint64_t size : 9; /**< Represents the \# of 32B instructions contained 2666232812Sjmallett within each DFA instruction chunk. At Power-on, 2667232812Sjmallett SW will seed the SIZE register with a fixed 2668232812Sjmallett chunk-size. (Must be at least 3) 2669232812Sjmallett DFA HW uses this field to determine the size 2670232812Sjmallett of each DFA instruction chunk, in order to: 2671232812Sjmallett a) determine when to read the next DFA 2672232812Sjmallett instruction chunk pointer which is 2673232812Sjmallett written by SW at the end of the current 2674232812Sjmallett DFA instruction chunk (see DFA description 2675232812Sjmallett of next chunk buffer Ptr for format). 2676232812Sjmallett b) determine when a DFA instruction chunk 2677232812Sjmallett can be returned to the Free Page List 2678232812Sjmallett maintained by the FPA HW. */ 2679232812Sjmallett#else 2680232812Sjmallett uint64_t size : 9; 2681232812Sjmallett uint64_t pool : 3; 2682232812Sjmallett uint64_t dwbcnt : 8; 2683232812Sjmallett uint64_t msegbase : 6; 2684232812Sjmallett uint64_t reserved_26_63 : 38; 2685232812Sjmallett#endif 2686232812Sjmallett } s; 2687232812Sjmallett struct cvmx_dfa_difctl_cn31xx { 2688232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2689215976Sjmallett uint64_t reserved_20_63 : 44; 2690215976Sjmallett uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction 2691215976Sjmallett buffer that may be dirty and should not be 2692215976Sjmallett written-back to memory when the instruction 2693215976Sjmallett chunk is returned to the Free Page list. 2694215976Sjmallett NOTE: Typically SW will want to mark all DFA 2695215976Sjmallett Instruction memory returned to the Free Page list 2696215976Sjmallett as DWB (Don't WriteBack), therefore SW should 2697215976Sjmallett seed this register as: 2698215976Sjmallett DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */ 2699215976Sjmallett uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW 2700215976Sjmallett when the DFA instruction chunk is recycled back 2701215976Sjmallett to the Free Page List maintained by the FPA HW 2702215976Sjmallett (once the DFA instruction has been issued). */ 2703215976Sjmallett uint64_t size : 9; /**< Represents the \# of 32B instructions contained 2704215976Sjmallett within each DFA instruction chunk. At Power-on, 2705215976Sjmallett SW will seed the SIZE register with a fixed 2706215976Sjmallett chunk-size. (Must be at least 3) 2707215976Sjmallett DFA HW uses this field to determine the size 2708215976Sjmallett of each DFA instruction chunk, in order to: 2709215976Sjmallett a) determine when to read the next DFA 2710215976Sjmallett instruction chunk pointer which is 2711215976Sjmallett written by SW at the end of the current 2712215976Sjmallett DFA instruction chunk (see DFA description 2713215976Sjmallett of next chunk buffer Ptr for format). 2714215976Sjmallett b) determine when a DFA instruction chunk 2715215976Sjmallett can be returned to the Free Page List 2716215976Sjmallett maintained by the FPA HW. */ 2717215976Sjmallett#else 2718215976Sjmallett uint64_t size : 9; 2719215976Sjmallett uint64_t pool : 3; 2720215976Sjmallett uint64_t dwbcnt : 8; 2721215976Sjmallett uint64_t reserved_20_63 : 44; 2722215976Sjmallett#endif 2723232812Sjmallett } cn31xx; 2724232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn38xx; 2725232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn38xxp2; 2726232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn58xx; 2727232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn58xxp1; 2728232812Sjmallett struct cvmx_dfa_difctl_s cn61xx; 2729232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn63xx; 2730232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn63xxp1; 2731232812Sjmallett struct cvmx_dfa_difctl_cn31xx cn66xx; 2732232812Sjmallett struct cvmx_dfa_difctl_s cn68xx; 2733232812Sjmallett struct cvmx_dfa_difctl_s cn68xxp1; 2734215976Sjmallett}; 2735215976Sjmalletttypedef union cvmx_dfa_difctl cvmx_dfa_difctl_t; 2736215976Sjmallett 2737215976Sjmallett/** 2738215976Sjmallett * cvmx_dfa_difrdptr 2739215976Sjmallett * 2740215976Sjmallett * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register 2741215976Sjmallett * 2742215976Sjmallett * Description: 2743215976Sjmallett * NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01. 2744215976Sjmallett * To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01. 2745215976Sjmallett * 2746215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect. 2747215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect. 2748215976Sjmallett */ 2749232812Sjmallettunion cvmx_dfa_difrdptr { 2750215976Sjmallett uint64_t u64; 2751232812Sjmallett struct cvmx_dfa_difrdptr_s { 2752232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2753215976Sjmallett uint64_t reserved_40_63 : 24; 2754215976Sjmallett uint64_t rdptr : 35; /**< Represents the 32B-aligned address of the current 2755215976Sjmallett instruction in the DFA Instruction FIFO in main 2756215976Sjmallett memory. The RDPTR must be seeded by software at 2757215976Sjmallett boot time, and is then maintained thereafter 2758215976Sjmallett by DFA HW. 2759215976Sjmallett During the seed write (by SW), RDPTR[6:5]=0, 2760215976Sjmallett since DFA instruction chunks must be 128B aligned. 2761215976Sjmallett During a read (by SW), the 'most recent' contents 2762215976Sjmallett of the RDPTR register are returned at the time 2763215976Sjmallett the NCB-INB bus is driven. 2764215976Sjmallett NOTE: Since DFA HW updates this register, its 2765215976Sjmallett contents are unpredictable in SW (unless 2766215976Sjmallett its guaranteed that no new DoorBell register 2767215976Sjmallett writes have occurred and the DoorBell register is 2768215976Sjmallett read as zero). */ 2769215976Sjmallett uint64_t reserved_0_4 : 5; 2770215976Sjmallett#else 2771215976Sjmallett uint64_t reserved_0_4 : 5; 2772215976Sjmallett uint64_t rdptr : 35; 2773215976Sjmallett uint64_t reserved_40_63 : 24; 2774215976Sjmallett#endif 2775215976Sjmallett } s; 2776232812Sjmallett struct cvmx_dfa_difrdptr_cn31xx { 2777232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2778215976Sjmallett uint64_t reserved_36_63 : 28; 2779215976Sjmallett uint64_t rdptr : 31; /**< Represents the 32B-aligned address of the current 2780215976Sjmallett instruction in the DFA Instruction FIFO in main 2781215976Sjmallett memory. The RDPTR must be seeded by software at 2782215976Sjmallett boot time, and is then maintained thereafter 2783215976Sjmallett by DFA HW. 2784215976Sjmallett During the seed write (by SW), RDPTR[6:5]=0, 2785215976Sjmallett since DFA instruction chunks must be 128B aligned. 2786215976Sjmallett During a read (by SW), the 'most recent' contents 2787215976Sjmallett of the RDPTR register are returned at the time 2788215976Sjmallett the NCB-INB bus is driven. 2789215976Sjmallett NOTE: Since DFA HW updates this register, its 2790215976Sjmallett contents are unpredictable in SW (unless 2791215976Sjmallett its guaranteed that no new DoorBell register 2792215976Sjmallett writes have occurred and the DoorBell register is 2793215976Sjmallett read as zero). */ 2794215976Sjmallett uint64_t reserved_0_4 : 5; 2795215976Sjmallett#else 2796215976Sjmallett uint64_t reserved_0_4 : 5; 2797215976Sjmallett uint64_t rdptr : 31; 2798215976Sjmallett uint64_t reserved_36_63 : 28; 2799215976Sjmallett#endif 2800215976Sjmallett } cn31xx; 2801215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn38xx; 2802215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn38xxp2; 2803215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn58xx; 2804215976Sjmallett struct cvmx_dfa_difrdptr_cn31xx cn58xxp1; 2805232812Sjmallett struct cvmx_dfa_difrdptr_s cn61xx; 2806215976Sjmallett struct cvmx_dfa_difrdptr_s cn63xx; 2807215976Sjmallett struct cvmx_dfa_difrdptr_s cn63xxp1; 2808232812Sjmallett struct cvmx_dfa_difrdptr_s cn66xx; 2809232812Sjmallett struct cvmx_dfa_difrdptr_s cn68xx; 2810232812Sjmallett struct cvmx_dfa_difrdptr_s cn68xxp1; 2811215976Sjmallett}; 2812215976Sjmalletttypedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t; 2813215976Sjmallett 2814215976Sjmallett/** 2815215976Sjmallett * cvmx_dfa_dtcfadr 2816215976Sjmallett * 2817215976Sjmallett * DFA_DTCFADR = DFA DTC Failing Address Register 2818215976Sjmallett * 2819215976Sjmallett * Description: DFA Node Cache Failing Address/Control Error Capture information 2820215976Sjmallett * This register contains useful information to help in isolating a Node Cache RAM failure. 2821215976Sjmallett * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the 2822215976Sjmallett * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]). 2823232812Sjmallett * NOTE: In the rare event that multiple parity errors are detected in the same cycle from multiple 2824232812Sjmallett * clusters, the FADR register will be locked down for the least signicant cluster \# (0->3). 2825215976Sjmallett */ 2826232812Sjmallettunion cvmx_dfa_dtcfadr { 2827215976Sjmallett uint64_t u64; 2828232812Sjmallett struct cvmx_dfa_dtcfadr_s { 2829232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2830215976Sjmallett uint64_t reserved_44_63 : 20; 2831215976Sjmallett uint64_t ram3fadr : 12; /**< DFA RAM3 Failing Address 2832215976Sjmallett If DFA_ERR[DC0PERR<2>]=1, this field indicates the 2833215976Sjmallett failing RAM3 Address. The failing address is locked 2834232812Sjmallett down until the DC0PERR<2> W1C occurs. 2835232812Sjmallett NOTE: If multiple DC0PERR<0>=1 errors are detected, 2836232812Sjmallett then the lsb cluster error information is captured. */ 2837215976Sjmallett uint64_t reserved_25_31 : 7; 2838215976Sjmallett uint64_t ram2fadr : 9; /**< DFA RAM2 Failing Address 2839215976Sjmallett If DFA_ERR[DC0PERR<1>]=1, this field indicates the 2840215976Sjmallett failing RAM2 Address. The failing address is locked 2841232812Sjmallett down until the DC0PERR<1> W1C occurs. 2842232812Sjmallett NOTE: If multiple DC0PERR<0>=1 errors are detected, 2843232812Sjmallett then the lsb cluster error information is captured. */ 2844215976Sjmallett uint64_t reserved_14_15 : 2; 2845215976Sjmallett uint64_t ram1fadr : 14; /**< DFA RAM1 Failing Address 2846215976Sjmallett If DFA_ERR[DC0PERR<0>]=1, this field indicates the 2847215976Sjmallett failing RAM1 Address. The failing address is locked 2848232812Sjmallett down until the DC0PERR<0> W1C occurs. 2849232812Sjmallett NOTE: If multiple DC0PERR<0>=1 errors are detected, 2850232812Sjmallett then the lsb cluster error information is captured. */ 2851215976Sjmallett#else 2852215976Sjmallett uint64_t ram1fadr : 14; 2853215976Sjmallett uint64_t reserved_14_15 : 2; 2854215976Sjmallett uint64_t ram2fadr : 9; 2855215976Sjmallett uint64_t reserved_25_31 : 7; 2856215976Sjmallett uint64_t ram3fadr : 12; 2857215976Sjmallett uint64_t reserved_44_63 : 20; 2858215976Sjmallett#endif 2859215976Sjmallett } s; 2860232812Sjmallett struct cvmx_dfa_dtcfadr_s cn61xx; 2861215976Sjmallett struct cvmx_dfa_dtcfadr_s cn63xx; 2862215976Sjmallett struct cvmx_dfa_dtcfadr_s cn63xxp1; 2863232812Sjmallett struct cvmx_dfa_dtcfadr_s cn66xx; 2864232812Sjmallett struct cvmx_dfa_dtcfadr_s cn68xx; 2865232812Sjmallett struct cvmx_dfa_dtcfadr_s cn68xxp1; 2866215976Sjmallett}; 2867215976Sjmalletttypedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t; 2868215976Sjmallett 2869215976Sjmallett/** 2870215976Sjmallett * cvmx_dfa_eclkcfg 2871215976Sjmallett * 2872215976Sjmallett * Specify the RSL base addresses for the block 2873215976Sjmallett * 2874215976Sjmallett * DFA_ECLKCFG = DFA eclk-domain Configuration Registers 2875215976Sjmallett * 2876215976Sjmallett * Description: 2877215976Sjmallett */ 2878232812Sjmallettunion cvmx_dfa_eclkcfg { 2879215976Sjmallett uint64_t u64; 2880232812Sjmallett struct cvmx_dfa_eclkcfg_s { 2881232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2882215976Sjmallett uint64_t reserved_19_63 : 45; 2883215976Sjmallett uint64_t sbdnum : 3; /**< SBD Debug Entry# 2884215976Sjmallett For internal use only. (DFA Scoreboard debug) 2885215976Sjmallett Selects which one of 8 DFA Scoreboard entries is 2886215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 2887215976Sjmallett uint64_t reserved_15_15 : 1; 2888215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 2889215976Sjmallett For internal use only. (DFA Scoreboard debug) 2890215976Sjmallett When written with a '1', the DFA Scoreboard Debug 2891215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 2892215976Sjmallett This allows SW to lock down the contents of the entire 2893215976Sjmallett SBD for a single instant in time. All subsequent reads 2894215976Sjmallett of the DFA scoreboard registers will return the data 2895215976Sjmallett from that instant in time. */ 2896215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 2897215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 2898215976Sjmallett NOTE: This should only be written to a different value 2899215976Sjmallett during power-on SW initialization. */ 2900215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 2901215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 2902215976Sjmallett NOTE: This should only be written to a different value 2903215976Sjmallett during power-on SW initialization. */ 2904215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 2905215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 2906215976Sjmallett NOTE: This should only be written to a different value 2907215976Sjmallett during power-on SW initialization. */ 2908215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 2909215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 2910215976Sjmallett NOTE: This should only be written to a different value 2911215976Sjmallett during power-on SW initialization. */ 2912215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 2913215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 2914215976Sjmallett NOTE: This should only be written to a different value 2915215976Sjmallett during power-on SW initialization. */ 2916215976Sjmallett uint64_t sarb : 1; /**< DFA Source Arbiter Mode 2917215976Sjmallett Selects the arbitration mode used to select DFA requests 2918215976Sjmallett issued from either CP2 or the DTE (NCB-CSR or DFA HW engine). 2919215976Sjmallett - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 2920215976Sjmallett - 1: Round-Robin 2921215976Sjmallett NOTE: This should only be written to a different value 2922215976Sjmallett during power-on SW initialization. */ 2923215976Sjmallett uint64_t reserved_3_7 : 5; 2924215976Sjmallett uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 2925215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 2926215976Sjmallett operation are disabled. 2927215976Sjmallett NOTE: When SET, SW MUST NEVER issue ANY operations to 2928215976Sjmallett the DFA via the NCB Bus. All DFA Operations must be 2929215976Sjmallett issued solely through the CP2 interface. */ 2930215976Sjmallett uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 2931215976Sjmallett when extracting address bits for the memory bank#. 2932215976Sjmallett - 0: 4 banks/device 2933215976Sjmallett - 1: 8 banks/device */ 2934215976Sjmallett uint64_t dfa_frstn : 1; /**< Hold this 0 until the DFA DDR PLL and DLL lock 2935215976Sjmallett and then write a 1. A 1 on this register deasserts 2936215976Sjmallett the internal frst_n. Refer to DFA_DDR2_PLL registers for more 2937215976Sjmallett startup information. 2938215976Sjmallett Startup sequence if DFA interface needs to be ON: 2939215976Sjmallett After valid power up, 2940215976Sjmallett Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS 2941215976Sjmallett to the appropriate values 2942215976Sjmallett Wait a few cycles 2943215976Sjmallett Write a 1 DFA_DDR2_PLL -> PLL_INIT 2944215976Sjmallett Wait 100 microseconds 2945215976Sjmallett Write a 1 to DFA_DDR2_PLL -> QDLL_ENA 2946215976Sjmallett Wait 10 microseconds 2947215976Sjmallett Write a 1 to this register DFA_FRSTN to pull DFA out of 2948215976Sjmallett reset 2949215976Sjmallett Now the DFA block is ready to be initialized (follow the 2950215976Sjmallett DDR init sequence). */ 2951215976Sjmallett#else 2952215976Sjmallett uint64_t dfa_frstn : 1; 2953215976Sjmallett uint64_t maxbnk : 1; 2954215976Sjmallett uint64_t dteclkdis : 1; 2955215976Sjmallett uint64_t reserved_3_7 : 5; 2956215976Sjmallett uint64_t sarb : 1; 2957215976Sjmallett uint64_t imode : 1; 2958215976Sjmallett uint64_t qmode : 1; 2959215976Sjmallett uint64_t pmode : 1; 2960215976Sjmallett uint64_t dtmode : 1; 2961215976Sjmallett uint64_t dcmode : 1; 2962215976Sjmallett uint64_t sbdlck : 1; 2963215976Sjmallett uint64_t reserved_15_15 : 1; 2964215976Sjmallett uint64_t sbdnum : 3; 2965215976Sjmallett uint64_t reserved_19_63 : 45; 2966215976Sjmallett#endif 2967215976Sjmallett } s; 2968215976Sjmallett struct cvmx_dfa_eclkcfg_s cn31xx; 2969215976Sjmallett}; 2970215976Sjmalletttypedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t; 2971215976Sjmallett 2972215976Sjmallett/** 2973215976Sjmallett * cvmx_dfa_err 2974215976Sjmallett * 2975215976Sjmallett * DFA_ERR = DFA ERROR Register 2976215976Sjmallett * 2977215976Sjmallett * Description: 2978215976Sjmallett */ 2979232812Sjmallettunion cvmx_dfa_err { 2980215976Sjmallett uint64_t u64; 2981232812Sjmallett struct cvmx_dfa_err_s { 2982232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2983215976Sjmallett uint64_t reserved_33_63 : 31; 2984215976Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 2985215976Sjmallett When set, doorbell overflow conditions are reported. */ 2986215976Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 2987215976Sjmallett When set, the 20b accumulated doorbell register 2988215976Sjmallett had overflowed (SW wrote too many doorbell requests). 2989215976Sjmallett If the DBLINA had previously been enabled(set), 2990215976Sjmallett an interrupt will be posted. Software can clear 2991215976Sjmallett the interrupt by writing a 1 to this register bit. 2992215976Sjmallett NOTE: Detection of a Doorbell Register overflow 2993215976Sjmallett is a catastrophic error which may leave the DFA 2994215976Sjmallett HW in an unrecoverable state. */ 2995215976Sjmallett uint64_t cp2pina : 1; /**< CP2 LW Mode Parity Error Interrupt Enable bit. 2996215976Sjmallett When set, all PP-generated LW Mode read 2997215976Sjmallett transactions which encounter a parity error (across 2998215976Sjmallett the 36b of data) are reported. */ 2999215976Sjmallett uint64_t cp2perr : 1; /**< PP-CP2 Parity Error Detected - Status bit 3000215976Sjmallett When set, a parity error had been detected for a 3001215976Sjmallett PP-generated LW Mode read transaction. 3002215976Sjmallett If the CP2PINA had previously been enabled(set), 3003215976Sjmallett an interrupt will be posted. Software can clear 3004215976Sjmallett the interrupt by writing a 1 to this register bit. 3005215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 3006215976Sjmallett about the memory address/control to help isolate 3007215976Sjmallett the failure. */ 3008215976Sjmallett uint64_t cp2parena : 1; /**< CP2 LW Mode Parity Error Enable 3009215976Sjmallett When set, all PP-generated LW Mode read 3010215976Sjmallett transactions which encounter a parity error (across 3011215976Sjmallett the 36b of data) are reported. 3012215976Sjmallett NOTE: This signal must only be written to a different 3013215976Sjmallett value when there are no PP-CP2 transactions 3014215976Sjmallett (preferrably during power-on software initialization). */ 3015215976Sjmallett uint64_t dtepina : 1; /**< DTE Parity Error Interrupt Enable bit 3016215976Sjmallett (for 18b SIMPLE mode ONLY). 3017215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 3018215976Sjmallett transactions which encounter a parity error (across 3019215976Sjmallett the 17b of data) are reported. */ 3020215976Sjmallett uint64_t dteperr : 1; /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY) 3021215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 3022215976Sjmallett transactions which encounter a parity error (across 3023215976Sjmallett the 17b of data) are reported. */ 3024215976Sjmallett uint64_t dteparena : 1; /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY) 3025215976Sjmallett When set, all DTE-generated 18b SIMPLE Mode read 3026215976Sjmallett transactions which encounter a parity error (across 3027215976Sjmallett the 17b of data) are reported. 3028215976Sjmallett NOTE: This signal must only be written to a different 3029215976Sjmallett value when there are no DFA thread engines active 3030215976Sjmallett (preferrably during power-on). */ 3031215976Sjmallett uint64_t dtesyn : 7; /**< DTE 29b ECC Failing 6bit Syndrome 3032215976Sjmallett When DTESBE or DTEDBE are set, this field contains 3033215976Sjmallett the failing 7b ECC syndrome. */ 3034215976Sjmallett uint64_t dtedbina : 1; /**< DTE 29b Double Bit Error Interrupt Enable bit 3035215976Sjmallett When set, an interrupt is posted for any DTE-generated 3036215976Sjmallett 36b SIMPLE Mode read which encounters a double bit 3037215976Sjmallett error. */ 3038215976Sjmallett uint64_t dtesbina : 1; /**< DTE 29b Single Bit Error Interrupt Enable bit 3039215976Sjmallett When set, an interrupt is posted for any DTE-generated 3040215976Sjmallett 36b SIMPLE Mode read which encounters a single bit 3041215976Sjmallett error (which is also corrected). */ 3042215976Sjmallett uint64_t dtedbe : 1; /**< DTE 29b Double Bit Error Detected - Status bit 3043215976Sjmallett When set, a double bit error had been detected 3044215976Sjmallett for a DTE-generated 36b SIMPLE Mode read transaction. 3045215976Sjmallett The DTESYN contains the failing syndrome. 3046215976Sjmallett If the DTEDBINA had previously been enabled(set), 3047215976Sjmallett an interrupt will be posted. Software can clear 3048215976Sjmallett the interrupt by writing a 1 to this register bit. 3049215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 3050215976Sjmallett about the memory address/control to help isolate 3051215976Sjmallett the failure. 3052215976Sjmallett NOTE: DTE-generated 18b SIMPLE Mode Read transactions 3053215976Sjmallett do not participate in ECC check/correct). */ 3054215976Sjmallett uint64_t dtesbe : 1; /**< DTE 29b Single Bit Error Corrected - Status bit 3055215976Sjmallett When set, a single bit error had been detected and 3056215976Sjmallett corrected for a DTE-generated 36b SIMPLE Mode read 3057215976Sjmallett transaction. 3058215976Sjmallett If the DTEDBE=0, then the DTESYN contains the 3059215976Sjmallett failing syndrome (used during correction). 3060215976Sjmallett NOTE: DTE-generated 18b SIMPLE Mode Read 3061215976Sjmallett transactions do not participate in ECC check/correct). 3062215976Sjmallett If the DTESBINA had previously been enabled(set), 3063215976Sjmallett an interrupt will be posted. Software can clear 3064215976Sjmallett the interrupt by writing a 1 to this register bit. 3065215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 3066215976Sjmallett about the memory address/control to help isolate 3067215976Sjmallett the failure. */ 3068215976Sjmallett uint64_t dteeccena : 1; /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY) 3069215976Sjmallett When set, 29b ECC is enabled on all DTE-generated 3070215976Sjmallett 36b SIMPLE Mode read transactions. 3071215976Sjmallett NOTE: This signal must only be written to a different 3072215976Sjmallett value when there are no DFA thread engines active 3073215976Sjmallett (preferrably during power-on software initialization). */ 3074215976Sjmallett uint64_t cp2syn : 8; /**< PP-CP2 QW ECC Failing 8bit Syndrome 3075215976Sjmallett When CP2SBE or CP2DBE are set, this field contains 3076215976Sjmallett the failing ECC 8b syndrome. 3077215976Sjmallett Refer to CP2ECCENA. */ 3078215976Sjmallett uint64_t cp2dbina : 1; /**< PP-CP2 Double Bit Error Interrupt Enable bit 3079215976Sjmallett When set, an interrupt is posted for any PP-generated 3080215976Sjmallett QW Mode read which encounters a double bit error. 3081215976Sjmallett Refer to CP2DBE. */ 3082215976Sjmallett uint64_t cp2sbina : 1; /**< PP-CP2 Single Bit Error Interrupt Enable bit 3083215976Sjmallett When set, an interrupt is posted for any PP-generated 3084215976Sjmallett QW Mode read which encounters a single bit error 3085215976Sjmallett (which is also corrected). 3086215976Sjmallett Refer to CP2SBE. */ 3087215976Sjmallett uint64_t cp2dbe : 1; /**< PP-CP2 Double Bit Error Detected - Status bit 3088215976Sjmallett When set, a double bit error had been detected 3089215976Sjmallett for a PP-generated QW Mode read transaction. 3090215976Sjmallett The CP2SYN contains the failing syndrome. 3091215976Sjmallett NOTE: PP-generated LW Mode Read transactions 3092215976Sjmallett do not participate in ECC check/correct). 3093215976Sjmallett Refer to CP2ECCENA. 3094215976Sjmallett If the CP2DBINA had previously been enabled(set), 3095215976Sjmallett an interrupt will be posted. Software can clear 3096215976Sjmallett the interrupt by writing a 1 to this register bit. 3097215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 3098215976Sjmallett about the memory address/control to help isolate 3099215976Sjmallett the failure. */ 3100215976Sjmallett uint64_t cp2sbe : 1; /**< PP-CP2 Single Bit Error Corrected - Status bit 3101215976Sjmallett When set, a single bit error had been detected and 3102215976Sjmallett corrected for a PP-generated QW Mode read 3103215976Sjmallett transaction. 3104215976Sjmallett If the CP2DBE=0, then the CP2SYN contains the 3105215976Sjmallett failing syndrome (used during correction). 3106215976Sjmallett Refer to CP2ECCENA. 3107215976Sjmallett If the CP2SBINA had previously been enabled(set), 3108215976Sjmallett an interrupt will be posted. Software can clear 3109215976Sjmallett the interrupt by writing a 1 to this register bit. 3110215976Sjmallett See also: DFA_MEMFADR CSR which contains more data 3111215976Sjmallett about the memory address/control to help isolate 3112215976Sjmallett the failure. 3113215976Sjmallett NOTE: PP-generated LW Mode Read transactions 3114215976Sjmallett do not participate in ECC check/correct). */ 3115215976Sjmallett uint64_t cp2eccena : 1; /**< PP-CP2 QW ECC Enable (for QW Mode transactions) 3116215976Sjmallett When set, 8bit QW ECC is enabled on all PP-generated 3117215976Sjmallett QW Mode read transactions, CP2SBE and 3118215976Sjmallett CP2DBE may be set, and CP2SYN may be filled. 3119215976Sjmallett NOTE: This signal must only be written to a different 3120215976Sjmallett value when there are no PP-CP2 transactions 3121215976Sjmallett (preferrably during power-on software initialization). 3122215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3123215976Sjmallett by a processor core). LW refers to a 36-bit load/store. */ 3124215976Sjmallett#else 3125215976Sjmallett uint64_t cp2eccena : 1; 3126215976Sjmallett uint64_t cp2sbe : 1; 3127215976Sjmallett uint64_t cp2dbe : 1; 3128215976Sjmallett uint64_t cp2sbina : 1; 3129215976Sjmallett uint64_t cp2dbina : 1; 3130215976Sjmallett uint64_t cp2syn : 8; 3131215976Sjmallett uint64_t dteeccena : 1; 3132215976Sjmallett uint64_t dtesbe : 1; 3133215976Sjmallett uint64_t dtedbe : 1; 3134215976Sjmallett uint64_t dtesbina : 1; 3135215976Sjmallett uint64_t dtedbina : 1; 3136215976Sjmallett uint64_t dtesyn : 7; 3137215976Sjmallett uint64_t dteparena : 1; 3138215976Sjmallett uint64_t dteperr : 1; 3139215976Sjmallett uint64_t dtepina : 1; 3140215976Sjmallett uint64_t cp2parena : 1; 3141215976Sjmallett uint64_t cp2perr : 1; 3142215976Sjmallett uint64_t cp2pina : 1; 3143215976Sjmallett uint64_t dblovf : 1; 3144215976Sjmallett uint64_t dblina : 1; 3145215976Sjmallett uint64_t reserved_33_63 : 31; 3146215976Sjmallett#endif 3147215976Sjmallett } s; 3148215976Sjmallett struct cvmx_dfa_err_s cn31xx; 3149215976Sjmallett struct cvmx_dfa_err_s cn38xx; 3150215976Sjmallett struct cvmx_dfa_err_s cn38xxp2; 3151215976Sjmallett struct cvmx_dfa_err_s cn58xx; 3152215976Sjmallett struct cvmx_dfa_err_s cn58xxp1; 3153215976Sjmallett}; 3154215976Sjmalletttypedef union cvmx_dfa_err cvmx_dfa_err_t; 3155215976Sjmallett 3156215976Sjmallett/** 3157215976Sjmallett * cvmx_dfa_error 3158215976Sjmallett * 3159215976Sjmallett * DFA_ERROR = DFA ERROR Register 3160215976Sjmallett * 3161215976Sjmallett * Description: 3162215976Sjmallett */ 3163232812Sjmallettunion cvmx_dfa_error { 3164215976Sjmallett uint64_t u64; 3165232812Sjmallett struct cvmx_dfa_error_s { 3166232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3167232812Sjmallett uint64_t reserved_19_63 : 45; 3168232812Sjmallett uint64_t replerr : 1; /**< DFA Illegal Replication Factor Error 3169232812Sjmallett For o68: DFA only supports 1x, 2x, and 4x port replication. 3170232812Sjmallett Legal configurations for memory are to support 2 port or 3171232812Sjmallett 4 port configurations. 3172232812Sjmallett The REPLERR interrupt will be set in the following illegal 3173232812Sjmallett configuration cases: 3174232812Sjmallett 1) An 8x replication factor is detected for any memory reference. 3175232812Sjmallett 2) A 4x replication factor is detected for any memory reference 3176232812Sjmallett when only 2 memory ports are enabled. 3177232812Sjmallett NOTE: If REPLERR is set during a DFA Graph Walk operation, 3178232812Sjmallett then the walk will prematurely terminate with RWORD0[REA]=ERR. 3179232812Sjmallett If REPLERR is set during a NCB-Direct CSR read access to DFA 3180232812Sjmallett Memory REGION, then the CSR read response data is UNPREDICTABLE. */ 3181232812Sjmallett uint64_t dfanxm : 1; /**< DFA Non-existent Memory Access 3182232812Sjmallett For o68: DTEs (and backdoor CSR DFA Memory REGION reads) 3183232812Sjmallett have access to the following 38bit L2/DRAM address space 3184232812Sjmallett which maps to a 37bit physical DDR3 SDRAM address space. 3185232812Sjmallett see: 3186232812Sjmallett DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF 3187232812Sjmallett maps to lower 256MB of physical DDR3 SDRAM 3188232812Sjmallett DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF 3189232812Sjmallett maps to upper 127.75GB of DDR3 SDRAM 3190232812Sjmallett L2/DRAM address space Physical DDR3 SDRAM Address space 3191232812Sjmallett (38bit address) (37bit address) 3192232812Sjmallett +-----------+ 0x0020.0FFF.FFFF 3193232812Sjmallett 3194232812Sjmallett === DR1 === +-----------+ 0x001F.FFFF.FFFF 3195232812Sjmallett (128GB-256MB)| | 3196232812Sjmallett | | => | | (128GB-256MB) 3197232812Sjmallett +-----------+ 0x0000.1FFF.FFFF | DR1 3198232812Sjmallett 256MB | HOLE | (DO NOT USE) 3199232812Sjmallett +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF 3200232812Sjmallett 256MB | DR0 | | DR0 | (256MB) 3201232812Sjmallett +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000 3202232812Sjmallett In the event the DFA generates a reference to the L2/DRAM 3203232812Sjmallett address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to 3204232812Sjmallett an address above 0x0020.0FFF.FFFF, the DFANXM programmable 3205232812Sjmallett interrupt bit will be set. 3206232812Sjmallett SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR 3207232812Sjmallett accesses to DFA Memory REGION MUST avoid making references 3208232812Sjmallett to these non-existent memory regions. 3209232812Sjmallett NOTE: If DFANXM is set during a DFA Graph Walk operation, 3210232812Sjmallett then the walk will prematurely terminate with RWORD0[REA]=ERR. 3211232812Sjmallett If DFANXM is set during a NCB-Direct CSR read access to DFA 3212232812Sjmallett Memory REGION, then the CSR read response data is forced to 3213232812Sjmallett 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW 3214232812Sjmallett being accessed, either the upper or lower QW will be returned). */ 3215232812Sjmallett uint64_t cndrd : 1; /**< If Any of the cluster's detected a Parity error on RAM1 3216232812Sjmallett this additional bit further specifies that the 3217232812Sjmallett RAM1 parity error was detected during a CND-RD 3218232812Sjmallett (Cache Node Metadata Read). 3219232812Sjmallett 3220232812Sjmallett For CNDRD Parity Error, the previous CNA arc fetch 3221232812Sjmallett information is written to RWORD1+ as follows: 3222232812Sjmallett RWORD1+[NTYPE]=MNODE 3223232812Sjmallett RWORD1+[NDNID]=cna.ndnid 3224232812Sjmallett RWORD1+[NHMSK]=cna.hmsk 3225232812Sjmallett RWORD1+[NNPTR]=cna.nnptr[13:0] 3226232812Sjmallett NOTE: This bit is set if ANY node cluster's RAM1 accesses 3227232812Sjmallett detect a CNDRD error. */ 3228232812Sjmallett uint64_t reserved_15_15 : 1; 3229232812Sjmallett uint64_t dlc1_ovferr : 1; /**< DLC1 Fifo Overflow Error Detected 3230232812Sjmallett This condition should NEVER architecturally occur, and 3231232812Sjmallett is here in case HW credit/debit scheme is not working. */ 3232232812Sjmallett uint64_t dlc0_ovferr : 1; /**< DLC0 Fifo Overflow Error Detected 3233232812Sjmallett This condition should NEVER architecturally occur, and 3234232812Sjmallett is here in case HW credit/debit scheme is not working. */ 3235232812Sjmallett uint64_t reserved_10_12 : 3; 3236232812Sjmallett uint64_t dc2perr : 3; /**< Cluster#2 RAM[3:1] Parity Error Detected 3237232812Sjmallett See also DFA_DTCFADR register which contains the 3238232812Sjmallett failing addresses for the internal node cache RAMs. */ 3239232812Sjmallett uint64_t dc1perr : 3; /**< Cluster#1 RAM[3:1] Parity Error Detected 3240232812Sjmallett See also DFA_DTCFADR register which contains the 3241232812Sjmallett failing addresses for the internal node cache RAMs. */ 3242232812Sjmallett uint64_t dc0perr : 3; /**< Cluster#0 RAM[3:1] Parity Error Detected 3243232812Sjmallett See also DFA_DTCFADR register which contains the 3244232812Sjmallett failing addresses for the internal node cache RAMs. */ 3245232812Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3246232812Sjmallett When set, the 20b accumulated doorbell register 3247232812Sjmallett had overflowed (SW wrote too many doorbell requests). 3248232812Sjmallett If the DBLINA had previously been enabled(set), 3249232812Sjmallett an interrupt will be posted. Software can clear 3250232812Sjmallett the interrupt by writing a 1 to this register bit. 3251232812Sjmallett NOTE: Detection of a Doorbell Register overflow 3252232812Sjmallett is a catastrophic error which may leave the DFA 3253232812Sjmallett HW in an unrecoverable state. */ 3254232812Sjmallett#else 3255232812Sjmallett uint64_t dblovf : 1; 3256232812Sjmallett uint64_t dc0perr : 3; 3257232812Sjmallett uint64_t dc1perr : 3; 3258232812Sjmallett uint64_t dc2perr : 3; 3259232812Sjmallett uint64_t reserved_10_12 : 3; 3260232812Sjmallett uint64_t dlc0_ovferr : 1; 3261232812Sjmallett uint64_t dlc1_ovferr : 1; 3262232812Sjmallett uint64_t reserved_15_15 : 1; 3263232812Sjmallett uint64_t cndrd : 1; 3264232812Sjmallett uint64_t dfanxm : 1; 3265232812Sjmallett uint64_t replerr : 1; 3266232812Sjmallett uint64_t reserved_19_63 : 45; 3267232812Sjmallett#endif 3268232812Sjmallett } s; 3269232812Sjmallett struct cvmx_dfa_error_cn61xx { 3270232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3271232812Sjmallett uint64_t reserved_19_63 : 45; 3272232812Sjmallett uint64_t replerr : 1; /**< DFA Illegal Replication Factor Error 3273232812Sjmallett For o68: DFA only supports 1x, 2x, and 4x port replication. 3274232812Sjmallett Legal configurations for memory are to support 2 port or 3275232812Sjmallett 4 port configurations. 3276232812Sjmallett The REPLERR interrupt will be set in the following illegal 3277232812Sjmallett configuration cases: 3278232812Sjmallett 1) An 8x replication factor is detected for any memory reference. 3279232812Sjmallett 2) A 4x replication factor is detected for any memory reference 3280232812Sjmallett when only 2 memory ports are enabled. 3281232812Sjmallett NOTE: If REPLERR is set during a DFA Graph Walk operation, 3282232812Sjmallett then the walk will prematurely terminate with RWORD0[REA]=ERR. 3283232812Sjmallett If REPLERR is set during a NCB-Direct CSR read access to DFA 3284232812Sjmallett Memory REGION, then the CSR read response data is UNPREDICTABLE. */ 3285232812Sjmallett uint64_t dfanxm : 1; /**< DFA Non-existent Memory Access 3286232812Sjmallett For o68/o61: DTEs (and backdoor CSR DFA Memory REGION reads) 3287232812Sjmallett have access to the following 38bit L2/DRAM address space 3288232812Sjmallett which maps to a 37bit physical DDR3 SDRAM address space. 3289232812Sjmallett see: 3290232812Sjmallett DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF 3291232812Sjmallett maps to lower 256MB of physical DDR3 SDRAM 3292232812Sjmallett DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF 3293232812Sjmallett maps to upper 127.75GB of DDR3 SDRAM 3294232812Sjmallett L2/DRAM address space Physical DDR3 SDRAM Address space 3295232812Sjmallett (38bit address) (37bit address) 3296232812Sjmallett +-----------+ 0x0020.0FFF.FFFF 3297232812Sjmallett | 3298232812Sjmallett === DR1 === +-----------+ 0x001F.FFFF.FFFF 3299232812Sjmallett (128GB-256MB)| | | 3300232812Sjmallett | | => | | (128GB-256MB) 3301232812Sjmallett +-----------+ 0x0000.1FFF.FFFF | DR1 3302232812Sjmallett 256MB | HOLE | (DO NOT USE) | 3303232812Sjmallett +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF 3304232812Sjmallett 256MB | DR0 | | DR0 | (256MB) 3305232812Sjmallett +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000 3306232812Sjmallett In the event the DFA generates a reference to the L2/DRAM 3307232812Sjmallett address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to 3308232812Sjmallett an address above 0x0020.0FFF.FFFF, the DFANXM programmable 3309232812Sjmallett interrupt bit will be set. 3310232812Sjmallett SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR 3311232812Sjmallett accesses to DFA Memory REGION MUST avoid making references 3312232812Sjmallett to these non-existent memory regions. 3313232812Sjmallett NOTE: If DFANXM is set during a DFA Graph Walk operation, 3314232812Sjmallett then the walk will prematurely terminate with RWORD0[REA]=ERR. 3315232812Sjmallett If DFANXM is set during a NCB-Direct CSR read access to DFA 3316232812Sjmallett Memory REGION, then the CSR read response data is forced to 3317232812Sjmallett 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW 3318232812Sjmallett being accessed, either the upper or lower QW will be returned). */ 3319232812Sjmallett uint64_t cndrd : 1; /**< If any of the cluster's detected a Parity error on RAM1 3320232812Sjmallett this additional bit further specifies that the 3321232812Sjmallett RAM1 parity error was detected during a CND-RD 3322232812Sjmallett (Cache Node Metadata Read). 3323232812Sjmallett 3324232812Sjmallett For CNDRD Parity Error, the previous CNA arc fetch 3325232812Sjmallett information is written to RWORD1+ as follows: 3326232812Sjmallett RWORD1+[NTYPE]=MNODE 3327232812Sjmallett RWORD1+[NDNID]=cna.ndnid 3328232812Sjmallett RWORD1+[NHMSK]=cna.hmsk 3329232812Sjmallett RWORD1+[NNPTR]=cna.nnptr[13:0] 3330232812Sjmallett NOTE: This bit is set if ANY node cluster's RAM1 accesses 3331232812Sjmallett detect a CNDRD error. */ 3332232812Sjmallett uint64_t reserved_14_15 : 2; 3333232812Sjmallett uint64_t dlc0_ovferr : 1; /**< DLC0 Fifo Overflow Error Detected 3334232812Sjmallett This condition should NEVER architecturally occur, and 3335232812Sjmallett is here in case HW credit/debit scheme is not working. */ 3336232812Sjmallett uint64_t reserved_4_12 : 9; 3337232812Sjmallett uint64_t dc0perr : 3; /**< Cluster#0 RAM[3:1] Parity Error Detected 3338232812Sjmallett See also DFA_DTCFADR register which contains the 3339232812Sjmallett failing addresses for the internal node cache RAMs. */ 3340232812Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3341232812Sjmallett When set, the 20b accumulated doorbell register 3342232812Sjmallett had overflowed (SW wrote too many doorbell requests). 3343232812Sjmallett If the DBLINA had previously been enabled(set), 3344232812Sjmallett an interrupt will be posted. Software can clear 3345232812Sjmallett the interrupt by writing a 1 to this register bit. 3346232812Sjmallett NOTE: Detection of a Doorbell Register overflow 3347232812Sjmallett is a catastrophic error which may leave the DFA 3348232812Sjmallett HW in an unrecoverable state. */ 3349232812Sjmallett#else 3350232812Sjmallett uint64_t dblovf : 1; 3351232812Sjmallett uint64_t dc0perr : 3; 3352232812Sjmallett uint64_t reserved_4_12 : 9; 3353232812Sjmallett uint64_t dlc0_ovferr : 1; 3354232812Sjmallett uint64_t reserved_14_15 : 2; 3355232812Sjmallett uint64_t cndrd : 1; 3356232812Sjmallett uint64_t dfanxm : 1; 3357232812Sjmallett uint64_t replerr : 1; 3358232812Sjmallett uint64_t reserved_19_63 : 45; 3359232812Sjmallett#endif 3360232812Sjmallett } cn61xx; 3361232812Sjmallett struct cvmx_dfa_error_cn63xx { 3362232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3363215976Sjmallett uint64_t reserved_17_63 : 47; 3364215976Sjmallett uint64_t cndrd : 1; /**< If DC0PERR[0]=1 indicating a RAM1 Parity error, 3365215976Sjmallett this additional bit further specifies that the 3366215976Sjmallett RAM1 parity error was detected during a CND-RD 3367215976Sjmallett (Cache Node Metadata Read). 3368215976Sjmallett 3369215976Sjmallett For CNDRD Parity Error, the previous CNA arc fetch 3370215976Sjmallett information is written to RWORD1+ as follows: 3371215976Sjmallett RWORD1+[NTYPE]=MNODE 3372215976Sjmallett RWORD1+[NDNID]=cna.ndnid 3373215976Sjmallett RWORD1+[NHMSK]=cna.hmsk 3374215976Sjmallett RWORD1+[NNPTR]=cna.nnptr[13:0] */ 3375215976Sjmallett uint64_t reserved_4_15 : 12; 3376215976Sjmallett uint64_t dc0perr : 3; /**< RAM[3:1] Parity Error Detected from Node Cluster \#0 3377215976Sjmallett See also DFA_DTCFADR register which contains the 3378215976Sjmallett failing addresses for the internal node cache RAMs. */ 3379215976Sjmallett uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3380215976Sjmallett When set, the 20b accumulated doorbell register 3381215976Sjmallett had overflowed (SW wrote too many doorbell requests). 3382215976Sjmallett If the DBLINA had previously been enabled(set), 3383215976Sjmallett an interrupt will be posted. Software can clear 3384215976Sjmallett the interrupt by writing a 1 to this register bit. 3385215976Sjmallett NOTE: Detection of a Doorbell Register overflow 3386215976Sjmallett is a catastrophic error which may leave the DFA 3387215976Sjmallett HW in an unrecoverable state. */ 3388215976Sjmallett#else 3389215976Sjmallett uint64_t dblovf : 1; 3390215976Sjmallett uint64_t dc0perr : 3; 3391215976Sjmallett uint64_t reserved_4_15 : 12; 3392215976Sjmallett uint64_t cndrd : 1; 3393215976Sjmallett uint64_t reserved_17_63 : 47; 3394215976Sjmallett#endif 3395232812Sjmallett } cn63xx; 3396232812Sjmallett struct cvmx_dfa_error_cn63xx cn63xxp1; 3397232812Sjmallett struct cvmx_dfa_error_cn63xx cn66xx; 3398232812Sjmallett struct cvmx_dfa_error_s cn68xx; 3399232812Sjmallett struct cvmx_dfa_error_s cn68xxp1; 3400215976Sjmallett}; 3401215976Sjmalletttypedef union cvmx_dfa_error cvmx_dfa_error_t; 3402215976Sjmallett 3403215976Sjmallett/** 3404215976Sjmallett * cvmx_dfa_intmsk 3405215976Sjmallett * 3406215976Sjmallett * DFA_INTMSK = DFA ERROR Interrupt Mask Register 3407215976Sjmallett * 3408215976Sjmallett * Description: 3409215976Sjmallett */ 3410232812Sjmallettunion cvmx_dfa_intmsk { 3411215976Sjmallett uint64_t u64; 3412232812Sjmallett struct cvmx_dfa_intmsk_s { 3413232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3414232812Sjmallett uint64_t reserved_19_63 : 45; 3415232812Sjmallett uint64_t replerrena : 1; /**< DFA Illegal Replication Factor Interrupt Enable */ 3416232812Sjmallett uint64_t dfanxmena : 1; /**< DFA Non-existent Memory Access Interrupt Enable */ 3417232812Sjmallett uint64_t reserved_15_16 : 2; 3418232812Sjmallett uint64_t dlc1_ovfena : 1; /**< DLC1 Fifo Overflow Error Interrupt Enable */ 3419232812Sjmallett uint64_t dlc0_ovfena : 1; /**< DLC0 Fifo Overflow Error Interrupt Enable */ 3420232812Sjmallett uint64_t reserved_10_12 : 3; 3421232812Sjmallett uint64_t dc2pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#2 */ 3422232812Sjmallett uint64_t dc1pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#1 */ 3423232812Sjmallett uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3424232812Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3425232812Sjmallett When set, doorbell overflow conditions are reported. */ 3426232812Sjmallett#else 3427232812Sjmallett uint64_t dblina : 1; 3428232812Sjmallett uint64_t dc0pena : 3; 3429232812Sjmallett uint64_t dc1pena : 3; 3430232812Sjmallett uint64_t dc2pena : 3; 3431232812Sjmallett uint64_t reserved_10_12 : 3; 3432232812Sjmallett uint64_t dlc0_ovfena : 1; 3433232812Sjmallett uint64_t dlc1_ovfena : 1; 3434232812Sjmallett uint64_t reserved_15_16 : 2; 3435232812Sjmallett uint64_t dfanxmena : 1; 3436232812Sjmallett uint64_t replerrena : 1; 3437232812Sjmallett uint64_t reserved_19_63 : 45; 3438232812Sjmallett#endif 3439232812Sjmallett } s; 3440232812Sjmallett struct cvmx_dfa_intmsk_cn61xx { 3441232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3442232812Sjmallett uint64_t reserved_19_63 : 45; 3443232812Sjmallett uint64_t replerrena : 1; /**< DFA Illegal Replication Factor Interrupt Enable */ 3444232812Sjmallett uint64_t dfanxmena : 1; /**< DFA Non-existent Memory Access Interrupt Enable */ 3445232812Sjmallett uint64_t reserved_14_16 : 3; 3446232812Sjmallett uint64_t dlc0_ovfena : 1; /**< DLC0 Fifo Overflow Error Interrupt Enable */ 3447232812Sjmallett uint64_t reserved_4_12 : 9; 3448232812Sjmallett uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3449232812Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3450232812Sjmallett When set, doorbell overflow conditions are reported. */ 3451232812Sjmallett#else 3452232812Sjmallett uint64_t dblina : 1; 3453232812Sjmallett uint64_t dc0pena : 3; 3454232812Sjmallett uint64_t reserved_4_12 : 9; 3455232812Sjmallett uint64_t dlc0_ovfena : 1; 3456232812Sjmallett uint64_t reserved_14_16 : 3; 3457232812Sjmallett uint64_t dfanxmena : 1; 3458232812Sjmallett uint64_t replerrena : 1; 3459232812Sjmallett uint64_t reserved_19_63 : 45; 3460232812Sjmallett#endif 3461232812Sjmallett } cn61xx; 3462232812Sjmallett struct cvmx_dfa_intmsk_cn63xx { 3463232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3464215976Sjmallett uint64_t reserved_4_63 : 60; 3465215976Sjmallett uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3466215976Sjmallett uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3467215976Sjmallett When set, doorbell overflow conditions are reported. */ 3468215976Sjmallett#else 3469215976Sjmallett uint64_t dblina : 1; 3470215976Sjmallett uint64_t dc0pena : 3; 3471215976Sjmallett uint64_t reserved_4_63 : 60; 3472215976Sjmallett#endif 3473232812Sjmallett } cn63xx; 3474232812Sjmallett struct cvmx_dfa_intmsk_cn63xx cn63xxp1; 3475232812Sjmallett struct cvmx_dfa_intmsk_cn63xx cn66xx; 3476232812Sjmallett struct cvmx_dfa_intmsk_s cn68xx; 3477232812Sjmallett struct cvmx_dfa_intmsk_s cn68xxp1; 3478215976Sjmallett}; 3479215976Sjmalletttypedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t; 3480215976Sjmallett 3481215976Sjmallett/** 3482215976Sjmallett * cvmx_dfa_memcfg0 3483215976Sjmallett * 3484215976Sjmallett * DFA_MEMCFG0 = DFA Memory Configuration 3485215976Sjmallett * 3486215976Sjmallett * Description: 3487215976Sjmallett */ 3488232812Sjmallettunion cvmx_dfa_memcfg0 { 3489215976Sjmallett uint64_t u64; 3490232812Sjmallett struct cvmx_dfa_memcfg0_s { 3491232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3492215976Sjmallett uint64_t reserved_32_63 : 32; 3493215976Sjmallett uint64_t rldqck90_rst : 1; /**< RLDCK90 and RLDQK90 DLL SW Reset 3494215976Sjmallett When written with a '1' the RLDCK90 and RLDQK90 DLL are 3495215976Sjmallett in soft-reset. */ 3496215976Sjmallett uint64_t rldck_rst : 1; /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset 3497215976Sjmallett When written with a '1' the RLDCK zero delay DLL is in 3498215976Sjmallett soft-reset. */ 3499215976Sjmallett uint64_t clkdiv : 2; /**< RLDCLK Divisor Select 3500215976Sjmallett - 0: RLDx_CK_H/L = Core Clock /2 3501215976Sjmallett - 1: RESERVED (must not be used) 3502215976Sjmallett - 2: RLDx_CK_H/L = Core Clock /3 3503215976Sjmallett - 3: RLDx_CK_H/L = Core Clock /4 3504215976Sjmallett The DFA LLM interface(s) are tied to the core clock 3505215976Sjmallett frequency through this programmable clock divisor. 3506215976Sjmallett Examples: 3507215976Sjmallett Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV 3508215976Sjmallett -----------------+--------------------+-------- 3509215976Sjmallett 800 | 400/(800-DDR) | /2 3510215976Sjmallett 1000 | 333/(666-DDR) | /3 3511215976Sjmallett 800 | 200/(400-DDR) | /4 3512215976Sjmallett NOTE: This value MUST BE programmed BEFORE doing a 3513215976Sjmallett Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits). */ 3514215976Sjmallett uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 3515215976Sjmallett When enabled, PP-core LLM accesses to the lower-512MB 3516215976Sjmallett LLM address space are sent to the single DFA port 3517215976Sjmallett which is enabled. NOTE: If LPP_ENA=1, only 3518215976Sjmallett one DFA RLDRAM port may be enabled for RLDRAM accesses 3519215976Sjmallett (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 3520215976Sjmallett PP-core LLM accesses to the upper-512MB LLM address 3521215976Sjmallett space are sent to the other 'disabled' DFA port. 3522215976Sjmallett SW RESTRICTION: If LPP_ENA=1, then only one DFA port 3523215976Sjmallett may be enabled for RLDRAM accesses (ie: ENA_P0 and 3524215976Sjmallett ENA_P1 CAN NEVER BOTH be set). 3525215976Sjmallett NOTE: This bit is used to allow PP-Core LLM accesses to a 3526215976Sjmallett disabled port, such that each port can be sequentially 3527215976Sjmallett addressed (ie: disable LW address interleaving). 3528215976Sjmallett Enabling this bit allows BOTH PORTs to be active and 3529215976Sjmallett sequentially addressable. The single port that is 3530215976Sjmallett enabled(ENA_Px) will respond to the low-512MB LLM address 3531215976Sjmallett space, and the other 'disabled' port will respond to the 3532215976Sjmallett high-512MB LLM address space. 3533215976Sjmallett Example usage: 3534215976Sjmallett - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 3535215976Sjmallett - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 3536215976Sjmallett USAGE NOTE: 3537215976Sjmallett If LPP_ENA=1 and SW DOES NOT initialize the disabled port 3538215976Sjmallett (ie: INIT_Px=0->1), then refreshes and the HW init 3539215976Sjmallett sequence WILL NOT occur for the disabled port. 3540215976Sjmallett If LPP_ENA=1 and SW does initialize the disabled port 3541215976Sjmallett (INIT_Px=0->1 with ENA_Px=0), then refreshes and 3542215976Sjmallett the HW init sequence WILL occur to the disabled port. */ 3543215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3544215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3545215976Sjmallett b) during a normal refresh sequence. If 3546215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3547215976Sjmallett NOTE: This is required for DRAM used in a 3548215976Sjmallett clamshell configuration, since the address lines 3549215976Sjmallett carry Mode Register write data that is unique 3550215976Sjmallett per bunk(or clam). In a clamshell configuration, 3551215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 3552215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 3553215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3554215976Sjmallett To support clamshell designs, SW must initiate 3555215976Sjmallett two separate HW init sequences for the two bunks 3556215976Sjmallett (or clams) . Before each HW init sequence is triggered, 3557215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 3558215976Sjmallett that will be driven onto the A[22:0] wires during 3559215976Sjmallett an MRS mode register write. 3560215976Sjmallett NOTE: After the final HW initialization sequence has 3561215976Sjmallett been triggered, SW must wait 64K eclks before writing 3562215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3563215976Sjmallett driven during refresh sequences in normal operation. 3564215976Sjmallett NOTE: This should only be written to a different value 3565215976Sjmallett during power-on SW initialization. */ 3566215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3567215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 3568215976Sjmallett initiated. 3569215976Sjmallett NOTE: To initialize memory, SW must: 3570215976Sjmallett 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 3571215976Sjmallett RLDRAM operation. 3572215976Sjmallett [legal values 0: DIV2 2: DIV3 3: DIV4] 3573215976Sjmallett 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 3574215976Sjmallett and DFA_MEM_CFG0[RLDQCK90_RST] field at 3575215976Sjmallett the SAME TIME. This step puts all three DLLs in 3576215976Sjmallett SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 3577215976Sjmallett 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 3578215976Sjmallett This step takes the RLDCK DLL out of soft-reset so 3579215976Sjmallett that the DLL can generate the RLDx_CK_H/L clock pins. 3580215976Sjmallett 4) Wait 1ms (for RLDCK DLL to achieve lock) 3581215976Sjmallett 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 3582215976Sjmallett This step takes the RLDCK90 DLL AND RLDQK90 DLL out 3583215976Sjmallett of soft-reset. 3584215976Sjmallett 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 3585215976Sjmallett 7) Enable memory port(s): ENA_P0=1/ENA_P1=1 3586215976Sjmallett 8) Wait 100us (to ensure a stable clock 3587215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3588215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 3589215976Sjmallett 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 3590215976Sjmallett intended to be initialized. 3591215976Sjmallett 10) Write a '1' to the corresponding INIT_Px which 3592215976Sjmallett will initiate a hardware initialization 3593215976Sjmallett sequence to that'specific' port. 3594215976Sjmallett 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 3595215976Sjmallett [to ensure the HW init sequence has completed 3596215976Sjmallett before writing to ANY of the DFA_MEM* registers] 3597215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 3598215976Sjmallett 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 3599215976Sjmallett refreshes to BOTH bunks. 3600215976Sjmallett NOTE: In some cases (where the address wires are routed 3601215976Sjmallett differently between the front and back 'bunks'), 3602215976Sjmallett SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 3603215976Sjmallett control the Hardware initialization sequence for a 3604215976Sjmallett 'specific bunk'. In these cases, SW would setup the 3605215976Sjmallett BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 3606215976Sjmallett NOTE: This should only be written to a different value 3607215976Sjmallett during power-on SW initialization. 3608215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3609215976Sjmallett RLD0_* pins. */ 3610215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3611215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 3612215976Sjmallett initiated. 3613215976Sjmallett NOTE: To initialize memory, SW must: 3614215976Sjmallett 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 3615215976Sjmallett RLDRAM operation. 3616215976Sjmallett [legal values 0: DIV2 2: DIV3 3: DIV4] 3617215976Sjmallett 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 3618215976Sjmallett and DFA_MEM_CFG0[RLDQCK90_RST] field at 3619215976Sjmallett the SAME TIME. This step puts all three DLLs in 3620215976Sjmallett SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 3621215976Sjmallett 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 3622215976Sjmallett This step takes the RLDCK DLL out of soft-reset so 3623215976Sjmallett that the DLL can generate the RLDx_CK_H/L clock pins. 3624215976Sjmallett 4) Wait 1ms (for RLDCK DLL to achieve lock) 3625215976Sjmallett 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 3626215976Sjmallett This step takes the RLDCK90 DLL AND RLDQK90 DLL out 3627215976Sjmallett of soft-reset. 3628215976Sjmallett 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 3629215976Sjmallett 7) Enable memory port(s) ENA_P0=1/ENA_P1=1 3630215976Sjmallett 8) Wait 100us (to ensure a stable clock 3631215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3632215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 3633215976Sjmallett 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 3634215976Sjmallett intended to be initialized. 3635215976Sjmallett 10) Write a '1' to the corresponding INIT_Px which 3636215976Sjmallett will initiate a hardware initialization 3637215976Sjmallett sequence to that'specific' port. 3638215976Sjmallett 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 3639215976Sjmallett [to ensure the HW init sequence has completed 3640215976Sjmallett before writing to ANY of the DFA_MEM* registers] 3641215976Sjmallett - - - - - Hardware Initialization Sequence - - - - - 3642215976Sjmallett 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 3643215976Sjmallett refreshes to BOTH bunks. 3644215976Sjmallett NOTE: In some cases (where the address wires are routed 3645215976Sjmallett differently between the front and back 'bunks'), 3646215976Sjmallett SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 3647215976Sjmallett control the Hardware initialization sequence for a 3648215976Sjmallett 'specific bunk'. In these cases, SW would setup the 3649215976Sjmallett BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 3650215976Sjmallett NOTE: This should only be written to a different value 3651215976Sjmallett during power-on SW initialization. 3652215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3653215976Sjmallett RLD1_* pins. */ 3654215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3655215976Sjmallett if back to back reads are issued to different physical 3656215976Sjmallett bunks. This is to avoid DQ data bus collisions when 3657215976Sjmallett references cross between physical bunks. 3658215976Sjmallett [NOTE: the physical bunk address boundary is determined 3659215976Sjmallett by the PBUNK bit]. 3660215976Sjmallett NOTE: This should only be written to a different value 3661215976Sjmallett during power-on SW initialization. */ 3662215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3663215976Sjmallett Specifies which address bit within the Longword 3664215976Sjmallett Memory address MA[23:0] is used to determine the 3665215976Sjmallett chip selects. 3666215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 3667215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 3668215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3669215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3670215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3671215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3672215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3673215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 3674215976Sjmallett Example(s): 3675215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 3676215976Sjmallett parts could be used to fill out TWO physical 3677215976Sjmallett bunks (clamshell configuration). Each (of the 3678215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 3679215976Sjmallett Each RLDRAM device also contains 8 internal banks, 3680215976Sjmallett therefore the memory Address is 16M/8banks = 2M 3681215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 3682215976Sjmallett select the physical bunk. 3683215976Sjmallett NOTE: This should only be written to a different value 3684215976Sjmallett during power-on SW initialization. 3685215976Sjmallett be used to determine the Chip Select(s). */ 3686215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3687215976Sjmallett NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */ 3688215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3689215976Sjmallett On reads, allows user to control the shape of the 3690215976Sjmallett tristate disable back porch for the DQ data bus. 3691215976Sjmallett This parameter is also very dependent on the 3692215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3693215976Sjmallett taken when programming these parameters to avoid 3694215976Sjmallett data bus contention. Valid range [0..2] 3695215976Sjmallett NOTE: This should only be written to a different value 3696215976Sjmallett during power-on SW initialization. */ 3697215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3698215976Sjmallett On reads, allows user to control the shape of the 3699215976Sjmallett tristate disable front porch for the DQ data bus. 3700215976Sjmallett This parameter is also very dependent on the 3701215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3702215976Sjmallett taken when programming these parameters to avoid 3703215976Sjmallett data bus contention. Valid range [0..2] 3704215976Sjmallett NOTE: This should only be written to a different value 3705215976Sjmallett during power-on SW initialization. */ 3706215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3707215976Sjmallett Determines \#mclk cycles to insert when controller 3708215976Sjmallett switches from write to read. This allows programmer 3709215976Sjmallett to control the data bus contention. 3710215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3711215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3712215976Sjmallett NOTE: This should only be written to a different value 3713215976Sjmallett during power-on SW initialization. 3714215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3715215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 3716215976Sjmallett on W->R transitions is not pronounced. */ 3717215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3718215976Sjmallett Determines \#mclk cycles to insert when controller 3719215976Sjmallett switches from read to write. This allows programmer 3720215976Sjmallett to control the data bus contention. 3721215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3722215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3723215976Sjmallett NOTE: This should only be written to a different value 3724215976Sjmallett during power-on SW initialization. 3725215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3726215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 3727215976Sjmallett on R->W transitions is not pronounced. */ 3728215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3729215976Sjmallett additional dclks to wait (on top of tRL+1) before 3730215976Sjmallett pulling data out of the padring silos used for time 3731215976Sjmallett domain boundary crossing. 3732215976Sjmallett NOTE: This should only be written to a different value 3733215976Sjmallett during power-on SW initialization. */ 3734215976Sjmallett uint64_t mtype : 1; /**< FCRAM-II Memory Type 3735215976Sjmallett *** CN58XX UNSUPPORTED *** */ 3736215976Sjmallett uint64_t reserved_2_2 : 1; 3737215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 3738215976Sjmallett When enabled, this bit lets N3K be the default 3739215976Sjmallett driver for memory port \#0. 3740215976Sjmallett NOTE: a customer is at 3741215976Sjmallett liberty to enable either Port#0 or Port#1 or both. 3742215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3743215976Sjmallett be re-enabled. [the only way to enable a port is 3744215976Sjmallett through a chip reset]. 3745215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3746215976Sjmallett RLD0_* pins. */ 3747215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 3748215976Sjmallett When enabled, this bit lets N3K be the default 3749215976Sjmallett driver for memory port \#1. 3750215976Sjmallett NOTE: a customer is at 3751215976Sjmallett liberty to enable either Port#0 or Port#1 or both. 3752215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 3753215976Sjmallett be re-enabled. [the only way to enable a port is 3754215976Sjmallett through a chip reset]. 3755215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3756215976Sjmallett RLD1_* pins. */ 3757215976Sjmallett#else 3758215976Sjmallett uint64_t ena_p1 : 1; 3759215976Sjmallett uint64_t ena_p0 : 1; 3760215976Sjmallett uint64_t reserved_2_2 : 1; 3761215976Sjmallett uint64_t mtype : 1; 3762215976Sjmallett uint64_t sil_lat : 2; 3763215976Sjmallett uint64_t rw_dly : 4; 3764215976Sjmallett uint64_t wr_dly : 4; 3765215976Sjmallett uint64_t fprch : 2; 3766215976Sjmallett uint64_t bprch : 2; 3767215976Sjmallett uint64_t blen : 1; 3768215976Sjmallett uint64_t pbunk : 3; 3769215976Sjmallett uint64_t r2r_pbunk : 1; 3770215976Sjmallett uint64_t init_p1 : 1; 3771215976Sjmallett uint64_t init_p0 : 1; 3772215976Sjmallett uint64_t bunk_init : 2; 3773215976Sjmallett uint64_t lpp_ena : 1; 3774215976Sjmallett uint64_t clkdiv : 2; 3775215976Sjmallett uint64_t rldck_rst : 1; 3776215976Sjmallett uint64_t rldqck90_rst : 1; 3777215976Sjmallett uint64_t reserved_32_63 : 32; 3778215976Sjmallett#endif 3779215976Sjmallett } s; 3780232812Sjmallett struct cvmx_dfa_memcfg0_cn38xx { 3781232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3782215976Sjmallett uint64_t reserved_28_63 : 36; 3783215976Sjmallett uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 3784215976Sjmallett When enabled, PP-core LLM accesses to the lower-512MB 3785215976Sjmallett LLM address space are sent to the single DFA port 3786215976Sjmallett which is enabled. NOTE: If LPP_ENA=1, only 3787215976Sjmallett one DFA RLDRAM port may be enabled for RLDRAM accesses 3788215976Sjmallett (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 3789215976Sjmallett PP-core LLM accesses to the upper-512MB LLM address 3790215976Sjmallett space are sent to the other 'disabled' DFA port. 3791215976Sjmallett SW RESTRICTION: If LPP_ENA=1, then only one DFA port 3792215976Sjmallett may be enabled for RLDRAM accesses (ie: ENA_P0 and 3793215976Sjmallett ENA_P1 CAN NEVER BOTH be set). 3794215976Sjmallett NOTE: This bit is used to allow PP-Core LLM accesses to a 3795215976Sjmallett disabled port, such that each port can be sequentially 3796215976Sjmallett addressed (ie: disable LW address interleaving). 3797215976Sjmallett Enabling this bit allows BOTH PORTs to be active and 3798215976Sjmallett sequentially addressable. The single port that is 3799215976Sjmallett enabled(ENA_Px) will respond to the low-512MB LLM address 3800215976Sjmallett space, and the other 'disabled' port will respond to the 3801215976Sjmallett high-512MB LLM address space. 3802215976Sjmallett Example usage: 3803215976Sjmallett - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 3804215976Sjmallett - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 3805215976Sjmallett USAGE NOTE: 3806215976Sjmallett If LPP_ENA=1 and SW DOES NOT initialize the disabled port 3807215976Sjmallett (ie: INIT_Px=0->1), then refreshes and the HW init 3808215976Sjmallett sequence WILL NOT occur for the disabled port. 3809215976Sjmallett If LPP_ENA=1 and SW does initialize the disabled port 3810215976Sjmallett (INIT_Px=0->1 with ENA_Px=0), then refreshes and 3811215976Sjmallett the HW init sequence WILL occur to the disabled port. */ 3812215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3813215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3814215976Sjmallett b) during a normal refresh sequence. If 3815215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3816215976Sjmallett NOTE: This is required for DRAM used in a 3817215976Sjmallett clamshell configuration, since the address lines 3818215976Sjmallett carry Mode Register write data that is unique 3819215976Sjmallett per bunk(or clam). In a clamshell configuration, 3820215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 3821215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 3822215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3823215976Sjmallett To support clamshell designs, SW must initiate 3824215976Sjmallett two separate HW init sequences for the two bunks 3825215976Sjmallett (or clams) . Before each HW init sequence is triggered, 3826215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 3827215976Sjmallett that will be driven onto the A[22:0] wires during 3828215976Sjmallett an MRS mode register write. 3829215976Sjmallett NOTE: After the final HW initialization sequence has 3830215976Sjmallett been triggered, SW must wait 64K eclks before writing 3831215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3832215976Sjmallett driven during refresh sequences in normal operation. 3833215976Sjmallett NOTE: This should only be written to a different value 3834215976Sjmallett during power-on SW initialization. 3835215976Sjmallett NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 3836215976Sjmallett initialized independently. In other words, a HW init 3837215976Sjmallett must be done for Bunk#0, and then another HW init 3838215976Sjmallett must be done for Bunk#1 at power-on. */ 3839215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3840215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 3841215976Sjmallett initiated. 3842215976Sjmallett NOTE: To initialize memory, SW must: 3843215976Sjmallett 1) Enable memory port(s): 3844215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3845215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3846215976Sjmallett 2) Wait 100us (to ensure a stable clock 3847215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3848215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3849215976Sjmallett will initiate a hardware initialization 3850215976Sjmallett sequence. 3851215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3852215976Sjmallett cycles to ensure the HW init sequence has completed 3853215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3854215976Sjmallett NOTE: This should only be written to a different value 3855215976Sjmallett during power-on SW initialization. 3856215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 3857215976Sjmallett RLD0_* pins. */ 3858215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3859215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 3860215976Sjmallett initiated. 3861215976Sjmallett NOTE: To initialize memory, SW must: 3862215976Sjmallett 1) Enable memory port(s): 3863215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 3864215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3865215976Sjmallett 2) Wait 100us (to ensure a stable clock 3866215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 3867215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 3868215976Sjmallett will initiate a hardware initialization 3869215976Sjmallett sequence. 3870215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 3871215976Sjmallett cycles to ensure the HW init sequence has completed 3872215976Sjmallett before writing to ANY of the DFA_MEM* registers. 3873215976Sjmallett NOTE: This should only be written to a different value 3874215976Sjmallett during power-on SW initialization. 3875215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 3876215976Sjmallett RLD1_* pins. */ 3877215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3878215976Sjmallett if back to back reads are issued to different physical 3879215976Sjmallett bunks. This is to avoid DQ data bus collisions when 3880215976Sjmallett references cross between physical bunks. 3881215976Sjmallett [NOTE: the physical bunk address boundary is determined 3882215976Sjmallett by the PBUNK bit]. 3883215976Sjmallett NOTE: This should only be written to a different value 3884215976Sjmallett during power-on SW initialization. 3885215976Sjmallett When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 3886215976Sjmallett ZERO(for optimal performance). However, if electrically, 3887215976Sjmallett DQ-sharing becomes a power/heat issue, then R2R_PBUNK 3888215976Sjmallett should be set (but at a cost to performance (1/2 BW). */ 3889215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3890215976Sjmallett Specifies which address bit within the Longword 3891215976Sjmallett Memory address MA[23:0] is used to determine the 3892215976Sjmallett chip selects. 3893215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 3894215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 3895215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3896215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3897215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3898215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3899215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3900215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 3901215976Sjmallett Example(s): 3902215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 3903215976Sjmallett parts could be used to fill out TWO physical 3904215976Sjmallett bunks (clamshell configuration). Each (of the 3905215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 3906215976Sjmallett Each RLDRAM device also contains 8 internal banks, 3907215976Sjmallett therefore the memory Address is 16M/8banks = 2M 3908215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 3909215976Sjmallett select the physical bunk. 3910215976Sjmallett NOTE: This should only be written to a different value 3911215976Sjmallett during power-on SW initialization. 3912215976Sjmallett be used to determine the Chip Select(s). 3913215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 3914215976Sjmallett "Redundant Bunk" scheme is employed to provide the 3915215976Sjmallett highest overall performance (1 Req/ MCLK cycle). 3916215976Sjmallett In this mode, it's imperative that SW set the PBUNK 3917215976Sjmallett field +1 'above' the highest address bit. (such that 3918215976Sjmallett the PBUNK extracted from the address will always be 3919215976Sjmallett zero). In this mode, the CS_N[1:0] pins are driven 3920215976Sjmallett to each redundant bunk based on a TDM scheme: 3921215976Sjmallett [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 3922215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3923215976Sjmallett When BLEN=0(BL2), all QW reads/writes from CP2 are 3924215976Sjmallett decomposed into 2 separate BL2(LW) requests to the 3925215976Sjmallett Low-Latency memory. 3926215976Sjmallett When BLEN=1(BL4), a LW request (from CP2 or NCB) is 3927215976Sjmallett treated as 1 BL4(QW) request to the low latency memory. 3928215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3929215976Sjmallett by a processor core). LW refers to a 36-bit load/store. 3930215976Sjmallett NOTE: This should only be written to a different value 3931215976Sjmallett during power-on SW initialization before the DFA LLM 3932215976Sjmallett (low latency memory) is used. 3933215976Sjmallett NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 3934215976Sjmallett NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 3935215976Sjmallett multi-bunk(clam) board design. 3936215976Sjmallett NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 3937215976Sjmallett SW SHOULD use CP2 QW read/write requests (for 3938215976Sjmallett optimal low-latency bus performance). 3939215976Sjmallett [LW length read/write requests(in BL4 mode) use 50% 3940215976Sjmallett of the available bus bandwidth] 3941215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 3942215976Sjmallett be used with FCRAM-II devices which support BL2 mode 3943215976Sjmallett (see: Toshiba FCRAM-II, where DQ tristate after 2 data 3944215976Sjmallett transfers). 3945215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 3946215976Sjmallett write requests (FCRAM-II+ device specification has removed 3947215976Sjmallett the variable write mask function from the devices). 3948215976Sjmallett As such, if this mode is used, SW must be careful to 3949215976Sjmallett issue only PP-CP2 QW write requests. */ 3950215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3951215976Sjmallett On reads, allows user to control the shape of the 3952215976Sjmallett tristate disable back porch for the DQ data bus. 3953215976Sjmallett This parameter is also very dependent on the 3954215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3955215976Sjmallett taken when programming these parameters to avoid 3956215976Sjmallett data bus contention. Valid range [0..2] 3957215976Sjmallett NOTE: This should only be written to a different value 3958215976Sjmallett during power-on SW initialization. */ 3959215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3960215976Sjmallett On reads, allows user to control the shape of the 3961215976Sjmallett tristate disable front porch for the DQ data bus. 3962215976Sjmallett This parameter is also very dependent on the 3963215976Sjmallett RW_DLY and WR_DLY parameters and care must be 3964215976Sjmallett taken when programming these parameters to avoid 3965215976Sjmallett data bus contention. Valid range [0..2] 3966215976Sjmallett NOTE: This should only be written to a different value 3967215976Sjmallett during power-on SW initialization. */ 3968215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3969215976Sjmallett Determines \#mclk cycles to insert when controller 3970215976Sjmallett switches from write to read. This allows programmer 3971215976Sjmallett to control the data bus contention. 3972215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 3973215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3974215976Sjmallett For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 3975215976Sjmallett For FCRAM-II (BL2 grepl>=2x): (TBL=3) 3976215976Sjmallett NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 3977215976Sjmallett grepl>=2x, writes require redundant bunk writes 3978215976Sjmallett which require an additional 2 cycles before slotting 3979215976Sjmallett the next read. 3980215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3981215976Sjmallett NOTE: This should only be written to a different value 3982215976Sjmallett during power-on SW initialization. 3983215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3984215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 3985215976Sjmallett on W->R transitions is not pronounced. */ 3986215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3987215976Sjmallett Determines \#mclk cycles to insert when controller 3988215976Sjmallett switches from read to write. This allows programmer 3989215976Sjmallett to control the data bus contention. 3990215976Sjmallett For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 3991215976Sjmallett For FCRAM-II (BL4): (TBL=2) 3992215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3993215976Sjmallett NOTE: This should only be written to a different value 3994215976Sjmallett during power-on SW initialization. 3995215976Sjmallett NOTE: For aggressive(performance optimal) designs, 3996215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 3997215976Sjmallett on R->W transitions is not pronounced. */ 3998215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3999215976Sjmallett additional dclks to wait (on top of tRL+1) before 4000215976Sjmallett pulling data out of the padring silos used for time 4001215976Sjmallett domain boundary crossing. 4002215976Sjmallett NOTE: This should only be written to a different value 4003215976Sjmallett during power-on SW initialization. */ 4004215976Sjmallett uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 4005215976Sjmallett NOTE: N3K-P1 only supports RLDRAM-II 4006215976Sjmallett NOTE: This should only be written to a different value 4007215976Sjmallett during power-on SW initialization. 4008215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 4009215976Sjmallett "unidirectional DS/QS" mode is supported. (see FCRAM 4010215976Sjmallett data sheet EMRS[A6:A5]=SS(Strobe Select) register 4011215976Sjmallett definition. [in FCRAM 2-burst mode, we use FCRAM 4012215976Sjmallett in a clamshell configuration such that clam0 is 4013215976Sjmallett addressed independently of clam1, and DQ is shared 4014215976Sjmallett for optimal performance. As such it's imperative that 4015215976Sjmallett the QS are conditionally received (and are NOT 4016215976Sjmallett free-running), as the N3K receive data capture silos 4017215976Sjmallett OR the clam0/1 QS strobes. 4018215976Sjmallett NOTE: If this bit is SET, the ASX0/1 4019215976Sjmallett ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 4020215976Sjmallett in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 4021215976Sjmallett uint64_t reserved_2_2 : 1; 4022215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 4023215976Sjmallett When enabled, this bit lets N3K be the default 4024215976Sjmallett driver for memory port \#0. 4025215976Sjmallett NOTE: For N3K-P1, to enable Port#0(2nd port), 4026215976Sjmallett Port#1 MUST ALSO be enabled. 4027215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 4028215976Sjmallett liberty to enable either Port#0 or Port#1. 4029215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 4030215976Sjmallett be re-enabled. [the only way to enable a port is 4031215976Sjmallett through a chip reset]. 4032215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 4033215976Sjmallett RLD0_* pins. */ 4034215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 4035215976Sjmallett When enabled, this bit lets N3K be the default 4036215976Sjmallett driver for memory port \#1. 4037215976Sjmallett NOTE: For N3K-P1, If the customer wishes to use a 4038215976Sjmallett single port, s/he must enable Port#1 (and not Port#0). 4039215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 4040215976Sjmallett liberty to enable either Port#0 or Port#1. 4041215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 4042215976Sjmallett be re-enabled. [the only way to enable a port is 4043215976Sjmallett through a chip reset]. 4044215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 4045215976Sjmallett RLD1_* pins. */ 4046215976Sjmallett#else 4047215976Sjmallett uint64_t ena_p1 : 1; 4048215976Sjmallett uint64_t ena_p0 : 1; 4049215976Sjmallett uint64_t reserved_2_2 : 1; 4050215976Sjmallett uint64_t mtype : 1; 4051215976Sjmallett uint64_t sil_lat : 2; 4052215976Sjmallett uint64_t rw_dly : 4; 4053215976Sjmallett uint64_t wr_dly : 4; 4054215976Sjmallett uint64_t fprch : 2; 4055215976Sjmallett uint64_t bprch : 2; 4056215976Sjmallett uint64_t blen : 1; 4057215976Sjmallett uint64_t pbunk : 3; 4058215976Sjmallett uint64_t r2r_pbunk : 1; 4059215976Sjmallett uint64_t init_p1 : 1; 4060215976Sjmallett uint64_t init_p0 : 1; 4061215976Sjmallett uint64_t bunk_init : 2; 4062215976Sjmallett uint64_t lpp_ena : 1; 4063215976Sjmallett uint64_t reserved_28_63 : 36; 4064215976Sjmallett#endif 4065215976Sjmallett } cn38xx; 4066232812Sjmallett struct cvmx_dfa_memcfg0_cn38xxp2 { 4067232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4068215976Sjmallett uint64_t reserved_27_63 : 37; 4069215976Sjmallett uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 4070215976Sjmallett sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 4071215976Sjmallett b) during a normal refresh sequence. If 4072215976Sjmallett the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 4073215976Sjmallett NOTE: This is required for DRAM used in a 4074215976Sjmallett clamshell configuration, since the address lines 4075215976Sjmallett carry Mode Register write data that is unique 4076215976Sjmallett per bunk(or clam). In a clamshell configuration, 4077215976Sjmallett The N3K A[x] pin may be tied into Clam#0's A[x] 4078215976Sjmallett and also into Clam#1's 'mirrored' address bit A[y] 4079215976Sjmallett (eg: Clam0 sees A[5] and Clam1 sees A[15]). 4080215976Sjmallett To support clamshell designs, SW must initiate 4081215976Sjmallett two separate HW init sequences for the two bunks 4082215976Sjmallett (or clams) . Before each HW init sequence is triggered, 4083215976Sjmallett SW must preload the DFA_MEMRLD[22:0] with the data 4084215976Sjmallett that will be driven onto the A[22:0] wires during 4085215976Sjmallett an MRS mode register write. 4086215976Sjmallett NOTE: After the final HW initialization sequence has 4087215976Sjmallett been triggered, SW must wait 64K eclks before writing 4088215976Sjmallett the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 4089215976Sjmallett driven during refresh sequences in normal operation. 4090215976Sjmallett NOTE: This should only be written to a different value 4091215976Sjmallett during power-on SW initialization. 4092215976Sjmallett NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 4093215976Sjmallett initialized independently. In other words, a HW init 4094215976Sjmallett must be done for Bunk#0, and then another HW init 4095215976Sjmallett must be done for Bunk#1 at power-on. */ 4096215976Sjmallett uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 4097215976Sjmallett the HW init sequence(s) for Memory Port \#0 is 4098215976Sjmallett initiated. 4099215976Sjmallett NOTE: To initialize memory, SW must: 4100215976Sjmallett 1) Enable memory port(s): 4101215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 4102215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 4103215976Sjmallett 2) Wait 100us (to ensure a stable clock 4104215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 4105215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 4106215976Sjmallett will initiate a hardware initialization 4107215976Sjmallett sequence. 4108215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 4109215976Sjmallett cycles to ensure the HW init sequence has completed 4110215976Sjmallett before writing to ANY of the DFA_MEM* registers. 4111215976Sjmallett NOTE: This should only be written to a different value 4112215976Sjmallett during power-on SW initialization. 4113215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 4114215976Sjmallett RLD0_* pins. */ 4115215976Sjmallett uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 4116215976Sjmallett the HW init sequence(s) for Memory Port \#1 is 4117215976Sjmallett initiated. 4118215976Sjmallett NOTE: To initialize memory, SW must: 4119215976Sjmallett 1) Enable memory port(s): 4120215976Sjmallett a) ENA_P1=1 (single port in pass 1) OR 4121215976Sjmallett b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 4122215976Sjmallett 2) Wait 100us (to ensure a stable clock 4123215976Sjmallett to the RLDRAMs) - as per RLDRAM spec. 4124215976Sjmallett 3) Write a '1' to the corresponding INIT_Px which 4125215976Sjmallett will initiate a hardware initialization 4126215976Sjmallett sequence. 4127215976Sjmallett NOTE: After writing a '1', SW must wait 64K eclk 4128215976Sjmallett cycles to ensure the HW init sequence has completed 4129215976Sjmallett before writing to ANY of the DFA_MEM* registers. 4130215976Sjmallett NOTE: This should only be written to a different value 4131215976Sjmallett during power-on SW initialization. 4132215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 4133215976Sjmallett RLD1_* pins. */ 4134215976Sjmallett uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 4135215976Sjmallett if back to back reads are issued to different physical 4136215976Sjmallett bunks. This is to avoid DQ data bus collisions when 4137215976Sjmallett references cross between physical bunks. 4138215976Sjmallett [NOTE: the physical bunk address boundary is determined 4139215976Sjmallett by the PBUNK bit]. 4140215976Sjmallett NOTE: This should only be written to a different value 4141215976Sjmallett during power-on SW initialization. 4142215976Sjmallett When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 4143215976Sjmallett ZERO(for optimal performance). However, if electrically, 4144215976Sjmallett DQ-sharing becomes a power/heat issue, then R2R_PBUNK 4145215976Sjmallett should be set (but at a cost to performance (1/2 BW). */ 4146215976Sjmallett uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 4147215976Sjmallett Specifies which address bit within the Longword 4148215976Sjmallett Memory address MA[23:0] is used to determine the 4149215976Sjmallett chip selects. 4150215976Sjmallett [RLD_CS0_N corresponds to physical bunk \#0, and 4151215976Sjmallett RLD_CS1_N corresponds to physical bunk \#1]. 4152215976Sjmallett - 000: CS0_N = MA[19]/CS1_N = !MA[19] 4153215976Sjmallett - 001: CS0_N = MA[20]/CS1_N = !MA[20] 4154215976Sjmallett - 010: CS0_N = MA[21]/CS1_N = !MA[21] 4155215976Sjmallett - 011: CS0_N = MA[22]/CS1_N = !MA[22] 4156215976Sjmallett - 100: CS0_N = MA[23]/CS1_N = !MA[23] 4157215976Sjmallett - 101-111: CS0_N = 0 /CS1_N = 1 4158215976Sjmallett Example(s): 4159215976Sjmallett To build out a 128MB DFA memory, 4x 32Mx9 4160215976Sjmallett parts could be used to fill out TWO physical 4161215976Sjmallett bunks (clamshell configuration). Each (of the 4162215976Sjmallett two) physical bunks contains 2x 32Mx9 = 16Mx36. 4163215976Sjmallett Each RLDRAM device also contains 8 internal banks, 4164215976Sjmallett therefore the memory Address is 16M/8banks = 2M 4165215976Sjmallett addresses/bunk (2^21). In this case, MA[21] would 4166215976Sjmallett select the physical bunk. 4167215976Sjmallett NOTE: This should only be written to a different value 4168215976Sjmallett during power-on SW initialization. 4169215976Sjmallett be used to determine the Chip Select(s). 4170215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 4171215976Sjmallett "Redundant Bunk" scheme is employed to provide the 4172215976Sjmallett highest overall performance (1 Req/ MCLK cycle). 4173215976Sjmallett In this mode, it's imperative that SW set the PBUNK 4174215976Sjmallett field +1 'above' the highest address bit. (such that 4175215976Sjmallett the PBUNK extracted from the address will always be 4176215976Sjmallett zero). In this mode, the CS_N[1:0] pins are driven 4177215976Sjmallett to each redundant bunk based on a TDM scheme: 4178215976Sjmallett [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 4179215976Sjmallett uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 4180215976Sjmallett When BLEN=0(BL2), all QW reads/writes from CP2 are 4181215976Sjmallett decomposed into 2 separate BL2(LW) requests to the 4182215976Sjmallett Low-Latency memory. 4183215976Sjmallett When BLEN=1(BL4), a LW request (from CP2 or NCB) is 4184215976Sjmallett treated as 1 BL4(QW) request to the low latency memory. 4185215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 4186215976Sjmallett by a processor core). LW refers to a 36-bit load/store. 4187215976Sjmallett NOTE: This should only be written to a different value 4188215976Sjmallett during power-on SW initialization before the DFA LLM 4189215976Sjmallett (low latency memory) is used. 4190215976Sjmallett NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 4191215976Sjmallett NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 4192215976Sjmallett multi-bunk(clam) board design. 4193215976Sjmallett NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 4194215976Sjmallett SW SHOULD use CP2 QW read/write requests (for 4195215976Sjmallett optimal low-latency bus performance). 4196215976Sjmallett [LW length read/write requests(in BL4 mode) use 50% 4197215976Sjmallett of the available bus bandwidth] 4198215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 4199215976Sjmallett be used with FCRAM-II devices which support BL2 mode 4200215976Sjmallett (see: Toshiba FCRAM-II, where DQ tristate after 2 data 4201215976Sjmallett transfers). 4202215976Sjmallett NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 4203215976Sjmallett write requests (FCRAM-II+ device specification has removed 4204215976Sjmallett the variable write mask function from the devices). 4205215976Sjmallett As such, if this mode is used, SW must be careful to 4206215976Sjmallett issue only PP-CP2 QW write requests. */ 4207215976Sjmallett uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 4208215976Sjmallett On reads, allows user to control the shape of the 4209215976Sjmallett tristate disable back porch for the DQ data bus. 4210215976Sjmallett This parameter is also very dependent on the 4211215976Sjmallett RW_DLY and WR_DLY parameters and care must be 4212215976Sjmallett taken when programming these parameters to avoid 4213215976Sjmallett data bus contention. Valid range [0..2] 4214215976Sjmallett NOTE: This should only be written to a different value 4215215976Sjmallett during power-on SW initialization. */ 4216215976Sjmallett uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 4217215976Sjmallett On reads, allows user to control the shape of the 4218215976Sjmallett tristate disable front porch for the DQ data bus. 4219215976Sjmallett This parameter is also very dependent on the 4220215976Sjmallett RW_DLY and WR_DLY parameters and care must be 4221215976Sjmallett taken when programming these parameters to avoid 4222215976Sjmallett data bus contention. Valid range [0..2] 4223215976Sjmallett NOTE: This should only be written to a different value 4224215976Sjmallett during power-on SW initialization. */ 4225215976Sjmallett uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 4226215976Sjmallett Determines \#mclk cycles to insert when controller 4227215976Sjmallett switches from write to read. This allows programmer 4228215976Sjmallett to control the data bus contention. 4229215976Sjmallett For RLDRAM-II(BL2): (TBL=1) 4230215976Sjmallett For FCRAM-II (BL4): (TBL=2) 4231215976Sjmallett For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 4232215976Sjmallett For FCRAM-II (BL2 grepl>=2x): (TBL=3) 4233215976Sjmallett NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 4234215976Sjmallett grepl>=2x, writes require redundant bunk writes 4235215976Sjmallett which require an additional 2 cycles before slotting 4236215976Sjmallett the next read. 4237215976Sjmallett WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 4238215976Sjmallett NOTE: This should only be written to a different value 4239215976Sjmallett during power-on SW initialization. 4240215976Sjmallett NOTE: For aggressive(performance optimal) designs, 4241215976Sjmallett the WR_DLY 'may' be tuned down(-1) if bus fight 4242215976Sjmallett on W->R transitions is not pronounced. */ 4243215976Sjmallett uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 4244215976Sjmallett Determines \#mclk cycles to insert when controller 4245215976Sjmallett switches from read to write. This allows programmer 4246215976Sjmallett to control the data bus contention. 4247215976Sjmallett For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 4248215976Sjmallett For FCRAM-II (BL4): (TBL=2) 4249215976Sjmallett RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 4250215976Sjmallett NOTE: This should only be written to a different value 4251215976Sjmallett during power-on SW initialization. 4252215976Sjmallett NOTE: For aggressive(performance optimal) designs, 4253215976Sjmallett the RW_DLY 'may' be tuned down(-1) if bus fight 4254215976Sjmallett on R->W transitions is not pronounced. */ 4255215976Sjmallett uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 4256215976Sjmallett additional dclks to wait (on top of tRL+1) before 4257215976Sjmallett pulling data out of the padring silos used for time 4258215976Sjmallett domain boundary crossing. 4259215976Sjmallett NOTE: This should only be written to a different value 4260215976Sjmallett during power-on SW initialization. */ 4261215976Sjmallett uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 4262215976Sjmallett NOTE: N3K-P1 only supports RLDRAM-II 4263215976Sjmallett NOTE: This should only be written to a different value 4264215976Sjmallett during power-on SW initialization. 4265215976Sjmallett NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 4266215976Sjmallett "unidirectional DS/QS" mode is supported. (see FCRAM 4267215976Sjmallett data sheet EMRS[A6:A5]=SS(Strobe Select) register 4268215976Sjmallett definition. [in FCRAM 2-burst mode, we use FCRAM 4269215976Sjmallett in a clamshell configuration such that clam0 is 4270215976Sjmallett addressed independently of clam1, and DQ is shared 4271215976Sjmallett for optimal performance. As such it's imperative that 4272215976Sjmallett the QS are conditionally received (and are NOT 4273215976Sjmallett free-running), as the N3K receive data capture silos 4274215976Sjmallett OR the clam0/1 QS strobes. 4275215976Sjmallett NOTE: If this bit is SET, the ASX0/1 4276215976Sjmallett ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 4277215976Sjmallett in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 4278215976Sjmallett uint64_t reserved_2_2 : 1; 4279215976Sjmallett uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 4280215976Sjmallett When enabled, this bit lets N3K be the default 4281215976Sjmallett driver for memory port \#0. 4282215976Sjmallett NOTE: For N3K-P1, to enable Port#0(2nd port), 4283215976Sjmallett Port#1 MUST ALSO be enabled. 4284215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 4285215976Sjmallett liberty to enable either Port#0 or Port#1. 4286215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 4287215976Sjmallett be re-enabled. [the only way to enable a port is 4288215976Sjmallett through a chip reset]. 4289215976Sjmallett NOTE: DFA Memory Port#0 corresponds to the Octeon 4290215976Sjmallett RLD0_* pins. */ 4291215976Sjmallett uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 4292215976Sjmallett When enabled, this bit lets N3K be the default 4293215976Sjmallett driver for memory port \#1. 4294215976Sjmallett NOTE: For N3K-P1, If the customer wishes to use a 4295215976Sjmallett single port, s/he must enable Port#1 (and not Port#0). 4296215976Sjmallett NOTE: For N3K-P2, single port mode, a customer is at 4297215976Sjmallett liberty to enable either Port#0 or Port#1. 4298215976Sjmallett NOTE: Once a port has been disabled, it MUST NEVER 4299215976Sjmallett be re-enabled. [the only way to enable a port is 4300215976Sjmallett through a chip reset]. 4301215976Sjmallett NOTE: DFA Memory Port#1 corresponds to the Octeon 4302215976Sjmallett RLD1_* pins. */ 4303215976Sjmallett#else 4304215976Sjmallett uint64_t ena_p1 : 1; 4305215976Sjmallett uint64_t ena_p0 : 1; 4306215976Sjmallett uint64_t reserved_2_2 : 1; 4307215976Sjmallett uint64_t mtype : 1; 4308215976Sjmallett uint64_t sil_lat : 2; 4309215976Sjmallett uint64_t rw_dly : 4; 4310215976Sjmallett uint64_t wr_dly : 4; 4311215976Sjmallett uint64_t fprch : 2; 4312215976Sjmallett uint64_t bprch : 2; 4313215976Sjmallett uint64_t blen : 1; 4314215976Sjmallett uint64_t pbunk : 3; 4315215976Sjmallett uint64_t r2r_pbunk : 1; 4316215976Sjmallett uint64_t init_p1 : 1; 4317215976Sjmallett uint64_t init_p0 : 1; 4318215976Sjmallett uint64_t bunk_init : 2; 4319215976Sjmallett uint64_t reserved_27_63 : 37; 4320215976Sjmallett#endif 4321215976Sjmallett } cn38xxp2; 4322215976Sjmallett struct cvmx_dfa_memcfg0_s cn58xx; 4323215976Sjmallett struct cvmx_dfa_memcfg0_s cn58xxp1; 4324215976Sjmallett}; 4325215976Sjmalletttypedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t; 4326215976Sjmallett 4327215976Sjmallett/** 4328215976Sjmallett * cvmx_dfa_memcfg1 4329215976Sjmallett * 4330215976Sjmallett * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration 4331215976Sjmallett * 4332215976Sjmallett * Description: 4333215976Sjmallett */ 4334232812Sjmallettunion cvmx_dfa_memcfg1 { 4335215976Sjmallett uint64_t u64; 4336232812Sjmallett struct cvmx_dfa_memcfg1_s { 4337232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4338215976Sjmallett uint64_t reserved_34_63 : 30; 4339215976Sjmallett uint64_t ref_intlo : 9; /**< Burst Refresh Interval[8:0] (\#dclks) 4340215976Sjmallett For finer refresh interval granularity control. 4341215976Sjmallett This field provides an additional level of granularity 4342215976Sjmallett for the refresh interval. It specifies the additional 4343215976Sjmallett \#dclks [0...511] to be added to the REF_INT[3:0] field. 4344215976Sjmallett For RLDRAM-II: For dclk(400MHz=2.5ns): 4345215976Sjmallett Example: 64K AREF cycles required within tREF=32ms 4346215976Sjmallett trefint = tREF(ms)/(64K cycles/8banks) 4347215976Sjmallett = 32ms/8K = 3.9us = 3900ns 4348215976Sjmallett REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512] 4349215976Sjmallett = ROUND_DOWN[(3900/2.5)/512] 4350215976Sjmallett = 3 4351215976Sjmallett REF_INTLO[8:0] = MOD[(trefint/dclk)/512] 4352215976Sjmallett = MOD[(3900/2.5)/512] 4353215976Sjmallett = 24 4354215976Sjmallett NOTE: This should only be written to a different value 4355215976Sjmallett during power-on SW initialization. */ 4356215976Sjmallett uint64_t aref_ena : 1; /**< Auto Refresh Cycle Enable 4357215976Sjmallett INTERNAL USE ONLY: 4358215976Sjmallett NOTE: This mode bit is ONLY intended to be used by 4359215976Sjmallett low-level power-on initialization routines in the 4360215976Sjmallett event that the hardware initialization routine 4361215976Sjmallett does not work. It allows SW to create AREF 4362215976Sjmallett commands on the RLDRAM bus directly. 4363215976Sjmallett When this bit is set, ALL RLDRAM writes (issued by 4364215976Sjmallett a PP through the NCB or CP2) are converted to AREF 4365215976Sjmallett commands on the RLDRAM bus. The write-address is 4366215976Sjmallett presented on the A[20:0]/BA[2:0] pins (for which 4367215976Sjmallett the RLDRAM only interprets BA[2:0]). 4368215976Sjmallett When this bit is set, only writes are allowed 4369215976Sjmallett and MUST use grepl=0 (1x). 4370215976Sjmallett NOTE: This should only be written to a different value 4371215976Sjmallett during power-on SW initialization. 4372215976Sjmallett NOTE: MRS_ENA and AREF_ENA are mutually exclusive 4373215976Sjmallett (SW can set one or the other, but never both!) 4374215976Sjmallett NOTE: AREF commands generated using this method target 4375215976Sjmallett the 'addressed' bunk. */ 4376215976Sjmallett uint64_t mrs_ena : 1; /**< Mode Register Set Cycle Enable 4377215976Sjmallett INTERNAL USE ONLY: 4378215976Sjmallett NOTE: This mode bit is ONLY intended to be used by 4379215976Sjmallett low-level power-on initialization routines in the 4380215976Sjmallett event that the hardware initialization routine 4381215976Sjmallett does not work. It allows SW to create MRS 4382215976Sjmallett commands on the RLDRAM bus directly. 4383215976Sjmallett When this bit is set, ALL RLDRAM writes (issued by 4384215976Sjmallett a PP through the NCB or CP2) are converted to MRS 4385215976Sjmallett commands on the RLDRAM bus. The write-address is 4386215976Sjmallett presented on the A[20:0]/BA[2:0] pins (for which 4387215976Sjmallett the RLDRAM only interprets A[17:0]). 4388215976Sjmallett When this bit is set, only writes are allowed 4389215976Sjmallett and MUST use grepl=0 (1x). 4390215976Sjmallett NOTE: This should only be written to a different value 4391215976Sjmallett during power-on SW initialization. 4392215976Sjmallett NOTE: MRS_ENA and AREF_ENA are mutually exclusive 4393215976Sjmallett (SW can set one or the other, but never both!) 4394215976Sjmallett NOTE: MRS commands generated using this method target 4395215976Sjmallett the 'addressed' bunk. */ 4396215976Sjmallett uint64_t tmrsc : 3; /**< Mode Register Set Cycle Time (represented in \#mclks) 4397215976Sjmallett - 000-001: RESERVED 4398215976Sjmallett - 010: tMRSC = 2 mclks 4399215976Sjmallett - 011: tMRSC = 3 mclks 4400215976Sjmallett - ... 4401215976Sjmallett - 111: tMRSC = 7 mclks 4402215976Sjmallett NOTE: The device tMRSC parameter is a function of CL 4403215976Sjmallett (which during HW initialization is not known. Its 4404215976Sjmallett recommended to load tMRSC(MAX) value to avoid timing 4405215976Sjmallett violations. 4406215976Sjmallett NOTE: This should only be written to a different value 4407215976Sjmallett during power-on SW initialization. */ 4408215976Sjmallett uint64_t trc : 4; /**< Row Cycle Time (represented in \#mclks) 4409215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 4410215976Sjmallett correspond with tRL/tWL parameter(s). 4411215976Sjmallett - 0000-0010: RESERVED 4412215976Sjmallett - 0011: tRC = 3 mclks 4413215976Sjmallett - 0100: tRC = 4 mclks 4414215976Sjmallett - 0101: tRC = 5 mclks 4415215976Sjmallett - 0110: tRC = 6 mclks 4416215976Sjmallett - 0111: tRC = 7 mclks 4417215976Sjmallett - 1000: tRC = 8 mclks 4418215976Sjmallett - 1001: tRC = 9 mclks 4419215976Sjmallett - 1010-1111: RESERVED 4420215976Sjmallett NOTE: This should only be written to a different value 4421215976Sjmallett during power-on SW initialization. */ 4422215976Sjmallett uint64_t twl : 4; /**< Write Latency (represented in \#mclks) 4423215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 4424215976Sjmallett correspond with tRL/tWL parameter(s). 4425215976Sjmallett - 0000-0001: RESERVED 4426215976Sjmallett - 0010: Write Latency (WL=2.0 mclk) 4427215976Sjmallett - 0011: Write Latency (WL=3.0 mclks) 4428215976Sjmallett - 0100: Write Latency (WL=4.0 mclks) 4429215976Sjmallett - 0101: Write Latency (WL=5.0 mclks) 4430215976Sjmallett - 0110: Write Latency (WL=6.0 mclks) 4431215976Sjmallett - 0111: Write Latency (WL=7.0 mclks) 4432215976Sjmallett - 1000: Write Latency (WL=8.0 mclks) 4433215976Sjmallett - 1001: Write Latency (WL=9.0 mclks) 4434215976Sjmallett - 1010: Write Latency (WL=10.0 mclks) 4435215976Sjmallett - 1011-1111: RESERVED 4436215976Sjmallett NOTE: This should only be written to a different value 4437215976Sjmallett during power-on SW initialization. */ 4438215976Sjmallett uint64_t trl : 4; /**< Read Latency (represented in \#mclks) 4439215976Sjmallett see also: DFA_MEMRLD[RLCFG] field which must 4440215976Sjmallett correspond with tRL/tWL parameter(s). 4441215976Sjmallett - 0000-0010: RESERVED 4442215976Sjmallett - 0011: Read Latency = 3 mclks 4443215976Sjmallett - 0100: Read Latency = 4 mclks 4444215976Sjmallett - 0101: Read Latency = 5 mclks 4445215976Sjmallett - 0110: Read Latency = 6 mclks 4446215976Sjmallett - 0111: Read Latency = 7 mclks 4447215976Sjmallett - 1000: Read Latency = 8 mclks 4448215976Sjmallett - 1001: Read Latency = 9 mclks 4449215976Sjmallett - 1010: Read Latency = 10 mclks 4450215976Sjmallett - 1011-1111: RESERVED 4451215976Sjmallett NOTE: This should only be written to a different value 4452215976Sjmallett during power-on SW initialization. */ 4453215976Sjmallett uint64_t reserved_6_7 : 2; 4454215976Sjmallett uint64_t tskw : 2; /**< Board Skew (represented in \#dclks) 4455215976Sjmallett Represents additional board skew of DQ/DQS. 4456215976Sjmallett - 00: board-skew = 0 dclk 4457215976Sjmallett - 01: board-skew = 1 dclk 4458215976Sjmallett - 10: board-skew = 2 dclk 4459215976Sjmallett - 11: board-skew = 3 dclk 4460215976Sjmallett NOTE: This should only be written to a different value 4461215976Sjmallett during power-on SW initialization. */ 4462215976Sjmallett uint64_t ref_int : 4; /**< Refresh Interval (represented in \#of 512 dclk 4463215976Sjmallett increments). 4464215976Sjmallett - 0000: RESERVED 4465215976Sjmallett - 0001: 1 * 512 = 512 dclks 4466215976Sjmallett - ... 4467215976Sjmallett - 1111: 15 * 512 = 7680 dclks 4468215976Sjmallett NOTE: For finer level of granularity, refer to 4469215976Sjmallett REF_INTLO[8:0] field. 4470215976Sjmallett For RLDRAM-II, each refresh interval will 4471215976Sjmallett generate a burst of 8 AREF commands, one to each of 4472215976Sjmallett 8 explicit banks (referenced using the RLD_BA[2:0] 4473215976Sjmallett pins. 4474215976Sjmallett Example: For mclk=200MHz/dclk(400MHz=2.5ns): 4475215976Sjmallett 64K AREF cycles required within tREF=32ms 4476215976Sjmallett trefint = tREF(ms)/(64K cycles/8banks) 4477215976Sjmallett = 32ms/8K = 3.9us = 3900ns 4478215976Sjmallett REF_INT = ROUND_DOWN[(trefint/dclk)/512] 4479215976Sjmallett = ROUND_DOWN[(3900/2.5)/512] 4480215976Sjmallett = 3 4481215976Sjmallett NOTE: This should only be written to a different value 4482215976Sjmallett during power-on SW initialization. */ 4483215976Sjmallett#else 4484215976Sjmallett uint64_t ref_int : 4; 4485215976Sjmallett uint64_t tskw : 2; 4486215976Sjmallett uint64_t reserved_6_7 : 2; 4487215976Sjmallett uint64_t trl : 4; 4488215976Sjmallett uint64_t twl : 4; 4489215976Sjmallett uint64_t trc : 4; 4490215976Sjmallett uint64_t tmrsc : 3; 4491215976Sjmallett uint64_t mrs_ena : 1; 4492215976Sjmallett uint64_t aref_ena : 1; 4493215976Sjmallett uint64_t ref_intlo : 9; 4494215976Sjmallett uint64_t reserved_34_63 : 30; 4495215976Sjmallett#endif 4496215976Sjmallett } s; 4497215976Sjmallett struct cvmx_dfa_memcfg1_s cn38xx; 4498215976Sjmallett struct cvmx_dfa_memcfg1_s cn38xxp2; 4499215976Sjmallett struct cvmx_dfa_memcfg1_s cn58xx; 4500215976Sjmallett struct cvmx_dfa_memcfg1_s cn58xxp1; 4501215976Sjmallett}; 4502215976Sjmalletttypedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t; 4503215976Sjmallett 4504215976Sjmallett/** 4505215976Sjmallett * cvmx_dfa_memcfg2 4506215976Sjmallett * 4507215976Sjmallett * DFA_MEMCFG2 = DFA Memory Config Register \#2 4508215976Sjmallett * *** NOTE: Pass2 Addition 4509215976Sjmallett * 4510215976Sjmallett * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II 4511215976Sjmallett */ 4512232812Sjmallettunion cvmx_dfa_memcfg2 { 4513215976Sjmallett uint64_t u64; 4514232812Sjmallett struct cvmx_dfa_memcfg2_s { 4515232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4516215976Sjmallett uint64_t reserved_12_63 : 52; 4517215976Sjmallett uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 4518215976Sjmallett When SET, the DFA clocks for DTE(thread engine) 4519215976Sjmallett operation are disabled. 4520215976Sjmallett NOTE: When SET, SW MUST NEVER issue ANY operations to 4521215976Sjmallett the DFA via the NCB Bus. All DFA Operations must be 4522215976Sjmallett issued solely through the CP2 interface. 4523215976Sjmallett 4524215976Sjmallett NOTE: When DTECLKDIS=1, if CP2 Errors are encountered 4525215976Sjmallett (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR 4526215976Sjmallett does not reflect the failing address/ctl information. */ 4527215976Sjmallett uint64_t silrst : 1; /**< LLM-PHY Silo Reset 4528215976Sjmallett When a '1' is written (when the previous 4529215976Sjmallett value was a '0') causes the the LLM-PHY Silo read/write 4530215976Sjmallett pointers to be reset. 4531215976Sjmallett NOTE: SW MUST WAIT 400 dclks after the LAST HW Init 4532215976Sjmallett sequence was launched (ie: INIT_START 0->1 CSR write), 4533215976Sjmallett before the SILRST can be triggered (0->1). */ 4534215976Sjmallett uint64_t trfc : 5; /**< FCRAM-II Refresh Interval 4535215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4536215976Sjmallett uint64_t refshort : 1; /**< FCRAM Short Refresh Mode 4537215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4538215976Sjmallett uint64_t ua_start : 2; /**< FCRAM-II Upper Addres Start 4539215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4540215976Sjmallett uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 4541215976Sjmallett when extracting address bits for the memory bank#. 4542215976Sjmallett - 0: 4 banks/device 4543215976Sjmallett - 1: 8 banks/device */ 4544215976Sjmallett uint64_t fcram2p : 1; /**< FCRAM-II+ Mode Enable 4545215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4546215976Sjmallett#else 4547215976Sjmallett uint64_t fcram2p : 1; 4548215976Sjmallett uint64_t maxbnk : 1; 4549215976Sjmallett uint64_t ua_start : 2; 4550215976Sjmallett uint64_t refshort : 1; 4551215976Sjmallett uint64_t trfc : 5; 4552215976Sjmallett uint64_t silrst : 1; 4553215976Sjmallett uint64_t dteclkdis : 1; 4554215976Sjmallett uint64_t reserved_12_63 : 52; 4555215976Sjmallett#endif 4556215976Sjmallett } s; 4557215976Sjmallett struct cvmx_dfa_memcfg2_s cn38xx; 4558215976Sjmallett struct cvmx_dfa_memcfg2_s cn38xxp2; 4559215976Sjmallett struct cvmx_dfa_memcfg2_s cn58xx; 4560215976Sjmallett struct cvmx_dfa_memcfg2_s cn58xxp1; 4561215976Sjmallett}; 4562215976Sjmalletttypedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t; 4563215976Sjmallett 4564215976Sjmallett/** 4565215976Sjmallett * cvmx_dfa_memfadr 4566215976Sjmallett * 4567215976Sjmallett * DFA_MEMFADR = RLDRAM Failing Address/Control Register 4568215976Sjmallett * 4569215976Sjmallett * Description: DFA Memory Failing Address/Control Error Capture information 4570215976Sjmallett * This register contains useful information to help in isolating an RLDRAM memory failure. 4571215976Sjmallett * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is 4572215976Sjmallett * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt 4573215976Sjmallett * via the FSRC field. 4574215976Sjmallett * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED. 4575215976Sjmallett */ 4576232812Sjmallettunion cvmx_dfa_memfadr { 4577215976Sjmallett uint64_t u64; 4578232812Sjmallett struct cvmx_dfa_memfadr_s { 4579232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4580215976Sjmallett uint64_t reserved_24_63 : 40; 4581215976Sjmallett uint64_t maddr : 24; /**< Memory Address */ 4582215976Sjmallett#else 4583215976Sjmallett uint64_t maddr : 24; 4584215976Sjmallett uint64_t reserved_24_63 : 40; 4585215976Sjmallett#endif 4586215976Sjmallett } s; 4587232812Sjmallett struct cvmx_dfa_memfadr_cn31xx { 4588232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4589215976Sjmallett uint64_t reserved_40_63 : 24; 4590215976Sjmallett uint64_t fdst : 9; /**< Fill-Destination 4591215976Sjmallett FSRC[1:0] | FDST[8:0] 4592215976Sjmallett -------------+------------------------------------- 4593215976Sjmallett 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 4594215976Sjmallett 1(NCB-CSR) | [ncbSRC[8:0]] 4595215976Sjmallett 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 4596215976Sjmallett where: 4597215976Sjmallett DTE: DFA Thread Engine ID# 4598215976Sjmallett PP: Packet Processor ID# 4599215976Sjmallett FID: Fill-ID# (unique per PP) 4600215976Sjmallett WIDX: 16b SIMPLE Mode (index) 4601215976Sjmallett DMODE: (0=16b SIMPLE/1=32b SIMPLE) 4602215976Sjmallett SIZE: (0=LW Mode access/1=QW Mode Access) 4603215976Sjmallett INDEX: (0=Low LW/1=High LW) 4604215976Sjmallett NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated 4605215976Sjmallett by a processor core). LW refers to a 32-bit load/store. */ 4606215976Sjmallett uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 4607215976Sjmallett uint64_t pnum : 1; /**< Memory Port 4608215976Sjmallett NOTE: For O2P, this bit will always return zero. */ 4609215976Sjmallett uint64_t bnum : 3; /**< Memory Bank 4610215976Sjmallett When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0]. 4611215976Sjmallett (RANK[1] can be inferred from MADDR[24:0]) */ 4612215976Sjmallett uint64_t maddr : 25; /**< Memory Address */ 4613215976Sjmallett#else 4614215976Sjmallett uint64_t maddr : 25; 4615215976Sjmallett uint64_t bnum : 3; 4616215976Sjmallett uint64_t pnum : 1; 4617215976Sjmallett uint64_t fsrc : 2; 4618215976Sjmallett uint64_t fdst : 9; 4619215976Sjmallett uint64_t reserved_40_63 : 24; 4620215976Sjmallett#endif 4621215976Sjmallett } cn31xx; 4622232812Sjmallett struct cvmx_dfa_memfadr_cn38xx { 4623232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4624215976Sjmallett uint64_t reserved_39_63 : 25; 4625215976Sjmallett uint64_t fdst : 9; /**< Fill-Destination 4626215976Sjmallett FSRC[1:0] | FDST[8:0] 4627215976Sjmallett -------------+------------------------------------- 4628215976Sjmallett 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 4629215976Sjmallett 1(NCB-CSR) | [ncbSRC[8:0]] 4630215976Sjmallett 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 4631215976Sjmallett where: 4632215976Sjmallett DTE: DFA Thread Engine ID# 4633215976Sjmallett PP: Packet Processor ID# 4634215976Sjmallett FID: Fill-ID# (unique per PP) 4635215976Sjmallett WIDX: 18b SIMPLE Mode (index) 4636215976Sjmallett DMODE: (0=18b SIMPLE/1=36b SIMPLE) 4637215976Sjmallett SIZE: (0=LW Mode access/1=QW Mode Access) 4638215976Sjmallett INDEX: (0=Low LW/1=High LW) 4639215976Sjmallett NOTE: QW refers to a 64-bit LLM Load/Store (intiated 4640215976Sjmallett by a processor core). LW refers to a 36-bit load/store. */ 4641215976Sjmallett uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 4642215976Sjmallett uint64_t pnum : 1; /**< Memory Port 4643215976Sjmallett NOTE: the port id's are reversed 4644215976Sjmallett PNUM==0 => port#1 4645215976Sjmallett PNUM==1 => port#0 */ 4646215976Sjmallett uint64_t bnum : 3; /**< Memory Bank */ 4647215976Sjmallett uint64_t maddr : 24; /**< Memory Address */ 4648215976Sjmallett#else 4649215976Sjmallett uint64_t maddr : 24; 4650215976Sjmallett uint64_t bnum : 3; 4651215976Sjmallett uint64_t pnum : 1; 4652215976Sjmallett uint64_t fsrc : 2; 4653215976Sjmallett uint64_t fdst : 9; 4654215976Sjmallett uint64_t reserved_39_63 : 25; 4655215976Sjmallett#endif 4656215976Sjmallett } cn38xx; 4657215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn38xxp2; 4658215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn58xx; 4659215976Sjmallett struct cvmx_dfa_memfadr_cn38xx cn58xxp1; 4660215976Sjmallett}; 4661215976Sjmalletttypedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t; 4662215976Sjmallett 4663215976Sjmallett/** 4664215976Sjmallett * cvmx_dfa_memfcr 4665215976Sjmallett * 4666215976Sjmallett * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0] 4667215976Sjmallett * *** CN58XX UNSUPPORTED *** 4668215976Sjmallett * 4669215976Sjmallett * Notes: 4670215976Sjmallett * For FCRAM-II please consult your device's data sheet for further details: 4671215976Sjmallett * MRS Definition: 4672215976Sjmallett * A[13:8]=0 RESERVED 4673215976Sjmallett * A[7]=0 TEST MODE (N3K requires test mode 0:"disabled") 4674215976Sjmallett * A[6:4] CAS LATENCY (fully programmable - SW must ensure that the value programmed 4675215976Sjmallett * into DFA_MEM_CFG0[TRL] corresponds with this value). 4676215976Sjmallett * A[3]=0 BURST TYPE (N3K requires 0:"Sequential" Burst Type) 4677215976Sjmallett * A[2:0] BURST LENGTH Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4) 4678215976Sjmallett * 4679215976Sjmallett * In BL2 mode(for highest performance), only 1/2 the phsyical 4680215976Sjmallett * memory is unique (ie: each bunk stores the same information). 4681215976Sjmallett * In BL4 mode(highest capacity), all of the physical memory 4682215976Sjmallett * is unique (ie: each bunk is uniquely addressable). 4683215976Sjmallett * EMRS Definition: 4684215976Sjmallett * A[13:12] REFRESH MODE (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes) 4685215976Sjmallett * 4686215976Sjmallett * (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT] 4687215976Sjmallett * is also reflected in the Refresh Mode encoding). 4688215976Sjmallett * A[11:7]=0 RESERVED 4689215976Sjmallett * A[6:5]=2 STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture 4690215976Sjmallett * silos rely on a conditional QS strobe) 4691215976Sjmallett * A[4:3] DIC(QS) QS Drive Strength: fully programmable (consult your FCRAM-II data sheet) 4692215976Sjmallett * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 4693215976Sjmallett * A[2:1] DIC(DQ) DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet) 4694215976Sjmallett * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 4695215976Sjmallett * A[0] DLL DLL Enable: Programmable [0:DLL Enable/1: DLL Disable] 4696215976Sjmallett * 4697215976Sjmallett * EMRS2 Definition: (for FCRAM-II+) 4698215976Sjmallett * A[13:11]=0 RESERVED 4699215976Sjmallett * A[10:8] ODTDS On Die Termination (DS+/-) 4700215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4701215976Sjmallett * A[7:6]=0 MBW Multi-Bank Write: (N3K requires use of 0:"single bank" mode only) 4702215976Sjmallett * A[5:3] ODTin On Die Termination (input pin) 4703215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4704215976Sjmallett * A[2:0] ODTDQ On Die Termination (DQ) 4705215976Sjmallett * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4706215976Sjmallett */ 4707232812Sjmallettunion cvmx_dfa_memfcr { 4708215976Sjmallett uint64_t u64; 4709232812Sjmallett struct cvmx_dfa_memfcr_s { 4710232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4711215976Sjmallett uint64_t reserved_47_63 : 17; 4712215976Sjmallett uint64_t emrs2 : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+) 4713215976Sjmallett *** CN58XX UNSUPPORTED *** */ 4714215976Sjmallett uint64_t reserved_31_31 : 1; 4715215976Sjmallett uint64_t emrs : 15; /**< Memory Address[14:0] during EMRS 4716215976Sjmallett *** CN58XX UNSUPPORTED *** 4717215976Sjmallett A[0]=1: DLL Enabled) */ 4718215976Sjmallett uint64_t reserved_15_15 : 1; 4719215976Sjmallett uint64_t mrs : 15; /**< FCRAM Memory Address[14:0] during MRS 4720215976Sjmallett *** CN58XX UNSUPPORTED *** 4721215976Sjmallett A[6:4]=4 CAS LATENCY=4(default) 4722215976Sjmallett A[3]=0 Burst Type(must be 0:Sequential) 4723215976Sjmallett A[2:0]=2 Burst Length=4(default) */ 4724215976Sjmallett#else 4725215976Sjmallett uint64_t mrs : 15; 4726215976Sjmallett uint64_t reserved_15_15 : 1; 4727215976Sjmallett uint64_t emrs : 15; 4728215976Sjmallett uint64_t reserved_31_31 : 1; 4729215976Sjmallett uint64_t emrs2 : 15; 4730215976Sjmallett uint64_t reserved_47_63 : 17; 4731215976Sjmallett#endif 4732215976Sjmallett } s; 4733215976Sjmallett struct cvmx_dfa_memfcr_s cn38xx; 4734215976Sjmallett struct cvmx_dfa_memfcr_s cn38xxp2; 4735215976Sjmallett struct cvmx_dfa_memfcr_s cn58xx; 4736215976Sjmallett struct cvmx_dfa_memfcr_s cn58xxp1; 4737215976Sjmallett}; 4738215976Sjmalletttypedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t; 4739215976Sjmallett 4740215976Sjmallett/** 4741215976Sjmallett * cvmx_dfa_memhidat 4742215976Sjmallett * 4743215976Sjmallett * DFA_MEMHIDAT = DFA NCB-Direct CSR access to DFM Memory Space (High QW) 4744215976Sjmallett * 4745215976Sjmallett * Description: 4746215976Sjmallett * DFA supports NCB-Direct CSR acccesses to DFM Memory space for debug purposes. Unfortunately, NCB-Direct accesses 4747215976Sjmallett * are limited to QW-size(64bits), whereas the minimum access granularity for DFM Memory space is OW(128bits). To 4748215976Sjmallett * support writes to DFM Memory space, the Hi-QW of data is sourced from the DFA_MEMHIDAT register. Recall, the 4749215976Sjmallett * OW(128b) in DDR3 memory space is fixed format: 4750215976Sjmallett * OWDATA[127:118]: OWECC[9:0] 10bits of in-band OWECC SEC/DED codeword 4751215976Sjmallett * This can be precomputed/written by SW OR 4752215976Sjmallett * if DFM_FNTCTL[ECC_WENA]=1, DFM hardware will auto-compute the 10b OWECC and place in the 4753215976Sjmallett * OWDATA[127:118] before being written to memory. 4754215976Sjmallett * OWDATA[117:0]: Memory Data (contains fixed MNODE/MONODE arc formats for use by DTEs(thread engines). 4755215976Sjmallett * Or, a user may choose to treat DFM Memory Space as 'scratch pad' in which case the 4756215976Sjmallett * OWDATA[117:0] may contain user-specified information accessible via NCB-Direct CSR mode 4757215976Sjmallett * accesses to DFA Memory Space. 4758215976Sjmallett * NOTE: To write to the DFA_MEMHIDAT register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b111. 4759215976Sjmallett * To read the DFA_MEMHIDAT register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b111. 4760215976Sjmallett * 4761215976Sjmallett * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect. 4762215976Sjmallett * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect. 4763232812Sjmallett * 4764232812Sjmallett * NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM 4765215976Sjmallett */ 4766232812Sjmallettunion cvmx_dfa_memhidat { 4767215976Sjmallett uint64_t u64; 4768232812Sjmallett struct cvmx_dfa_memhidat_s { 4769232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4770215976Sjmallett uint64_t hidat : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3 4771215976Sjmallett Memory accesses. 4772215976Sjmallett All DFM DDR3 memory accesses are OW(128b) references, 4773215976Sjmallett and since NCB-Direct Mode writes only support QW(64b), 4774215976Sjmallett the Hi QW of data must be sourced from a CSR register. 4775215976Sjmallett NOTE: This single register is 'shared' for ALL DFM 4776232812Sjmallett DDR3 Memory writes. 4777232812Sjmallett For o68: This register is UNUSED. Treat as spare bits. 4778232812Sjmallett NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM */ 4779215976Sjmallett#else 4780215976Sjmallett uint64_t hidat : 64; 4781215976Sjmallett#endif 4782215976Sjmallett } s; 4783232812Sjmallett struct cvmx_dfa_memhidat_s cn61xx; 4784215976Sjmallett struct cvmx_dfa_memhidat_s cn63xx; 4785215976Sjmallett struct cvmx_dfa_memhidat_s cn63xxp1; 4786232812Sjmallett struct cvmx_dfa_memhidat_s cn66xx; 4787232812Sjmallett struct cvmx_dfa_memhidat_s cn68xx; 4788232812Sjmallett struct cvmx_dfa_memhidat_s cn68xxp1; 4789215976Sjmallett}; 4790215976Sjmalletttypedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t; 4791215976Sjmallett 4792215976Sjmallett/** 4793215976Sjmallett * cvmx_dfa_memrld 4794215976Sjmallett * 4795215976Sjmallett * DFA_MEMRLD = DFA RLDRAM MRS Register Values 4796215976Sjmallett * 4797215976Sjmallett * Description: 4798215976Sjmallett */ 4799232812Sjmallettunion cvmx_dfa_memrld { 4800215976Sjmallett uint64_t u64; 4801232812Sjmallett struct cvmx_dfa_memrld_s { 4802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4803215976Sjmallett uint64_t reserved_23_63 : 41; 4804215976Sjmallett uint64_t mrsdat : 23; /**< This field represents the data driven onto the 4805215976Sjmallett A[22:0] address lines during MRS(Mode Register Set) 4806215976Sjmallett commands (during a HW init sequence). This field 4807215976Sjmallett corresponds with the Mode Register Bit Map from 4808215976Sjmallett your RLDRAM-II device specific data sheet. 4809215976Sjmallett A[17:10]: RESERVED 4810215976Sjmallett A[9]: ODT (on die termination) 4811215976Sjmallett A[8]: Impedance Matching 4812215976Sjmallett A[7]: DLL Reset 4813215976Sjmallett A[6]: UNUSED 4814215976Sjmallett A[5]: Address Mux (for N3K: MUST BE ZERO) 4815215976Sjmallett A[4:3]: Burst Length (for N3K: MUST BE ZERO) 4816215976Sjmallett A[2:0]: Configuration (see data sheet for 4817215976Sjmallett specific RLDRAM-II device). 4818215976Sjmallett - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5] 4819215976Sjmallett - 010: CFG=2 [tRC=6/tRL=6/tWL=7] 4820215976Sjmallett - 011: CFG=3 [tRC=8/tRL=8/tWL=9] 4821215976Sjmallett - 100-111: RESERVED 4822215976Sjmallett NOTE: For additional density, the RLDRAM-II parts 4823215976Sjmallett can be 'clamshelled' (ie: two devices mounted on 4824215976Sjmallett different sides of the PCB board), since the BGA 4825215976Sjmallett pinout supports 'mirroring'. 4826215976Sjmallett To support a clamshell design, SW must preload 4827215976Sjmallett the MRSDAT[22:0] with the proper A[22:0] pin mapping 4828215976Sjmallett which is dependent on the 'selected' bunk/clam 4829215976Sjmallett (see also: DFA_MEMCFG0[BUNK_INIT] field). 4830215976Sjmallett NOTE: Care MUST BE TAKEN NOT to write to this register 4831215976Sjmallett within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1). 4832215976Sjmallett NOTE: This should only be written to a different value 4833215976Sjmallett during power-on SW initialization. */ 4834215976Sjmallett#else 4835215976Sjmallett uint64_t mrsdat : 23; 4836215976Sjmallett uint64_t reserved_23_63 : 41; 4837215976Sjmallett#endif 4838215976Sjmallett } s; 4839215976Sjmallett struct cvmx_dfa_memrld_s cn38xx; 4840215976Sjmallett struct cvmx_dfa_memrld_s cn38xxp2; 4841215976Sjmallett struct cvmx_dfa_memrld_s cn58xx; 4842215976Sjmallett struct cvmx_dfa_memrld_s cn58xxp1; 4843215976Sjmallett}; 4844215976Sjmalletttypedef union cvmx_dfa_memrld cvmx_dfa_memrld_t; 4845215976Sjmallett 4846215976Sjmallett/** 4847215976Sjmallett * cvmx_dfa_ncbctl 4848215976Sjmallett * 4849215976Sjmallett * DFA_NCBCTL = DFA NCB CTL Register 4850215976Sjmallett * 4851215976Sjmallett * Description: 4852215976Sjmallett */ 4853232812Sjmallettunion cvmx_dfa_ncbctl { 4854215976Sjmallett uint64_t u64; 4855232812Sjmallett struct cvmx_dfa_ncbctl_s { 4856232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4857215976Sjmallett uint64_t reserved_11_63 : 53; 4858215976Sjmallett uint64_t sbdnum : 5; /**< SBD Debug Entry# 4859215976Sjmallett For internal use only. (DFA Scoreboard debug) 4860215976Sjmallett Selects which one of 32 DFA Scoreboard entries is 4861215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 4862215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4863215976Sjmallett For internal use only. (DFA Scoreboard debug) 4864215976Sjmallett When written with a '1', the DFA Scoreboard Debug 4865215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 4866215976Sjmallett This allows SW to lock down the contents of the entire 4867215976Sjmallett SBD for a single instant in time. All subsequent reads 4868215976Sjmallett of the DFA scoreboard registers will return the data 4869215976Sjmallett from that instant in time. */ 4870215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4871215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4872215976Sjmallett NOTE: This should only be written to a different value 4873215976Sjmallett during power-on SW initialization. */ 4874215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4875215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4876215976Sjmallett NOTE: This should only be written to a different value 4877215976Sjmallett during power-on SW initialization. */ 4878215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4879215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4880215976Sjmallett NOTE: This should only be written to a different value 4881215976Sjmallett during power-on SW initialization. */ 4882215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4883215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4884215976Sjmallett NOTE: This should only be written to a different value 4885215976Sjmallett during power-on SW initialization. */ 4886215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 4887215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 4888215976Sjmallett NOTE: This should only be written to a different value 4889215976Sjmallett during power-on SW initialization. */ 4890215976Sjmallett#else 4891215976Sjmallett uint64_t imode : 1; 4892215976Sjmallett uint64_t qmode : 1; 4893215976Sjmallett uint64_t pmode : 1; 4894215976Sjmallett uint64_t dtmode : 1; 4895215976Sjmallett uint64_t dcmode : 1; 4896215976Sjmallett uint64_t sbdlck : 1; 4897215976Sjmallett uint64_t sbdnum : 5; 4898215976Sjmallett uint64_t reserved_11_63 : 53; 4899215976Sjmallett#endif 4900215976Sjmallett } s; 4901232812Sjmallett struct cvmx_dfa_ncbctl_cn38xx { 4902232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4903215976Sjmallett uint64_t reserved_10_63 : 54; 4904215976Sjmallett uint64_t sbdnum : 4; /**< SBD Debug Entry# 4905215976Sjmallett For internal use only. (DFA Scoreboard debug) 4906215976Sjmallett Selects which one of 16 DFA Scoreboard entries is 4907215976Sjmallett latched into the DFA_SBD_DBG[0-3] registers. */ 4908215976Sjmallett uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4909215976Sjmallett For internal use only. (DFA Scoreboard debug) 4910215976Sjmallett When written with a '1', the DFA Scoreboard Debug 4911215976Sjmallett registers (DFA_SBD_DBG[0-3]) are all locked down. 4912215976Sjmallett This allows SW to lock down the contents of the entire 4913215976Sjmallett SBD for a single instant in time. All subsequent reads 4914215976Sjmallett of the DFA scoreboard registers will return the data 4915215976Sjmallett from that instant in time. */ 4916215976Sjmallett uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4917215976Sjmallett DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4918215976Sjmallett NOTE: This should only be written to a different value 4919215976Sjmallett during power-on SW initialization. */ 4920215976Sjmallett uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4921215976Sjmallett DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4922215976Sjmallett NOTE: This should only be written to a different value 4923215976Sjmallett during power-on SW initialization. */ 4924215976Sjmallett uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4925215976Sjmallett (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4926215976Sjmallett NOTE: This should only be written to a different value 4927215976Sjmallett during power-on SW initialization. */ 4928215976Sjmallett uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4929215976Sjmallett (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4930215976Sjmallett NOTE: This should only be written to a different value 4931215976Sjmallett during power-on SW initialization. */ 4932215976Sjmallett uint64_t imode : 1; /**< NCB-Inbound Arbiter 4933215976Sjmallett (0=FP [LP=NRQ,HP=NRP], 1=RR) 4934215976Sjmallett NOTE: This should only be written to a different value 4935215976Sjmallett during power-on SW initialization. */ 4936215976Sjmallett#else 4937215976Sjmallett uint64_t imode : 1; 4938215976Sjmallett uint64_t qmode : 1; 4939215976Sjmallett uint64_t pmode : 1; 4940215976Sjmallett uint64_t dtmode : 1; 4941215976Sjmallett uint64_t dcmode : 1; 4942215976Sjmallett uint64_t sbdlck : 1; 4943215976Sjmallett uint64_t sbdnum : 4; 4944215976Sjmallett uint64_t reserved_10_63 : 54; 4945215976Sjmallett#endif 4946215976Sjmallett } cn38xx; 4947215976Sjmallett struct cvmx_dfa_ncbctl_cn38xx cn38xxp2; 4948215976Sjmallett struct cvmx_dfa_ncbctl_s cn58xx; 4949215976Sjmallett struct cvmx_dfa_ncbctl_s cn58xxp1; 4950215976Sjmallett}; 4951215976Sjmalletttypedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t; 4952215976Sjmallett 4953215976Sjmallett/** 4954215976Sjmallett * cvmx_dfa_pfc0_cnt 4955215976Sjmallett * 4956215976Sjmallett * DFA_PFC0_CNT = DFA Performance Counter \#0 4957215976Sjmallett * *FOR INTERNAL USE ONLY* 4958215976Sjmallett * Description: 4959215976Sjmallett */ 4960232812Sjmallettunion cvmx_dfa_pfc0_cnt { 4961215976Sjmallett uint64_t u64; 4962232812Sjmallett struct cvmx_dfa_pfc0_cnt_s { 4963232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4964215976Sjmallett uint64_t pfcnt0 : 64; /**< Performance Counter \#0 4965215976Sjmallett When DFA_PFC_GCTL[CNT0ENA]=1, the event selected 4966215976Sjmallett by DFA_PFC0_CTL[EVSEL] is counted. 4967215976Sjmallett See also DFA_PFC_GCTL[CNT0WCLR] and DFA_PFC_GCTL 4968215976Sjmallett [CNT0RCLR] for special clear count cases available 4969215976Sjmallett for SW data collection. */ 4970215976Sjmallett#else 4971215976Sjmallett uint64_t pfcnt0 : 64; 4972215976Sjmallett#endif 4973215976Sjmallett } s; 4974232812Sjmallett struct cvmx_dfa_pfc0_cnt_s cn61xx; 4975215976Sjmallett struct cvmx_dfa_pfc0_cnt_s cn63xx; 4976215976Sjmallett struct cvmx_dfa_pfc0_cnt_s cn63xxp1; 4977232812Sjmallett struct cvmx_dfa_pfc0_cnt_s cn66xx; 4978232812Sjmallett struct cvmx_dfa_pfc0_cnt_s cn68xx; 4979232812Sjmallett struct cvmx_dfa_pfc0_cnt_s cn68xxp1; 4980215976Sjmallett}; 4981215976Sjmalletttypedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t; 4982215976Sjmallett 4983215976Sjmallett/** 4984215976Sjmallett * cvmx_dfa_pfc0_ctl 4985215976Sjmallett * 4986215976Sjmallett * DFA_PFC0_CTL = DFA Performance Counter#0 Control 4987215976Sjmallett * *FOR INTERNAL USE ONLY* 4988215976Sjmallett * Description: 4989215976Sjmallett */ 4990232812Sjmallettunion cvmx_dfa_pfc0_ctl { 4991215976Sjmallett uint64_t u64; 4992232812Sjmallett struct cvmx_dfa_pfc0_ctl_s { 4993232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4994215976Sjmallett uint64_t reserved_14_63 : 50; 4995215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#0 Event Selector 4996215976Sjmallett // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph) 4997215976Sjmallett - 0: \#Total Cycles 4998215976Sjmallett - 1: \#LDNODE visits 4999215976Sjmallett - 2: \#SDNODE visits 5000215976Sjmallett - 3: \#DNODE visits (LD/SD) 5001215976Sjmallett - 4: \#LCNODE visits 5002215976Sjmallett - 5: \#SCNODE visits 5003215976Sjmallett - 6: \#CNODE visits (LC/SC) 5004215976Sjmallett - 7: \#LMNODE visits 5005215976Sjmallett - 8: \#SMNODE visits 5006215976Sjmallett - 9: \#MNODE visits (LM/SM) 5007215976Sjmallett - 10: \#MONODE visits 5008215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5009215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5010215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 5011215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5012215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5013215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 5014215976Sjmallett - 17: \#GWALK iterations STALLED - Packet data/Result Buffer 5015215976Sjmallett - 18: \#GWALK iterations NON-STALLED 5016215976Sjmallett - 19: \#CLOAD iterations 5017215976Sjmallett - 20: \#MLOAD iterations 5018215976Sjmallett [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 5019215976Sjmallett - 21: \#RWORD1+ writes 5020215976Sjmallett - 22: \#cycles Cluster is busy 5021215976Sjmallett - 23: \#GWALK Instructions 5022215976Sjmallett - 24: \#CLOAD Instructions 5023215976Sjmallett - 25: \#MLOAD Instructions 5024215976Sjmallett [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 5025215976Sjmallett - 26: \#GFREE Instructions 5026215976Sjmallett - 27-30: RESERVED 5027215976Sjmallett - 31: \# Node Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE,EDNODE] registers 5028215976Sjmallett //============================================================= 5029215976Sjmallett // Events [32-63] are used ONLY FOR PMODE=0(per-cluster DTE mode): 5030215976Sjmallett - 32: \#cycles a specific cluster-DTE remains active(valid state) 5031215976Sjmallett - 33: \#cycles a specific cluster-DTE waits for Memory Response Data 5032215976Sjmallett - 34: \#cycles a specific cluster-DTE waits in resource stall state 5033215976Sjmallett (waiting for packet data or result buffer space) 5034215976Sjmallett - 35: \#cycles a specific cluster-DTE waits in resource pending state 5035215976Sjmallett - 36-63: RESERVED 5036215976Sjmallett //============================================================= */ 5037215976Sjmallett uint64_t reserved_6_7 : 2; 5038215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#0 Cluster DTE Selector 5039215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5040215976Sjmallett is used to select/monitor the cluster's DTE# for all events 5041215976Sjmallett associated with Performance Counter#0. */ 5042215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#0 Cluster Selector 5043215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5044215976Sjmallett is used to select/monitor the cluster# for all events 5045215976Sjmallett associated with Performance Counter#0. */ 5046215976Sjmallett#else 5047215976Sjmallett uint64_t clnum : 2; 5048215976Sjmallett uint64_t cldte : 4; 5049215976Sjmallett uint64_t reserved_6_7 : 2; 5050215976Sjmallett uint64_t evsel : 6; 5051215976Sjmallett uint64_t reserved_14_63 : 50; 5052215976Sjmallett#endif 5053215976Sjmallett } s; 5054232812Sjmallett struct cvmx_dfa_pfc0_ctl_s cn61xx; 5055215976Sjmallett struct cvmx_dfa_pfc0_ctl_s cn63xx; 5056215976Sjmallett struct cvmx_dfa_pfc0_ctl_s cn63xxp1; 5057232812Sjmallett struct cvmx_dfa_pfc0_ctl_s cn66xx; 5058232812Sjmallett struct cvmx_dfa_pfc0_ctl_s cn68xx; 5059232812Sjmallett struct cvmx_dfa_pfc0_ctl_s cn68xxp1; 5060215976Sjmallett}; 5061215976Sjmalletttypedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t; 5062215976Sjmallett 5063215976Sjmallett/** 5064215976Sjmallett * cvmx_dfa_pfc1_cnt 5065215976Sjmallett * 5066215976Sjmallett * DFA_PFC1_CNT = DFA Performance Counter \#1 5067215976Sjmallett * *FOR INTERNAL USE ONLY* 5068215976Sjmallett * Description: 5069215976Sjmallett */ 5070232812Sjmallettunion cvmx_dfa_pfc1_cnt { 5071215976Sjmallett uint64_t u64; 5072232812Sjmallett struct cvmx_dfa_pfc1_cnt_s { 5073232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5074215976Sjmallett uint64_t pfcnt1 : 64; /**< Performance Counter \#1 5075215976Sjmallett When DFA_PFC_GCTL[CNT1ENA]=1, the event selected 5076215976Sjmallett by DFA_PFC1_CTL[EVSEL] is counted. 5077215976Sjmallett See also DFA_PFC_GCTL[CNT1WCLR] and DFA_PFC_GCTL 5078215976Sjmallett [CNT1RCLR] for special clear count cases available 5079215976Sjmallett for SW data collection. */ 5080215976Sjmallett#else 5081215976Sjmallett uint64_t pfcnt1 : 64; 5082215976Sjmallett#endif 5083215976Sjmallett } s; 5084232812Sjmallett struct cvmx_dfa_pfc1_cnt_s cn61xx; 5085215976Sjmallett struct cvmx_dfa_pfc1_cnt_s cn63xx; 5086215976Sjmallett struct cvmx_dfa_pfc1_cnt_s cn63xxp1; 5087232812Sjmallett struct cvmx_dfa_pfc1_cnt_s cn66xx; 5088232812Sjmallett struct cvmx_dfa_pfc1_cnt_s cn68xx; 5089232812Sjmallett struct cvmx_dfa_pfc1_cnt_s cn68xxp1; 5090215976Sjmallett}; 5091215976Sjmalletttypedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t; 5092215976Sjmallett 5093215976Sjmallett/** 5094215976Sjmallett * cvmx_dfa_pfc1_ctl 5095215976Sjmallett * 5096215976Sjmallett * DFA_PFC1_CTL = DFA Performance Counter#1 Control 5097215976Sjmallett * *FOR INTERNAL USE ONLY* 5098215976Sjmallett * Description: 5099215976Sjmallett */ 5100232812Sjmallettunion cvmx_dfa_pfc1_ctl { 5101215976Sjmallett uint64_t u64; 5102232812Sjmallett struct cvmx_dfa_pfc1_ctl_s { 5103232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5104215976Sjmallett uint64_t reserved_14_63 : 50; 5105215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#1 Event Selector 5106215976Sjmallett - 0: \#Cycles 5107215976Sjmallett - 1: \#LDNODE visits 5108215976Sjmallett - 2: \#SDNODE visits 5109215976Sjmallett - 3: \#DNODE visits (LD/SD) 5110215976Sjmallett - 4: \#LCNODE visits 5111215976Sjmallett - 5: \#SCNODE visits 5112215976Sjmallett - 6: \#CNODE visits (LC/SC) 5113215976Sjmallett - 7: \#LMNODE visits 5114215976Sjmallett - 8: \#SMNODE visits 5115215976Sjmallett - 9: \#MNODE visits (LM/SM) 5116215976Sjmallett - 10: \#MONODE visits 5117215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5118215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5119215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 5120215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5121215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5122215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 5123215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5124215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5125215976Sjmallett - 19: \#CLOAD DTE cycles 5126215976Sjmallett - 20: \#MLOAD DTE cycles 5127215976Sjmallett - 21: \#cycles waiting for Memory Response Data 5128215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5129215976Sjmallett - 23: \#cycles waiting in resource pending state 5130215976Sjmallett - 24: \#RWORD1+ writes 5131215976Sjmallett - 25: \#DTE-VLD cycles 5132215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5133215976Sjmallett - 27: \#GWALK Instructions 5134215976Sjmallett - 28: \#CLOAD Instructions 5135215976Sjmallett - 29: \#MLOAD Instructions 5136215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5137215976Sjmallett - 31: RESERVED 5138215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5139215976Sjmallett uint64_t reserved_6_7 : 2; 5140215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#1 Cluster DTE Selector 5141215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5142215976Sjmallett is used to select/monitor the cluster's DTE# for all events 5143215976Sjmallett associated with Performance Counter#1. */ 5144215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#1 Cluster Selector 5145215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5146215976Sjmallett is used to select/monitor the cluster# for all events 5147215976Sjmallett associated with Performance Counter#1. */ 5148215976Sjmallett#else 5149215976Sjmallett uint64_t clnum : 2; 5150215976Sjmallett uint64_t cldte : 4; 5151215976Sjmallett uint64_t reserved_6_7 : 2; 5152215976Sjmallett uint64_t evsel : 6; 5153215976Sjmallett uint64_t reserved_14_63 : 50; 5154215976Sjmallett#endif 5155215976Sjmallett } s; 5156232812Sjmallett struct cvmx_dfa_pfc1_ctl_s cn61xx; 5157215976Sjmallett struct cvmx_dfa_pfc1_ctl_s cn63xx; 5158215976Sjmallett struct cvmx_dfa_pfc1_ctl_s cn63xxp1; 5159232812Sjmallett struct cvmx_dfa_pfc1_ctl_s cn66xx; 5160232812Sjmallett struct cvmx_dfa_pfc1_ctl_s cn68xx; 5161232812Sjmallett struct cvmx_dfa_pfc1_ctl_s cn68xxp1; 5162215976Sjmallett}; 5163215976Sjmalletttypedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t; 5164215976Sjmallett 5165215976Sjmallett/** 5166215976Sjmallett * cvmx_dfa_pfc2_cnt 5167215976Sjmallett * 5168215976Sjmallett * DFA_PFC2_CNT = DFA Performance Counter \#2 5169215976Sjmallett * *FOR INTERNAL USE ONLY* 5170215976Sjmallett * Description: 5171215976Sjmallett */ 5172232812Sjmallettunion cvmx_dfa_pfc2_cnt { 5173215976Sjmallett uint64_t u64; 5174232812Sjmallett struct cvmx_dfa_pfc2_cnt_s { 5175232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5176215976Sjmallett uint64_t pfcnt2 : 64; /**< Performance Counter \#2 5177215976Sjmallett When DFA_PFC_GCTL[CNT2ENA]=1, the event selected 5178215976Sjmallett by DFA_PFC2_CTL[EVSEL] is counted. 5179215976Sjmallett See also DFA_PFC_GCTL[CNT2WCLR] and DFA_PFC_GCTL 5180215976Sjmallett [CNT2RCLR] for special clear count cases available 5181215976Sjmallett for SW data collection. */ 5182215976Sjmallett#else 5183215976Sjmallett uint64_t pfcnt2 : 64; 5184215976Sjmallett#endif 5185215976Sjmallett } s; 5186232812Sjmallett struct cvmx_dfa_pfc2_cnt_s cn61xx; 5187215976Sjmallett struct cvmx_dfa_pfc2_cnt_s cn63xx; 5188215976Sjmallett struct cvmx_dfa_pfc2_cnt_s cn63xxp1; 5189232812Sjmallett struct cvmx_dfa_pfc2_cnt_s cn66xx; 5190232812Sjmallett struct cvmx_dfa_pfc2_cnt_s cn68xx; 5191232812Sjmallett struct cvmx_dfa_pfc2_cnt_s cn68xxp1; 5192215976Sjmallett}; 5193215976Sjmalletttypedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t; 5194215976Sjmallett 5195215976Sjmallett/** 5196215976Sjmallett * cvmx_dfa_pfc2_ctl 5197215976Sjmallett * 5198215976Sjmallett * DFA_PFC2_CTL = DFA Performance Counter#2 Control 5199215976Sjmallett * *FOR INTERNAL USE ONLY* 5200215976Sjmallett * Description: 5201215976Sjmallett */ 5202232812Sjmallettunion cvmx_dfa_pfc2_ctl { 5203215976Sjmallett uint64_t u64; 5204232812Sjmallett struct cvmx_dfa_pfc2_ctl_s { 5205232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5206215976Sjmallett uint64_t reserved_14_63 : 50; 5207215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#2 Event Selector 5208215976Sjmallett - 0: \#Cycles 5209215976Sjmallett - 1: \#LDNODE visits 5210215976Sjmallett - 2: \#SDNODE visits 5211215976Sjmallett - 3: \#DNODE visits (LD/SD) 5212215976Sjmallett - 4: \#LCNODE visits 5213215976Sjmallett - 5: \#SCNODE visits 5214215976Sjmallett - 6: \#CNODE visits (LC/SC) 5215215976Sjmallett - 7: \#LMNODE visits 5216215976Sjmallett - 8: \#SMNODE visits 5217215976Sjmallett - 9: \#MNODE visits (LM/SM) 5218215976Sjmallett - 10: \#MONODE visits 5219215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5220215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5221215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 5222215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5223215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5224215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 5225215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5226215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5227215976Sjmallett - 19: \#CLOAD DTE cycles 5228215976Sjmallett - 20: \#MLOAD DTE cycles 5229215976Sjmallett - 21: \#cycles waiting for Memory Response Data 5230215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5231215976Sjmallett - 23: \#cycles waiting in resource pending state 5232215976Sjmallett - 24: \#RWORD1+ writes 5233215976Sjmallett - 25: \#DTE-VLD cycles 5234215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5235215976Sjmallett - 27: \#GWALK Instructions 5236215976Sjmallett - 28: \#CLOAD Instructions 5237215976Sjmallett - 29: \#MLOAD Instructions 5238215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5239215976Sjmallett - 31: RESERVED 5240215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5241215976Sjmallett uint64_t reserved_6_7 : 2; 5242215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#2 Cluster DTE Selector 5243215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5244215976Sjmallett is used to select/monitor the cluster's DTE# for all events 5245215976Sjmallett associated with Performance Counter#2. */ 5246215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#2 Cluster Selector 5247215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5248215976Sjmallett is used to select/monitor the cluster# for all events 5249215976Sjmallett associated with Performance Counter#2. */ 5250215976Sjmallett#else 5251215976Sjmallett uint64_t clnum : 2; 5252215976Sjmallett uint64_t cldte : 4; 5253215976Sjmallett uint64_t reserved_6_7 : 2; 5254215976Sjmallett uint64_t evsel : 6; 5255215976Sjmallett uint64_t reserved_14_63 : 50; 5256215976Sjmallett#endif 5257215976Sjmallett } s; 5258232812Sjmallett struct cvmx_dfa_pfc2_ctl_s cn61xx; 5259215976Sjmallett struct cvmx_dfa_pfc2_ctl_s cn63xx; 5260215976Sjmallett struct cvmx_dfa_pfc2_ctl_s cn63xxp1; 5261232812Sjmallett struct cvmx_dfa_pfc2_ctl_s cn66xx; 5262232812Sjmallett struct cvmx_dfa_pfc2_ctl_s cn68xx; 5263232812Sjmallett struct cvmx_dfa_pfc2_ctl_s cn68xxp1; 5264215976Sjmallett}; 5265215976Sjmalletttypedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t; 5266215976Sjmallett 5267215976Sjmallett/** 5268215976Sjmallett * cvmx_dfa_pfc3_cnt 5269215976Sjmallett * 5270215976Sjmallett * DFA_PFC3_CNT = DFA Performance Counter \#3 5271215976Sjmallett * *FOR INTERNAL USE ONLY* 5272215976Sjmallett * Description: 5273215976Sjmallett */ 5274232812Sjmallettunion cvmx_dfa_pfc3_cnt { 5275215976Sjmallett uint64_t u64; 5276232812Sjmallett struct cvmx_dfa_pfc3_cnt_s { 5277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5278215976Sjmallett uint64_t pfcnt3 : 64; /**< Performance Counter \#3 5279215976Sjmallett When DFA_PFC_GCTL[CNT3ENA]=1, the event selected 5280215976Sjmallett by DFA_PFC3_CTL[EVSEL] is counted. 5281215976Sjmallett See also DFA_PFC_GCTL[CNT3WCLR] and DFA_PFC_GCTL 5282215976Sjmallett [CNT3RCLR] for special clear count cases available 5283215976Sjmallett for SW data collection. */ 5284215976Sjmallett#else 5285215976Sjmallett uint64_t pfcnt3 : 64; 5286215976Sjmallett#endif 5287215976Sjmallett } s; 5288232812Sjmallett struct cvmx_dfa_pfc3_cnt_s cn61xx; 5289215976Sjmallett struct cvmx_dfa_pfc3_cnt_s cn63xx; 5290215976Sjmallett struct cvmx_dfa_pfc3_cnt_s cn63xxp1; 5291232812Sjmallett struct cvmx_dfa_pfc3_cnt_s cn66xx; 5292232812Sjmallett struct cvmx_dfa_pfc3_cnt_s cn68xx; 5293232812Sjmallett struct cvmx_dfa_pfc3_cnt_s cn68xxp1; 5294215976Sjmallett}; 5295215976Sjmalletttypedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t; 5296215976Sjmallett 5297215976Sjmallett/** 5298215976Sjmallett * cvmx_dfa_pfc3_ctl 5299215976Sjmallett * 5300215976Sjmallett * DFA_PFC3_CTL = DFA Performance Counter#3 Control 5301215976Sjmallett * *FOR INTERNAL USE ONLY* 5302215976Sjmallett * Description: 5303215976Sjmallett */ 5304232812Sjmallettunion cvmx_dfa_pfc3_ctl { 5305215976Sjmallett uint64_t u64; 5306232812Sjmallett struct cvmx_dfa_pfc3_ctl_s { 5307232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5308215976Sjmallett uint64_t reserved_14_63 : 50; 5309215976Sjmallett uint64_t evsel : 6; /**< Performance Counter#3 Event Selector 5310215976Sjmallett - 0: \#Cycles 5311215976Sjmallett - 1: \#LDNODE visits 5312215976Sjmallett - 2: \#SDNODE visits 5313215976Sjmallett - 3: \#DNODE visits (LD/SD) 5314215976Sjmallett - 4: \#LCNODE visits 5315215976Sjmallett - 5: \#SCNODE visits 5316215976Sjmallett - 6: \#CNODE visits (LC/SC) 5317215976Sjmallett - 7: \#LMNODE visits 5318215976Sjmallett - 8: \#SMNODE visits 5319215976Sjmallett - 9: \#MNODE visits (LM/SM) 5320215976Sjmallett - 10: \#MONODE visits 5321215976Sjmallett - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5322215976Sjmallett - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5323215976Sjmallett - 13: \#MEMORY visits (MNODE+MONODE) 5324215976Sjmallett - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5325215976Sjmallett - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5326215976Sjmallett - 16: \#RESCANs detected (occur when HASH collision is detected) 5327215976Sjmallett - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5328215976Sjmallett - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5329215976Sjmallett - 19: \#CLOAD DTE cycles 5330215976Sjmallett - 20: \#MLOAD DTE cycles 5331215976Sjmallett - 21: \#cycles waiting for Memory Response Data 5332215976Sjmallett - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5333215976Sjmallett - 23: \#cycles waiting in resource pending state 5334215976Sjmallett - 24: \#RWORD1+ writes 5335215976Sjmallett - 25: \#DTE-VLD cycles 5336215976Sjmallett - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5337215976Sjmallett - 27: \#GWALK Instructions 5338215976Sjmallett - 28: \#CLOAD Instructions 5339215976Sjmallett - 29: \#MLOAD Instructions 5340215976Sjmallett - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5341215976Sjmallett - 31: RESERVED 5342215976Sjmallett - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5343215976Sjmallett uint64_t reserved_6_7 : 2; 5344215976Sjmallett uint64_t cldte : 4; /**< Performance Counter#3 Cluster DTE Selector 5345215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5346215976Sjmallett is used to select/monitor the cluster's DTE# for all events 5347215976Sjmallett associated with Performance Counter#3. */ 5348215976Sjmallett uint64_t clnum : 2; /**< Performance Counter#3 Cluster Selector 5349215976Sjmallett When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5350215976Sjmallett is used to select/monitor the cluster# for all events 5351215976Sjmallett associated with Performance Counter#3. */ 5352215976Sjmallett#else 5353215976Sjmallett uint64_t clnum : 2; 5354215976Sjmallett uint64_t cldte : 4; 5355215976Sjmallett uint64_t reserved_6_7 : 2; 5356215976Sjmallett uint64_t evsel : 6; 5357215976Sjmallett uint64_t reserved_14_63 : 50; 5358215976Sjmallett#endif 5359215976Sjmallett } s; 5360232812Sjmallett struct cvmx_dfa_pfc3_ctl_s cn61xx; 5361215976Sjmallett struct cvmx_dfa_pfc3_ctl_s cn63xx; 5362215976Sjmallett struct cvmx_dfa_pfc3_ctl_s cn63xxp1; 5363232812Sjmallett struct cvmx_dfa_pfc3_ctl_s cn66xx; 5364232812Sjmallett struct cvmx_dfa_pfc3_ctl_s cn68xx; 5365232812Sjmallett struct cvmx_dfa_pfc3_ctl_s cn68xxp1; 5366215976Sjmallett}; 5367215976Sjmalletttypedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t; 5368215976Sjmallett 5369215976Sjmallett/** 5370215976Sjmallett * cvmx_dfa_pfc_gctl 5371215976Sjmallett * 5372215976Sjmallett * DFA_PFC_GCTL = DFA Performance Counter Global Control 5373215976Sjmallett * *FOR INTERNAL USE ONLY* 5374215976Sjmallett * Description: 5375215976Sjmallett */ 5376232812Sjmallettunion cvmx_dfa_pfc_gctl { 5377215976Sjmallett uint64_t u64; 5378232812Sjmallett struct cvmx_dfa_pfc_gctl_s { 5379232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5380215976Sjmallett uint64_t reserved_29_63 : 35; 5381215976Sjmallett uint64_t vgid : 8; /**< Virtual Graph Id# 5382215976Sjmallett When PMODE=1(per-graph selector), this field is used 5383215976Sjmallett to select/monitor only those events which are 5384215976Sjmallett associated with this selected VGID(virtual graph ID). 5385215976Sjmallett This field is used globally across all four performance 5386215976Sjmallett counters. 5387215976Sjmallett IMPNOTE: I implemented a global VGID across all 4 performance 5388215976Sjmallett counters to save wires/area. */ 5389215976Sjmallett uint64_t pmode : 1; /**< Select Mode 5390215976Sjmallett - 0: Events are selected on a per-cluster DTE# (CLNUM/CLDTE) 5391215976Sjmallett DFA_PFCx_CTL[CLNUM,CLDTE] specifies the cluster-DTE for 5392215976Sjmallett each 1(of 4) performance counters. 5393215976Sjmallett - 1: Events are selected on a per-graph basis (VGID=virtual Graph ID). 5394215976Sjmallett NOTE: Only EVSEL=[0...31] can be used in conjunction with PMODE=1. 5395215976Sjmallett DFA_PFC_GCTL[VGID] specifies the Virtual graph ID used across 5396215976Sjmallett all four performance counters. */ 5397215976Sjmallett uint64_t ednode : 2; /**< Ending DNODE Selector 5398215976Sjmallett When ENODE=0/1(*DNODE), this field is used to further 5399215976Sjmallett specify the Ending DNODE transition sub-type: 5400215976Sjmallett - 0: ALL DNODE sub-types 5401215976Sjmallett - 1: ->D2e (explicit DNODE transition node-arc alone transitions to DNODE) 5402215976Sjmallett - 2: ->D2i (implicit DNODE transition:arc-present triggers transition) 5403215976Sjmallett - 3: ->D1r (rescan DNODE transition) */ 5404215976Sjmallett uint64_t enode : 3; /**< Ending Node Selector 5405215976Sjmallett When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the ENODE 5406215976Sjmallett field is used to select Ending Node, and the SNODE 5407215976Sjmallett field is used to select the Starting Node. 5408215976Sjmallett - 0: LDNODE 5409215976Sjmallett - 1: SDNODE 5410215976Sjmallett - 2: LCNODE 5411215976Sjmallett - 3: SCNODE 5412215976Sjmallett - 4: LMNODE 5413215976Sjmallett - 5: SMNODE 5414215976Sjmallett - 6: MONODE 5415215976Sjmallett - 7: RESERVED */ 5416215976Sjmallett uint64_t snode : 3; /**< Starting Node Selector 5417215976Sjmallett When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the SNODE 5418215976Sjmallett field is used to select Starting Node, and the ENODE 5419215976Sjmallett field is used to select the Ending Node. 5420215976Sjmallett - 0: LDNODE 5421215976Sjmallett - 1: SDNODE 5422215976Sjmallett - 2: LCNODE 5423215976Sjmallett - 3: SCNODE 5424215976Sjmallett - 4: LMNODE 5425215976Sjmallett - 5: SMNODE 5426215976Sjmallett - 6: MONODE 5427215976Sjmallett - 7: RESERVED */ 5428215976Sjmallett uint64_t cnt3rclr : 1; /**< Performance Counter \#3 Read Clear 5429215976Sjmallett If this bit is set, CSR reads to the DFA_PFC3_CNT 5430215976Sjmallett will clear the count value. This allows SW to maintain 5431215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 5432215976Sjmallett uint64_t cnt2rclr : 1; /**< Performance Counter \#2 Read Clear 5433215976Sjmallett If this bit is set, CSR reads to the DFA_PFC2_CNT 5434215976Sjmallett will clear the count value. This allows SW to maintain 5435215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 5436215976Sjmallett uint64_t cnt1rclr : 1; /**< Performance Counter \#1 Read Clear 5437215976Sjmallett If this bit is set, CSR reads to the DFA_PFC1_CNT 5438215976Sjmallett will clear the count value. This allows SW to maintain 5439215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 5440215976Sjmallett uint64_t cnt0rclr : 1; /**< Performance Counter \#0 Read Clear 5441215976Sjmallett If this bit is set, CSR reads to the DFA_PFC0_CNT 5442215976Sjmallett will clear the count value. This allows SW to maintain 5443215976Sjmallett 'cumulative' counters to avoid HW wraparound. */ 5444215976Sjmallett uint64_t cnt3wclr : 1; /**< Performance Counter \#3 Write Clear 5445215976Sjmallett If this bit is set, CSR writes to the DFA_PFC3_CNT 5446215976Sjmallett will clear the count value. 5447215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC3_CNT 5448215976Sjmallett will continue the count from the written value. */ 5449215976Sjmallett uint64_t cnt2wclr : 1; /**< Performance Counter \#2 Write Clear 5450215976Sjmallett If this bit is set, CSR writes to the DFA_PFC2_CNT 5451215976Sjmallett will clear the count value. 5452215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC2_CNT 5453215976Sjmallett will continue the count from the written value. */ 5454215976Sjmallett uint64_t cnt1wclr : 1; /**< Performance Counter \#1 Write Clear 5455215976Sjmallett If this bit is set, CSR writes to the DFA_PFC1_CNT 5456215976Sjmallett will clear the count value. 5457215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC1_CNT 5458215976Sjmallett will continue the count from the written value. */ 5459215976Sjmallett uint64_t cnt0wclr : 1; /**< Performance Counter \#0 Write Clear 5460215976Sjmallett If this bit is set, CSR writes to the DFA_PFC0_CNT 5461215976Sjmallett will clear the count value. 5462215976Sjmallett If this bit is clear, CSR writes to the DFA_PFC0_CNT 5463215976Sjmallett will continue the count from the written value. */ 5464215976Sjmallett uint64_t cnt3ena : 1; /**< Performance Counter 3 Enable 5465215976Sjmallett When this bit is set, the performance counter \#3 5466215976Sjmallett is enabled. */ 5467215976Sjmallett uint64_t cnt2ena : 1; /**< Performance Counter 2 Enable 5468215976Sjmallett When this bit is set, the performance counter \#2 5469215976Sjmallett is enabled. */ 5470215976Sjmallett uint64_t cnt1ena : 1; /**< Performance Counter 1 Enable 5471215976Sjmallett When this bit is set, the performance counter \#1 5472215976Sjmallett is enabled. */ 5473215976Sjmallett uint64_t cnt0ena : 1; /**< Performance Counter 0 Enable 5474215976Sjmallett When this bit is set, the performance counter \#0 5475215976Sjmallett is enabled. */ 5476215976Sjmallett#else 5477215976Sjmallett uint64_t cnt0ena : 1; 5478215976Sjmallett uint64_t cnt1ena : 1; 5479215976Sjmallett uint64_t cnt2ena : 1; 5480215976Sjmallett uint64_t cnt3ena : 1; 5481215976Sjmallett uint64_t cnt0wclr : 1; 5482215976Sjmallett uint64_t cnt1wclr : 1; 5483215976Sjmallett uint64_t cnt2wclr : 1; 5484215976Sjmallett uint64_t cnt3wclr : 1; 5485215976Sjmallett uint64_t cnt0rclr : 1; 5486215976Sjmallett uint64_t cnt1rclr : 1; 5487215976Sjmallett uint64_t cnt2rclr : 1; 5488215976Sjmallett uint64_t cnt3rclr : 1; 5489215976Sjmallett uint64_t snode : 3; 5490215976Sjmallett uint64_t enode : 3; 5491215976Sjmallett uint64_t ednode : 2; 5492215976Sjmallett uint64_t pmode : 1; 5493215976Sjmallett uint64_t vgid : 8; 5494215976Sjmallett uint64_t reserved_29_63 : 35; 5495215976Sjmallett#endif 5496215976Sjmallett } s; 5497232812Sjmallett struct cvmx_dfa_pfc_gctl_s cn61xx; 5498215976Sjmallett struct cvmx_dfa_pfc_gctl_s cn63xx; 5499215976Sjmallett struct cvmx_dfa_pfc_gctl_s cn63xxp1; 5500232812Sjmallett struct cvmx_dfa_pfc_gctl_s cn66xx; 5501232812Sjmallett struct cvmx_dfa_pfc_gctl_s cn68xx; 5502232812Sjmallett struct cvmx_dfa_pfc_gctl_s cn68xxp1; 5503215976Sjmallett}; 5504215976Sjmalletttypedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t; 5505215976Sjmallett 5506215976Sjmallett/** 5507215976Sjmallett * cvmx_dfa_rodt_comp_ctl 5508215976Sjmallett * 5509215976Sjmallett * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination") 5510215976Sjmallett * 5511215976Sjmallett */ 5512232812Sjmallettunion cvmx_dfa_rodt_comp_ctl { 5513215976Sjmallett uint64_t u64; 5514232812Sjmallett struct cvmx_dfa_rodt_comp_ctl_s { 5515232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5516215976Sjmallett uint64_t reserved_17_63 : 47; 5517215976Sjmallett uint64_t enable : 1; /**< Read On Die Termination Enable 5518215976Sjmallett (0=disable, 1=enable) */ 5519215976Sjmallett uint64_t reserved_12_15 : 4; 5520215976Sjmallett uint64_t nctl : 4; /**< Compensation control bits */ 5521215976Sjmallett uint64_t reserved_5_7 : 3; 5522215976Sjmallett uint64_t pctl : 5; /**< Compensation control bits */ 5523215976Sjmallett#else 5524215976Sjmallett uint64_t pctl : 5; 5525215976Sjmallett uint64_t reserved_5_7 : 3; 5526215976Sjmallett uint64_t nctl : 4; 5527215976Sjmallett uint64_t reserved_12_15 : 4; 5528215976Sjmallett uint64_t enable : 1; 5529215976Sjmallett uint64_t reserved_17_63 : 47; 5530215976Sjmallett#endif 5531215976Sjmallett } s; 5532215976Sjmallett struct cvmx_dfa_rodt_comp_ctl_s cn58xx; 5533215976Sjmallett struct cvmx_dfa_rodt_comp_ctl_s cn58xxp1; 5534215976Sjmallett}; 5535215976Sjmalletttypedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t; 5536215976Sjmallett 5537215976Sjmallett/** 5538215976Sjmallett * cvmx_dfa_sbd_dbg0 5539215976Sjmallett * 5540215976Sjmallett * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register 5541215976Sjmallett * 5542215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5543215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5544215976Sjmallett * CSR read. 5545215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5546215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5547215976Sjmallett * instruction. 5548215976Sjmallett */ 5549232812Sjmallettunion cvmx_dfa_sbd_dbg0 { 5550215976Sjmallett uint64_t u64; 5551232812Sjmallett struct cvmx_dfa_sbd_dbg0_s { 5552232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5553215976Sjmallett uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 5554215976Sjmallett For internal use only! (DFA Scoreboard Debug) 5555215976Sjmallett [63:40] rptr[26:3]: Result Base Pointer 5556215976Sjmallett [39:24] rwcnt[15:0] Cumulative Result Write Counter 5557215976Sjmallett [23] lastgrdrsp: Last Gather-Rd Response 5558215976Sjmallett [22] wtgrdrsp: Waiting Gather-Rd Response 5559215976Sjmallett [21] wtgrdreq: Waiting for Gather-Rd Issue 5560215976Sjmallett [20] glvld: GLPTR/GLCNT Valid 5561215976Sjmallett [19] cmpmark: Completion Marked Node Detected 5562215976Sjmallett [18:17] cmpcode[1:0]: Completion Code 5563215976Sjmallett [0=PDGONE/1=PERR/2=RFULL/3=TERM] 5564215976Sjmallett [16] cmpdet: Completion Detected 5565215976Sjmallett [15] wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp 5566215976Sjmallett [14] wtlastwrcmtrsp: Waiting for LAST RESULT 5567215976Sjmallett RWrCmtRsp 5568215976Sjmallett [13] hdrwrreq: Waiting for HDR RWrReq 5569215976Sjmallett [12] wtrwrreq: Waiting for RWrReq 5570215976Sjmallett [11] wtwqwrreq: Waiting for WQWrReq issue 5571215976Sjmallett [10] lastprdrspeot: Last Packet-Rd Response 5572215976Sjmallett [9] lastprdrsp: Last Packet-Rd Response 5573215976Sjmallett [8] wtprdrsp: Waiting for PRdRsp EOT 5574215976Sjmallett [7] wtprdreq: Waiting for PRdReq Issue 5575215976Sjmallett [6] lastpdvld: PDPTR/PDLEN Valid 5576215976Sjmallett [5] pdvld: Packet Data Valid 5577215976Sjmallett [4] wqvld: WQVLD 5578215976Sjmallett [3] wqdone: WorkQueue Done condition 5579215976Sjmallett a) WQWrReq issued(for WQPTR<>0) OR 5580215976Sjmallett b) HDR RWrCmtRsp completed) 5581215976Sjmallett [2] rwstf: Resultant write STF/P Mode 5582215976Sjmallett [1] pdldt: Packet-Data LDT mode 5583215976Sjmallett [0] gmode: Gather-Mode */ 5584215976Sjmallett#else 5585215976Sjmallett uint64_t sbd0 : 64; 5586215976Sjmallett#endif 5587215976Sjmallett } s; 5588215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn31xx; 5589215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn38xx; 5590215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn38xxp2; 5591215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn58xx; 5592215976Sjmallett struct cvmx_dfa_sbd_dbg0_s cn58xxp1; 5593215976Sjmallett}; 5594215976Sjmalletttypedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t; 5595215976Sjmallett 5596215976Sjmallett/** 5597215976Sjmallett * cvmx_dfa_sbd_dbg1 5598215976Sjmallett * 5599215976Sjmallett * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register 5600215976Sjmallett * 5601215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5602215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5603215976Sjmallett * CSR read. 5604215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5605215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5606215976Sjmallett * instruction. 5607215976Sjmallett */ 5608232812Sjmallettunion cvmx_dfa_sbd_dbg1 { 5609215976Sjmallett uint64_t u64; 5610232812Sjmallett struct cvmx_dfa_sbd_dbg1_s { 5611232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5612215976Sjmallett uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 5613215976Sjmallett For internal use only! (DFA Scoreboard Debug) 5614215976Sjmallett [63:61] wqptr[35:33]: Work Queue Pointer 5615215976Sjmallett [60:52] rptr[35:27]: Result Base Pointer 5616215976Sjmallett [51:16] pdptr[35:0]: Packet Data Pointer 5617215976Sjmallett [15:0] pdcnt[15:0]: Packet Data Counter */ 5618215976Sjmallett#else 5619215976Sjmallett uint64_t sbd1 : 64; 5620215976Sjmallett#endif 5621215976Sjmallett } s; 5622215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn31xx; 5623215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn38xx; 5624215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn38xxp2; 5625215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn58xx; 5626215976Sjmallett struct cvmx_dfa_sbd_dbg1_s cn58xxp1; 5627215976Sjmallett}; 5628215976Sjmalletttypedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t; 5629215976Sjmallett 5630215976Sjmallett/** 5631215976Sjmallett * cvmx_dfa_sbd_dbg2 5632215976Sjmallett * 5633215976Sjmallett * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register 5634215976Sjmallett * 5635215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5636215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5637215976Sjmallett * CSR read. 5638215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5639215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5640215976Sjmallett * instruction. 5641215976Sjmallett */ 5642232812Sjmallettunion cvmx_dfa_sbd_dbg2 { 5643215976Sjmallett uint64_t u64; 5644232812Sjmallett struct cvmx_dfa_sbd_dbg2_s { 5645232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5646215976Sjmallett uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 5647215976Sjmallett [63:49] wqptr[17:3]: Work Queue Pointer 5648215976Sjmallett [48:16] rwptr[35:3]: Result Write Pointer 5649215976Sjmallett [15:0] prwcnt[15:0]: Pending Result Write Counter */ 5650215976Sjmallett#else 5651215976Sjmallett uint64_t sbd2 : 64; 5652215976Sjmallett#endif 5653215976Sjmallett } s; 5654215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn31xx; 5655215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn38xx; 5656215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn38xxp2; 5657215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn58xx; 5658215976Sjmallett struct cvmx_dfa_sbd_dbg2_s cn58xxp1; 5659215976Sjmallett}; 5660215976Sjmalletttypedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t; 5661215976Sjmallett 5662215976Sjmallett/** 5663215976Sjmallett * cvmx_dfa_sbd_dbg3 5664215976Sjmallett * 5665215976Sjmallett * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register 5666215976Sjmallett * 5667215976Sjmallett * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5668215976Sjmallett * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5669215976Sjmallett * CSR read. 5670215976Sjmallett * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5671215976Sjmallett * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5672215976Sjmallett * instruction. 5673215976Sjmallett */ 5674232812Sjmallettunion cvmx_dfa_sbd_dbg3 { 5675215976Sjmallett uint64_t u64; 5676232812Sjmallett struct cvmx_dfa_sbd_dbg3_s { 5677232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5678215976Sjmallett uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 5679215976Sjmallett [63:49] wqptr[32:18]: Work Queue Pointer 5680215976Sjmallett [48:16] glptr[35:3]: Gather List Pointer 5681215976Sjmallett [15:0] glcnt[15:0]: Gather List Counter */ 5682215976Sjmallett#else 5683215976Sjmallett uint64_t sbd3 : 64; 5684215976Sjmallett#endif 5685215976Sjmallett } s; 5686215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn31xx; 5687215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn38xx; 5688215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn38xxp2; 5689215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn58xx; 5690215976Sjmallett struct cvmx_dfa_sbd_dbg3_s cn58xxp1; 5691215976Sjmallett}; 5692215976Sjmalletttypedef union cvmx_dfa_sbd_dbg3 cvmx_dfa_sbd_dbg3_t; 5693215976Sjmallett 5694215976Sjmallett#endif 5695