1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Configuration and status register (CSR) address and type definitions for 50210284Sjmallett * Octoen. 51210284Sjmallett * 52232812Sjmallett * <hr>$Revision: 70030 $<hr> 53210284Sjmallett * 54210284Sjmallett */ 55210284Sjmallett#ifndef __CVMX_CSR_H__ 56210284Sjmallett#define __CVMX_CSR_H__ 57210284Sjmallett 58210284Sjmallett#ifndef CVMX_ENABLE_CSR_ADDRESS_CHECKING 59210284Sjmallett#define CVMX_ENABLE_CSR_ADDRESS_CHECKING 0 60210284Sjmallett#endif 61210284Sjmallett 62210284Sjmallett#include "cvmx-platform.h" 63210284Sjmallett#include "cvmx-csr-enums.h" 64210284Sjmallett#include "cvmx-csr-typedefs.h" 65210284Sjmallett 66210284Sjmallett/* Map the HW names to the SDK historical names */ 67210284Sjmalletttypedef cvmx_ciu_intx_en1_t cvmx_ciu_int1_t; 68210284Sjmalletttypedef cvmx_ciu_intx_sum0_t cvmx_ciu_intx0_t; 69210284Sjmalletttypedef cvmx_ciu_mbox_setx_t cvmx_ciu_mbox_t; 70210284Sjmalletttypedef cvmx_fpa_fpfx_marks_t cvmx_fpa_fpf_marks_t; 71210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que0_page_index_t; 72210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que1_page_index_t; 73210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que2_page_index_t; 74210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que3_page_index_t; 75210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que4_page_index_t; 76210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que5_page_index_t; 77210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que6_page_index_t; 78210284Sjmalletttypedef cvmx_fpa_quex_page_index_t cvmx_fpa_que7_page_index_t; 79210284Sjmalletttypedef cvmx_ipd_1st_mbuff_skip_t cvmx_ipd_mbuff_first_skip_t; 80210284Sjmalletttypedef cvmx_ipd_1st_next_ptr_back_t cvmx_ipd_first_next_ptr_back_t; 81210284Sjmalletttypedef cvmx_ipd_packet_mbuff_size_t cvmx_ipd_mbuff_size_t; 82210284Sjmalletttypedef cvmx_ipd_qosx_red_marks_t cvmx_ipd_qos_red_marks_t; 83210284Sjmalletttypedef cvmx_ipd_wqe_fpa_queue_t cvmx_ipd_wqe_fpa_pool_t; 84210284Sjmalletttypedef cvmx_l2c_pfcx_t cvmx_l2c_pfc0_t; 85210284Sjmalletttypedef cvmx_l2c_pfcx_t cvmx_l2c_pfc1_t; 86210284Sjmalletttypedef cvmx_l2c_pfcx_t cvmx_l2c_pfc2_t; 87210284Sjmalletttypedef cvmx_l2c_pfcx_t cvmx_l2c_pfc3_t; 88210284Sjmalletttypedef cvmx_lmcx_bist_ctl_t cvmx_lmc_bist_ctl_t; 89210284Sjmalletttypedef cvmx_lmcx_bist_result_t cvmx_lmc_bist_result_t; 90210284Sjmalletttypedef cvmx_lmcx_comp_ctl_t cvmx_lmc_comp_ctl_t; 91210284Sjmalletttypedef cvmx_lmcx_ctl_t cvmx_lmc_ctl_t; 92210284Sjmalletttypedef cvmx_lmcx_ctl1_t cvmx_lmc_ctl1_t; 93210284Sjmalletttypedef cvmx_lmcx_dclk_cnt_hi_t cvmx_lmc_dclk_cnt_hi_t; 94210284Sjmalletttypedef cvmx_lmcx_dclk_cnt_lo_t cvmx_lmc_dclk_cnt_lo_t; 95210284Sjmalletttypedef cvmx_lmcx_dclk_ctl_t cvmx_lmc_dclk_ctl_t; 96210284Sjmalletttypedef cvmx_lmcx_ddr2_ctl_t cvmx_lmc_ddr2_ctl_t; 97210284Sjmalletttypedef cvmx_lmcx_delay_cfg_t cvmx_lmc_delay_cfg_t; 98210284Sjmalletttypedef cvmx_lmcx_dll_ctl_t cvmx_lmc_dll_ctl_t; 99210284Sjmalletttypedef cvmx_lmcx_dual_memcfg_t cvmx_lmc_dual_memcfg_t; 100210284Sjmalletttypedef cvmx_lmcx_ecc_synd_t cvmx_lmc_ecc_synd_t; 101210284Sjmalletttypedef cvmx_lmcx_fadr_t cvmx_lmc_fadr_t; 102210284Sjmalletttypedef cvmx_lmcx_ifb_cnt_hi_t cvmx_lmc_ifb_cnt_hi_t; 103210284Sjmalletttypedef cvmx_lmcx_ifb_cnt_lo_t cvmx_lmc_ifb_cnt_lo_t; 104210284Sjmalletttypedef cvmx_lmcx_mem_cfg0_t cvmx_lmc_mem_cfg0_t; 105210284Sjmalletttypedef cvmx_lmcx_mem_cfg1_t cvmx_lmc_mem_cfg1_t; 106210284Sjmalletttypedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_odt_ctl_t; 107210284Sjmalletttypedef cvmx_lmcx_ops_cnt_hi_t cvmx_lmc_ops_cnt_hi_t; 108210284Sjmalletttypedef cvmx_lmcx_ops_cnt_lo_t cvmx_lmc_ops_cnt_lo_t; 109210284Sjmalletttypedef cvmx_lmcx_pll_bwctl_t cvmx_lmc_pll_bwctl_t; 110210284Sjmalletttypedef cvmx_lmcx_pll_ctl_t cvmx_lmc_pll_ctl_t; 111210284Sjmalletttypedef cvmx_lmcx_pll_status_t cvmx_lmc_pll_status_t; 112210284Sjmalletttypedef cvmx_lmcx_read_level_ctl_t cvmx_lmc_read_level_ctl_t; 113210284Sjmalletttypedef cvmx_lmcx_read_level_dbg_t cvmx_lmc_read_level_dbg_t; 114210284Sjmalletttypedef cvmx_lmcx_read_level_rankx_t cvmx_lmc_read_level_rankx_t; 115210284Sjmalletttypedef cvmx_lmcx_rodt_comp_ctl_t cvmx_lmc_rodt_comp_ctl_t; 116210284Sjmalletttypedef cvmx_lmcx_rodt_ctl_t cvmx_lmc_rodt_ctl_t; 117210284Sjmalletttypedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_wodt_ctl_t; 118210284Sjmalletttypedef cvmx_lmcx_wodt_ctl0_t cvmx_lmc_wodt_ctl0_t; 119210284Sjmalletttypedef cvmx_lmcx_wodt_ctl1_t cvmx_lmc_wodt_ctl1_t; 120210284Sjmalletttypedef cvmx_mio_boot_reg_cfgx_t cvmx_mio_boot_reg_cfg0_t; 121210284Sjmalletttypedef cvmx_mio_boot_reg_timx_t cvmx_mio_boot_reg_tim0_t; 122210284Sjmalletttypedef cvmx_mio_twsx_int_t cvmx_mio_tws_int_t; 123210284Sjmalletttypedef cvmx_mio_twsx_sw_twsi_t cvmx_mio_tws_sw_twsi_t; 124210284Sjmalletttypedef cvmx_mio_twsx_sw_twsi_ext_t cvmx_mio_tws_sw_twsi_ext_t; 125210284Sjmalletttypedef cvmx_mio_twsx_twsi_sw_t cvmx_mio_tws_twsi_sw_t; 126210284Sjmalletttypedef cvmx_npi_base_addr_inputx_t cvmx_npi_base_addr_input_t; 127210284Sjmalletttypedef cvmx_npi_base_addr_outputx_t cvmx_npi_base_addr_output_t; 128210284Sjmalletttypedef cvmx_npi_buff_size_outputx_t cvmx_npi_buff_size_output_t; 129210284Sjmalletttypedef cvmx_npi_dma_highp_counts_t cvmx_npi_dma_counts_t; 130210284Sjmalletttypedef cvmx_npi_dma_highp_naddr_t cvmx_npi_dma_naddr_t; 131210284Sjmalletttypedef cvmx_npi_highp_dbell_t cvmx_npi_dbell_t; 132210284Sjmalletttypedef cvmx_npi_highp_ibuff_saddr_t cvmx_npi_dma_ibuff_saddr_t; 133210284Sjmalletttypedef cvmx_npi_mem_access_subidx_t cvmx_npi_mem_access_subid_t; 134210284Sjmalletttypedef cvmx_npi_num_desc_outputx_t cvmx_npi_num_desc_output_t; 135210284Sjmalletttypedef cvmx_npi_px_dbpair_addr_t cvmx_npi_dbpair_addr_t; 136210284Sjmalletttypedef cvmx_npi_px_instr_addr_t cvmx_npi_instr_addr_t; 137210284Sjmalletttypedef cvmx_npi_px_instr_cnts_t cvmx_npi_instr_cnts_t; 138210284Sjmalletttypedef cvmx_npi_px_pair_cnts_t cvmx_npi_pair_cnts_t; 139210284Sjmalletttypedef cvmx_npi_size_inputx_t cvmx_npi_size_input_t; 140210284Sjmalletttypedef cvmx_pci_dbellx_t cvmx_pci_dbell_t; 141210284Sjmalletttypedef cvmx_pci_dma_cntx_t cvmx_pci_dma_cnt_t; 142210284Sjmalletttypedef cvmx_pci_dma_int_levx_t cvmx_pci_dma_int_lev_t; 143210284Sjmalletttypedef cvmx_pci_dma_timex_t cvmx_pci_dma_time_t; 144210284Sjmalletttypedef cvmx_pci_instr_countx_t cvmx_pci_instr_count_t; 145210284Sjmalletttypedef cvmx_pci_pkt_creditsx_t cvmx_pci_pkt_credits_t; 146210284Sjmalletttypedef cvmx_pci_pkts_sent_int_levx_t cvmx_pci_pkts_sent_int_lev_t; 147210284Sjmalletttypedef cvmx_pci_pkts_sent_timex_t cvmx_pci_pkts_sent_time_t; 148210284Sjmalletttypedef cvmx_pci_pkts_sentx_t cvmx_pci_pkts_sent_t; 149210284Sjmalletttypedef cvmx_pip_prt_cfgx_t cvmx_pip_port_cfg_t; 150210284Sjmalletttypedef cvmx_pip_prt_tagx_t cvmx_pip_port_tag_cfg_t; 151210284Sjmalletttypedef cvmx_pip_qos_watchx_t cvmx_pip_port_watcher_cfg_t; 152210284Sjmalletttypedef cvmx_pko_mem_queue_ptrs_t cvmx_pko_queue_cfg_t; 153210284Sjmalletttypedef cvmx_pko_reg_cmd_buf_t cvmx_pko_pool_cfg_t; 154210284Sjmalletttypedef cvmx_smix_clk_t cvmx_smi_clk_t; 155210284Sjmalletttypedef cvmx_smix_cmd_t cvmx_smi_cmd_t; 156210284Sjmalletttypedef cvmx_smix_en_t cvmx_smi_en_t; 157210284Sjmalletttypedef cvmx_smix_rd_dat_t cvmx_smi_rd_dat_t; 158210284Sjmalletttypedef cvmx_smix_wr_dat_t cvmx_smi_wr_dat_t; 159210284Sjmalletttypedef cvmx_tim_reg_flags_t cvmx_tim_control_t; 160210284Sjmallett 161210284Sjmallett/* The CSRs for bootbus region zero used to be independent of the 162210284Sjmallett other 1-7. As of SDK 1.7.0 these were combined. These macros 163210284Sjmallett are for backwards compactability */ 164210284Sjmallett#define CVMX_MIO_BOOT_REG_CFG0 CVMX_MIO_BOOT_REG_CFGX(0) 165210284Sjmallett#define CVMX_MIO_BOOT_REG_TIM0 CVMX_MIO_BOOT_REG_TIMX(0) 166210284Sjmallett 167215990Sjmallett/* The CN3XXX and CN58XX chips used to not have a LMC number 168210284Sjmallett passed to the address macros. These are here to supply backwards 169210284Sjmallett compatability with old code. Code should really use the new addresses 170210284Sjmallett with bus arguments for support on other chips */ 171210284Sjmallett#define CVMX_LMC_BIST_CTL CVMX_LMCX_BIST_CTL(0) 172210284Sjmallett#define CVMX_LMC_BIST_RESULT CVMX_LMCX_BIST_RESULT(0) 173210284Sjmallett#define CVMX_LMC_COMP_CTL CVMX_LMCX_COMP_CTL(0) 174210284Sjmallett#define CVMX_LMC_CTL CVMX_LMCX_CTL(0) 175210284Sjmallett#define CVMX_LMC_CTL1 CVMX_LMCX_CTL1(0) 176210284Sjmallett#define CVMX_LMC_DCLK_CNT_HI CVMX_LMCX_DCLK_CNT_HI(0) 177210284Sjmallett#define CVMX_LMC_DCLK_CNT_LO CVMX_LMCX_DCLK_CNT_LO(0) 178210284Sjmallett#define CVMX_LMC_DCLK_CTL CVMX_LMCX_DCLK_CTL(0) 179210284Sjmallett#define CVMX_LMC_DDR2_CTL CVMX_LMCX_DDR2_CTL(0) 180210284Sjmallett#define CVMX_LMC_DELAY_CFG CVMX_LMCX_DELAY_CFG(0) 181210284Sjmallett#define CVMX_LMC_DLL_CTL CVMX_LMCX_DLL_CTL(0) 182210284Sjmallett#define CVMX_LMC_DUAL_MEMCFG CVMX_LMCX_DUAL_MEMCFG(0) 183210284Sjmallett#define CVMX_LMC_ECC_SYND CVMX_LMCX_ECC_SYND(0) 184210284Sjmallett#define CVMX_LMC_FADR CVMX_LMCX_FADR(0) 185210284Sjmallett#define CVMX_LMC_IFB_CNT_HI CVMX_LMCX_IFB_CNT_HI(0) 186210284Sjmallett#define CVMX_LMC_IFB_CNT_LO CVMX_LMCX_IFB_CNT_LO(0) 187210284Sjmallett#define CVMX_LMC_MEM_CFG0 CVMX_LMCX_MEM_CFG0(0) 188210284Sjmallett#define CVMX_LMC_MEM_CFG1 CVMX_LMCX_MEM_CFG1(0) 189210284Sjmallett#define CVMX_LMC_OPS_CNT_HI CVMX_LMCX_OPS_CNT_HI(0) 190210284Sjmallett#define CVMX_LMC_OPS_CNT_LO CVMX_LMCX_OPS_CNT_LO(0) 191210284Sjmallett#define CVMX_LMC_PLL_BWCTL CVMX_LMCX_PLL_BWCTL(0) 192210284Sjmallett#define CVMX_LMC_PLL_CTL CVMX_LMCX_PLL_CTL(0) 193210284Sjmallett#define CVMX_LMC_PLL_STATUS CVMX_LMCX_PLL_STATUS(0) 194210284Sjmallett#define CVMX_LMC_READ_LEVEL_CTL CVMX_LMCX_READ_LEVEL_CTL(0) 195210284Sjmallett#define CVMX_LMC_READ_LEVEL_DBG CVMX_LMCX_READ_LEVEL_DBG(0) 196210284Sjmallett#define CVMX_LMC_READ_LEVEL_RANKX CVMX_LMCX_READ_LEVEL_RANKX(0) 197210284Sjmallett#define CVMX_LMC_RODT_COMP_CTL CVMX_LMCX_RODT_COMP_CTL(0) 198210284Sjmallett#define CVMX_LMC_RODT_CTL CVMX_LMCX_RODT_CTL(0) 199210284Sjmallett#define CVMX_LMC_WODT_CTL CVMX_LMCX_WODT_CTL0(0) 200210284Sjmallett#define CVMX_LMC_WODT_CTL0 CVMX_LMCX_WODT_CTL0(0) 201210284Sjmallett#define CVMX_LMC_WODT_CTL1 CVMX_LMCX_WODT_CTL1(0) 202210284Sjmallett 203215990Sjmallett/* The CN3XXX and CN58XX chips used to not have a TWSI bus number 204210284Sjmallett passed to the address macros. These are here to supply backwards 205210284Sjmallett compatability with old code. Code should really use the new addresses 206210284Sjmallett with bus arguments for support on other chips */ 207210284Sjmallett#define CVMX_MIO_TWS_INT CVMX_MIO_TWSX_INT(0) 208210284Sjmallett#define CVMX_MIO_TWS_SW_TWSI CVMX_MIO_TWSX_SW_TWSI(0) 209210284Sjmallett#define CVMX_MIO_TWS_SW_TWSI_EXT CVMX_MIO_TWSX_SW_TWSI_EXT(0) 210210284Sjmallett#define CVMX_MIO_TWS_TWSI_SW CVMX_MIO_TWSX_TWSI_SW(0) 211210284Sjmallett 212215990Sjmallett/* The CN3XXX and CN58XX chips used to not have a SMI/MDIO bus number 213210284Sjmallett passed to the address macros. These are here to supply backwards 214210284Sjmallett compatability with old code. Code should really use the new addresses 215210284Sjmallett with bus arguments for support on other chips */ 216210284Sjmallett#define CVMX_SMI_CLK CVMX_SMIX_CLK(0) 217210284Sjmallett#define CVMX_SMI_CMD CVMX_SMIX_CMD(0) 218210284Sjmallett#define CVMX_SMI_EN CVMX_SMIX_EN(0) 219210284Sjmallett#define CVMX_SMI_RD_DAT CVMX_SMIX_RD_DAT(0) 220210284Sjmallett#define CVMX_SMI_WR_DAT CVMX_SMIX_WR_DAT(0) 221210284Sjmallett 222210284Sjmallett#endif /* __CVMX_CSR_H__ */ 223210284Sjmallett 224