1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * Definitions for enumerations used with Octeon CSRs. 49210284Sjmallett * 50232812Sjmallett * <hr>$Revision: 70030 $<hr> 51210284Sjmallett * 52210284Sjmallett */ 53210284Sjmallett#ifndef __CVMX_CSR_ENUMS_H__ 54210284Sjmallett#define __CVMX_CSR_ENUMS_H__ 55210284Sjmallett 56210284Sjmalletttypedef enum { 57210284Sjmallett CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ 58215990Sjmallett CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */ 59210284Sjmallett CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ 60210284Sjmallett CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ 61210284Sjmallett} cvmx_ipd_mode_t; 62210284Sjmallett 63210284Sjmallett 64210284Sjmallett/** 65210284Sjmallett * Enumeration representing the amount of packet processing 66210284Sjmallett * and validation performed by the input hardware. 67210284Sjmallett */ 68210284Sjmalletttypedef enum 69210284Sjmallett{ 70210284Sjmallett CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any 71210284Sjmallett processing of the input packet. */ 72210284Sjmallett CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed 73210284Sjmallett with pointer starting at the L2 74210284Sjmallett (ethernet MAC) header. */ 75210284Sjmallett CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP. 76210284Sjmallett Results from non IP packets is 77210284Sjmallett undefined. Pointers reference the 78210284Sjmallett beginning of the IP header. */ 79210284Sjmallett} cvmx_pip_port_parse_mode_t; 80210284Sjmallett 81210284Sjmallett 82210284Sjmallett/** 83210284Sjmallett * This enumeration controls how a QoS watcher matches a packet. 84210284Sjmallett * 85210284Sjmallett * @deprecated This enumeration was used with cvmx_pip_config_watcher which has 86210284Sjmallett * been deprecated. 87210284Sjmallett */ 88210284Sjmalletttypedef enum 89210284Sjmallett{ 90210284Sjmallett CVMX_PIP_QOS_WATCH_DISABLE = 0ull, /**< QoS watcher is diabled */ 91210284Sjmallett CVMX_PIP_QOS_WATCH_PROTNH = 1ull, /**< QoS watcher will match based on the IP protocol */ 92210284Sjmallett CVMX_PIP_QOS_WATCH_TCP = 2ull, /**< QoS watcher will match TCP packets to a specific destination port */ 93210284Sjmallett CVMX_PIP_QOS_WATCH_UDP = 3ull /**< QoS watcher will match UDP packets to a specific destination port */ 94210284Sjmallett} cvmx_pip_qos_watch_types; 95210284Sjmallett 96210284Sjmallett/** 97210284Sjmallett * This enumeration is used in PIP tag config to control how 98210284Sjmallett * POW tags are generated by the hardware. 99210284Sjmallett */ 100210284Sjmalletttypedef enum 101210284Sjmallett{ 102210284Sjmallett CVMX_PIP_TAG_MODE_TUPLE = 0ull, /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */ 103210284Sjmallett CVMX_PIP_TAG_MODE_MASK = 1ull, /**< Always use mask tag algorithm */ 104210284Sjmallett CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, /**< If packet is IP, use tuple else use mask */ 105210284Sjmallett CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull /**< tuple XOR mask */ 106210284Sjmallett} cvmx_pip_tag_mode_t; 107210284Sjmallett 108210284Sjmallett/** 109210284Sjmallett * Tag type definitions 110210284Sjmallett */ 111210284Sjmalletttypedef enum 112210284Sjmallett{ 113210284Sjmallett CVMX_POW_TAG_TYPE_ORDERED = 0L, /**< Tag ordering is maintained */ 114210284Sjmallett CVMX_POW_TAG_TYPE_ATOMIC = 1L, /**< Tag ordering is maintained, and at most one PP has the tag */ 115210284Sjmallett CVMX_POW_TAG_TYPE_NULL = 2L, /**< The work queue entry from the order 116210284Sjmallett - NEVER tag switch from NULL to NULL */ 117210284Sjmallett CVMX_POW_TAG_TYPE_NULL_NULL = 3L /**< A tag switch to NULL, and there is no space reserved in POW 118210284Sjmallett - NEVER tag switch to NULL_NULL 119210284Sjmallett - NEVER tag switch from NULL_NULL 120210284Sjmallett - NULL_NULL is entered at the beginning of time and on a deschedule. 121210284Sjmallett - NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */ 122210284Sjmallett} cvmx_pow_tag_type_t; 123210284Sjmallett 124210284Sjmallett 125210284Sjmallett/** 126210284Sjmallett * LCR bits 0 and 1 control the number of bits per character. See the following table for encodings: 127210284Sjmallett * 128210284Sjmallett * - 00 = 5 bits (bits 0-4 sent) 129210284Sjmallett * - 01 = 6 bits (bits 0-5 sent) 130210284Sjmallett * - 10 = 7 bits (bits 0-6 sent) 131210284Sjmallett * - 11 = 8 bits (all bits sent) 132210284Sjmallett */ 133210284Sjmalletttypedef enum 134210284Sjmallett{ 135210284Sjmallett CVMX_UART_BITS5 = 0, 136210284Sjmallett CVMX_UART_BITS6 = 1, 137210284Sjmallett CVMX_UART_BITS7 = 2, 138210284Sjmallett CVMX_UART_BITS8 = 3 139210284Sjmallett} cvmx_uart_bits_t; 140210284Sjmallett 141210284Sjmallett 142210284Sjmallett/** 143210284Sjmallett * Interrupt Priority Interrupt Interrupt Interrupt 144210284Sjmallett * ID Level Type Source Reset By 145210284Sjmallett * --------------------------------------------------------------------------------------------------------------------------------- 146210284Sjmallett * 0001 - None None - 147210284Sjmallett * 148210284Sjmallett * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register 149210284Sjmallett * Status interrupt 150210284Sjmallett * 151210284Sjmallett * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register 152210284Sjmallett * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below 153210284Sjmallett * enabled) the trigger level (FIFOs enabled) 154210284Sjmallett * 155210284Sjmallett * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register 156210284Sjmallett * Timeout during the last 4 character times and there 157210284Sjmallett * Indication is at least 1 character in it during this 158210284Sjmallett * time 159210284Sjmallett * 160210284Sjmallett * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register 161210284Sjmallett * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into 162210284Sjmallett * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX 163210284Sjmallett * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE 164210284Sjmallett * Mode enabled) 165210284Sjmallett * 166210284Sjmallett * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register 167210284Sjmallett * Changed or Ring Indicator (RI) or Data Center 168210284Sjmallett * Detect (DCD) changed 169210284Sjmallett * 170210284Sjmallett * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register 171210284Sjmallett * Indication Control Register while the BUSY bit of the 172210284Sjmallett * UART Status Register was set 173210284Sjmallett */ 174210284Sjmalletttypedef enum 175210284Sjmallett{ 176210284Sjmallett CVMX_UART_IID_NONE = 1, 177210284Sjmallett CVMX_UART_IID_RX_ERROR = 6, 178210284Sjmallett CVMX_UART_IID_RX_DATA = 4, 179210284Sjmallett CVMX_UART_IID_RX_TIMEOUT = 12, 180210284Sjmallett CVMX_UART_IID_TX_EMPTY = 2, 181210284Sjmallett CVMX_UART_IID_MODEM = 0, 182210284Sjmallett CVMX_UART_IID_BUSY = 7 183210284Sjmallett} cvmx_uart_iid_t; 184210284Sjmallett 185210284Sjmallett#endif /* __CVMX_CSR_ENUMS_H__ */ 186