fasttrap_isa.c revision 265273
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Portions Copyright 2010 The FreeBSD Foundation 22 * 23 * $FreeBSD$ 24 */ 25 26/* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31#if defined(sun) 32#pragma ident "%Z%%M% %I% %E% SMI" 33#endif 34 35#include <sys/fasttrap_isa.h> 36#include <sys/fasttrap_impl.h> 37#include <sys/dtrace.h> 38#include <sys/dtrace_impl.h> 39#include <sys/cmn_err.h> 40#if defined(sun) 41#include <sys/regset.h> 42#include <sys/privregs.h> 43#include <sys/segments.h> 44#include <sys/x86_archext.h> 45#else 46#include <cddl/dev/dtrace/dtrace_cddl.h> 47#include <sys/types.h> 48#include <sys/proc.h> 49#include <sys/dtrace_bsd.h> 50#include <cddl/dev/dtrace/x86/regset.h> 51#include <machine/segments.h> 52#include <machine/reg.h> 53#include <machine/pcb.h> 54#endif 55#include <sys/sysmacros.h> 56#if defined(sun) 57#include <sys/trap.h> 58#include <sys/archsystm.h> 59#else 60#include <sys/ptrace.h> 61 62static int 63proc_ops(int op, proc_t *p, void *kaddr, off_t uaddr, size_t len) 64{ 65 struct iovec iov; 66 struct uio uio; 67 68 iov.iov_base = kaddr; 69 iov.iov_len = len; 70 uio.uio_offset = uaddr; 71 uio.uio_iov = &iov; 72 uio.uio_resid = len; 73 uio.uio_iovcnt = 1; 74 uio.uio_segflg = UIO_SYSSPACE; 75 uio.uio_td = curthread; 76 uio.uio_rw = op; 77 PHOLD(p); 78 if (proc_rwmem(p, &uio) < 0) { 79 PRELE(p); 80 return (-1); 81 } 82 PRELE(p); 83 84 return (0); 85} 86 87static int 88uread(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 89{ 90 91 return (proc_ops(UIO_READ, p, kaddr, uaddr, len)); 92} 93 94static int 95uwrite(proc_t *p, void *kaddr, size_t len, uintptr_t uaddr) 96{ 97 98 return (proc_ops(UIO_WRITE, p, kaddr, uaddr, len)); 99} 100#endif /* sun */ 101#ifdef __i386__ 102#define r_rax r_eax 103#define r_rbx r_ebx 104#define r_rip r_eip 105#define r_rflags r_eflags 106#define r_rsp r_esp 107#define r_rbp r_ebp 108#endif 109 110/* 111 * Lossless User-Land Tracing on x86 112 * --------------------------------- 113 * 114 * The execution of most instructions is not dependent on the address; for 115 * these instructions it is sufficient to copy them into the user process's 116 * address space and execute them. To effectively single-step an instruction 117 * in user-land, we copy out the following sequence of instructions to scratch 118 * space in the user thread's ulwp_t structure. 119 * 120 * We then set the program counter (%eip or %rip) to point to this scratch 121 * space. Once execution resumes, the original instruction is executed and 122 * then control flow is redirected to what was originally the subsequent 123 * instruction. If the kernel attemps to deliver a signal while single- 124 * stepping, the signal is deferred and the program counter is moved into the 125 * second sequence of instructions. The second sequence ends in a trap into 126 * the kernel where the deferred signal is then properly handled and delivered. 127 * 128 * For instructions whose execute is position dependent, we perform simple 129 * emulation. These instructions are limited to control transfer 130 * instructions in 32-bit mode, but in 64-bit mode there's the added wrinkle 131 * of %rip-relative addressing that means that almost any instruction can be 132 * position dependent. For all the details on how we emulate generic 133 * instructions included %rip-relative instructions, see the code in 134 * fasttrap_pid_probe() below where we handle instructions of type 135 * FASTTRAP_T_COMMON (under the header: Generic Instruction Tracing). 136 */ 137 138#define FASTTRAP_MODRM_MOD(modrm) (((modrm) >> 6) & 0x3) 139#define FASTTRAP_MODRM_REG(modrm) (((modrm) >> 3) & 0x7) 140#define FASTTRAP_MODRM_RM(modrm) ((modrm) & 0x7) 141#define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm)) 142 143#define FASTTRAP_SIB_SCALE(sib) (((sib) >> 6) & 0x3) 144#define FASTTRAP_SIB_INDEX(sib) (((sib) >> 3) & 0x7) 145#define FASTTRAP_SIB_BASE(sib) ((sib) & 0x7) 146 147#define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) 148#define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) 149#define FASTTRAP_REX_X(rex) (((rex) >> 1) & 1) 150#define FASTTRAP_REX_B(rex) ((rex) & 1) 151#define FASTTRAP_REX(w, r, x, b) \ 152 (0x40 | ((w) << 3) | ((r) << 2) | ((x) << 1) | (b)) 153 154/* 155 * Single-byte op-codes. 156 */ 157#define FASTTRAP_PUSHL_EBP 0x55 158 159#define FASTTRAP_JO 0x70 160#define FASTTRAP_JNO 0x71 161#define FASTTRAP_JB 0x72 162#define FASTTRAP_JAE 0x73 163#define FASTTRAP_JE 0x74 164#define FASTTRAP_JNE 0x75 165#define FASTTRAP_JBE 0x76 166#define FASTTRAP_JA 0x77 167#define FASTTRAP_JS 0x78 168#define FASTTRAP_JNS 0x79 169#define FASTTRAP_JP 0x7a 170#define FASTTRAP_JNP 0x7b 171#define FASTTRAP_JL 0x7c 172#define FASTTRAP_JGE 0x7d 173#define FASTTRAP_JLE 0x7e 174#define FASTTRAP_JG 0x7f 175 176#define FASTTRAP_NOP 0x90 177 178#define FASTTRAP_MOV_EAX 0xb8 179#define FASTTRAP_MOV_ECX 0xb9 180 181#define FASTTRAP_RET16 0xc2 182#define FASTTRAP_RET 0xc3 183 184#define FASTTRAP_LOOPNZ 0xe0 185#define FASTTRAP_LOOPZ 0xe1 186#define FASTTRAP_LOOP 0xe2 187#define FASTTRAP_JCXZ 0xe3 188 189#define FASTTRAP_CALL 0xe8 190#define FASTTRAP_JMP32 0xe9 191#define FASTTRAP_JMP8 0xeb 192 193#define FASTTRAP_INT3 0xcc 194#define FASTTRAP_INT 0xcd 195 196#define FASTTRAP_2_BYTE_OP 0x0f 197#define FASTTRAP_GROUP5_OP 0xff 198 199/* 200 * Two-byte op-codes (second byte only). 201 */ 202#define FASTTRAP_0F_JO 0x80 203#define FASTTRAP_0F_JNO 0x81 204#define FASTTRAP_0F_JB 0x82 205#define FASTTRAP_0F_JAE 0x83 206#define FASTTRAP_0F_JE 0x84 207#define FASTTRAP_0F_JNE 0x85 208#define FASTTRAP_0F_JBE 0x86 209#define FASTTRAP_0F_JA 0x87 210#define FASTTRAP_0F_JS 0x88 211#define FASTTRAP_0F_JNS 0x89 212#define FASTTRAP_0F_JP 0x8a 213#define FASTTRAP_0F_JNP 0x8b 214#define FASTTRAP_0F_JL 0x8c 215#define FASTTRAP_0F_JGE 0x8d 216#define FASTTRAP_0F_JLE 0x8e 217#define FASTTRAP_0F_JG 0x8f 218 219#define FASTTRAP_EFLAGS_OF 0x800 220#define FASTTRAP_EFLAGS_DF 0x400 221#define FASTTRAP_EFLAGS_SF 0x080 222#define FASTTRAP_EFLAGS_ZF 0x040 223#define FASTTRAP_EFLAGS_AF 0x010 224#define FASTTRAP_EFLAGS_PF 0x004 225#define FASTTRAP_EFLAGS_CF 0x001 226 227/* 228 * Instruction prefixes. 229 */ 230#define FASTTRAP_PREFIX_OPERAND 0x66 231#define FASTTRAP_PREFIX_ADDRESS 0x67 232#define FASTTRAP_PREFIX_CS 0x2E 233#define FASTTRAP_PREFIX_DS 0x3E 234#define FASTTRAP_PREFIX_ES 0x26 235#define FASTTRAP_PREFIX_FS 0x64 236#define FASTTRAP_PREFIX_GS 0x65 237#define FASTTRAP_PREFIX_SS 0x36 238#define FASTTRAP_PREFIX_LOCK 0xF0 239#define FASTTRAP_PREFIX_REP 0xF3 240#define FASTTRAP_PREFIX_REPNE 0xF2 241 242#define FASTTRAP_NOREG 0xff 243 244/* 245 * Map between instruction register encodings and the kernel constants which 246 * correspond to indicies into struct regs. 247 */ 248#ifdef __amd64 249static const uint8_t regmap[16] = { 250 REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI, 251 REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15, 252}; 253#else 254static const uint8_t regmap[8] = { 255 EAX, ECX, EDX, EBX, UESP, EBP, ESI, EDI 256}; 257#endif 258 259static ulong_t fasttrap_getreg(struct reg *, uint_t); 260 261static uint64_t 262fasttrap_anarg(struct reg *rp, int function_entry, int argno) 263{ 264 uint64_t value = 0; 265 int shift = function_entry ? 1 : 0; 266 267#ifdef __amd64 268 if (curproc->p_model == DATAMODEL_LP64) { 269 uintptr_t *stack; 270 271 /* 272 * In 64-bit mode, the first six arguments are stored in 273 * registers. 274 */ 275 if (argno < 6) 276 return ((&rp->r_rdi)[argno]); 277 278 stack = (uintptr_t *)rp->r_rsp; 279 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 280 value = dtrace_fulword(&stack[argno - 6 + shift]); 281 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 282 } else { 283#endif 284#ifdef __i386 285 uint32_t *stack = (uint32_t *)rp->r_esp; 286 DTRACE_CPUFLAG_SET(CPU_DTRACE_NOFAULT); 287 value = dtrace_fuword32(&stack[argno + shift]); 288 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_NOFAULT | CPU_DTRACE_BADADDR); 289#endif 290#ifdef __amd64 291 } 292#endif 293 294 return (value); 295} 296 297/*ARGSUSED*/ 298int 299fasttrap_tracepoint_init(proc_t *p, fasttrap_tracepoint_t *tp, uintptr_t pc, 300 fasttrap_probe_type_t type) 301{ 302 uint8_t instr[FASTTRAP_MAX_INSTR_SIZE + 10]; 303 size_t len = FASTTRAP_MAX_INSTR_SIZE; 304 size_t first = MIN(len, PAGESIZE - (pc & PAGEOFFSET)); 305 uint_t start = 0; 306 int rmindex, size; 307 uint8_t seg, rex = 0; 308 309 /* 310 * Read the instruction at the given address out of the process's 311 * address space. We don't have to worry about a debugger 312 * changing this instruction before we overwrite it with our trap 313 * instruction since P_PR_LOCK is set. Since instructions can span 314 * pages, we potentially read the instruction in two parts. If the 315 * second part fails, we just zero out that part of the instruction. 316 */ 317 if (uread(p, &instr[0], first, pc) != 0) 318 return (-1); 319 if (len > first && 320 uread(p, &instr[first], len - first, pc + first) != 0) { 321 bzero(&instr[first], len - first); 322 len = first; 323 } 324 325 /* 326 * If the disassembly fails, then we have a malformed instruction. 327 */ 328 if ((size = dtrace_instr_size_isa(instr, p->p_model, &rmindex)) <= 0) 329 return (-1); 330 331 /* 332 * Make sure the disassembler isn't completely broken. 333 */ 334 ASSERT(-1 <= rmindex && rmindex < size); 335 336 /* 337 * If the computed size is greater than the number of bytes read, 338 * then it was a malformed instruction possibly because it fell on a 339 * page boundary and the subsequent page was missing or because of 340 * some malicious user. 341 */ 342 if (size > len) 343 return (-1); 344 345 tp->ftt_size = (uint8_t)size; 346 tp->ftt_segment = FASTTRAP_SEG_NONE; 347 348 /* 349 * Find the start of the instruction's opcode by processing any 350 * legacy prefixes. 351 */ 352 for (;;) { 353 seg = 0; 354 switch (instr[start]) { 355 case FASTTRAP_PREFIX_SS: 356 seg++; 357 /*FALLTHRU*/ 358 case FASTTRAP_PREFIX_GS: 359 seg++; 360 /*FALLTHRU*/ 361 case FASTTRAP_PREFIX_FS: 362 seg++; 363 /*FALLTHRU*/ 364 case FASTTRAP_PREFIX_ES: 365 seg++; 366 /*FALLTHRU*/ 367 case FASTTRAP_PREFIX_DS: 368 seg++; 369 /*FALLTHRU*/ 370 case FASTTRAP_PREFIX_CS: 371 seg++; 372 /*FALLTHRU*/ 373 case FASTTRAP_PREFIX_OPERAND: 374 case FASTTRAP_PREFIX_ADDRESS: 375 case FASTTRAP_PREFIX_LOCK: 376 case FASTTRAP_PREFIX_REP: 377 case FASTTRAP_PREFIX_REPNE: 378 if (seg != 0) { 379 /* 380 * It's illegal for an instruction to specify 381 * two segment prefixes -- give up on this 382 * illegal instruction. 383 */ 384 if (tp->ftt_segment != FASTTRAP_SEG_NONE) 385 return (-1); 386 387 tp->ftt_segment = seg; 388 } 389 start++; 390 continue; 391 } 392 break; 393 } 394 395#ifdef __amd64 396 /* 397 * Identify the REX prefix on 64-bit processes. 398 */ 399 if (p->p_model == DATAMODEL_LP64 && (instr[start] & 0xf0) == 0x40) 400 rex = instr[start++]; 401#endif 402 403 /* 404 * Now that we're pretty sure that the instruction is okay, copy the 405 * valid part to the tracepoint. 406 */ 407 bcopy(instr, tp->ftt_instr, FASTTRAP_MAX_INSTR_SIZE); 408 409 tp->ftt_type = FASTTRAP_T_COMMON; 410 if (instr[start] == FASTTRAP_2_BYTE_OP) { 411 switch (instr[start + 1]) { 412 case FASTTRAP_0F_JO: 413 case FASTTRAP_0F_JNO: 414 case FASTTRAP_0F_JB: 415 case FASTTRAP_0F_JAE: 416 case FASTTRAP_0F_JE: 417 case FASTTRAP_0F_JNE: 418 case FASTTRAP_0F_JBE: 419 case FASTTRAP_0F_JA: 420 case FASTTRAP_0F_JS: 421 case FASTTRAP_0F_JNS: 422 case FASTTRAP_0F_JP: 423 case FASTTRAP_0F_JNP: 424 case FASTTRAP_0F_JL: 425 case FASTTRAP_0F_JGE: 426 case FASTTRAP_0F_JLE: 427 case FASTTRAP_0F_JG: 428 tp->ftt_type = FASTTRAP_T_JCC; 429 tp->ftt_code = (instr[start + 1] & 0x0f) | FASTTRAP_JO; 430 tp->ftt_dest = pc + tp->ftt_size + 431 /* LINTED - alignment */ 432 *(int32_t *)&instr[start + 2]; 433 break; 434 } 435 } else if (instr[start] == FASTTRAP_GROUP5_OP) { 436 uint_t mod = FASTTRAP_MODRM_MOD(instr[start + 1]); 437 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); 438 uint_t rm = FASTTRAP_MODRM_RM(instr[start + 1]); 439 440 if (reg == 2 || reg == 4) { 441 uint_t i, sz; 442 443 if (reg == 2) 444 tp->ftt_type = FASTTRAP_T_CALL; 445 else 446 tp->ftt_type = FASTTRAP_T_JMP; 447 448 if (mod == 3) 449 tp->ftt_code = 2; 450 else 451 tp->ftt_code = 1; 452 453 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 454 455 /* 456 * See AMD x86-64 Architecture Programmer's Manual 457 * Volume 3, Section 1.2.7, Table 1-12, and 458 * Appendix A.3.1, Table A-15. 459 */ 460 if (mod != 3 && rm == 4) { 461 uint8_t sib = instr[start + 2]; 462 uint_t index = FASTTRAP_SIB_INDEX(sib); 463 uint_t base = FASTTRAP_SIB_BASE(sib); 464 465 tp->ftt_scale = FASTTRAP_SIB_SCALE(sib); 466 467 tp->ftt_index = (index == 4) ? 468 FASTTRAP_NOREG : 469 regmap[index | (FASTTRAP_REX_X(rex) << 3)]; 470 tp->ftt_base = (mod == 0 && base == 5) ? 471 FASTTRAP_NOREG : 472 regmap[base | (FASTTRAP_REX_B(rex) << 3)]; 473 474 i = 3; 475 sz = mod == 1 ? 1 : 4; 476 } else { 477 /* 478 * In 64-bit mode, mod == 0 and r/m == 5 479 * denotes %rip-relative addressing; in 32-bit 480 * mode, the base register isn't used. In both 481 * modes, there is a 32-bit operand. 482 */ 483 if (mod == 0 && rm == 5) { 484#ifdef __amd64 485 if (p->p_model == DATAMODEL_LP64) 486 tp->ftt_base = REG_RIP; 487 else 488#endif 489 tp->ftt_base = FASTTRAP_NOREG; 490 sz = 4; 491 } else { 492 uint8_t base = rm | 493 (FASTTRAP_REX_B(rex) << 3); 494 495 tp->ftt_base = regmap[base]; 496 sz = mod == 1 ? 1 : mod == 2 ? 4 : 0; 497 } 498 tp->ftt_index = FASTTRAP_NOREG; 499 i = 2; 500 } 501 502 if (sz == 1) { 503 tp->ftt_dest = *(int8_t *)&instr[start + i]; 504 } else if (sz == 4) { 505 /* LINTED - alignment */ 506 tp->ftt_dest = *(int32_t *)&instr[start + i]; 507 } else { 508 tp->ftt_dest = 0; 509 } 510 } 511 } else { 512 switch (instr[start]) { 513 case FASTTRAP_RET: 514 tp->ftt_type = FASTTRAP_T_RET; 515 break; 516 517 case FASTTRAP_RET16: 518 tp->ftt_type = FASTTRAP_T_RET16; 519 /* LINTED - alignment */ 520 tp->ftt_dest = *(uint16_t *)&instr[start + 1]; 521 break; 522 523 case FASTTRAP_JO: 524 case FASTTRAP_JNO: 525 case FASTTRAP_JB: 526 case FASTTRAP_JAE: 527 case FASTTRAP_JE: 528 case FASTTRAP_JNE: 529 case FASTTRAP_JBE: 530 case FASTTRAP_JA: 531 case FASTTRAP_JS: 532 case FASTTRAP_JNS: 533 case FASTTRAP_JP: 534 case FASTTRAP_JNP: 535 case FASTTRAP_JL: 536 case FASTTRAP_JGE: 537 case FASTTRAP_JLE: 538 case FASTTRAP_JG: 539 tp->ftt_type = FASTTRAP_T_JCC; 540 tp->ftt_code = instr[start]; 541 tp->ftt_dest = pc + tp->ftt_size + 542 (int8_t)instr[start + 1]; 543 break; 544 545 case FASTTRAP_LOOPNZ: 546 case FASTTRAP_LOOPZ: 547 case FASTTRAP_LOOP: 548 tp->ftt_type = FASTTRAP_T_LOOP; 549 tp->ftt_code = instr[start]; 550 tp->ftt_dest = pc + tp->ftt_size + 551 (int8_t)instr[start + 1]; 552 break; 553 554 case FASTTRAP_JCXZ: 555 tp->ftt_type = FASTTRAP_T_JCXZ; 556 tp->ftt_dest = pc + tp->ftt_size + 557 (int8_t)instr[start + 1]; 558 break; 559 560 case FASTTRAP_CALL: 561 tp->ftt_type = FASTTRAP_T_CALL; 562 tp->ftt_dest = pc + tp->ftt_size + 563 /* LINTED - alignment */ 564 *(int32_t *)&instr[start + 1]; 565 tp->ftt_code = 0; 566 break; 567 568 case FASTTRAP_JMP32: 569 tp->ftt_type = FASTTRAP_T_JMP; 570 tp->ftt_dest = pc + tp->ftt_size + 571 /* LINTED - alignment */ 572 *(int32_t *)&instr[start + 1]; 573 break; 574 case FASTTRAP_JMP8: 575 tp->ftt_type = FASTTRAP_T_JMP; 576 tp->ftt_dest = pc + tp->ftt_size + 577 (int8_t)instr[start + 1]; 578 break; 579 580 case FASTTRAP_PUSHL_EBP: 581 if (start == 0) 582 tp->ftt_type = FASTTRAP_T_PUSHL_EBP; 583 break; 584 585 case FASTTRAP_NOP: 586#ifdef __amd64 587 ASSERT(p->p_model == DATAMODEL_LP64 || rex == 0); 588 589 /* 590 * On amd64 we have to be careful not to confuse a nop 591 * (actually xchgl %eax, %eax) with an instruction using 592 * the same opcode, but that does something different 593 * (e.g. xchgl %r8d, %eax or xcghq %r8, %rax). 594 */ 595 if (FASTTRAP_REX_B(rex) == 0) 596#endif 597 tp->ftt_type = FASTTRAP_T_NOP; 598 break; 599 600 case FASTTRAP_INT3: 601 /* 602 * The pid provider shares the int3 trap with debugger 603 * breakpoints so we can't instrument them. 604 */ 605 ASSERT(instr[start] == FASTTRAP_INSTR); 606 return (-1); 607 608 case FASTTRAP_INT: 609 /* 610 * Interrupts seem like they could be traced with 611 * no negative implications, but it's possible that 612 * a thread could be redirected by the trap handling 613 * code which would eventually return to the 614 * instruction after the interrupt. If the interrupt 615 * were in our scratch space, the subsequent 616 * instruction might be overwritten before we return. 617 * Accordingly we refuse to instrument any interrupt. 618 */ 619 return (-1); 620 } 621 } 622 623#ifdef __amd64 624 if (p->p_model == DATAMODEL_LP64 && tp->ftt_type == FASTTRAP_T_COMMON) { 625 /* 626 * If the process is 64-bit and the instruction type is still 627 * FASTTRAP_T_COMMON -- meaning we're going to copy it out an 628 * execute it -- we need to watch for %rip-relative 629 * addressing mode. See the portion of fasttrap_pid_probe() 630 * below where we handle tracepoints with type 631 * FASTTRAP_T_COMMON for how we emulate instructions that 632 * employ %rip-relative addressing. 633 */ 634 if (rmindex != -1) { 635 uint_t mod = FASTTRAP_MODRM_MOD(instr[rmindex]); 636 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); 637 uint_t rm = FASTTRAP_MODRM_RM(instr[rmindex]); 638 639 ASSERT(rmindex > start); 640 641 if (mod == 0 && rm == 5) { 642 /* 643 * We need to be sure to avoid other 644 * registers used by this instruction. While 645 * the reg field may determine the op code 646 * rather than denoting a register, assuming 647 * that it denotes a register is always safe. 648 * We leave the REX field intact and use 649 * whatever value's there for simplicity. 650 */ 651 if (reg != 0) { 652 tp->ftt_ripmode = FASTTRAP_RIP_1 | 653 (FASTTRAP_RIP_X * 654 FASTTRAP_REX_B(rex)); 655 rm = 0; 656 } else { 657 tp->ftt_ripmode = FASTTRAP_RIP_2 | 658 (FASTTRAP_RIP_X * 659 FASTTRAP_REX_B(rex)); 660 rm = 1; 661 } 662 663 tp->ftt_modrm = tp->ftt_instr[rmindex]; 664 tp->ftt_instr[rmindex] = 665 FASTTRAP_MODRM(2, reg, rm); 666 } 667 } 668 } 669#endif 670 671 return (0); 672} 673 674int 675fasttrap_tracepoint_install(proc_t *p, fasttrap_tracepoint_t *tp) 676{ 677 fasttrap_instr_t instr = FASTTRAP_INSTR; 678 679 if (uwrite(p, &instr, 1, tp->ftt_pc) != 0) 680 return (-1); 681 682 return (0); 683} 684 685int 686fasttrap_tracepoint_remove(proc_t *p, fasttrap_tracepoint_t *tp) 687{ 688 uint8_t instr; 689 690 /* 691 * Distinguish between read or write failures and a changed 692 * instruction. 693 */ 694 if (uread(p, &instr, 1, tp->ftt_pc) != 0) 695 return (0); 696 if (instr != FASTTRAP_INSTR) 697 return (0); 698 if (uwrite(p, &tp->ftt_instr[0], 1, tp->ftt_pc) != 0) 699 return (-1); 700 701 return (0); 702} 703 704#ifdef __amd64 705static uintptr_t 706fasttrap_fulword_noerr(const void *uaddr) 707{ 708 uintptr_t ret; 709 710 if ((ret = fasttrap_fulword(uaddr)) != -1) 711 return (ret); 712 713 return (0); 714} 715#endif 716 717#ifdef __i386__ 718static uint32_t 719fasttrap_fuword32_noerr(const void *uaddr) 720{ 721 uint32_t ret; 722 723 if ((ret = fasttrap_fuword32(uaddr)) != -1) 724 return (ret); 725 726 return (0); 727} 728#endif 729 730static void 731fasttrap_return_common(struct reg *rp, uintptr_t pc, pid_t pid, 732 uintptr_t new_pc) 733{ 734 fasttrap_tracepoint_t *tp; 735 fasttrap_bucket_t *bucket; 736 fasttrap_id_t *id; 737#if defined(sun) 738 kmutex_t *pid_mtx; 739#endif 740 741#if defined(sun) 742 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 743 mutex_enter(pid_mtx); 744#endif 745 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 746 747 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 748 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 749 tp->ftt_proc->ftpc_acount != 0) 750 break; 751 } 752 753 /* 754 * Don't sweat it if we can't find the tracepoint again; unlike 755 * when we're in fasttrap_pid_probe(), finding the tracepoint here 756 * is not essential to the correct execution of the process. 757 */ 758 if (tp == NULL) { 759#if defined(sun) 760 mutex_exit(pid_mtx); 761#endif 762 return; 763 } 764 765 for (id = tp->ftt_retids; id != NULL; id = id->fti_next) { 766 /* 767 * If there's a branch that could act as a return site, we 768 * need to trace it, and check here if the program counter is 769 * external to the function. 770 */ 771 if (tp->ftt_type != FASTTRAP_T_RET && 772 tp->ftt_type != FASTTRAP_T_RET16 && 773 new_pc - id->fti_probe->ftp_faddr < 774 id->fti_probe->ftp_fsize) 775 continue; 776 777 dtrace_probe(id->fti_probe->ftp_id, 778 pc - id->fti_probe->ftp_faddr, 779 rp->r_rax, rp->r_rbx, 0, 0); 780 } 781 782#if defined(sun) 783 mutex_exit(pid_mtx); 784#endif 785} 786 787static void 788fasttrap_sigsegv(proc_t *p, kthread_t *t, uintptr_t addr) 789{ 790#if defined(sun) 791 sigqueue_t *sqp = kmem_zalloc(sizeof (sigqueue_t), KM_SLEEP); 792 793 sqp->sq_info.si_signo = SIGSEGV; 794 sqp->sq_info.si_code = SEGV_MAPERR; 795 sqp->sq_info.si_addr = (caddr_t)addr; 796 797 mutex_enter(&p->p_lock); 798 sigaddqa(p, t, sqp); 799 mutex_exit(&p->p_lock); 800 801 if (t != NULL) 802 aston(t); 803#else 804 ksiginfo_t *ksi = kmem_zalloc(sizeof (ksiginfo_t), KM_SLEEP); 805 806 ksiginfo_init(ksi); 807 ksi->ksi_signo = SIGSEGV; 808 ksi->ksi_code = SEGV_MAPERR; 809 ksi->ksi_addr = (caddr_t)addr; 810 (void) tdksignal(t, SIGSEGV, ksi); 811#endif 812} 813 814#ifdef __amd64 815static void 816fasttrap_usdt_args64(fasttrap_probe_t *probe, struct reg *rp, int argc, 817 uintptr_t *argv) 818{ 819 int i, x, cap = MIN(argc, probe->ftp_nargs); 820 uintptr_t *stack = (uintptr_t *)rp->r_rsp; 821 822 for (i = 0; i < cap; i++) { 823 x = probe->ftp_argmap[i]; 824 825 if (x < 6) 826 argv[i] = (&rp->r_rdi)[x]; 827 else 828 argv[i] = fasttrap_fulword_noerr(&stack[x]); 829 } 830 831 for (; i < argc; i++) { 832 argv[i] = 0; 833 } 834} 835#endif 836 837#ifdef __i386__ 838static void 839fasttrap_usdt_args32(fasttrap_probe_t *probe, struct reg *rp, int argc, 840 uint32_t *argv) 841{ 842 int i, x, cap = MIN(argc, probe->ftp_nargs); 843 uint32_t *stack = (uint32_t *)rp->r_rsp; 844 845 for (i = 0; i < cap; i++) { 846 x = probe->ftp_argmap[i]; 847 848 argv[i] = fasttrap_fuword32_noerr(&stack[x]); 849 } 850 851 for (; i < argc; i++) { 852 argv[i] = 0; 853 } 854} 855#endif 856 857static int 858fasttrap_do_seg(fasttrap_tracepoint_t *tp, struct reg *rp, uintptr_t *addr) 859{ 860 proc_t *p = curproc; 861#ifdef __i386__ 862 struct segment_descriptor *desc; 863#else 864 struct user_segment_descriptor *desc; 865#endif 866 uint16_t sel = 0, ndx, type; 867 uintptr_t limit; 868 869 switch (tp->ftt_segment) { 870 case FASTTRAP_SEG_CS: 871 sel = rp->r_cs; 872 break; 873 case FASTTRAP_SEG_DS: 874 sel = rp->r_ds; 875 break; 876 case FASTTRAP_SEG_ES: 877 sel = rp->r_es; 878 break; 879 case FASTTRAP_SEG_FS: 880 sel = rp->r_fs; 881 break; 882 case FASTTRAP_SEG_GS: 883 sel = rp->r_gs; 884 break; 885 case FASTTRAP_SEG_SS: 886 sel = rp->r_ss; 887 break; 888 } 889 890 /* 891 * Make sure the given segment register specifies a user priority 892 * selector rather than a kernel selector. 893 */ 894 if (ISPL(sel) != SEL_UPL) 895 return (-1); 896 897 ndx = IDXSEL(sel); 898 899 /* 900 * Check the bounds and grab the descriptor out of the specified 901 * descriptor table. 902 */ 903 if (ISLDT(sel)) { 904#ifdef __i386__ 905 if (ndx > p->p_md.md_ldt->ldt_len) 906 return (-1); 907 908 desc = (struct segment_descriptor *) 909 p->p_md.md_ldt[ndx].ldt_base; 910#else 911 if (ndx > max_ldt_segment) 912 return (-1); 913 914 desc = (struct user_segment_descriptor *) 915 p->p_md.md_ldt[ndx].ldt_base; 916#endif 917 918 } else { 919 if (ndx >= NGDT) 920 return (-1); 921 922#ifdef __i386__ 923 desc = &gdt[ndx].sd; 924#else 925 desc = &gdt[ndx]; 926#endif 927 } 928 929 /* 930 * The descriptor must have user privilege level and it must be 931 * present in memory. 932 */ 933 if (desc->sd_dpl != SEL_UPL || desc->sd_p != 1) 934 return (-1); 935 936 type = desc->sd_type; 937 938 /* 939 * If the S bit in the type field is not set, this descriptor can 940 * only be used in system context. 941 */ 942 if ((type & 0x10) != 0x10) 943 return (-1); 944 945 limit = USD_GETLIMIT(desc) * (desc->sd_gran ? PAGESIZE : 1); 946 947 if (tp->ftt_segment == FASTTRAP_SEG_CS) { 948 /* 949 * The code/data bit and readable bit must both be set. 950 */ 951 if ((type & 0xa) != 0xa) 952 return (-1); 953 954 if (*addr > limit) 955 return (-1); 956 } else { 957 /* 958 * The code/data bit must be clear. 959 */ 960 if ((type & 0x8) != 0) 961 return (-1); 962 963 /* 964 * If the expand-down bit is clear, we just check the limit as 965 * it would naturally be applied. Otherwise, we need to check 966 * that the address is the range [limit + 1 .. 0xffff] or 967 * [limit + 1 ... 0xffffffff] depending on if the default 968 * operand size bit is set. 969 */ 970 if ((type & 0x4) == 0) { 971 if (*addr > limit) 972 return (-1); 973 } else if (desc->sd_def32) { 974 if (*addr < limit + 1 || 0xffff < *addr) 975 return (-1); 976 } else { 977 if (*addr < limit + 1 || 0xffffffff < *addr) 978 return (-1); 979 } 980 } 981 982 *addr += USD_GETBASE(desc); 983 984 return (0); 985} 986 987int 988fasttrap_pid_probe(struct reg *rp) 989{ 990 proc_t *p = curproc; 991#if !defined(sun) 992 proc_t *pp; 993#endif 994 uintptr_t pc = rp->r_rip - 1; 995 uintptr_t new_pc = 0; 996 fasttrap_bucket_t *bucket; 997#if defined(sun) 998 kmutex_t *pid_mtx; 999#endif 1000 fasttrap_tracepoint_t *tp, tp_local; 1001 pid_t pid; 1002 dtrace_icookie_t cookie; 1003 uint_t is_enabled = 0; 1004 1005 /* 1006 * It's possible that a user (in a veritable orgy of bad planning) 1007 * could redirect this thread's flow of control before it reached the 1008 * return probe fasttrap. In this case we need to kill the process 1009 * since it's in a unrecoverable state. 1010 */ 1011 if (curthread->t_dtrace_step) { 1012 ASSERT(curthread->t_dtrace_on); 1013 fasttrap_sigtrap(p, curthread, pc); 1014 return (0); 1015 } 1016 1017 /* 1018 * Clear all user tracing flags. 1019 */ 1020 curthread->t_dtrace_ft = 0; 1021 curthread->t_dtrace_pc = 0; 1022 curthread->t_dtrace_npc = 0; 1023 curthread->t_dtrace_scrpc = 0; 1024 curthread->t_dtrace_astpc = 0; 1025#ifdef __amd64 1026 curthread->t_dtrace_regv = 0; 1027#endif 1028 1029 /* 1030 * Treat a child created by a call to vfork(2) as if it were its 1031 * parent. We know that there's only one thread of control in such a 1032 * process: this one. 1033 */ 1034#if defined(sun) 1035 while (p->p_flag & SVFORK) { 1036 p = p->p_parent; 1037 } 1038 1039 pid = p->p_pid; 1040 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 1041 mutex_enter(pid_mtx); 1042#else 1043 pp = p; 1044 sx_slock(&proctree_lock); 1045 while (pp->p_vmspace == pp->p_pptr->p_vmspace) 1046 pp = pp->p_pptr; 1047 pid = pp->p_pid; 1048 sx_sunlock(&proctree_lock); 1049 pp = NULL; 1050 1051 PROC_LOCK(p); 1052 _PHOLD(p); 1053#endif 1054 1055 bucket = &fasttrap_tpoints.fth_table[FASTTRAP_TPOINTS_INDEX(pid, pc)]; 1056 1057 /* 1058 * Lookup the tracepoint that the process just hit. 1059 */ 1060 for (tp = bucket->ftb_data; tp != NULL; tp = tp->ftt_next) { 1061 if (pid == tp->ftt_pid && pc == tp->ftt_pc && 1062 tp->ftt_proc->ftpc_acount != 0) 1063 break; 1064 } 1065 1066 /* 1067 * If we couldn't find a matching tracepoint, either a tracepoint has 1068 * been inserted without using the pid<pid> ioctl interface (see 1069 * fasttrap_ioctl), or somehow we have mislaid this tracepoint. 1070 */ 1071 if (tp == NULL) { 1072#if defined(sun) 1073 mutex_exit(pid_mtx); 1074#else 1075 _PRELE(p); 1076 PROC_UNLOCK(p); 1077#endif 1078 return (-1); 1079 } 1080 1081 /* 1082 * Set the program counter to the address of the traced instruction 1083 * so that it looks right in ustack() output. 1084 */ 1085 rp->r_rip = pc; 1086 1087 if (tp->ftt_ids != NULL) { 1088 fasttrap_id_t *id; 1089 1090#ifdef __amd64 1091 if (p->p_model == DATAMODEL_LP64) { 1092 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1093 fasttrap_probe_t *probe = id->fti_probe; 1094 1095 if (id->fti_ptype == DTFTP_ENTRY) { 1096 /* 1097 * We note that this was an entry 1098 * probe to help ustack() find the 1099 * first caller. 1100 */ 1101 cookie = dtrace_interrupt_disable(); 1102 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1103 dtrace_probe(probe->ftp_id, rp->r_rdi, 1104 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1105 rp->r_r8); 1106 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1107 dtrace_interrupt_enable(cookie); 1108 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1109 /* 1110 * Note that in this case, we don't 1111 * call dtrace_probe() since it's only 1112 * an artificial probe meant to change 1113 * the flow of control so that it 1114 * encounters the true probe. 1115 */ 1116 is_enabled = 1; 1117 } else if (probe->ftp_argmap == NULL) { 1118 dtrace_probe(probe->ftp_id, rp->r_rdi, 1119 rp->r_rsi, rp->r_rdx, rp->r_rcx, 1120 rp->r_r8); 1121 } else { 1122 uintptr_t t[5]; 1123 1124 fasttrap_usdt_args64(probe, rp, 1125 sizeof (t) / sizeof (t[0]), t); 1126 1127 dtrace_probe(probe->ftp_id, t[0], t[1], 1128 t[2], t[3], t[4]); 1129 } 1130 } 1131 } else { 1132#else /* __amd64 */ 1133 uintptr_t s0, s1, s2, s3, s4, s5; 1134 uint32_t *stack = (uint32_t *)rp->r_esp; 1135 1136 /* 1137 * In 32-bit mode, all arguments are passed on the 1138 * stack. If this is a function entry probe, we need 1139 * to skip the first entry on the stack as it 1140 * represents the return address rather than a 1141 * parameter to the function. 1142 */ 1143 s0 = fasttrap_fuword32_noerr(&stack[0]); 1144 s1 = fasttrap_fuword32_noerr(&stack[1]); 1145 s2 = fasttrap_fuword32_noerr(&stack[2]); 1146 s3 = fasttrap_fuword32_noerr(&stack[3]); 1147 s4 = fasttrap_fuword32_noerr(&stack[4]); 1148 s5 = fasttrap_fuword32_noerr(&stack[5]); 1149 1150 for (id = tp->ftt_ids; id != NULL; id = id->fti_next) { 1151 fasttrap_probe_t *probe = id->fti_probe; 1152 1153 if (id->fti_ptype == DTFTP_ENTRY) { 1154 /* 1155 * We note that this was an entry 1156 * probe to help ustack() find the 1157 * first caller. 1158 */ 1159 cookie = dtrace_interrupt_disable(); 1160 DTRACE_CPUFLAG_SET(CPU_DTRACE_ENTRY); 1161 dtrace_probe(probe->ftp_id, s1, s2, 1162 s3, s4, s5); 1163 DTRACE_CPUFLAG_CLEAR(CPU_DTRACE_ENTRY); 1164 dtrace_interrupt_enable(cookie); 1165 } else if (id->fti_ptype == DTFTP_IS_ENABLED) { 1166 /* 1167 * Note that in this case, we don't 1168 * call dtrace_probe() since it's only 1169 * an artificial probe meant to change 1170 * the flow of control so that it 1171 * encounters the true probe. 1172 */ 1173 is_enabled = 1; 1174 } else if (probe->ftp_argmap == NULL) { 1175 dtrace_probe(probe->ftp_id, s0, s1, 1176 s2, s3, s4); 1177 } else { 1178 uint32_t t[5]; 1179 1180 fasttrap_usdt_args32(probe, rp, 1181 sizeof (t) / sizeof (t[0]), t); 1182 1183 dtrace_probe(probe->ftp_id, t[0], t[1], 1184 t[2], t[3], t[4]); 1185 } 1186 } 1187#endif /* __amd64 */ 1188#ifdef __amd64 1189 } 1190#endif 1191 } 1192 1193 /* 1194 * We're about to do a bunch of work so we cache a local copy of 1195 * the tracepoint to emulate the instruction, and then find the 1196 * tracepoint again later if we need to light up any return probes. 1197 */ 1198 tp_local = *tp; 1199#if defined(sun) 1200 mutex_exit(pid_mtx); 1201#else 1202 PROC_UNLOCK(p); 1203#endif 1204 tp = &tp_local; 1205 1206 /* 1207 * Set the program counter to appear as though the traced instruction 1208 * had completely executed. This ensures that fasttrap_getreg() will 1209 * report the expected value for REG_RIP. 1210 */ 1211 rp->r_rip = pc + tp->ftt_size; 1212 1213 /* 1214 * If there's an is-enabled probe connected to this tracepoint it 1215 * means that there was a 'xorl %eax, %eax' or 'xorq %rax, %rax' 1216 * instruction that was placed there by DTrace when the binary was 1217 * linked. As this probe is, in fact, enabled, we need to stuff 1 1218 * into %eax or %rax. Accordingly, we can bypass all the instruction 1219 * emulation logic since we know the inevitable result. It's possible 1220 * that a user could construct a scenario where the 'is-enabled' 1221 * probe was on some other instruction, but that would be a rather 1222 * exotic way to shoot oneself in the foot. 1223 */ 1224 if (is_enabled) { 1225 rp->r_rax = 1; 1226 new_pc = rp->r_rip; 1227 goto done; 1228 } 1229 1230 /* 1231 * We emulate certain types of instructions to ensure correctness 1232 * (in the case of position dependent instructions) or optimize 1233 * common cases. The rest we have the thread execute back in user- 1234 * land. 1235 */ 1236 switch (tp->ftt_type) { 1237 case FASTTRAP_T_RET: 1238 case FASTTRAP_T_RET16: 1239 { 1240 uintptr_t dst = 0; 1241 uintptr_t addr = 0; 1242 int ret = 0; 1243 1244 /* 1245 * We have to emulate _every_ facet of the behavior of a ret 1246 * instruction including what happens if the load from %esp 1247 * fails; in that case, we send a SIGSEGV. 1248 */ 1249#ifdef __amd64 1250 if (p->p_model == DATAMODEL_NATIVE) { 1251 ret = dst = fasttrap_fulword((void *)rp->r_rsp); 1252 addr = rp->r_rsp + sizeof (uintptr_t); 1253 } else { 1254#endif 1255#ifdef __i386__ 1256 uint32_t dst32; 1257 ret = dst32 = fasttrap_fuword32((void *)rp->r_esp); 1258 dst = dst32; 1259 addr = rp->r_esp + sizeof (uint32_t); 1260#endif 1261#ifdef __amd64 1262 } 1263#endif 1264 1265 if (ret == -1) { 1266 fasttrap_sigsegv(p, curthread, rp->r_rsp); 1267 new_pc = pc; 1268 break; 1269 } 1270 1271 if (tp->ftt_type == FASTTRAP_T_RET16) 1272 addr += tp->ftt_dest; 1273 1274 rp->r_rsp = addr; 1275 new_pc = dst; 1276 break; 1277 } 1278 1279 case FASTTRAP_T_JCC: 1280 { 1281 uint_t taken = 0; 1282 1283 switch (tp->ftt_code) { 1284 case FASTTRAP_JO: 1285 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) != 0; 1286 break; 1287 case FASTTRAP_JNO: 1288 taken = (rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0; 1289 break; 1290 case FASTTRAP_JB: 1291 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0; 1292 break; 1293 case FASTTRAP_JAE: 1294 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0; 1295 break; 1296 case FASTTRAP_JE: 1297 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1298 break; 1299 case FASTTRAP_JNE: 1300 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1301 break; 1302 case FASTTRAP_JBE: 1303 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) != 0 || 1304 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0; 1305 break; 1306 case FASTTRAP_JA: 1307 taken = (rp->r_rflags & FASTTRAP_EFLAGS_CF) == 0 && 1308 (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0; 1309 break; 1310 case FASTTRAP_JS: 1311 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) != 0; 1312 break; 1313 case FASTTRAP_JNS: 1314 taken = (rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0; 1315 break; 1316 case FASTTRAP_JP: 1317 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) != 0; 1318 break; 1319 case FASTTRAP_JNP: 1320 taken = (rp->r_rflags & FASTTRAP_EFLAGS_PF) == 0; 1321 break; 1322 case FASTTRAP_JL: 1323 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1324 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1325 break; 1326 case FASTTRAP_JGE: 1327 taken = ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1328 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1329 break; 1330 case FASTTRAP_JLE: 1331 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 || 1332 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) != 1333 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1334 break; 1335 case FASTTRAP_JG: 1336 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1337 ((rp->r_rflags & FASTTRAP_EFLAGS_SF) == 0) == 1338 ((rp->r_rflags & FASTTRAP_EFLAGS_OF) == 0); 1339 break; 1340 1341 } 1342 1343 if (taken) 1344 new_pc = tp->ftt_dest; 1345 else 1346 new_pc = pc + tp->ftt_size; 1347 break; 1348 } 1349 1350 case FASTTRAP_T_LOOP: 1351 { 1352 uint_t taken = 0; 1353#ifdef __amd64 1354 greg_t cx = rp->r_rcx--; 1355#else 1356 greg_t cx = rp->r_ecx--; 1357#endif 1358 1359 switch (tp->ftt_code) { 1360 case FASTTRAP_LOOPNZ: 1361 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) == 0 && 1362 cx != 0; 1363 break; 1364 case FASTTRAP_LOOPZ: 1365 taken = (rp->r_rflags & FASTTRAP_EFLAGS_ZF) != 0 && 1366 cx != 0; 1367 break; 1368 case FASTTRAP_LOOP: 1369 taken = (cx != 0); 1370 break; 1371 } 1372 1373 if (taken) 1374 new_pc = tp->ftt_dest; 1375 else 1376 new_pc = pc + tp->ftt_size; 1377 break; 1378 } 1379 1380 case FASTTRAP_T_JCXZ: 1381 { 1382#ifdef __amd64 1383 greg_t cx = rp->r_rcx; 1384#else 1385 greg_t cx = rp->r_ecx; 1386#endif 1387 1388 if (cx == 0) 1389 new_pc = tp->ftt_dest; 1390 else 1391 new_pc = pc + tp->ftt_size; 1392 break; 1393 } 1394 1395 case FASTTRAP_T_PUSHL_EBP: 1396 { 1397 int ret = 0; 1398 1399#ifdef __amd64 1400 if (p->p_model == DATAMODEL_NATIVE) { 1401 rp->r_rsp -= sizeof (uintptr_t); 1402 ret = fasttrap_sulword((void *)rp->r_rsp, rp->r_rbp); 1403 } else { 1404#endif 1405#ifdef __i386__ 1406 rp->r_rsp -= sizeof (uint32_t); 1407 ret = fasttrap_suword32((void *)rp->r_rsp, rp->r_rbp); 1408#endif 1409#ifdef __amd64 1410 } 1411#endif 1412 1413 if (ret == -1) { 1414 fasttrap_sigsegv(p, curthread, rp->r_rsp); 1415 new_pc = pc; 1416 break; 1417 } 1418 1419 new_pc = pc + tp->ftt_size; 1420 break; 1421 } 1422 1423 case FASTTRAP_T_NOP: 1424 new_pc = pc + tp->ftt_size; 1425 break; 1426 1427 case FASTTRAP_T_JMP: 1428 case FASTTRAP_T_CALL: 1429 if (tp->ftt_code == 0) { 1430 new_pc = tp->ftt_dest; 1431 } else { 1432#ifdef __amd64 1433 uintptr_t value; 1434#endif 1435 uintptr_t addr = tp->ftt_dest; 1436 1437 if (tp->ftt_base != FASTTRAP_NOREG) 1438 addr += fasttrap_getreg(rp, tp->ftt_base); 1439 if (tp->ftt_index != FASTTRAP_NOREG) 1440 addr += fasttrap_getreg(rp, tp->ftt_index) << 1441 tp->ftt_scale; 1442 1443 if (tp->ftt_code == 1) { 1444 /* 1445 * If there's a segment prefix for this 1446 * instruction, we'll need to check permissions 1447 * and bounds on the given selector, and adjust 1448 * the address accordingly. 1449 */ 1450 if (tp->ftt_segment != FASTTRAP_SEG_NONE && 1451 fasttrap_do_seg(tp, rp, &addr) != 0) { 1452 fasttrap_sigsegv(p, curthread, addr); 1453 new_pc = pc; 1454 break; 1455 } 1456 1457#ifdef __amd64 1458 if (p->p_model == DATAMODEL_NATIVE) { 1459 if ((value = fasttrap_fulword((void *)addr)) 1460 == -1) { 1461 fasttrap_sigsegv(p, curthread, 1462 addr); 1463 new_pc = pc; 1464 break; 1465 } 1466 new_pc = value; 1467 } else { 1468#endif 1469#ifdef __i386__ 1470 uint32_t value32; 1471 addr = (uintptr_t)(uint32_t)addr; 1472 if ((value32 = fasttrap_fuword32((void *)addr)) 1473 == -1) { 1474 fasttrap_sigsegv(p, curthread, 1475 addr); 1476 new_pc = pc; 1477 break; 1478 } 1479 new_pc = value32; 1480#endif 1481 } 1482#ifdef __amd64 1483 } else { 1484 new_pc = addr; 1485 } 1486#endif 1487 } 1488 1489 /* 1490 * If this is a call instruction, we need to push the return 1491 * address onto the stack. If this fails, we send the process 1492 * a SIGSEGV and reset the pc to emulate what would happen if 1493 * this instruction weren't traced. 1494 */ 1495 if (tp->ftt_type == FASTTRAP_T_CALL) { 1496 int ret = 0; 1497 uintptr_t addr = 0, pcps; 1498#ifdef __amd64 1499 if (p->p_model == DATAMODEL_NATIVE) { 1500 addr = rp->r_rsp - sizeof (uintptr_t); 1501 pcps = pc + tp->ftt_size; 1502 ret = fasttrap_sulword((void *)addr, pcps); 1503 } else { 1504#endif 1505#ifdef __i386__ 1506 addr = rp->r_rsp - sizeof (uint32_t); 1507 pcps = (uint32_t)(pc + tp->ftt_size); 1508 ret = fasttrap_suword32((void *)addr, pcps); 1509#endif 1510#ifdef __amd64 1511 } 1512#endif 1513 1514 if (ret == -1) { 1515 fasttrap_sigsegv(p, curthread, addr); 1516 new_pc = pc; 1517 break; 1518 } 1519 1520 rp->r_rsp = addr; 1521 } 1522 1523 break; 1524 1525 case FASTTRAP_T_COMMON: 1526 { 1527 uintptr_t addr; 1528#if defined(__amd64) 1529 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 22]; 1530#else 1531 uint8_t scratch[2 * FASTTRAP_MAX_INSTR_SIZE + 7]; 1532#endif 1533 uint_t i = 0; 1534#if defined(sun) 1535 klwp_t *lwp = ttolwp(curthread); 1536#endif 1537 1538 /* 1539 * Compute the address of the ulwp_t and step over the 1540 * ul_self pointer. The method used to store the user-land 1541 * thread pointer is very different on 32- and 64-bit 1542 * kernels. 1543 */ 1544#if defined(sun) 1545#if defined(__amd64) 1546 if (p->p_model == DATAMODEL_LP64) { 1547 addr = lwp->lwp_pcb.pcb_fsbase; 1548 addr += sizeof (void *); 1549 } else { 1550 addr = lwp->lwp_pcb.pcb_gsbase; 1551 addr += sizeof (caddr32_t); 1552 } 1553#else 1554 addr = USD_GETBASE(&lwp->lwp_pcb.pcb_gsdesc); 1555 addr += sizeof (void *); 1556#endif 1557#endif /* sun */ 1558#ifdef __i386__ 1559 addr = USD_GETBASE(&curthread->td_pcb->pcb_gsd); 1560#else 1561 addr = curthread->td_pcb->pcb_gsbase; 1562#endif 1563 addr += sizeof (void *); 1564 1565 /* 1566 * Generic Instruction Tracing 1567 * --------------------------- 1568 * 1569 * This is the layout of the scratch space in the user-land 1570 * thread structure for our generated instructions. 1571 * 1572 * 32-bit mode bytes 1573 * ------------------------ ----- 1574 * a: <original instruction> <= 15 1575 * jmp <pc + tp->ftt_size> 5 1576 * b: <original instruction> <= 15 1577 * int T_DTRACE_RET 2 1578 * ----- 1579 * <= 37 1580 * 1581 * 64-bit mode bytes 1582 * ------------------------ ----- 1583 * a: <original instruction> <= 15 1584 * jmp 0(%rip) 6 1585 * <pc + tp->ftt_size> 8 1586 * b: <original instruction> <= 15 1587 * int T_DTRACE_RET 2 1588 * ----- 1589 * <= 46 1590 * 1591 * The %pc is set to a, and curthread->t_dtrace_astpc is set 1592 * to b. If we encounter a signal on the way out of the 1593 * kernel, trap() will set %pc to curthread->t_dtrace_astpc 1594 * so that we execute the original instruction and re-enter 1595 * the kernel rather than redirecting to the next instruction. 1596 * 1597 * If there are return probes (so we know that we're going to 1598 * need to reenter the kernel after executing the original 1599 * instruction), the scratch space will just contain the 1600 * original instruction followed by an interrupt -- the same 1601 * data as at b. 1602 * 1603 * %rip-relative Addressing 1604 * ------------------------ 1605 * 1606 * There's a further complication in 64-bit mode due to %rip- 1607 * relative addressing. While this is clearly a beneficial 1608 * architectural decision for position independent code, it's 1609 * hard not to see it as a personal attack against the pid 1610 * provider since before there was a relatively small set of 1611 * instructions to emulate; with %rip-relative addressing, 1612 * almost every instruction can potentially depend on the 1613 * address at which it's executed. Rather than emulating 1614 * the broad spectrum of instructions that can now be 1615 * position dependent, we emulate jumps and others as in 1616 * 32-bit mode, and take a different tack for instructions 1617 * using %rip-relative addressing. 1618 * 1619 * For every instruction that uses the ModRM byte, the 1620 * in-kernel disassembler reports its location. We use the 1621 * ModRM byte to identify that an instruction uses 1622 * %rip-relative addressing and to see what other registers 1623 * the instruction uses. To emulate those instructions, 1624 * we modify the instruction to be %rax-relative rather than 1625 * %rip-relative (or %rcx-relative if the instruction uses 1626 * %rax; or %r8- or %r9-relative if the REX.B is present so 1627 * we don't have to rewrite the REX prefix). We then load 1628 * the value that %rip would have been into the scratch 1629 * register and generate an instruction to reset the scratch 1630 * register back to its original value. The instruction 1631 * sequence looks like this: 1632 * 1633 * 64-mode %rip-relative bytes 1634 * ------------------------ ----- 1635 * a: <modified instruction> <= 15 1636 * movq $<value>, %<scratch> 6 1637 * jmp 0(%rip) 6 1638 * <pc + tp->ftt_size> 8 1639 * b: <modified instruction> <= 15 1640 * int T_DTRACE_RET 2 1641 * ----- 1642 * 52 1643 * 1644 * We set curthread->t_dtrace_regv so that upon receiving 1645 * a signal we can reset the value of the scratch register. 1646 */ 1647 1648 ASSERT(tp->ftt_size < FASTTRAP_MAX_INSTR_SIZE); 1649 1650 curthread->t_dtrace_scrpc = addr; 1651 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1652 i += tp->ftt_size; 1653 1654#ifdef __amd64 1655 if (tp->ftt_ripmode != 0) { 1656 greg_t *reg = NULL; 1657 1658 ASSERT(p->p_model == DATAMODEL_LP64); 1659 ASSERT(tp->ftt_ripmode & 1660 (FASTTRAP_RIP_1 | FASTTRAP_RIP_2)); 1661 1662 /* 1663 * If this was a %rip-relative instruction, we change 1664 * it to be either a %rax- or %rcx-relative 1665 * instruction (depending on whether those registers 1666 * are used as another operand; or %r8- or %r9- 1667 * relative depending on the value of REX.B). We then 1668 * set that register and generate a movq instruction 1669 * to reset the value. 1670 */ 1671 if (tp->ftt_ripmode & FASTTRAP_RIP_X) 1672 scratch[i++] = FASTTRAP_REX(1, 0, 0, 1); 1673 else 1674 scratch[i++] = FASTTRAP_REX(1, 0, 0, 0); 1675 1676 if (tp->ftt_ripmode & FASTTRAP_RIP_1) 1677 scratch[i++] = FASTTRAP_MOV_EAX; 1678 else 1679 scratch[i++] = FASTTRAP_MOV_ECX; 1680 1681 switch (tp->ftt_ripmode) { 1682 case FASTTRAP_RIP_1: 1683 reg = &rp->r_rax; 1684 curthread->t_dtrace_reg = REG_RAX; 1685 break; 1686 case FASTTRAP_RIP_2: 1687 reg = &rp->r_rcx; 1688 curthread->t_dtrace_reg = REG_RCX; 1689 break; 1690 case FASTTRAP_RIP_1 | FASTTRAP_RIP_X: 1691 reg = &rp->r_r8; 1692 curthread->t_dtrace_reg = REG_R8; 1693 break; 1694 case FASTTRAP_RIP_2 | FASTTRAP_RIP_X: 1695 reg = &rp->r_r9; 1696 curthread->t_dtrace_reg = REG_R9; 1697 break; 1698 } 1699 1700 /* LINTED - alignment */ 1701 *(uint64_t *)&scratch[i] = *reg; 1702 curthread->t_dtrace_regv = *reg; 1703 *reg = pc + tp->ftt_size; 1704 i += sizeof (uint64_t); 1705 } 1706#endif 1707 1708 /* 1709 * Generate the branch instruction to what would have 1710 * normally been the subsequent instruction. In 32-bit mode, 1711 * this is just a relative branch; in 64-bit mode this is a 1712 * %rip-relative branch that loads the 64-bit pc value 1713 * immediately after the jmp instruction. 1714 */ 1715#ifdef __amd64 1716 if (p->p_model == DATAMODEL_LP64) { 1717 scratch[i++] = FASTTRAP_GROUP5_OP; 1718 scratch[i++] = FASTTRAP_MODRM(0, 4, 5); 1719 /* LINTED - alignment */ 1720 *(uint32_t *)&scratch[i] = 0; 1721 i += sizeof (uint32_t); 1722 /* LINTED - alignment */ 1723 *(uint64_t *)&scratch[i] = pc + tp->ftt_size; 1724 i += sizeof (uint64_t); 1725 } else { 1726#endif 1727#ifdef __i386__ 1728 /* 1729 * Set up the jmp to the next instruction; note that 1730 * the size of the traced instruction cancels out. 1731 */ 1732 scratch[i++] = FASTTRAP_JMP32; 1733 /* LINTED - alignment */ 1734 *(uint32_t *)&scratch[i] = pc - addr - 5; 1735 i += sizeof (uint32_t); 1736#endif 1737#ifdef __amd64 1738 } 1739#endif 1740 1741 curthread->t_dtrace_astpc = addr + i; 1742 bcopy(tp->ftt_instr, &scratch[i], tp->ftt_size); 1743 i += tp->ftt_size; 1744 scratch[i++] = FASTTRAP_INT; 1745 scratch[i++] = T_DTRACE_RET; 1746 1747 ASSERT(i <= sizeof (scratch)); 1748 1749#if defined(sun) 1750 if (fasttrap_copyout(scratch, (char *)addr, i)) { 1751#else 1752 if (uwrite(p, scratch, i, addr)) { 1753#endif 1754 fasttrap_sigtrap(p, curthread, pc); 1755 new_pc = pc; 1756 break; 1757 } 1758 if (tp->ftt_retids != NULL) { 1759 curthread->t_dtrace_step = 1; 1760 curthread->t_dtrace_ret = 1; 1761 new_pc = curthread->t_dtrace_astpc; 1762 } else { 1763 new_pc = curthread->t_dtrace_scrpc; 1764 } 1765 1766 curthread->t_dtrace_pc = pc; 1767 curthread->t_dtrace_npc = pc + tp->ftt_size; 1768 curthread->t_dtrace_on = 1; 1769 break; 1770 } 1771 1772 default: 1773 panic("fasttrap: mishandled an instruction"); 1774 } 1775 1776done: 1777 /* 1778 * If there were no return probes when we first found the tracepoint, 1779 * we should feel no obligation to honor any return probes that were 1780 * subsequently enabled -- they'll just have to wait until the next 1781 * time around. 1782 */ 1783 if (tp->ftt_retids != NULL) { 1784 /* 1785 * We need to wait until the results of the instruction are 1786 * apparent before invoking any return probes. If this 1787 * instruction was emulated we can just call 1788 * fasttrap_return_common(); if it needs to be executed, we 1789 * need to wait until the user thread returns to the kernel. 1790 */ 1791 if (tp->ftt_type != FASTTRAP_T_COMMON) { 1792 /* 1793 * Set the program counter to the address of the traced 1794 * instruction so that it looks right in ustack() 1795 * output. We had previously set it to the end of the 1796 * instruction to simplify %rip-relative addressing. 1797 */ 1798 rp->r_rip = pc; 1799 1800 fasttrap_return_common(rp, pc, pid, new_pc); 1801 } else { 1802 ASSERT(curthread->t_dtrace_ret != 0); 1803 ASSERT(curthread->t_dtrace_pc == pc); 1804 ASSERT(curthread->t_dtrace_scrpc != 0); 1805 ASSERT(new_pc == curthread->t_dtrace_astpc); 1806 } 1807 } 1808 1809 rp->r_rip = new_pc; 1810 1811#if !defined(sun) 1812 PROC_LOCK(p); 1813 proc_write_regs(curthread, rp); 1814 _PRELE(p); 1815 PROC_UNLOCK(p); 1816#endif 1817 1818 return (0); 1819} 1820 1821int 1822fasttrap_return_probe(struct reg *rp) 1823{ 1824 proc_t *p = curproc; 1825 uintptr_t pc = curthread->t_dtrace_pc; 1826 uintptr_t npc = curthread->t_dtrace_npc; 1827 1828 curthread->t_dtrace_pc = 0; 1829 curthread->t_dtrace_npc = 0; 1830 curthread->t_dtrace_scrpc = 0; 1831 curthread->t_dtrace_astpc = 0; 1832 1833#if defined(sun) 1834 /* 1835 * Treat a child created by a call to vfork(2) as if it were its 1836 * parent. We know that there's only one thread of control in such a 1837 * process: this one. 1838 */ 1839 while (p->p_flag & SVFORK) { 1840 p = p->p_parent; 1841 } 1842#endif 1843 1844 /* 1845 * We set rp->r_rip to the address of the traced instruction so 1846 * that it appears to dtrace_probe() that we're on the original 1847 * instruction, and so that the user can't easily detect our 1848 * complex web of lies. dtrace_return_probe() (our caller) 1849 * will correctly set %pc after we return. 1850 */ 1851 rp->r_rip = pc; 1852 1853 fasttrap_return_common(rp, pc, p->p_pid, npc); 1854 1855 return (0); 1856} 1857 1858/*ARGSUSED*/ 1859uint64_t 1860fasttrap_pid_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1861 int aframes) 1862{ 1863 struct reg r; 1864 1865 fill_regs(curthread, &r); 1866 1867 return (fasttrap_anarg(&r, 1, argno)); 1868} 1869 1870/*ARGSUSED*/ 1871uint64_t 1872fasttrap_usdt_getarg(void *arg, dtrace_id_t id, void *parg, int argno, 1873 int aframes) 1874{ 1875 struct reg r; 1876 1877 fill_regs(curthread, &r); 1878 1879 return (fasttrap_anarg(&r, 0, argno)); 1880} 1881 1882static ulong_t 1883fasttrap_getreg(struct reg *rp, uint_t reg) 1884{ 1885#ifdef __amd64 1886 switch (reg) { 1887 case REG_R15: return (rp->r_r15); 1888 case REG_R14: return (rp->r_r14); 1889 case REG_R13: return (rp->r_r13); 1890 case REG_R12: return (rp->r_r12); 1891 case REG_R11: return (rp->r_r11); 1892 case REG_R10: return (rp->r_r10); 1893 case REG_R9: return (rp->r_r9); 1894 case REG_R8: return (rp->r_r8); 1895 case REG_RDI: return (rp->r_rdi); 1896 case REG_RSI: return (rp->r_rsi); 1897 case REG_RBP: return (rp->r_rbp); 1898 case REG_RBX: return (rp->r_rbx); 1899 case REG_RDX: return (rp->r_rdx); 1900 case REG_RCX: return (rp->r_rcx); 1901 case REG_RAX: return (rp->r_rax); 1902 case REG_TRAPNO: return (rp->r_trapno); 1903 case REG_ERR: return (rp->r_err); 1904 case REG_RIP: return (rp->r_rip); 1905 case REG_CS: return (rp->r_cs); 1906#if defined(sun) 1907 case REG_RFL: return (rp->r_rfl); 1908#endif 1909 case REG_RSP: return (rp->r_rsp); 1910 case REG_SS: return (rp->r_ss); 1911 case REG_FS: return (rp->r_fs); 1912 case REG_GS: return (rp->r_gs); 1913 case REG_DS: return (rp->r_ds); 1914 case REG_ES: return (rp->r_es); 1915 case REG_FSBASE: return (rdmsr(MSR_FSBASE)); 1916 case REG_GSBASE: return (rdmsr(MSR_GSBASE)); 1917 } 1918 1919 panic("dtrace: illegal register constant"); 1920 /*NOTREACHED*/ 1921#else 1922#define _NGREG 19 1923 if (reg >= _NGREG) 1924 panic("dtrace: illegal register constant"); 1925 1926 return (((greg_t *)&rp->r_gs)[reg]); 1927#endif 1928} 1929