1170101Ssimokawa/* 2170101Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3170101Ssimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4170101Ssimokawa * All rights reserved. 5170101Ssimokawa * 6170101Ssimokawa * Redistribution and use in source and binary forms, with or without 7170101Ssimokawa * modification, are permitted provided that the following conditions 8170101Ssimokawa * are met: 9170101Ssimokawa * 1. Redistributions of source code must retain the above copyright 10170101Ssimokawa * notice, this list of conditions and the following disclaimer. 11170101Ssimokawa * 2. Redistributions in binary form must reproduce the above copyright 12170101Ssimokawa * notice, this list of conditions and the following disclaimer in the 13170101Ssimokawa * documentation and/or other materials provided with the distribution. 14170101Ssimokawa * 3. All advertising materials mentioning features or use of this software 15170101Ssimokawa * must display the acknowledgement as bellow: 16170101Ssimokawa * 17170101Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18170101Ssimokawa * 19170101Ssimokawa * 4. The name of the author may not be used to endorse or promote products 20170101Ssimokawa * derived from this software without specific prior written permission. 21170101Ssimokawa * 22170101Ssimokawa * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23170101Ssimokawa * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24170101Ssimokawa * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25170101Ssimokawa * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26170101Ssimokawa * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27170101Ssimokawa * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28170101Ssimokawa * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29170101Ssimokawa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30170101Ssimokawa * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31170101Ssimokawa * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32170101Ssimokawa * POSSIBILITY OF SUCH DAMAGE. 33170101Ssimokawa * 34170101Ssimokawa * $FreeBSD$ 35170101Ssimokawa * 36170101Ssimokawa */ 37170101Ssimokawa#define PCI_CBMEM PCIR_BAR(0) 38170101Ssimokawa 39170101Ssimokawa#define FW_VENDORID_NATSEMI 0x100B 40170101Ssimokawa#define FW_VENDORID_NEC 0x1033 41170101Ssimokawa#define FW_VENDORID_SIS 0x1039 42170101Ssimokawa#define FW_VENDORID_TI 0x104c 43170101Ssimokawa#define FW_VENDORID_SONY 0x104d 44170101Ssimokawa#define FW_VENDORID_VIA 0x1106 45170101Ssimokawa#define FW_VENDORID_RICOH 0x1180 46170101Ssimokawa#define FW_VENDORID_APPLE 0x106b 47170101Ssimokawa#define FW_VENDORID_LUCENT 0x11c1 48170101Ssimokawa#define FW_VENDORID_INTEL 0x8086 49170101Ssimokawa#define FW_VENDORID_ADAPTEC 0x9004 50170101Ssimokawa 51170101Ssimokawa#define FW_DEVICE_CS4210 (0x000f << 16) 52170101Ssimokawa#define FW_DEVICE_UPD861 (0x0063 << 16) 53170101Ssimokawa#define FW_DEVICE_UPD871 (0x00ce << 16) 54170101Ssimokawa#define FW_DEVICE_UPD72870 (0x00cd << 16) 55170101Ssimokawa#define FW_DEVICE_UPD72873 (0x00e7 << 16) 56170101Ssimokawa#define FW_DEVICE_UPD72874 (0x00f2 << 16) 57170101Ssimokawa#define FW_DEVICE_TITSB22 (0x8009 << 16) 58170101Ssimokawa#define FW_DEVICE_TITSB23 (0x8019 << 16) 59170101Ssimokawa#define FW_DEVICE_TITSB26 (0x8020 << 16) 60170101Ssimokawa#define FW_DEVICE_TITSB43 (0x8021 << 16) 61170101Ssimokawa#define FW_DEVICE_TITSB43A (0x8023 << 16) 62170101Ssimokawa#define FW_DEVICE_TITSB43AB23 (0x8024 << 16) 63170101Ssimokawa#define FW_DEVICE_TITSB82AA2 (0x8025 << 16) 64170101Ssimokawa#define FW_DEVICE_TITSB43AB21 (0x8026 << 16) 65170101Ssimokawa#define FW_DEVICE_TIPCI4410A (0x8017 << 16) 66170101Ssimokawa#define FW_DEVICE_TIPCI4450 (0x8011 << 16) 67170101Ssimokawa#define FW_DEVICE_TIPCI4451 (0x8027 << 16) 68170101Ssimokawa#define FW_DEVICE_CXD1947 (0x8009 << 16) 69170101Ssimokawa#define FW_DEVICE_CXD3222 (0x8039 << 16) 70170101Ssimokawa#define FW_DEVICE_VT6306 (0x3044 << 16) 71170101Ssimokawa#define FW_DEVICE_R5C551 (0x0551 << 16) 72170101Ssimokawa#define FW_DEVICE_R5C552 (0x0552 << 16) 73170101Ssimokawa#define FW_DEVICE_PANGEA (0x0030 << 16) 74170101Ssimokawa#define FW_DEVICE_UNINORTH (0x0031 << 16) 75170101Ssimokawa#define FW_DEVICE_AIC5800 (0x5800 << 16) 76170101Ssimokawa#define FW_DEVICE_FW322 (0x5811 << 16) 77170101Ssimokawa#define FW_DEVICE_7007 (0x7007 << 16) 78170101Ssimokawa#define FW_DEVICE_82372FB (0x7605 << 16) 79170101Ssimokawa 80170101Ssimokawa#define PCI_INTERFACE_OHCI 0x10 81170101Ssimokawa 82170101Ssimokawa#define FW_OHCI_BASE_REG 0x10 83170101Ssimokawa 84170101Ssimokawa#define OHCI_DMA_ITCH 0x20 85170101Ssimokawa#define OHCI_DMA_IRCH 0x20 86170101Ssimokawa 87170101Ssimokawa#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 88170101Ssimokawa 89170101Ssimokawa 90170101Ssimokawatypedef uint32_t fwohcireg_t; 91170101Ssimokawa 92170101Ssimokawa/* for PCI */ 93170101Ssimokawa#if BYTE_ORDER == BIG_ENDIAN 94170101Ssimokawa#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 95170101Ssimokawa#define FWOHCI_DMA_READ(x) le32toh(x) 96170101Ssimokawa#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 97170101Ssimokawa#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 98170101Ssimokawa#else 99170101Ssimokawa#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 100170101Ssimokawa#define FWOHCI_DMA_READ(x) (x) 101170101Ssimokawa#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 102170101Ssimokawa#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 103170101Ssimokawa#endif 104170101Ssimokawa 105170101Ssimokawastruct fwohcidb { 106170101Ssimokawa union { 107170101Ssimokawa struct { 108170101Ssimokawa uint32_t cmd; 109170101Ssimokawa uint32_t addr; 110170101Ssimokawa uint32_t depend; 111170101Ssimokawa uint32_t res; 112170101Ssimokawa } desc; 113170101Ssimokawa uint32_t immed[4]; 114170101Ssimokawa } db; 115170101Ssimokawa#define OHCI_STATUS_SHIFT 16 116170101Ssimokawa#define OHCI_COUNT_MASK 0xffff 117170101Ssimokawa#define OHCI_OUTPUT_MORE (0 << 28) 118170101Ssimokawa#define OHCI_OUTPUT_LAST (1 << 28) 119170101Ssimokawa#define OHCI_INPUT_MORE (2 << 28) 120170101Ssimokawa#define OHCI_INPUT_LAST (3 << 28) 121170101Ssimokawa#define OHCI_STORE_QUAD (4 << 28) 122170101Ssimokawa#define OHCI_LOAD_QUAD (5 << 28) 123170101Ssimokawa#define OHCI_NOP (6 << 28) 124170101Ssimokawa#define OHCI_STOP (7 << 28) 125170101Ssimokawa#define OHCI_STORE (8 << 28) 126170101Ssimokawa#define OHCI_CMD_MASK (0xf << 28) 127170101Ssimokawa 128170101Ssimokawa#define OHCI_UPDATE (1 << 27) 129170101Ssimokawa 130170101Ssimokawa#define OHCI_KEY_ST0 (0 << 24) 131170101Ssimokawa#define OHCI_KEY_ST1 (1 << 24) 132170101Ssimokawa#define OHCI_KEY_ST2 (2 << 24) 133170101Ssimokawa#define OHCI_KEY_ST3 (3 << 24) 134170101Ssimokawa#define OHCI_KEY_REGS (5 << 24) 135170101Ssimokawa#define OHCI_KEY_SYS (6 << 24) 136170101Ssimokawa#define OHCI_KEY_DEVICE (7 << 24) 137170101Ssimokawa#define OHCI_KEY_MASK (7 << 24) 138170101Ssimokawa 139170101Ssimokawa#define OHCI_INTERRUPT_NEVER (0 << 20) 140170101Ssimokawa#define OHCI_INTERRUPT_TRUE (1 << 20) 141170101Ssimokawa#define OHCI_INTERRUPT_FALSE (2 << 20) 142170101Ssimokawa#define OHCI_INTERRUPT_ALWAYS (3 << 20) 143170101Ssimokawa 144170101Ssimokawa#define OHCI_BRANCH_NEVER (0 << 18) 145170101Ssimokawa#define OHCI_BRANCH_TRUE (1 << 18) 146170101Ssimokawa#define OHCI_BRANCH_FALSE (2 << 18) 147170101Ssimokawa#define OHCI_BRANCH_ALWAYS (3 << 18) 148170101Ssimokawa#define OHCI_BRANCH_MASK (3 << 18) 149170101Ssimokawa 150170101Ssimokawa#define OHCI_WAIT_NEVER (0 << 16) 151170101Ssimokawa#define OHCI_WAIT_TRUE (1 << 16) 152170101Ssimokawa#define OHCI_WAIT_FALSE (2 << 16) 153170101Ssimokawa#define OHCI_WAIT_ALWAYS (3 << 16) 154170101Ssimokawa}; 155170101Ssimokawa 156170101Ssimokawa#define OHCI_SPD_S100 0x4 157170101Ssimokawa#define OHCI_SPD_S200 0x1 158170101Ssimokawa#define OHCI_SPD_S400 0x2 159170101Ssimokawa 160170101Ssimokawa 161170101Ssimokawa#define FWOHCIEV_NOSTAT 0 162170101Ssimokawa#define FWOHCIEV_LONGP 2 163170101Ssimokawa#define FWOHCIEV_MISSACK 3 164170101Ssimokawa#define FWOHCIEV_UNDRRUN 4 165170101Ssimokawa#define FWOHCIEV_OVRRUN 5 166170101Ssimokawa#define FWOHCIEV_DESCERR 6 167170101Ssimokawa#define FWOHCIEV_DTRDERR 7 168170101Ssimokawa#define FWOHCIEV_DTWRERR 8 169170101Ssimokawa#define FWOHCIEV_BUSRST 9 170170101Ssimokawa#define FWOHCIEV_TIMEOUT 0xa 171170101Ssimokawa#define FWOHCIEV_TCODERR 0xb 172170101Ssimokawa#define FWOHCIEV_UNKNOWN 0xe 173170101Ssimokawa#define FWOHCIEV_FLUSHED 0xf 174170101Ssimokawa#define FWOHCIEV_ACKCOMPL 0x11 175170101Ssimokawa#define FWOHCIEV_ACKPEND 0x12 176170101Ssimokawa#define FWOHCIEV_ACKBSX 0x14 177170101Ssimokawa#define FWOHCIEV_ACKBSA 0x15 178170101Ssimokawa#define FWOHCIEV_ACKBSB 0x16 179170101Ssimokawa#define FWOHCIEV_ACKTARD 0x1b 180170101Ssimokawa#define FWOHCIEV_ACKDERR 0x1d 181170101Ssimokawa#define FWOHCIEV_ACKTERR 0x1e 182170101Ssimokawa 183170101Ssimokawa#define FWOHCIEV_MASK 0x1f 184170101Ssimokawa 185170101Ssimokawastruct ohci_dma{ 186170101Ssimokawa fwohcireg_t cntl; 187170101Ssimokawa 188170101Ssimokawa#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 189170101Ssimokawa 190170101Ssimokawa#define OHCI_CNTL_BUFFIL (0x1 << 31) 191170101Ssimokawa#define OHCI_CNTL_ISOHDR (0x1 << 30) 192170101Ssimokawa#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 193170101Ssimokawa#define OHCI_CNTL_MULTICH (0x1 << 28) 194170101Ssimokawa 195170101Ssimokawa#define OHCI_CNTL_DMA_RUN (0x1 << 15) 196170101Ssimokawa#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 197170101Ssimokawa#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 198170101Ssimokawa#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 199170101Ssimokawa#define OHCI_CNTL_DMA_BT (0x1 << 8) 200170101Ssimokawa#define OHCI_CNTL_DMA_BAD (0x1 << 7) 201170101Ssimokawa#define OHCI_CNTL_DMA_STAT (0xff) 202170101Ssimokawa 203170101Ssimokawa fwohcireg_t cntl_clr; 204170101Ssimokawa fwohcireg_t dummy0; 205170101Ssimokawa fwohcireg_t cmd; 206170101Ssimokawa fwohcireg_t match; 207170101Ssimokawa fwohcireg_t dummy1; 208170101Ssimokawa fwohcireg_t dummy2; 209170101Ssimokawa fwohcireg_t dummy3; 210170101Ssimokawa}; 211170101Ssimokawa 212170101Ssimokawastruct ohci_itdma{ 213170101Ssimokawa fwohcireg_t cntl; 214170101Ssimokawa fwohcireg_t cntl_clr; 215170101Ssimokawa fwohcireg_t dummy0; 216170101Ssimokawa fwohcireg_t cmd; 217170101Ssimokawa}; 218170101Ssimokawa 219170101Ssimokawastruct ohci_registers { 220170101Ssimokawa fwohcireg_t ver; /* Version No. 0x0 */ 221170101Ssimokawa fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 222170101Ssimokawa fwohcireg_t retry; /* AT retries 0x8 */ 223170101Ssimokawa#define FWOHCI_RETRY 0x8 224170101Ssimokawa fwohcireg_t csr_data; /* CSR data 0xc */ 225170101Ssimokawa fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 226170101Ssimokawa fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 227170101Ssimokawa fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 228170101Ssimokawa fwohcireg_t bus_id; /* BUS_ID 0x1c */ 229170101Ssimokawa fwohcireg_t bus_opt; /* BUS option 0x20 */ 230170101Ssimokawa#define FWOHCIGUID_H 0x24 231170101Ssimokawa#define FWOHCIGUID_L 0x28 232170101Ssimokawa fwohcireg_t guid_hi; /* GUID hi 0x24 */ 233170101Ssimokawa fwohcireg_t guid_lo; /* GUID lo 0x28 */ 234170101Ssimokawa fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 235170101Ssimokawa fwohcireg_t config_rom; /* config ROM map 0x34 */ 236170101Ssimokawa fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 237170101Ssimokawa fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 238170101Ssimokawa fwohcireg_t vender; /* vender ID 0x40 */ 239170101Ssimokawa fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 240170101Ssimokawa fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 241170101Ssimokawa fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 242261455Seadler#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */ 243170101Ssimokawa#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 244170101Ssimokawa#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 245170101Ssimokawa#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 246170101Ssimokawa#define OHCI_HCC_LPS (1 << 19) /* LPS */ 247170101Ssimokawa#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 248170101Ssimokawa#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 249170101Ssimokawa#define OHCI_HCC_RESET (1 << 16) /* softReset */ 250170101Ssimokawa fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 251170101Ssimokawa fwohcireg_t dummy3[1]; /* dummy 0x60 */ 252170101Ssimokawa fwohcireg_t sid_buf; /* self id buffer 0x64 */ 253170101Ssimokawa fwohcireg_t sid_cnt; /* self id count 0x68 */ 254170101Ssimokawa fwohcireg_t dummy4[1]; /* dummy 0x6c */ 255170101Ssimokawa fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 256170101Ssimokawa fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 257170101Ssimokawa fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 258170101Ssimokawa fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 259170101Ssimokawa#define FWOHCI_INTSTAT 0x80 260170101Ssimokawa#define FWOHCI_INTSTATCLR 0x84 261170101Ssimokawa#define FWOHCI_INTMASK 0x88 262170101Ssimokawa#define FWOHCI_INTMASKCLR 0x8c 263170101Ssimokawa fwohcireg_t int_stat; /* 0x80 */ 264170101Ssimokawa fwohcireg_t int_clear; /* 0x84 */ 265170101Ssimokawa fwohcireg_t int_mask; /* 0x88 */ 266170101Ssimokawa fwohcireg_t int_mask_clear; /* 0x8c */ 267170101Ssimokawa fwohcireg_t it_int_stat; /* 0x90 */ 268170101Ssimokawa fwohcireg_t it_int_clear; /* 0x94 */ 269170101Ssimokawa fwohcireg_t it_int_mask; /* 0x98 */ 270170101Ssimokawa fwohcireg_t it_mask_clear; /* 0x9c */ 271170101Ssimokawa fwohcireg_t ir_int_stat; /* 0xa0 */ 272170101Ssimokawa fwohcireg_t ir_int_clear; /* 0xa4 */ 273170101Ssimokawa fwohcireg_t ir_int_mask; /* 0xa8 */ 274170101Ssimokawa fwohcireg_t ir_mask_clear; /* 0xac */ 275170101Ssimokawa fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 276170101Ssimokawa fwohcireg_t fairness; /* fairness control 0xdc */ 277170101Ssimokawa fwohcireg_t link_cntl; /* Chip control 0xe0*/ 278170101Ssimokawa fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 279170101Ssimokawa#define FWOHCI_NODEID 0xe8 280170101Ssimokawa fwohcireg_t node; /* Node ID 0xe8 */ 281261455Seadler#define OHCI_NODE_VALID (1U << 31) 282170101Ssimokawa#define OHCI_NODE_ROOT (1 << 30) 283170101Ssimokawa 284170101Ssimokawa#define OHCI_ASYSRCBUS 1 285170101Ssimokawa 286170101Ssimokawa fwohcireg_t phy_access; /* PHY cntl 0xec */ 287170101Ssimokawa#define PHYDEV_RDDONE (1<<31) 288170101Ssimokawa#define PHYDEV_RDCMD (1<<15) 289170101Ssimokawa#define PHYDEV_WRCMD (1<<14) 290170101Ssimokawa#define PHYDEV_REGADDR 8 291170101Ssimokawa#define PHYDEV_WRDATA 0 292170101Ssimokawa#define PHYDEV_RDADDR 24 293170101Ssimokawa#define PHYDEV_RDDATA 16 294170101Ssimokawa 295170101Ssimokawa fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 296170101Ssimokawa fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 297170101Ssimokawa fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 298170101Ssimokawa fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 299170101Ssimokawa fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 300170101Ssimokawa fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 301170101Ssimokawa fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 302170101Ssimokawa fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 303170101Ssimokawa fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 304170101Ssimokawa fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 305170101Ssimokawa 306170101Ssimokawa fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 307170101Ssimokawa 308170101Ssimokawa fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 309170101Ssimokawa 310170101Ssimokawa /* 0x180, 0x184, 0x188, 0x18c */ 311170101Ssimokawa /* 0x190, 0x194, 0x198, 0x19c */ 312170101Ssimokawa /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 313170101Ssimokawa /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 314170101Ssimokawa /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 315170101Ssimokawa /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 316170101Ssimokawa /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 317170101Ssimokawa /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 318170101Ssimokawa struct ohci_dma dma_ch[0x4]; 319170101Ssimokawa 320170101Ssimokawa /* 0x200, 0x204, 0x208, 0x20c */ 321170101Ssimokawa /* 0x210, 0x204, 0x208, 0x20c */ 322170101Ssimokawa struct ohci_itdma dma_itch[0x20]; 323170101Ssimokawa 324170101Ssimokawa /* 0x400, 0x404, 0x408, 0x40c */ 325170101Ssimokawa /* 0x410, 0x404, 0x408, 0x40c */ 326170101Ssimokawa struct ohci_dma dma_irch[0x20]; 327170101Ssimokawa}; 328170101Ssimokawa 329170101Ssimokawa#define OHCI_CNTL_CYCSRC (0x1 << 22) 330170101Ssimokawa#define OHCI_CNTL_CYCMTR (0x1 << 21) 331170101Ssimokawa#define OHCI_CNTL_CYCTIMER (0x1 << 20) 332170101Ssimokawa#define OHCI_CNTL_PHYPKT (0x1 << 10) 333170101Ssimokawa#define OHCI_CNTL_SID (0x1 << 9) 334170101Ssimokawa 335170101Ssimokawa#define OHCI_INT_DMA_ATRQ (0x1 << 0) 336170101Ssimokawa#define OHCI_INT_DMA_ATRS (0x1 << 1) 337170101Ssimokawa#define OHCI_INT_DMA_ARRQ (0x1 << 2) 338170101Ssimokawa#define OHCI_INT_DMA_ARRS (0x1 << 3) 339170101Ssimokawa#define OHCI_INT_DMA_PRRQ (0x1 << 4) 340170101Ssimokawa#define OHCI_INT_DMA_PRRS (0x1 << 5) 341170101Ssimokawa#define OHCI_INT_DMA_IT (0x1 << 6) 342170101Ssimokawa#define OHCI_INT_DMA_IR (0x1 << 7) 343170101Ssimokawa#define OHCI_INT_PW_ERR (0x1 << 8) 344170101Ssimokawa#define OHCI_INT_LR_ERR (0x1 << 9) 345170101Ssimokawa 346170101Ssimokawa#define OHCI_INT_PHY_SID (0x1 << 16) 347170101Ssimokawa#define OHCI_INT_PHY_BUS_R (0x1 << 17) 348170101Ssimokawa 349170101Ssimokawa#define OHCI_INT_REG_FAIL (0x1 << 18) 350170101Ssimokawa 351170101Ssimokawa#define OHCI_INT_PHY_INT (0x1 << 19) 352170101Ssimokawa#define OHCI_INT_CYC_START (0x1 << 20) 353170101Ssimokawa#define OHCI_INT_CYC_64SECOND (0x1 << 21) 354170101Ssimokawa#define OHCI_INT_CYC_LOST (0x1 << 22) 355170101Ssimokawa#define OHCI_INT_CYC_ERR (0x1 << 23) 356170101Ssimokawa 357170101Ssimokawa#define OHCI_INT_ERR (0x1 << 24) 358170101Ssimokawa#define OHCI_INT_CYC_LONG (0x1 << 25) 359170101Ssimokawa#define OHCI_INT_PHY_REG (0x1 << 26) 360170101Ssimokawa 361170101Ssimokawa#define OHCI_INT_EN (0x1 << 31) 362170101Ssimokawa 363170101Ssimokawa#define IP_CHANNELS 0x0234 364170101Ssimokawa#define FWOHCI_MAXREC 2048 365170101Ssimokawa 366170101Ssimokawa#define OHCI_ISORA 0x02 367170101Ssimokawa#define OHCI_ISORB 0x04 368170101Ssimokawa 369170101Ssimokawa#define FWOHCITCODE_PHY 0xe 370