p1020rdb.dts revision 266364
1/* 2 * P1020 RDB Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* $FreeBSD: stable/10/sys/boot/fdt/dts/powerpc/p1020rdb.dts 266364 2014-05-17 21:55:00Z ian $ */ 35 36/dts-v1/; 37 38/ { 39 model = "fsl,P1020"; 40 compatible = "fsl,P1020RDB"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 44 aliases { 45 serial0 = &serial0; 46 serial1 = &serial1; 47 ethernet0 = &enet0; 48 ethernet1 = &enet1; 49 ethernet2 = &enet2; 50 pci0 = &pci0; 51 pci1 = &pci1; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 PowerPC,P1020@0 { 59 device_type = "cpu"; 60 reg = <0x0>; 61 next-level-cache = <&L2>; 62 }; 63 64 PowerPC,P1020@1 { 65 device_type = "cpu"; 66 reg = <0x1>; 67 next-level-cache = <&L2>; 68 }; 69 }; 70 71 memory { 72 device_type = "memory"; 73 }; 74 75 localbus@ffe05000 { 76 #address-cells = <2>; 77 #size-cells = <1>; 78 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; 79 reg = <0 0xffe05000 0 0x1000>; 80 interrupts = <19 2>; 81 interrupt-parent = <&mpic>; 82 83 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 84 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 85 0x1 0x0 0x0 0xffa00000 0x00040000 86 0x2 0x0 0x0 0xffb00000 0x00020000>; 87 88 nor@0,0 { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "cfi-flash"; 92 reg = <0x0 0x0 0x1000000>; 93 bank-width = <2>; 94 device-width = <1>; 95 96 partition@0 { 97 /* This location must not be altered */ 98 /* 256KB for Vitesse 7385 Switch firmware */ 99 reg = <0x0 0x00040000>; 100 label = "NOR (RO) Vitesse-7385 Firmware"; 101 read-only; 102 }; 103 104 partition@40000 { 105 /* 256KB for DTB Image */ 106 reg = <0x00040000 0x00040000>; 107 label = "NOR (RO) DTB Image"; 108 read-only; 109 }; 110 111 partition@80000 { 112 /* 3.5 MB for Linux Kernel Image */ 113 reg = <0x00080000 0x00380000>; 114 label = "NOR (RO) Linux Kernel Image"; 115 read-only; 116 }; 117 118 partition@400000 { 119 /* 11MB for JFFS2 based Root file System */ 120 reg = <0x00400000 0x00b00000>; 121 label = "NOR (RW) JFFS2 Root File System"; 122 }; 123 124 partition@f00000 { 125 /* This location must not be altered */ 126 /* 512KB for u-boot Bootloader Image */ 127 /* 512KB for u-boot Environment Variables */ 128 reg = <0x00f00000 0x00100000>; 129 label = "NOR (RO) U-Boot Image"; 130 read-only; 131 }; 132 }; 133 134 nand@1,0 { 135 #address-cells = <1>; 136 #size-cells = <1>; 137 compatible = "fsl,p1020-fcm-nand", 138 "fsl,elbc-fcm-nand"; 139 reg = <0x1 0x0 0x40000>; 140 141 partition@0 { 142 /* This location must not be altered */ 143 /* 1MB for u-boot Bootloader Image */ 144 reg = <0x0 0x00100000>; 145 label = "NAND (RO) U-Boot Image"; 146 read-only; 147 }; 148 149 partition@100000 { 150 /* 1MB for DTB Image */ 151 reg = <0x00100000 0x00100000>; 152 label = "NAND (RO) DTB Image"; 153 read-only; 154 }; 155 156 partition@200000 { 157 /* 4MB for Linux Kernel Image */ 158 reg = <0x00200000 0x00400000>; 159 label = "NAND (RO) Linux Kernel Image"; 160 read-only; 161 }; 162 163 partition@600000 { 164 /* 4MB for Compressed Root file System Image */ 165 reg = <0x00600000 0x00400000>; 166 label = "NAND (RO) Compressed RFS Image"; 167 read-only; 168 }; 169 170 partition@a00000 { 171 /* 7MB for JFFS2 based Root file System */ 172 reg = <0x00a00000 0x00700000>; 173 label = "NAND (RW) JFFS2 Root File System"; 174 }; 175 176 partition@1100000 { 177 /* 15MB for JFFS2 based Root file System */ 178 reg = <0x01100000 0x00f00000>; 179 label = "NAND (RW) Writable User area"; 180 }; 181 }; 182 183 L2switch@2,0 { 184 #address-cells = <1>; 185 #size-cells = <1>; 186 compatible = "vitesse-7385"; 187 reg = <0x2 0x0 0x20000>; 188 }; 189 190 }; 191 192 soc@ffe00000 { 193 #address-cells = <1>; 194 #size-cells = <1>; 195 device_type = "soc"; 196 compatible = "fsl,p1020-immr", "simple-bus"; 197 ranges = <0x0 0x0 0xffe00000 0x100000>; 198 bus-frequency = <0>; // Filled out by uboot. 199 200 ecm-law@0 { 201 compatible = "fsl,ecm-law"; 202 reg = <0x0 0x1000>; 203 fsl,num-laws = <12>; 204 }; 205 206 ecm@1000 { 207 compatible = "fsl,p1020-ecm", "fsl,ecm"; 208 reg = <0x1000 0x1000>; 209 interrupts = <16 2>; 210 interrupt-parent = <&mpic>; 211 }; 212 213 memory-controller@2000 { 214 compatible = "fsl,p1020-memory-controller"; 215 reg = <0x2000 0x1000>; 216 interrupt-parent = <&mpic>; 217 interrupts = <16 2>; 218 }; 219 220 i2c@3000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 cell-index = <0>; 224 compatible = "fsl-i2c"; 225 reg = <0x3000 0x100>; 226 interrupts = <43 2>; 227 interrupt-parent = <&mpic>; 228 dfsrr; 229 rtc@68 { 230 compatible = "dallas,ds1339"; 231 reg = <0x68>; 232 }; 233 }; 234 235 i2c@3100 { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 cell-index = <1>; 239 compatible = "fsl-i2c"; 240 reg = <0x3100 0x100>; 241 interrupts = <43 2>; 242 interrupt-parent = <&mpic>; 243 dfsrr; 244 }; 245 246 serial0: serial@4500 { 247 cell-index = <0>; 248 device_type = "serial"; 249 compatible = "ns16550"; 250 reg = <0x4500 0x100>; 251 clock-frequency = <0>; 252 interrupts = <42 2>; 253 interrupt-parent = <&mpic>; 254 }; 255 256 serial1: serial@4600 { 257 cell-index = <1>; 258 device_type = "serial"; 259 compatible = "ns16550"; 260 reg = <0x4600 0x100>; 261 clock-frequency = <0>; 262 interrupts = <42 2>; 263 interrupt-parent = <&mpic>; 264 }; 265 266 spi@7000 { 267 cell-index = <0>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "fsl,espi"; 271 reg = <0x7000 0x1000>; 272 interrupts = <59 0x2>; 273 interrupt-parent = <&mpic>; 274 mode = "cpu"; 275 276 fsl_m25p80@0 { 277 #address-cells = <1>; 278 #size-cells = <1>; 279 compatible = "fsl,espi-flash"; 280 reg = <0>; 281 linux,modalias = "fsl_m25p80"; 282 modal = "s25sl128b"; 283 spi-max-frequency = <50000000>; 284 mode = <0>; 285 286 partition@0 { 287 /* 512KB for u-boot Bootloader Image */ 288 reg = <0x0 0x00080000>; 289 label = "SPI (RO) U-Boot Image"; 290 read-only; 291 }; 292 293 partition@80000 { 294 /* 512KB for DTB Image */ 295 reg = <0x00080000 0x00080000>; 296 label = "SPI (RO) DTB Image"; 297 read-only; 298 }; 299 300 partition@100000 { 301 /* 4MB for Linux Kernel Image */ 302 reg = <0x00100000 0x00400000>; 303 label = "SPI (RO) Linux Kernel Image"; 304 read-only; 305 }; 306 307 partition@500000 { 308 /* 4MB for Compressed RFS Image */ 309 reg = <0x00500000 0x00400000>; 310 label = "SPI (RO) Compressed RFS Image"; 311 read-only; 312 }; 313 314 partition@900000 { 315 /* 7MB for JFFS2 based RFS */ 316 reg = <0x00900000 0x00700000>; 317 label = "SPI (RW) JFFS2 RFS"; 318 }; 319 }; 320 }; 321 322 gpio: gpio-controller@f000 { 323 #gpio-cells = <2>; 324 compatible = "fsl,mpc8572-gpio"; 325 reg = <0xf000 0x100>; 326 interrupts = <47 0x2>; 327 interrupt-parent = <&mpic>; 328 gpio-controller; 329 }; 330 331 L2: l2-cache-controller@20000 { 332 compatible = "fsl,p1020-l2-cache-controller"; 333 reg = <0x20000 0x1000>; 334 cache-line-size = <32>; // 32 bytes 335 cache-size = <0x40000>; // L2,256K 336 interrupt-parent = <&mpic>; 337 interrupts = <16 2>; 338 }; 339 340 dma@21300 { 341 #address-cells = <1>; 342 #size-cells = <1>; 343 compatible = "fsl,eloplus-dma"; 344 reg = <0x21300 0x4>; 345 ranges = <0x0 0x21100 0x200>; 346 cell-index = <0>; 347 dma-channel@0 { 348 compatible = "fsl,eloplus-dma-channel"; 349 reg = <0x0 0x80>; 350 cell-index = <0>; 351 interrupt-parent = <&mpic>; 352 interrupts = <20 2>; 353 }; 354 dma-channel@80 { 355 compatible = "fsl,eloplus-dma-channel"; 356 reg = <0x80 0x80>; 357 cell-index = <1>; 358 interrupt-parent = <&mpic>; 359 interrupts = <21 2>; 360 }; 361 dma-channel@100 { 362 compatible = "fsl,eloplus-dma-channel"; 363 reg = <0x100 0x80>; 364 cell-index = <2>; 365 interrupt-parent = <&mpic>; 366 interrupts = <22 2>; 367 }; 368 dma-channel@180 { 369 compatible = "fsl,eloplus-dma-channel"; 370 reg = <0x180 0x80>; 371 cell-index = <3>; 372 interrupt-parent = <&mpic>; 373 interrupts = <23 2>; 374 }; 375 }; 376 377 mdio@24000 { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 compatible = "fsl,etsec2-mdio"; 381 reg = <0x24000 0x1000 0xb0030 0x4>; 382 383 phy0: ethernet-phy@0 { 384 interrupt-parent = <&mpic>; 385 interrupts = <3 1>; 386 reg = <0x0>; 387 }; 388 389 phy1: ethernet-phy@1 { 390 interrupt-parent = <&mpic>; 391 interrupts = <2 1>; 392 reg = <0x1>; 393 }; 394 }; 395 396 mdio@25000 { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 compatible = "fsl,etsec2-tbi"; 400 reg = <0x25000 0x1000 0xb1030 0x4>; 401 402 tbi0: tbi-phy@11 { 403 reg = <0x11>; 404 device_type = "tbi-phy"; 405 }; 406 }; 407 408 enet0: ethernet@b0000 { 409 #address-cells = <1>; 410 #size-cells = <1>; 411 device_type = "network"; 412 model = "eTSEC"; 413 compatible = "fsl,etsec2"; 414 fsl,num_rx_queues = <0x8>; 415 fsl,num_tx_queues = <0x8>; 416 local-mac-address = [ 00 00 00 00 00 00 ]; 417 interrupt-parent = <&mpic>; 418 fixed-link = <1 1 1000 0 0>; 419 phy-connection-type = "rgmii-id"; 420 421 queue-group@0 { 422 #address-cells = <1>; 423 #size-cells = <1>; 424 reg = <0xb0000 0x1000>; 425 interrupts = <29 2 30 2 34 2>; 426 }; 427 428 queue-group@1 { 429 #address-cells = <1>; 430 #size-cells = <1>; 431 reg = <0xb4000 0x1000>; 432 interrupts = <17 2 18 2 24 2>; 433 }; 434 }; 435 436 enet1: ethernet@b1000 { 437 #address-cells = <1>; 438 #size-cells = <1>; 439 device_type = "network"; 440 model = "eTSEC"; 441 compatible = "fsl,etsec2"; 442 fsl,num_rx_queues = <0x8>; 443 fsl,num_tx_queues = <0x8>; 444 local-mac-address = [ 00 00 00 00 00 00 ]; 445 interrupt-parent = <&mpic>; 446 phy-handle = <&phy0>; 447 tbi-handle = <&tbi0>; 448 phy-connection-type = "sgmii"; 449 450 queue-group@0 { 451 #address-cells = <1>; 452 #size-cells = <1>; 453 reg = <0xb1000 0x1000>; 454 interrupts = <35 2 36 2 40 2>; 455 }; 456 457 queue-group@1 { 458 #address-cells = <1>; 459 #size-cells = <1>; 460 reg = <0xb5000 0x1000>; 461 interrupts = <51 2 52 2 67 2>; 462 }; 463 }; 464 465 enet2: ethernet@b2000 { 466 #address-cells = <1>; 467 #size-cells = <1>; 468 device_type = "network"; 469 model = "eTSEC"; 470 compatible = "fsl,etsec2"; 471 fsl,num_rx_queues = <0x8>; 472 fsl,num_tx_queues = <0x8>; 473 local-mac-address = [ 00 00 00 00 00 00 ]; 474 interrupt-parent = <&mpic>; 475 phy-handle = <&phy1>; 476 phy-connection-type = "rgmii-id"; 477 478 queue-group@0 { 479 #address-cells = <1>; 480 #size-cells = <1>; 481 reg = <0xb2000 0x1000>; 482 interrupts = <31 2 32 2 33 2>; 483 }; 484 485 queue-group@1 { 486 #address-cells = <1>; 487 #size-cells = <1>; 488 reg = <0xb6000 0x1000>; 489 interrupts = <25 2 26 2 27 2>; 490 }; 491 }; 492 493 usb@22000 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 compatible = "fsl-usb2-dr"; 497 reg = <0x22000 0x1000>; 498 interrupt-parent = <&mpic>; 499 interrupts = <28 0x2>; 500 phy_type = "ulpi"; 501 }; 502 503 /* USB2 is shared with localbus, so it must be disabled 504 by default. We can't put 'status = "disabled";' here 505 since U-Boot doesn't clear the status property when 506 it enables USB2. OTOH, U-Boot does create a new node 507 when there isn't any. So, just comment it out. 508 usb@23000 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 compatible = "fsl-usb2-dr"; 512 reg = <0x23000 0x1000>; 513 interrupt-parent = <&mpic>; 514 interrupts = <46 0x2>; 515 phy_type = "ulpi"; 516 }; 517 */ 518 519 sdhci@2e000 { 520 compatible = "fsl,p1020-esdhc", "fsl,esdhc"; 521 reg = <0x2e000 0x1000>; 522 interrupts = <72 0x2>; 523 interrupt-parent = <&mpic>; 524 /* Filled in by U-Boot */ 525 clock-frequency = <0>; 526 }; 527 528 crypto@30000 { 529 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", 530 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 531 reg = <0x30000 0x10000>; 532 interrupts = <45 2 58 2>; 533 interrupt-parent = <&mpic>; 534 fsl,num-channels = <4>; 535 fsl,channel-fifo-len = <24>; 536 fsl,exec-units-mask = <0xbfe>; 537 fsl,descriptor-types-mask = <0x3ab0ebf>; 538 }; 539 540 mpic: pic@40000 { 541 interrupt-controller; 542 #address-cells = <0>; 543 #interrupt-cells = <2>; 544 reg = <0x40000 0x40000>; 545 compatible = "chrp,open-pic"; 546 device_type = "open-pic"; 547 }; 548 549 msi@41600 { 550 compatible = "fsl,p1020-msi", "fsl,mpic-msi"; 551 reg = <0x41600 0x80>; 552 msi-available-ranges = <0 0x100>; 553 interrupts = < 554 0xe0 0 555 0xe1 0 556 0xe2 0 557 0xe3 0 558 0xe4 0 559 0xe5 0 560 0xe6 0 561 0xe7 0>; 562 interrupt-parent = <&mpic>; 563 }; 564 565 global-utilities@e0000 { //global utilities block 566 compatible = "fsl,p1020-guts"; 567 reg = <0xe0000 0x1000>; 568 fsl,has-rstcr; 569 }; 570 }; 571 572 pci0: pcie@ffe09000 { 573 compatible = "fsl,mpc8548-pcie"; 574 device_type = "pci"; 575 #interrupt-cells = <1>; 576 #size-cells = <2>; 577 #address-cells = <3>; 578 reg = <0 0xffe09000 0 0x1000>; 579 bus-range = <0 255>; 580 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 581 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 582 clock-frequency = <33333333>; 583 interrupt-parent = <&mpic>; 584 interrupts = <16 2>; 585 pcie@0 { 586 reg = <0x0 0x0 0x0 0x0 0x0>; 587 #size-cells = <2>; 588 #address-cells = <3>; 589 device_type = "pci"; 590 ranges = <0x2000000 0x0 0xa0000000 591 0x2000000 0x0 0xa0000000 592 0x0 0x20000000 593 594 0x1000000 0x0 0x0 595 0x1000000 0x0 0x0 596 0x0 0x100000>; 597 }; 598 }; 599 600 pci1: pcie@ffe0a000 { 601 compatible = "fsl,mpc8548-pcie"; 602 device_type = "pci"; 603 #interrupt-cells = <1>; 604 #size-cells = <2>; 605 #address-cells = <3>; 606 reg = <0 0xffe0a000 0 0x1000>; 607 bus-range = <0 255>; 608 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 609 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 610 clock-frequency = <33333333>; 611 interrupt-parent = <&mpic>; 612 interrupts = <16 2>; 613 pcie@0 { 614 reg = <0x0 0x0 0x0 0x0 0x0>; 615 #size-cells = <2>; 616 #address-cells = <3>; 617 device_type = "pci"; 618 ranges = <0x2000000 0x0 0xc0000000 619 0x2000000 0x0 0xc0000000 620 0x0 0x20000000 621 622 0x1000000 0x0 0x0 623 0x1000000 0x0 0x0 624 0x0 0x100000>; 625 }; 626 }; 627}; 628