exynos5250.dtsi revision 266332
1/*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/exynos5250.dtsi 266332 2014-05-17 17:54:38Z ian $ 27 */ 28 29/ { 30 compatible = "samsung,exynos5250"; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 interrupt-parent = <&GIC>; 34 35 aliases { 36 soc = &SOC; 37 serial0 = &serial0; 38 serial1 = &serial1; 39 clk0 = &clk0; 40 dp0 = &dp0; 41 fimd0 = &fimd0; 42 }; 43 44 SOC: Exynos5@0 { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 compatible = "simple-bus"; 48 ranges; 49 bus-frequency = <0>; 50 51 GIC: interrupt-controller@10481000 { 52 compatible = "arm,gic"; 53 reg = < 0x10481000 0x1000 >, /* Distributor Registers */ 54 < 0x10482000 0x2000 >; /* CPU Interface Registers */ 55 interrupt-controller; 56 #address-cells = <0>; 57 #interrupt-cells = <1>; 58 }; 59 60 clk0: clk@10010000 { 61 compatible = "exynos,clk"; 62 reg = < 0x10020000 0x20000 >; 63 }; 64 65 mct { 66 compatible = "exynos,mct"; 67 reg = < 0x101C0000 0x1000 >; 68 clock-frequency = <24000000>; 69 }; 70 71 generic_timer { 72 compatible = "arm,armv7-timer"; 73 clock-frequency = <24000000>; 74 }; 75 76 pwm { 77 compatible = "samsung,s3c24x0-timer"; 78 reg = <0x12DD0000 0x1000>; 79 interrupts = < 71 >; 80 interrupt-parent = <&GIC>; 81 clock-frequency = <24000000>; 82 }; 83 84 usb@12110000 { 85 compatible = "exynos,usb-ehci", "usb-ehci"; 86 reg = <0x12110000 0x1000>, /* EHCI */ 87 <0x12130000 0x1000>, /* EHCI host ctrl */ 88 <0x10040000 0x1000>, /* Power */ 89 <0x10050230 0x10>, /* Sysreg */ 90 <0x11400C60 0x10>; /* GPIO left */ 91 interrupts = < 103 >; 92 interrupt-parent = <&GIC>; 93 }; 94 95 usb@12120000 { 96 compatible = "exynos,usb-ohci", "usb-ohci"; 97 reg = <0x12120000 0x10000>; 98 interrupts = < 103 >; 99 interrupt-parent = <&GIC>; 100 }; 101 102 sdhci@12200000 { 103 compatible = "sdhci_generic"; 104 reg = <0x12200000 0x1000>; 105 interrupts = <107>; 106 interrupt-parent = <&GIC>; 107 clock-frequency = <24000000>; /* TODO: verify freq */ 108 }; 109 110 sdhci@12210000 { 111 compatible = "sdhci_generic"; 112 reg = <0x12210000 0x1000>; 113 interrupts = <108>; 114 interrupt-parent = <&GIC>; 115 clock-frequency = <24000000>; 116 }; 117 118 sdhci@12220000 { 119 compatible = "sdhci_generic"; 120 reg = <0x12220000 0x1000>; 121 interrupts = <109>; 122 interrupt-parent = <&GIC>; 123 clock-frequency = <24000000>; 124 }; 125 126 sdhci@12230000 { 127 compatible = "sdhci_generic"; 128 reg = <0x12230000 0x1000>; 129 interrupts = <110>; 130 interrupt-parent = <&GIC>; 131 clock-frequency = <24000000>; 132 }; 133 134 serial0: serial@12C00000 { 135 compatible = "exynos"; 136 reg = <0x12C00000 0x100>; 137 interrupts = < 83 >; 138 interrupt-parent = <&GIC>; 139 clock-frequency = < 100000000 >; 140 current-speed = <115200>; 141 }; 142 143 serial1: serial@12C10000 { 144 compatible = "exynos"; 145 reg = <0x12C10000 0x100>; 146 interrupts = < 84 >; 147 interrupt-parent = <&GIC>; 148 clock-frequency = < 100000000 >; 149 current-speed = <115200>; 150 }; 151 152 serial2: serial@12C20000 { 153 compatible = "exynos"; 154 reg = <0x12C20000 0x100>; 155 interrupts = < 85 >; 156 interrupt-parent = <&GIC>; 157 clock-frequency = < 100000000 >; 158 current-speed = <115200>; 159 }; 160 161 serial3: serial@12C30000 { 162 compatible = "exynos"; 163 reg = <0x12C30000 0x100>; 164 interrupts = < 86 >; 165 interrupt-parent = <&GIC>; 166 clock-frequency = < 100000000 >; 167 current-speed = <115200>; 168 }; 169 170 fimd0: fimd@14400000 { 171 compatible = "exynos,fimd"; 172 status = "disabled"; 173 reg = < 0x14400000 0x10000 >, /* fimd */ 174 < 0x14420000 0x10000 >, /* disp */ 175 < 0x10050000 0x220 >; /* sysreg */ 176 interrupt-parent = <&GIC>; 177 }; 178 179 dp0: dp@145B0000 { 180 compatible = "exynos,dp"; 181 status = "disabled"; 182 reg = < 0x145B0000 0x10000 >, 183 < 0x10040720 0x10 >; /* PHY */ 184 interrupt-parent = <&GIC>; 185 }; 186 }; 187}; 188