efipciio.h revision 295872
1/* $FreeBSD: stable/10/sys/boot/efi/include/efipciio.h 295872 2016-02-22 00:49:35Z marius $ */ 2/** @file 3 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, 4 and DMA interfaces that a driver uses to access its PCI controller. 5 6 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> 7 This program and the accompanying materials 8 are licensed and made available under the terms and conditions of the BSD License 9 which accompanies this distribution. The full text of the license may be found at 10 http://opensource.org/licenses/bsd-license.php 11 12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 15**/ 16 17#ifndef __PCI_IO_H__ 18#define __PCI_IO_H__ 19 20/// 21/// Global ID for the PCI I/O Protocol 22/// 23#define EFI_PCI_IO_PROTOCOL_GUID \ 24 { 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a} } 25 26typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL; 27 28/// 29/// ******************************************************* 30/// EFI_PCI_IO_PROTOCOL_WIDTH 31/// ******************************************************* 32/// 33typedef enum { 34 EfiPciIoWidthUint8 = 0, 35 EfiPciIoWidthUint16, 36 EfiPciIoWidthUint32, 37 EfiPciIoWidthUint64, 38 EfiPciIoWidthFifoUint8, 39 EfiPciIoWidthFifoUint16, 40 EfiPciIoWidthFifoUint32, 41 EfiPciIoWidthFifoUint64, 42 EfiPciIoWidthFillUint8, 43 EfiPciIoWidthFillUint16, 44 EfiPciIoWidthFillUint32, 45 EfiPciIoWidthFillUint64, 46 EfiPciIoWidthMaximum 47} EFI_PCI_IO_PROTOCOL_WIDTH; 48 49// 50// Complete PCI address generater 51// 52#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged 53#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles 54#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode) 55#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode) 56#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode) 57#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode) 58#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode) 59#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode) 60#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode) 61#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined 62#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header 63#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header 64#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header 65#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached 66#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range 67#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device 68#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR 69#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC 70#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode) 71#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode) 72#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode) 73 74#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) 75#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO) 76 77/// 78/// ******************************************************* 79/// EFI_PCI_IO_PROTOCOL_OPERATION 80/// ******************************************************* 81/// 82typedef enum { 83 /// 84 /// A read operation from system memory by a bus master. 85 /// 86 EfiPciIoOperationBusMasterRead, 87 /// 88 /// A write operation from system memory by a bus master. 89 /// 90 EfiPciIoOperationBusMasterWrite, 91 /// 92 /// Provides both read and write access to system memory by both the processor and a 93 /// bus master. The buffer is coherent from both the processor's and the bus master's point of view. 94 /// 95 EfiPciIoOperationBusMasterCommonBuffer, 96 EfiPciIoOperationMaximum 97} EFI_PCI_IO_PROTOCOL_OPERATION; 98 99/// 100/// ******************************************************* 101/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION 102/// ******************************************************* 103/// 104typedef enum { 105 /// 106 /// Retrieve the PCI controller's current attributes, and return them in Result. 107 /// 108 EfiPciIoAttributeOperationGet, 109 /// 110 /// Set the PCI controller's current attributes to Attributes. 111 /// 112 EfiPciIoAttributeOperationSet, 113 /// 114 /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller. 115 /// 116 EfiPciIoAttributeOperationEnable, 117 /// 118 /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller. 119 /// 120 EfiPciIoAttributeOperationDisable, 121 /// 122 /// Retrieve the PCI controller's supported attributes, and return them in Result. 123 /// 124 EfiPciIoAttributeOperationSupported, 125 EfiPciIoAttributeOperationMaximum 126} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION; 127 128/** 129 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is 130 satisfied or after a defined duration. 131 132 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 133 @param Width Signifies the width of the memory or I/O operations. 134 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 135 base address for the memory operation to perform. 136 @param Offset The offset within the selected BAR to start the memory operation. 137 @param Mask Mask used for the polling criteria. 138 @param Value The comparison value used for the polling exit criteria. 139 @param Delay The number of 100 ns units to poll. 140 @param Result Pointer to the last value read from the memory location. 141 142 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 143 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 144 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller. 145 @retval EFI_TIMEOUT Delay expired before a match occurred. 146 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 147 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 148 149**/ 150typedef 151EFI_STATUS 152(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)( 153 IN EFI_PCI_IO_PROTOCOL *This, 154 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 155 IN UINT8 BarIndex, 156 IN UINT64 Offset, 157 IN UINT64 Mask, 158 IN UINT64 Value, 159 IN UINT64 Delay, 160 OUT UINT64 *Result 161 ); 162 163/** 164 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space. 165 166 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 167 @param Width Signifies the width of the memory or I/O operations. 168 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 169 base address for the memory or I/O operation to perform. 170 @param Offset The offset within the selected BAR to start the memory or I/O operation. 171 @param Count The number of memory or I/O operations to perform. 172 @param Buffer For read operations, the destination buffer to store the results. For write 173 operations, the source buffer to write data from. 174 175 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 176 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 177 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 178 valid for the PCI BAR specified by BarIndex. 179 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 180 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 181 182**/ 183typedef 184EFI_STATUS 185(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)( 186 IN EFI_PCI_IO_PROTOCOL *This, 187 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 188 IN UINT8 BarIndex, 189 IN UINT64 Offset, 190 IN UINTN Count, 191 IN OUT VOID *Buffer 192 ); 193 194typedef struct { 195 /// 196 /// Read PCI controller registers in the PCI memory or I/O space. 197 /// 198 EFI_PCI_IO_PROTOCOL_IO_MEM Read; 199 /// 200 /// Write PCI controller registers in the PCI memory or I/O space. 201 /// 202 EFI_PCI_IO_PROTOCOL_IO_MEM Write; 203} EFI_PCI_IO_PROTOCOL_ACCESS; 204 205/** 206 Enable a PCI driver to access PCI controller registers in PCI configuration space. 207 208 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 209 @param Width Signifies the width of the memory operations. 210 @param Offset The offset within the PCI configuration space for the PCI controller. 211 @param Count The number of PCI configuration operations to perform. 212 @param Buffer For read operations, the destination buffer to store the results. For write 213 operations, the source buffer to write data from. 214 215 216 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 217 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 218 valid for the PCI configuration header of the PCI controller. 219 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 220 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. 221 222**/ 223typedef 224EFI_STATUS 225(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)( 226 IN EFI_PCI_IO_PROTOCOL *This, 227 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 228 IN UINT32 Offset, 229 IN UINTN Count, 230 IN OUT VOID *Buffer 231 ); 232 233typedef struct { 234 /// 235 /// Read PCI controller registers in PCI configuration space. 236 /// 237 EFI_PCI_IO_PROTOCOL_CONFIG Read; 238 /// 239 /// Write PCI controller registers in PCI configuration space. 240 /// 241 EFI_PCI_IO_PROTOCOL_CONFIG Write; 242} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; 243 244/** 245 Enables a PCI driver to copy one region of PCI memory space to another region of PCI 246 memory space. 247 248 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 249 @param Width Signifies the width of the memory operations. 250 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the 251 base address for the memory operation to perform. 252 @param DestOffset The destination offset within the BAR specified by DestBarIndex to 253 start the memory writes for the copy operation. 254 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the 255 base address for the memory operation to perform. 256 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start 257 the memory reads for the copy operation. 258 @param Count The number of memory operations to perform. Bytes moved is Width 259 size * Count, starting at DestOffset and SrcOffset. 260 261 @retval EFI_SUCCESS The data was copied from one memory region to another memory region. 262 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller. 263 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller. 264 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count 265 is not valid for the PCI BAR specified by DestBarIndex. 266 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is 267 not valid for the PCI BAR specified by SrcBarIndex. 268 @retval EFI_INVALID_PARAMETER Width is invalid. 269 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 270 271**/ 272typedef 273EFI_STATUS 274(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)( 275 IN EFI_PCI_IO_PROTOCOL *This, 276 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 277 IN UINT8 DestBarIndex, 278 IN UINT64 DestOffset, 279 IN UINT8 SrcBarIndex, 280 IN UINT64 SrcOffset, 281 IN UINTN Count 282 ); 283 284/** 285 Provides the PCI controller-specific addresses needed to access system memory. 286 287 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 288 @param Operation Indicates if the bus master is going to read or write to system memory. 289 @param HostAddress The system memory address to map to the PCI controller. 290 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes 291 that were mapped. 292 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 293 access the hosts HostAddress. 294 @param Mapping A resulting value to pass to Unmap(). 295 296 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 297 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. 298 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 299 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 300 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. 301 302**/ 303typedef 304EFI_STATUS 305(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)( 306 IN EFI_PCI_IO_PROTOCOL *This, 307 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, 308 IN VOID *HostAddress, 309 IN OUT UINTN *NumberOfBytes, 310 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 311 OUT VOID **Mapping 312 ); 313 314/** 315 Completes the Map() operation and releases any corresponding resources. 316 317 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 318 @param Mapping The mapping value returned from Map(). 319 320 @retval EFI_SUCCESS The range was unmapped. 321 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. 322 323**/ 324typedef 325EFI_STATUS 326(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)( 327 IN EFI_PCI_IO_PROTOCOL *This, 328 IN VOID *Mapping 329 ); 330 331/** 332 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer 333 mapping. 334 335 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 336 @param Type This parameter is not used and must be ignored. 337 @param MemoryType The type of memory to allocate, EfiBootServicesData or 338 EfiRuntimeServicesData. 339 @param Pages The number of pages to allocate. 340 @param HostAddress A pointer to store the base system memory address of the 341 allocated range. 342 @param Attributes The requested bit mask of attributes for the allocated range. 343 344 @retval EFI_SUCCESS The requested memory pages were allocated. 345 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are 346 MEMORY_WRITE_COMBINE and MEMORY_CACHED. 347 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 348 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. 349 350**/ 351typedef 352EFI_STATUS 353(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)( 354 IN EFI_PCI_IO_PROTOCOL *This, 355 IN EFI_ALLOCATE_TYPE Type, 356 IN EFI_MEMORY_TYPE MemoryType, 357 IN UINTN Pages, 358 OUT VOID **HostAddress, 359 IN UINT64 Attributes 360 ); 361 362/** 363 Frees memory that was allocated with AllocateBuffer(). 364 365 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 366 @param Pages The number of pages to free. 367 @param HostAddress The base system memory address of the allocated range. 368 369 @retval EFI_SUCCESS The requested memory pages were freed. 370 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages 371 was not allocated with AllocateBuffer(). 372 373**/ 374typedef 375EFI_STATUS 376(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)( 377 IN EFI_PCI_IO_PROTOCOL *This, 378 IN UINTN Pages, 379 IN VOID *HostAddress 380 ); 381 382/** 383 Flushes all PCI posted write transactions from a PCI host bridge to system memory. 384 385 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 386 387 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host 388 bridge to system memory. 389 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI 390 host bridge due to a hardware error. 391 392**/ 393typedef 394EFI_STATUS 395(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)( 396 IN EFI_PCI_IO_PROTOCOL *This 397 ); 398 399/** 400 Retrieves this PCI controller's current PCI bus number, device number, and function number. 401 402 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 403 @param SegmentNumber The PCI controller's current PCI segment number. 404 @param BusNumber The PCI controller's current PCI bus number. 405 @param DeviceNumber The PCI controller's current PCI device number. 406 @param FunctionNumber The PCI controller's current PCI function number. 407 408 @retval EFI_SUCCESS The PCI controller location was returned. 409 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 410 411**/ 412typedef 413EFI_STATUS 414(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)( 415 IN EFI_PCI_IO_PROTOCOL *This, 416 OUT UINTN *SegmentNumber, 417 OUT UINTN *BusNumber, 418 OUT UINTN *DeviceNumber, 419 OUT UINTN *FunctionNumber 420 ); 421 422/** 423 Performs an operation on the attributes that this PCI controller supports. The operations include 424 getting the set of supported attributes, retrieving the current attributes, setting the current 425 attributes, enabling attributes, and disabling attributes. 426 427 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 428 @param Operation The operation to perform on the attributes for this PCI controller. 429 @param Attributes The mask of attributes that are used for Set, Enable, and Disable 430 operations. 431 @param Result A pointer to the result mask of attributes that are returned for the Get 432 and Supported operations. 433 434 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed. 435 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 436 @retval EFI_UNSUPPORTED one or more of the bits set in 437 Attributes are not supported by this PCI controller or one of 438 its parent bridges when Operation is Set, Enable or Disable. 439 440**/ 441typedef 442EFI_STATUS 443(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)( 444 IN EFI_PCI_IO_PROTOCOL *This, 445 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, 446 IN UINT64 Attributes, 447 OUT UINT64 *Result OPTIONAL 448 ); 449 450/** 451 Gets the attributes that this PCI controller supports setting on a BAR using 452 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR. 453 454 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 455 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 456 base address for resource range. The legal range for this field is 0..5. 457 @param Supports A pointer to the mask of attributes that this PCI controller supports 458 setting for this BAR with SetBarAttributes(). 459 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current 460 configuration of this BAR of the PCI controller. 461 462 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI 463 controller supports are returned in Supports. If Resources 464 is not NULL, then the ACPI 2.0 resource descriptors that the PCI 465 controller is currently using are returned in Resources. 466 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. 467 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 468 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate 469 Resources. 470 471**/ 472typedef 473EFI_STATUS 474(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)( 475 IN EFI_PCI_IO_PROTOCOL *This, 476 IN UINT8 BarIndex, 477 OUT UINT64 *Supports, OPTIONAL 478 OUT VOID **Resources OPTIONAL 479 ); 480 481/** 482 Sets the attributes for a range of a BAR on a PCI controller. 483 484 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 485 @param Attributes The mask of attributes to set for the resource range specified by 486 BarIndex, Offset, and Length. 487 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 488 base address for resource range. The legal range for this field is 0..5. 489 @param Offset A pointer to the BAR relative base address of the resource range to be 490 modified by the attributes specified by Attributes. 491 @param Length A pointer to the length of the resource range to be modified by the 492 attributes specified by Attributes. 493 494 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource 495 range specified by BarIndex, Offset, and Length were 496 set on the PCI controller, and the actual resource range is returned 497 in Offset and Length. 498 @retval EFI_INVALID_PARAMETER Offset or Length is NULL. 499 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 500 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the 501 resource range specified by BarIndex, Offset, and 502 Length. 503 504**/ 505typedef 506EFI_STATUS 507(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)( 508 IN EFI_PCI_IO_PROTOCOL *This, 509 IN UINT64 Attributes, 510 IN UINT8 BarIndex, 511 IN OUT UINT64 *Offset, 512 IN OUT UINT64 *Length 513 ); 514 515/// 516/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, 517/// and DMA interfaces used to abstract accesses to PCI controllers. 518/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. 519/// A device driver that wishes to manage a PCI controller in a system will have to 520/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. 521/// 522struct _EFI_PCI_IO_PROTOCOL { 523 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem; 524 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo; 525 EFI_PCI_IO_PROTOCOL_ACCESS Mem; 526 EFI_PCI_IO_PROTOCOL_ACCESS Io; 527 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; 528 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem; 529 EFI_PCI_IO_PROTOCOL_MAP Map; 530 EFI_PCI_IO_PROTOCOL_UNMAP Unmap; 531 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer; 532 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer; 533 EFI_PCI_IO_PROTOCOL_FLUSH Flush; 534 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation; 535 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes; 536 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes; 537 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes; 538 539 /// 540 /// The size, in bytes, of the ROM image. 541 /// 542 UINT64 RomSize; 543 544 /// 545 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible 546 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. 547 /// The contents of this buffer are either from the PCI option ROM that can be accessed 548 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. 549 /// The Attributes() function can be used to determine from which of these two sources 550 /// the RomImage buffer was initialized. 551 /// 552 VOID *RomImage; 553}; 554 555extern EFI_GUID gEfiPciIoProtocolGuid; 556 557#endif 558