pxa_timer.c revision 278613 
1/*-
2 * Copyright (c) 2006 Benno Rice.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25#include <sys/cdefs.h>
26__FBSDID("$FreeBSD: stable/10/sys/arm/xscale/pxa/pxa_timer.c 278613 2015-02-12 03:50:33Z ian $");
27
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/bus.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/malloc.h>
34#include <sys/rman.h>
35#include <sys/timetc.h>
36#include <machine/armreg.h>
37#include <machine/bus.h>
38#include <machine/cpu.h>
39#include <machine/frame.h>
40#include <machine/intr.h>
41
42#include <arm/xscale/pxa/pxavar.h>
43#include <arm/xscale/pxa/pxareg.h>
44
45#define	PXA_TIMER_FREQUENCY	3686400
46#define	PXA_TIMER_TICK		(PXA_TIMER_FREQUENCY / hz)
47
48struct pxa_timer_softc {
49	struct resource	*	pt_res[5];
50	bus_space_tag_t		pt_bst;
51	bus_space_handle_t	pt_bsh;
52};
53
54static struct resource_spec pxa_timer_spec[] = {
55	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
56	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
57	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
58	{ SYS_RES_IRQ,		2,	RF_ACTIVE },
59	{ SYS_RES_IRQ,		3,	RF_ACTIVE },
60	{ -1, 0 }
61};
62
63static struct pxa_timer_softc *timer_softc = NULL;
64
65static int	pxa_timer_probe(device_t);
66static int	pxa_timer_attach(device_t);
67
68static driver_filter_t	pxa_hardclock;
69
70static unsigned	pxa_timer_get_timecount(struct timecounter *);
71
72uint32_t	pxa_timer_get_osmr(int);
73void		pxa_timer_set_osmr(int, uint32_t);
74uint32_t	pxa_timer_get_oscr(void);
75void		pxa_timer_set_oscr(uint32_t);
76uint32_t	pxa_timer_get_ossr(void);
77void		pxa_timer_clear_ossr(uint32_t);
78void		pxa_timer_watchdog_enable(void);
79void		pxa_timer_watchdog_disable(void);
80void		pxa_timer_interrupt_enable(int);
81void		pxa_timer_interrupt_disable(int);
82
83static struct timecounter pxa_timer_timecounter = {
84	.tc_get_timecount = pxa_timer_get_timecount,
85	.tc_name = "OS Timer",
86	.tc_frequency = PXA_TIMER_FREQUENCY,
87	.tc_counter_mask = ~0u,
88	.tc_quality = 1000,
89};
90
91static int
92pxa_timer_probe(device_t dev)
93{
94
95	device_set_desc(dev, "OS Timer");
96	return (0);
97}
98
99static int
100pxa_timer_attach(device_t dev)
101{
102	int	error;
103	void	*ihl;
104	struct	pxa_timer_softc *sc;
105
106	sc = (struct pxa_timer_softc *)device_get_softc(dev);
107
108	if (timer_softc != NULL)
109		return (ENXIO);
110
111	error = bus_alloc_resources(dev, pxa_timer_spec, sc->pt_res);
112	if (error) {
113		device_printf(dev, "could not allocate resources\n");
114		return (ENXIO);
115	}
116
117	sc->pt_bst = rman_get_bustag(sc->pt_res[0]);
118	sc->pt_bsh = rman_get_bushandle(sc->pt_res[0]);
119
120	timer_softc = sc;
121
122	pxa_timer_interrupt_disable(-1);
123	pxa_timer_watchdog_disable();
124
125	if (bus_setup_intr(dev, sc->pt_res[1], INTR_TYPE_CLK,
126	    pxa_hardclock, NULL, NULL, &ihl) != 0) {
127		bus_release_resources(dev, pxa_timer_spec, sc->pt_res);
128		device_printf(dev, "could not setup hardclock interrupt\n");
129		return (ENXIO);
130	}
131
132	return (0);
133}
134
135static int
136pxa_hardclock(void *arg)
137{
138	struct		trapframe *frame;
139
140	frame = (struct trapframe *)arg;
141
142	/* Clear the interrupt */
143	pxa_timer_clear_ossr(OST_SR_CH0);
144
145	/* Schedule next tick */
146	pxa_timer_set_osmr(0, pxa_timer_get_oscr() + PXA_TIMER_TICK);
147
148	/* Do what we came here for */
149	hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
150
151	return (FILTER_HANDLED);
152}
153
154static device_method_t pxa_timer_methods[] = {
155	DEVMETHOD(device_probe, pxa_timer_probe),
156	DEVMETHOD(device_attach, pxa_timer_attach),
157
158	{0, 0}
159};
160
161static driver_t pxa_timer_driver = {
162	"timer",
163	pxa_timer_methods,
164	sizeof(struct pxa_timer_softc),
165};
166
167static devclass_t pxa_timer_devclass;
168
169DRIVER_MODULE(pxatimer, pxa, pxa_timer_driver, pxa_timer_devclass, 0, 0);
170
171static unsigned
172pxa_timer_get_timecount(struct timecounter *tc)
173{
174
175	return (pxa_timer_get_oscr());
176}
177
178void
179cpu_initclocks(void)
180{
181
182	pxa_timer_set_oscr(0);
183	pxa_timer_set_osmr(0, PXA_TIMER_TICK);
184	pxa_timer_interrupt_enable(0);
185
186	tc_init(&pxa_timer_timecounter);
187}
188
189void
190cpu_reset(void)
191{
192	uint32_t	val;
193
194	(void)disable_interrupts(PSR_I|PSR_F);
195
196	val = pxa_timer_get_oscr();
197	val += PXA_TIMER_FREQUENCY;
198	pxa_timer_set_osmr(3, val);
199	pxa_timer_watchdog_enable();
200
201	for(;;);
202}
203
204void
205DELAY(int usec)
206{
207	uint32_t	val;
208
209	if (timer_softc == NULL) {
210		for (; usec > 0; usec--)
211			for (val = 100; val > 0; val--)
212				;
213		return;
214	}
215
216	val = pxa_timer_get_oscr();
217	val += (PXA_TIMER_FREQUENCY * usec) / 1000000;
218	while (pxa_timer_get_oscr() <= val);
219}
220
221uint32_t
222pxa_timer_get_osmr(int which)
223{
224
225	return (bus_space_read_4(timer_softc->pt_bst,
226	    timer_softc->pt_bsh, which * 0x4));
227}
228
229void
230pxa_timer_set_osmr(int which, uint32_t val)
231{
232
233	bus_space_write_4(timer_softc->pt_bst,
234	    timer_softc->pt_bsh, which * 0x4, val);
235}
236
237uint32_t
238pxa_timer_get_oscr()
239{
240
241	return (bus_space_read_4(timer_softc->pt_bst,
242	    timer_softc->pt_bsh, OST_CR));
243}
244
245void
246pxa_timer_set_oscr(uint32_t val)
247{
248
249	bus_space_write_4(timer_softc->pt_bst,
250	    timer_softc->pt_bsh, OST_CR, val);
251}
252
253uint32_t
254pxa_timer_get_ossr()
255{
256
257	return (bus_space_read_4(timer_softc->pt_bst,
258	    timer_softc->pt_bsh, OST_SR));
259}
260
261void
262pxa_timer_clear_ossr(uint32_t val)
263{
264
265	bus_space_write_4(timer_softc->pt_bst,
266	    timer_softc->pt_bsh, OST_SR, val);
267}
268
269void
270pxa_timer_watchdog_enable()
271{
272
273	bus_space_write_4(timer_softc->pt_bst,
274	    timer_softc->pt_bsh, OST_WR, 0x1);
275}
276
277void
278pxa_timer_watchdog_disable()
279{
280
281	bus_space_write_4(timer_softc->pt_bst,
282	    timer_softc->pt_bsh, OST_WR, 0x0);
283}
284
285void
286pxa_timer_interrupt_enable(int which)
287{
288	uint32_t	oier;
289
290	if (which == -1) {
291		bus_space_write_4(timer_softc->pt_bst,
292		    timer_softc->pt_bsh, OST_IR, 0xf);
293		return;
294	}
295
296	oier = bus_space_read_4(timer_softc->pt_bst,
297	    timer_softc->pt_bsh, OST_IR);
298	oier |= 1 << which;
299	bus_space_write_4(timer_softc->pt_bst,
300	    timer_softc->pt_bsh, OST_IR, oier);
301}
302
303void
304pxa_timer_interrupt_disable(int which)
305{
306	uint32_t	oier;
307
308	if (which == -1) {
309		bus_space_write_4(timer_softc->pt_bst,
310		    timer_softc->pt_bsh, OST_IR, 0);
311	}
312
313	oier = bus_space_read_4(timer_softc->pt_bst,
314	    timer_softc->pt_bsh, OST_IR);
315	oier &= ~(1 << which);
316	bus_space_write_4(timer_softc->pt_bst,
317	    timer_softc->pt_bsh, OST_IR, oier);
318}
319