ti_gpio.c revision 266105
1/*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/** 29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's. 30 * 31 * Currently this driver only does the basics, get a value on a pin & set a 32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic 33 * and support interrupts and other various bits on the SoC can do ... in the 34 * meantime this is all you get. 35 * 36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here 37 * in the code. 38 * 39 * 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_gpio.c 266105 2014-05-15 01:27:53Z loos $"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/rman.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/gpio.h> 55 56#include <machine/bus.h> 57#include <machine/resource.h> 58 59#include <arm/ti/ti_scm.h> 60#include <arm/ti/ti_prcm.h> 61 62#include <dev/fdt/fdt_common.h> 63#include <dev/ofw/openfirm.h> 64#include <dev/ofw/ofw_bus.h> 65#include <dev/ofw/ofw_bus_subr.h> 66 67#include "gpio_if.h" 68 69 /* Register definitions */ 70#define TI_GPIO_REVISION 0x0000 71#define TI_GPIO_SYSCONFIG 0x0010 72#if defined(SOC_OMAP3) 73#define TI_GPIO_REVISION 0x0000 74#define TI_GPIO_SYSCONFIG 0x0010 75#define TI_GPIO_SYSSTATUS 0x0014 76#define TI_GPIO_IRQSTATUS1 0x0018 77#define TI_GPIO_IRQENABLE1 0x001C 78#define TI_GPIO_WAKEUPENABLE 0x0020 79#define TI_GPIO_IRQSTATUS2 0x0028 80#define TI_GPIO_IRQENABLE2 0x002C 81#define TI_GPIO_CTRL 0x0030 82#define TI_GPIO_OE 0x0034 83#define TI_GPIO_DATAIN 0x0038 84#define TI_GPIO_DATAOUT 0x003C 85#define TI_GPIO_LEVELDETECT0 0x0040 86#define TI_GPIO_LEVELDETECT1 0x0044 87#define TI_GPIO_RISINGDETECT 0x0048 88#define TI_GPIO_FALLINGDETECT 0x004C 89#define TI_GPIO_DEBOUNCENABLE 0x0050 90#define TI_GPIO_DEBOUNCINGTIME 0x0054 91#define TI_GPIO_CLEARIRQENABLE1 0x0060 92#define TI_GPIO_SETIRQENABLE1 0x0064 93#define TI_GPIO_CLEARIRQENABLE2 0x0070 94#define TI_GPIO_SETIRQENABLE2 0x0074 95#define TI_GPIO_CLEARWKUENA 0x0080 96#define TI_GPIO_SETWKUENA 0x0084 97#define TI_GPIO_CLEARDATAOUT 0x0090 98#define TI_GPIO_SETDATAOUT 0x0094 99#elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 100#define TI_GPIO_IRQSTATUS_RAW_0 0x0024 101#define TI_GPIO_IRQSTATUS_RAW_1 0x0028 102#define TI_GPIO_IRQSTATUS_0 0x002C 103#define TI_GPIO_IRQSTATUS_1 0x0030 104#define TI_GPIO_IRQSTATUS_SET_0 0x0034 105#define TI_GPIO_IRQSTATUS_SET_1 0x0038 106#define TI_GPIO_IRQSTATUS_CLR_0 0x003C 107#define TI_GPIO_IRQSTATUS_CLR_1 0x0040 108#define TI_GPIO_IRQWAKEN_0 0x0044 109#define TI_GPIO_IRQWAKEN_1 0x0048 110#define TI_GPIO_SYSSTATUS 0x0114 111#define TI_GPIO_IRQSTATUS1 0x0118 112#define TI_GPIO_IRQENABLE1 0x011C 113#define TI_GPIO_WAKEUPENABLE 0x0120 114#define TI_GPIO_IRQSTATUS2 0x0128 115#define TI_GPIO_IRQENABLE2 0x012C 116#define TI_GPIO_CTRL 0x0130 117#define TI_GPIO_OE 0x0134 118#define TI_GPIO_DATAIN 0x0138 119#define TI_GPIO_DATAOUT 0x013C 120#define TI_GPIO_LEVELDETECT0 0x0140 121#define TI_GPIO_LEVELDETECT1 0x0144 122#define TI_GPIO_RISINGDETECT 0x0148 123#define TI_GPIO_FALLINGDETECT 0x014C 124#define TI_GPIO_DEBOUNCENABLE 0x0150 125#define TI_GPIO_DEBOUNCINGTIME 0x0154 126#define TI_GPIO_CLEARIRQENABLE1 0x0160 127#define TI_GPIO_SETIRQENABLE1 0x0164 128#define TI_GPIO_CLEARIRQENABLE2 0x0170 129#define TI_GPIO_SETIRQENABLE2 0x0174 130#define TI_GPIO_CLEARWKUPENA 0x0180 131#define TI_GPIO_SETWKUENA 0x0184 132#define TI_GPIO_CLEARDATAOUT 0x0190 133#define TI_GPIO_SETDATAOUT 0x0194 134#else 135#error "Unknown SoC" 136#endif 137 138 /*Other SoC Specific definitions*/ 139#if defined(SOC_OMAP3) 140#define MAX_GPIO_BANKS 6 141#define FIRST_GPIO_BANK 1 142#define PINS_PER_BANK 32 143#define TI_GPIO_REV 0x00000025 144#elif defined(SOC_OMAP4) 145#define MAX_GPIO_BANKS 6 146#define FIRST_GPIO_BANK 1 147#define PINS_PER_BANK 32 148#define TI_GPIO_REV 0x50600801 149#elif defined(SOC_TI_AM335X) 150#define MAX_GPIO_BANKS 4 151#define FIRST_GPIO_BANK 0 152#define PINS_PER_BANK 32 153#define TI_GPIO_REV 0x50600801 154#endif 155 156/** 157 * ti_gpio_mem_spec - Resource specification used when allocating resources 158 * ti_gpio_irq_spec - Resource specification used when allocating resources 159 * 160 * This driver module can have up to six independent memory regions, each 161 * region typically controls 32 GPIO pins. 162 */ 163static struct resource_spec ti_gpio_mem_spec[] = { 164 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 165 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 166 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 167 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 168#if !defined(SOC_TI_AM335X) 169 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 170 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 171#endif 172 { -1, 0, 0 } 173}; 174static struct resource_spec ti_gpio_irq_spec[] = { 175 { SYS_RES_IRQ, 0, RF_ACTIVE }, 176 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 177 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 178 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 179#if !defined(SOC_TI_AM335X) 180 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 181 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 182#endif 183 { -1, 0, 0 } 184}; 185 186/** 187 * Structure that stores the driver context. 188 * 189 * This structure is allocated during driver attach. 190 */ 191struct ti_gpio_softc { 192 device_t sc_dev; 193 194 /* The memory resource(s) for the PRCM register set, when the device is 195 * created the caller can assign up to 4 memory regions. 196 */ 197 struct resource* sc_mem_res[MAX_GPIO_BANKS]; 198 struct resource* sc_irq_res[MAX_GPIO_BANKS]; 199 200 /* The handle for the register IRQ handlers */ 201 void* sc_irq_hdl[MAX_GPIO_BANKS]; 202 203 /* The following describes the H/W revision of each of the GPIO banks */ 204 uint32_t sc_revision[MAX_GPIO_BANKS]; 205 206 struct mtx sc_mtx; 207}; 208 209/** 210 * Macros for driver mutex locking 211 */ 212#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 213#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 214#define TI_GPIO_LOCK_INIT(_sc) \ 215 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 216 "ti_gpio", MTX_DEF) 217#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 218#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 219#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 220 221/** 222 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers 223 * @sc: GPIO device context 224 * @bank: The bank to read from 225 * @off: The offset of a register from the GPIO register address range 226 * 227 * 228 * RETURNS: 229 * 32-bit value read from the register. 230 */ 231static inline uint32_t 232ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 233{ 234 return (bus_read_4(sc->sc_mem_res[bank], off)); 235} 236 237/** 238 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers 239 * @sc: GPIO device context 240 * @bank: The bank to write to 241 * @off: The offset of a register from the GPIO register address range 242 * @val: The value to write into the register 243 * 244 * RETURNS: 245 * nothing 246 */ 247static inline void 248ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 249 uint32_t val) 250{ 251 bus_write_4(sc->sc_mem_res[bank], off, val); 252} 253 254/** 255 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 256 * @dev: gpio device handle 257 * @maxpin: pointer to a value that upon return will contain the maximum number 258 * of pins in the device. 259 * 260 * 261 * LOCKING: 262 * Internally locks the context 263 * 264 * RETURNS: 265 * Returns 0 on success otherwise an error code 266 */ 267static int 268ti_gpio_pin_max(device_t dev, int *maxpin) 269{ 270 struct ti_gpio_softc *sc = device_get_softc(dev); 271 unsigned int i; 272 unsigned int banks = 0; 273 274 TI_GPIO_LOCK(sc); 275 276 /* Calculate how many valid banks we have and then multiply that by 32 to 277 * give use the total number of pins. 278 */ 279 for (i = 0; i < MAX_GPIO_BANKS; i++) { 280 if (sc->sc_mem_res[i] != NULL) 281 banks++; 282 } 283 284 *maxpin = (banks * PINS_PER_BANK) - 1; 285 286 TI_GPIO_UNLOCK(sc); 287 288 return (0); 289} 290 291/** 292 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 293 * @dev: gpio device handle 294 * @pin: the number of the pin 295 * @caps: pointer to a value that upon return will contain the capabilities 296 * 297 * Currently all pins have the same capability, notably: 298 * - GPIO_PIN_INPUT 299 * - GPIO_PIN_OUTPUT 300 * - GPIO_PIN_PULLUP 301 * - GPIO_PIN_PULLDOWN 302 * 303 * LOCKING: 304 * Internally locks the context 305 * 306 * RETURNS: 307 * Returns 0 on success otherwise an error code 308 */ 309static int 310ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 311{ 312 struct ti_gpio_softc *sc = device_get_softc(dev); 313 uint32_t bank = (pin / PINS_PER_BANK); 314 315 TI_GPIO_LOCK(sc); 316 317 /* Sanity check the pin number is valid */ 318 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 319 TI_GPIO_UNLOCK(sc); 320 return (EINVAL); 321 } 322 323 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP | 324 GPIO_PIN_PULLDOWN); 325 326 TI_GPIO_UNLOCK(sc); 327 328 return (0); 329} 330 331/** 332 * ti_gpio_pin_getflags - Gets the current flags of a given pin 333 * @dev: gpio device handle 334 * @pin: the number of the pin 335 * @flags: upon return will contain the current flags of the pin 336 * 337 * Reads the current flags of a given pin, here we actually read the H/W 338 * registers to determine the flags, rather than storing the value in the 339 * setflags call. 340 * 341 * LOCKING: 342 * Internally locks the context 343 * 344 * RETURNS: 345 * Returns 0 on success otherwise an error code 346 */ 347static int 348ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 349{ 350 struct ti_gpio_softc *sc = device_get_softc(dev); 351 uint32_t bank = (pin / PINS_PER_BANK); 352 353 TI_GPIO_LOCK(sc); 354 355 /* Sanity check the pin number is valid */ 356 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 357 TI_GPIO_UNLOCK(sc); 358 return (EINVAL); 359 } 360 361 /* Get the current pin state */ 362 ti_scm_padconf_get_gpioflags(pin, flags); 363 364 TI_GPIO_UNLOCK(sc); 365 366 return (0); 367} 368 369/** 370 * ti_gpio_pin_getname - Gets the name of a given pin 371 * @dev: gpio device handle 372 * @pin: the number of the pin 373 * @name: buffer to put the name in 374 * 375 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 376 * of the pin. 377 * 378 * LOCKING: 379 * Internally locks the context 380 * 381 * RETURNS: 382 * Returns 0 on success otherwise an error code 383 */ 384static int 385ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 386{ 387 struct ti_gpio_softc *sc = device_get_softc(dev); 388 uint32_t bank = (pin / PINS_PER_BANK); 389 390 TI_GPIO_LOCK(sc); 391 392 /* Sanity check the pin number is valid */ 393 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 394 TI_GPIO_UNLOCK(sc); 395 return (EINVAL); 396 } 397 398 /* Set a very simple name */ 399 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 400 name[GPIOMAXNAME - 1] = '\0'; 401 402 TI_GPIO_UNLOCK(sc); 403 404 return (0); 405} 406 407/** 408 * ti_gpio_pin_setflags - Sets the flags for a given pin 409 * @dev: gpio device handle 410 * @pin: the number of the pin 411 * @flags: the flags to set 412 * 413 * The flags of the pin correspond to things like input/output mode, pull-ups, 414 * pull-downs, etc. This driver doesn't support all flags, only the following: 415 * - GPIO_PIN_INPUT 416 * - GPIO_PIN_OUTPUT 417 * - GPIO_PIN_PULLUP 418 * - GPIO_PIN_PULLDOWN 419 * 420 * LOCKING: 421 * Internally locks the context 422 * 423 * RETURNS: 424 * Returns 0 on success otherwise an error code 425 */ 426static int 427ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 428{ 429 struct ti_gpio_softc *sc = device_get_softc(dev); 430 uint32_t bank = (pin / PINS_PER_BANK); 431 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 432 uint32_t reg_val; 433 434 /* Sanity check the flags supplied are valid, i.e. not input and output */ 435 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000) 436 return (EINVAL); 437 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 438 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) 439 return (EINVAL); 440 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) == 441 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) 442 return (EINVAL); 443 444 445 TI_GPIO_LOCK(sc); 446 447 /* Sanity check the pin number is valid */ 448 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 449 TI_GPIO_UNLOCK(sc); 450 return (EINVAL); 451 } 452 453 /* Set the GPIO mode and state */ 454 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) { 455 TI_GPIO_UNLOCK(sc); 456 return (EINVAL); 457 } 458 459 /* If configuring as an output set the "output enable" bit */ 460 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 461 if (flags & GPIO_PIN_INPUT) 462 reg_val |= mask; 463 else 464 reg_val &= ~mask; 465 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); 466 467 468 TI_GPIO_UNLOCK(sc); 469 470 return (0); 471} 472 473/** 474 * ti_gpio_pin_set - Sets the current level on a GPIO pin 475 * @dev: gpio device handle 476 * @pin: the number of the pin 477 * @value: non-zero value will drive the pin high, otherwise the pin is 478 * driven low. 479 * 480 * 481 * LOCKING: 482 * Internally locks the context 483 * 484 * RETURNS: 485 * Returns 0 on success otherwise a error code 486 */ 487static int 488ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 489{ 490 struct ti_gpio_softc *sc = device_get_softc(dev); 491 uint32_t bank = (pin / PINS_PER_BANK); 492 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 493 494 TI_GPIO_LOCK(sc); 495 496 /* Sanity check the pin number is valid */ 497 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 498 TI_GPIO_UNLOCK(sc); 499 return (EINVAL); 500 } 501 502 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT 503 : TI_GPIO_SETDATAOUT, mask); 504 505 TI_GPIO_UNLOCK(sc); 506 507 return (0); 508} 509 510/** 511 * ti_gpio_pin_get - Gets the current level on a GPIO pin 512 * @dev: gpio device handle 513 * @pin: the number of the pin 514 * @value: pointer to a value that upond return will contain the pin value 515 * 516 * The pin must be configured as an input pin beforehand, otherwise this 517 * function will fail. 518 * 519 * LOCKING: 520 * Internally locks the context 521 * 522 * RETURNS: 523 * Returns 0 on success otherwise a error code 524 */ 525static int 526ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 527{ 528 struct ti_gpio_softc *sc = device_get_softc(dev); 529 uint32_t bank = (pin / PINS_PER_BANK); 530 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 531 uint32_t val = 0; 532 533 TI_GPIO_LOCK(sc); 534 535 /* Sanity check the pin number is valid */ 536 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 537 TI_GPIO_UNLOCK(sc); 538 return (EINVAL); 539 } 540 541 /* Sanity check the pin is not configured as an output */ 542 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 543 544 /* Read the value on the pin */ 545 if (val & mask) 546 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0; 547 else 548 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0; 549 550 TI_GPIO_UNLOCK(sc); 551 552 return (0); 553} 554 555/** 556 * ti_gpio_pin_toggle - Toggles a given GPIO pin 557 * @dev: gpio device handle 558 * @pin: the number of the pin 559 * 560 * 561 * LOCKING: 562 * Internally locks the context 563 * 564 * RETURNS: 565 * Returns 0 on success otherwise a error code 566 */ 567static int 568ti_gpio_pin_toggle(device_t dev, uint32_t pin) 569{ 570 struct ti_gpio_softc *sc = device_get_softc(dev); 571 uint32_t bank = (pin / PINS_PER_BANK); 572 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 573 uint32_t val; 574 575 TI_GPIO_LOCK(sc); 576 577 /* Sanity check the pin number is valid */ 578 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { 579 TI_GPIO_UNLOCK(sc); 580 return (EINVAL); 581 } 582 583 /* Toggle the pin */ 584 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT); 585 if (val & mask) 586 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask); 587 else 588 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask); 589 590 TI_GPIO_UNLOCK(sc); 591 592 return (0); 593} 594 595/** 596 * ti_gpio_intr - ISR for all GPIO modules 597 * @arg: the soft context pointer 598 * 599 * Unsused 600 * 601 * LOCKING: 602 * Internally locks the context 603 * 604 */ 605static void 606ti_gpio_intr(void *arg) 607{ 608 struct ti_gpio_softc *sc = arg; 609 610 TI_GPIO_LOCK(sc); 611 /* TODO: something useful */ 612 TI_GPIO_UNLOCK(sc); 613} 614 615/** 616 * ti_gpio_probe - probe function for the driver 617 * @dev: gpio device handle 618 * 619 * Simply sets the name of the driver 620 * 621 * LOCKING: 622 * None 623 * 624 * RETURNS: 625 * Always returns 0 626 */ 627static int 628ti_gpio_probe(device_t dev) 629{ 630 if (!ofw_bus_is_compatible(dev, "ti,gpio")) 631 return (ENXIO); 632 633 device_set_desc(dev, "TI General Purpose I/O (GPIO)"); 634 return (0); 635} 636 637/** 638 * ti_gpio_attach - attach function for the driver 639 * @dev: gpio device handle 640 * 641 * Allocates and sets up the driver context for all GPIO banks. This function 642 * expects the memory ranges and IRQs to already be allocated to the driver. 643 * 644 * LOCKING: 645 * None 646 * 647 * RETURNS: 648 * Always returns 0 649 */ 650static int 651ti_gpio_attach(device_t dev) 652{ 653 struct ti_gpio_softc *sc = device_get_softc(dev); 654 unsigned int i; 655 int err = 0; 656 int pin; 657 uint32_t flags; 658 uint32_t reg_oe; 659 660 sc->sc_dev = dev; 661 662 TI_GPIO_LOCK_INIT(sc); 663 664 665 /* There are up to 6 different GPIO register sets located in different 666 * memory areas on the chip. The memory range should have been set for 667 * the driver when it was added as a child. 668 */ 669 err = bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 670 if (err) { 671 device_printf(dev, "Error: could not allocate mem resources\n"); 672 return (ENXIO); 673 } 674 675 /* Request the IRQ resources */ 676 err = bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 677 if (err) { 678 device_printf(dev, "Error: could not allocate irq resources\n"); 679 return (ENXIO); 680 } 681 682 /* Setup the IRQ resources */ 683 for (i = 0; i < MAX_GPIO_BANKS; i++) { 684 if (sc->sc_irq_res[i] == NULL) 685 break; 686 687 /* Register an interrupt handler for each of the IRQ resources */ 688 if ((bus_setup_intr(dev, sc->sc_irq_res[i], INTR_TYPE_MISC | INTR_MPSAFE, 689 NULL, ti_gpio_intr, sc, &(sc->sc_irq_hdl[i])))) { 690 device_printf(dev, "WARNING: unable to register interrupt handler\n"); 691 return (ENXIO); 692 } 693 } 694 695 /* Store the device handle back in the sc */ 696 sc->sc_dev = dev; 697 698 /* We need to go through each block and ensure the clocks are running and 699 * the module is enabled. It might be better to do this only when the 700 * pins are configured which would result in less power used if the GPIO 701 * pins weren't used ... 702 */ 703 for (i = 0; i < MAX_GPIO_BANKS; i++) { 704 if (sc->sc_mem_res[i] != NULL) { 705 706 /* Enable the interface and functional clocks for the module */ 707 ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + i); 708 709 /* Read the revision number of the module. TI don't publish the 710 * actual revision numbers, so instead the values have been 711 * determined by experimentation. 712 */ 713 sc->sc_revision[i] = ti_gpio_read_4(sc, i, TI_GPIO_REVISION); 714 715 /* Check the revision */ 716 if (sc->sc_revision[i] != TI_GPIO_REV) { 717 device_printf(dev, "Warning: could not determine the revision" 718 "of %u GPIO module (revision:0x%08x)\n", 719 i, sc->sc_revision[i]); 720 continue; 721 } 722 723 /* Disable interrupts for all pins */ 724 ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); 725 ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); 726 727 /* Init OE register based on pads configuration */ 728 reg_oe = 0xffffffff; 729 for (pin = 0; pin < 32; pin++) { 730 ti_scm_padconf_get_gpioflags( 731 PINS_PER_BANK*i + pin, &flags); 732 if (flags & GPIO_PIN_OUTPUT) 733 reg_oe &= ~(1U << pin); 734 } 735 736 ti_gpio_write_4(sc, i, TI_GPIO_OE, reg_oe); 737 } 738 } 739 740 /* Finish of the probe call */ 741 device_add_child(dev, "gpioc", device_get_unit(dev)); 742 device_add_child(dev, "gpiobus", device_get_unit(dev)); 743 744 return (bus_generic_attach(dev)); 745} 746 747/** 748 * ti_gpio_detach - detach function for the driver 749 * @dev: scm device handle 750 * 751 * Allocates and sets up the driver context, this simply entails creating a 752 * bus mappings for the SCM register set. 753 * 754 * LOCKING: 755 * None 756 * 757 * RETURNS: 758 * Always returns 0 759 */ 760static int 761ti_gpio_detach(device_t dev) 762{ 763 struct ti_gpio_softc *sc = device_get_softc(dev); 764 unsigned int i; 765 766 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 767 768 /* Disable all interrupts */ 769 for (i = 0; i < MAX_GPIO_BANKS; i++) { 770 if (sc->sc_mem_res[i] != NULL) { 771 ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); 772 ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); 773 } 774 } 775 776 bus_generic_detach(dev); 777 778 /* Release the memory and IRQ resources */ 779 for (i = 0; i < MAX_GPIO_BANKS; i++) { 780 if (sc->sc_mem_res[i] != NULL) 781 bus_release_resource(dev, SYS_RES_MEMORY, i, sc->sc_mem_res[i]); 782 if (sc->sc_irq_res[i] != NULL) 783 bus_release_resource(dev, SYS_RES_IRQ, i, sc->sc_irq_res[i]); 784 } 785 786 TI_GPIO_LOCK_DESTROY(sc); 787 788 return(0); 789} 790 791static phandle_t 792ti_gpio_get_node(device_t bus, device_t dev) 793{ 794 795 /* We only have one child, the GPIO bus, which needs our own node. */ 796 return (ofw_bus_get_node(bus)); 797} 798 799static device_method_t ti_gpio_methods[] = { 800 DEVMETHOD(device_probe, ti_gpio_probe), 801 DEVMETHOD(device_attach, ti_gpio_attach), 802 DEVMETHOD(device_detach, ti_gpio_detach), 803 804 /* GPIO protocol */ 805 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 806 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 807 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 808 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 809 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 810 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 811 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 812 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 813 814 /* ofw_bus interface */ 815 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 816 817 {0, 0}, 818}; 819 820static driver_t ti_gpio_driver = { 821 "gpio", 822 ti_gpio_methods, 823 sizeof(struct ti_gpio_softc), 824}; 825static devclass_t ti_gpio_devclass; 826 827DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0); 828