mv_machdep.c revision 266046
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: stable/10/sys/arm/mv/mv_machdep.c 266046 2014-05-14 16:32:27Z ian $"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/devmap.h> 54#include <machine/machdep.h> 55 56#include <arm/mv/mvreg.h> /* XXX */ 57#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 58#include <arm/mv/mvwin.h> 59 60#include <dev/fdt/fdt_common.h> 61 62static int platform_mpp_init(void); 63#if defined(SOC_MV_ARMADAXP) 64void armadaxp_init_coher_fabric(void); 65void armadaxp_l2_init(void); 66#endif 67 68#define MPP_PIN_MAX 68 69#define MPP_PIN_CELLS 2 70#define MPP_PINS_PER_REG 8 71#define MPP_SEL(pin,func) (((func) & 0xf) << \ 72 (((pin) % MPP_PINS_PER_REG) * 4)) 73 74static int 75platform_mpp_init(void) 76{ 77 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 78 int mpp[MPP_PIN_MAX]; 79 uint32_t ctrl_val, ctrl_offset; 80 pcell_t reg[4]; 81 u_long start, size; 82 phandle_t node; 83 pcell_t pin_cells, *pinmap_ptr, pin_count; 84 ssize_t len; 85 int par_addr_cells, par_size_cells; 86 int tuple_size, tuples, rv, pins, i, j; 87 int mpp_pin, mpp_function; 88 89 /* 90 * Try to access the MPP node directly i.e. through /aliases/mpp. 91 */ 92 if ((node = OF_finddevice("mpp")) != -1) 93 if (fdt_is_compatible(node, "mrvl,mpp")) 94 goto moveon; 95 /* 96 * Find the node the long way. 97 */ 98 if ((node = OF_finddevice("/")) == -1) 99 return (ENXIO); 100 101 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 102 return (ENXIO); 103 104 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 105 /* 106 * No MPP node. Fall back to how MPP got set by the 107 * first-stage loader and try to continue booting. 108 */ 109 return (0); 110moveon: 111 /* 112 * Process 'reg' prop. 113 */ 114 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 115 &par_size_cells)) != 0) 116 return(ENXIO); 117 118 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 119 len = OF_getprop(node, "reg", reg, sizeof(reg)); 120 tuples = len / tuple_size; 121 if (tuple_size <= 0) 122 return (EINVAL); 123 124 /* 125 * Get address/size. XXX we assume only the first 'reg' tuple is used. 126 */ 127 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 128 &start, &size); 129 if (rv != 0) 130 return (rv); 131 start += fdt_immr_va; 132 133 /* 134 * Process 'pin-count' and 'pin-map' props. 135 */ 136 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 137 return (ENXIO); 138 pin_count = fdt32_to_cpu(pin_count); 139 if (pin_count > MPP_PIN_MAX) 140 return (ERANGE); 141 142 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 143 pin_cells = MPP_PIN_CELLS; 144 pin_cells = fdt32_to_cpu(pin_cells); 145 if (pin_cells > MPP_PIN_CELLS) 146 return (ERANGE); 147 tuple_size = sizeof(pcell_t) * pin_cells; 148 149 bzero(pinmap, sizeof(pinmap)); 150 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 151 if (len <= 0) 152 return (ERANGE); 153 if (len % tuple_size) 154 return (ERANGE); 155 pins = len / tuple_size; 156 if (pins > pin_count) 157 return (ERANGE); 158 /* 159 * Fill out a "mpp[pin] => function" table. All pins unspecified in 160 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 161 */ 162 bzero(mpp, sizeof(mpp)); 163 pinmap_ptr = pinmap; 164 for (i = 0; i < pins; i++) { 165 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 166 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 167 mpp[mpp_pin] = mpp_function; 168 pinmap_ptr += pin_cells; 169 } 170 171 /* 172 * Prepare and program MPP control register values. 173 */ 174 ctrl_offset = 0; 175 for (i = 0; i < pin_count;) { 176 ctrl_val = 0; 177 178 for (j = 0; j < MPP_PINS_PER_REG; j++) { 179 if (i + j == pin_count - 1) 180 break; 181 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 182 } 183 i += MPP_PINS_PER_REG; 184 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 185 ctrl_val); 186 187#if defined(SOC_MV_ORION) 188 /* 189 * Third MPP reg on Orion SoC is placed 190 * non-linearly (with different offset). 191 */ 192 if (i == (2 * MPP_PINS_PER_REG)) 193 ctrl_offset = 0x50; 194 else 195#endif 196 ctrl_offset += 4; 197 } 198 199 return (0); 200} 201 202vm_offset_t 203initarm_lastaddr(void) 204{ 205 206 return (fdt_immr_va); 207} 208 209void 210initarm_early_init(void) 211{ 212 213 if (fdt_immr_addr(MV_BASE) != 0) 214 while (1); 215} 216 217void 218initarm_gpio_init(void) 219{ 220 221 /* 222 * Re-initialise MPP. It is important to call this prior to using 223 * console as the physical connection can be routed via MPP. 224 */ 225 if (platform_mpp_init() != 0) 226 while (1); 227} 228 229void 230initarm_late_init(void) 231{ 232 /* 233 * Re-initialise decode windows 234 */ 235#if !defined(SOC_MV_FREY) 236 if (soc_decode_win() != 0) 237 printf("WARNING: could not re-initialise decode windows! " 238 "Running with existing settings...\n"); 239#else 240 /* Disable watchdog and timers */ 241 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 242#endif 243#if defined(SOC_MV_ARMADAXP) 244#if !defined(SMP) 245 /* For SMP case it should be initialized after APs are booted */ 246 armadaxp_init_coher_fabric(); 247#endif 248 armadaxp_l2_init(); 249#endif 250} 251 252#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 253static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 254 { 0, 0, 0, 0, 0, } 255}; 256 257static int 258platform_sram_devmap(struct arm_devmap_entry *map) 259{ 260#if !defined(SOC_MV_ARMADAXP) 261 phandle_t child, root; 262 u_long base, size; 263 /* 264 * SRAM range. 265 */ 266 if ((child = OF_finddevice("/sram")) != 0) 267 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 268 fdt_is_compatible(child, "mrvl,scratchpad")) 269 goto moveon; 270 271 if ((root = OF_finddevice("/")) == 0) 272 return (ENXIO); 273 274 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 275 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 276 goto out; 277 278moveon: 279 if (fdt_regsize(child, &base, &size) != 0) 280 return (EINVAL); 281 282 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 283 map->pd_pa = base; 284 map->pd_size = size; 285 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 286 map->pd_cache = PTE_NOCACHE; 287 288 return (0); 289out: 290#endif 291 return (ENOENT); 292 293} 294 295/* 296 * Supply a default do-nothing implementation of fdt_pci_devmap() via a weak 297 * alias. Many Marvell platforms don't support a PCI interface, but to support 298 * those that do, we end up with a reference to this function below, in 299 * platform_devmap_init(). If "device pci" appears in the kernel config, the 300 * real implementation of this function in dev/fdt/fdt_pci.c overrides the weak 301 * alias defined here. 302 */ 303int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 304 vm_offset_t io_va, vm_offset_t mem_va); 305int 306mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, 307 vm_offset_t io_va, vm_offset_t mem_va) 308{ 309 310 return (0); 311} 312__weak_reference(mv_default_fdt_pci_devmap, fdt_pci_devmap); 313 314/* 315 * XXX: When device entry in devmap has pd_size smaller than section size, 316 * system will freeze during initialization 317 */ 318 319/* 320 * Construct pmap_devmap[] with DT-derived config data. 321 */ 322int 323initarm_devmap_init(void) 324{ 325 phandle_t root, child; 326 pcell_t bank_count; 327 int i, num_mapped; 328 329 i = 0; 330 arm_devmap_register_table(&fdt_devmap[0]); 331 332#ifdef SOC_MV_ARMADAXP 333 vm_paddr_t cur_immr_pa; 334 335 /* 336 * Acquire SoC registers' base passed by u-boot and fill devmap 337 * accordingly. DTB is going to be modified basing on this data 338 * later. 339 */ 340 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 341 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 342 if (cur_immr_pa != 0) 343 fdt_immr_pa = cur_immr_pa; 344#endif 345 /* 346 * IMMR range. 347 */ 348 fdt_devmap[i].pd_va = fdt_immr_va; 349 fdt_devmap[i].pd_pa = fdt_immr_pa; 350 fdt_devmap[i].pd_size = fdt_immr_size; 351 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 352 fdt_devmap[i].pd_cache = PTE_NOCACHE; 353 i++; 354 355 /* 356 * SRAM range. 357 */ 358 if (i < FDT_DEVMAP_MAX) 359 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 360 i++; 361 362 /* 363 * PCI range(s). 364 * PCI range(s) and localbus. 365 */ 366 if ((root = OF_finddevice("/")) == -1) 367 return (ENXIO); 368 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 369 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 370 /* 371 * Check space: each PCI node will consume 2 devmap 372 * entries. 373 */ 374 if (i + 1 >= FDT_DEVMAP_MAX) 375 return (ENOMEM); 376 377 /* 378 * XXX this should account for PCI and multiple ranges 379 * of a given kind. 380 */ 381 if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 382 MV_PCI_VA_MEM_BASE) != 0) 383 return (ENXIO); 384 i += 2; 385 } 386 387 if (fdt_is_compatible(child, "mrvl,lbc")) { 388 /* Check available space */ 389 if (OF_getprop(child, "bank-count", (void *)&bank_count, 390 sizeof(bank_count)) <= 0) 391 /* If no property, use default value */ 392 bank_count = 1; 393 else 394 bank_count = fdt32_to_cpu(bank_count); 395 396 if ((i + bank_count) >= FDT_DEVMAP_MAX) 397 return (ENOMEM); 398 399 /* Add all localbus ranges to device map */ 400 num_mapped = 0; 401 402 if (fdt_localbus_devmap(child, &fdt_devmap[i], 403 (int)bank_count, &num_mapped) != 0) 404 return (ENXIO); 405 406 i += num_mapped; 407 } 408 } 409 410 return (0); 411} 412 413struct arm32_dma_range * 414bus_dma_get_range(void) 415{ 416 417 return (NULL); 418} 419 420int 421bus_dma_get_range_nb(void) 422{ 423 424 return (0); 425} 426 427#if defined(CPU_MV_PJ4B) 428#ifdef DDB 429#include <ddb/ddb.h> 430 431DB_SHOW_COMMAND(cp15, db_show_cp15) 432{ 433 u_int reg; 434 435 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 436 db_printf("Cpu ID: 0x%08x\n", reg); 437 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 438 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 439 440 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 441 db_printf("Ctrl: 0x%08x\n",reg); 442 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 443 db_printf("Aux Ctrl: 0x%08x\n",reg); 444 445 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 446 db_printf("Processor Feat 0: 0x%08x\n", reg); 447 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 448 db_printf("Processor Feat 1: 0x%08x\n", reg); 449 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 450 db_printf("Debug Feat 0: 0x%08x\n", reg); 451 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 452 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 453 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 454 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 455 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 456 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 457 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 458 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 459 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 460 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 461 462 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 463 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 464 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 465 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 466 467 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 468 db_printf("CPU ID code extension: 0x%08x\n",reg); 469} 470 471DB_SHOW_COMMAND(vtop, db_show_vtop) 472{ 473 u_int reg; 474 475 if (have_addr) { 476 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 477 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 478 db_printf("Physical address reg: 0x%08x\n",reg); 479 } else 480 db_printf("show vtop <virt_addr>\n"); 481} 482#endif /* DDB */ 483#endif /* CPU_MV_PJ4B */ 484 485