cpufunc_asm_arm11x6.S revision 275767 
10Sduke/*	$NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $	*/
22362Sohair
30Sduke/*
40Sduke * Copyright (c) 2007 Microsoft
50Sduke * All rights reserved.
60Sduke *
70Sduke * Redistribution and use in source and binary forms, with or without
80Sduke * modification, are permitted provided that the following conditions
90Sduke * are met:
100Sduke * 1. Redistributions of source code must retain the above copyright
110Sduke *    notice, this list of conditions and the following disclaimer.
120Sduke * 2. Redistributions in binary form must reproduce the above copyright
130Sduke *    notice, this list of conditions and the following disclaimer in the
140Sduke *    documentation and/or other materials provided with the distribution.
150Sduke * 3. All advertising materials mentioning features or use of this software
160Sduke *    must display the following acknowledgement:
170Sduke *	This product includes software developed by Microsoft
180Sduke *
192362Sohair * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
202362Sohair * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
212362Sohair * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
220Sduke * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
230Sduke * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
240Sduke * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
250Sduke * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
260Sduke * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
270Sduke * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
280Sduke * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
290Sduke * SUCH DAMAGE.
300Sduke */
310Sduke
320Sduke/*-
330Sduke * Copyright (c) 2012 The NetBSD Foundation, Inc.
340Sduke * All rights reserved.
350Sduke *
360Sduke * This code is derived from software contributed to The NetBSD Foundation
370Sduke * by Eben Upton
380Sduke *
390Sduke * Redistribution and use in source and binary forms, with or without
400Sduke * modification, are permitted provided that the following conditions
410Sduke * are met:
420Sduke * 1. Redistributions of source code must retain the above copyright
430Sduke *    notice, this list of conditions and the following disclaimer.
440Sduke * 2. Redistributions in binary form must reproduce the above copyright
450Sduke *    notice, this list of conditions and the following disclaimer in the
460Sduke *    documentation and/or other materials provided with the distribution.
470Sduke *
480Sduke * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
490Sduke * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
500Sduke * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
510Sduke * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
520Sduke * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
530Sduke * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
540Sduke * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61
62#include <machine/asm.h>
63__FBSDID("$FreeBSD: stable/10/sys/arm/arm/cpufunc_asm_arm11x6.S 275767 2014-12-14 16:28:53Z andrew $");
64
65	.cpu arm1176jz-s
66
67#if 0
68#define Invalidate_I_cache(Rtmp1, Rtmp2) \
69	mcr	p15, 0, Rtmp1, c7, c5, 0	/* Invalidate Entire I cache */
70#else
71/*
72 * Workaround for
73 *
74 *    Erratum 411920 in ARM1136 (fixed in r1p4)
75 *    Erratum 415045 in ARM1176 (fixed in r0p5?)
76 *
77 *	- value of arg 'reg' Should Be Zero
78 */
79#define Invalidate_I_cache(Rtmp1, Rtmp2) \
80	mov	Rtmp1, #0;		/* SBZ */			\
81	mrs	Rtmp2, cpsr;						\
82	cpsid	ifa;							\
83	mcr	p15, 0, Rtmp1, c7, c5, 0;	/* Nuke Whole Icache */	\
84	mcr	p15, 0, Rtmp1, c7, c5, 0;	/* Nuke Whole Icache */	\
85	mcr	p15, 0, Rtmp1, c7, c5, 0;	/* Nuke Whole Icache */	\
86	mcr	p15, 0, Rtmp1, c7, c5, 0;	/* Nuke Whole Icache */	\
87	msr	cpsr_cx, Rtmp2;						\
88	nop;								\
89	nop;								\
90	nop;								\
91	nop;								\
92	nop;								\
93	nop;								\
94	nop;								\
95	nop;								\
96	nop;								\
97	nop;								\
98	nop;
99#endif
100
101#if 1
102#define Flush_D_cache(reg) \
103	mov	reg, #0;		/* SBZ */					\
104	mcr	p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */	\
105	mcr	p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
106#else
107#define Flush_D_cache(reg) \
1081:	mov	reg, #0;		/* SBZ */					\
109	mcr	p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */	\
110	mrc	p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */		\
111	ands	reg, reg, #01;		/* Check if it is clean */			\
112	bne	1b;			/* loop if not */				\
113	mcr	p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
114#endif
115
116ENTRY(arm11x6_setttb)
117	mov	r1, #0
118	mcr	p15, 0, r0, c2, c0, 0	/* load new TTB */
119	mcr	p15, 0, r1, c8, c7, 0	/* invalidate I+D TLBs */
120	mcr	p15, 0, r1, c7, c10, 4	/* drain write buffer */
121	RET
122END(arm11x6_setttb)
123
124ENTRY_NP(arm11x6_idcache_wbinv_all)
125	Flush_D_cache(r0)
126	Invalidate_I_cache(r0, r1)
127	RET
128END(arm11x6_idcache_wbinv_all)
129
130ENTRY_NP(arm11x6_dcache_wbinv_all)
131	Flush_D_cache(r0)
132	RET
133END(arm11x6_dcache_wbinv_all)
134
135ENTRY_NP(arm11x6_icache_sync_all)
136	Flush_D_cache(r0)
137	Invalidate_I_cache(r0, r1)
138	RET
139END(arm11x6_icache_sync_all)
140
141ENTRY_NP(arm11x6_flush_prefetchbuf)
142	mcr	p15, 0, r0, c7, c5, 4	/* Flush Prefetch Buffer */
143	RET
144END(arm11x6_flush_prefetchbuf)
145
146ENTRY_NP(arm11x6_icache_sync_range)
147	add	r1, r1, r0
148	sub	r1, r1, #1
149	/* Erratum ARM1136 371025, workaround #2 */
150	/* Erratum ARM1176 371367 */
151	mrs	r2, cpsr		/* save the CPSR */
152	cpsid	ifa			/* disable interrupts (irq,fiq,abort) */
153	mov	r3, #0
154	mcr	p15, 0, r3, c13, c0, 0	/* write FCSE (uTLB invalidate) */
155	mcr	p15, 0, r3, c7, c5, 4	/* flush prefetch buffer */
156	add	r3, pc, #0x24
157	mcr	p15, 0, r3, c7, c13, 1	/* prefetch I-cache line */
158	mcrr	p15, 0, r1, r0, c5	/* invalidate I-cache range */
159	msr	cpsr_cx, r2		/* local_irq_restore */
160	nop
161	nop
162	nop
163	nop
164	nop
165	nop
166	nop
167
168	mcrr	p15, 0, r1, r0, c12	/* clean and invalidate D cache range */ /* XXXNH */
169	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
170	RET
171END(arm11x6_icache_sync_range)
172
173ENTRY_NP(arm11x6_idcache_wbinv_range)
174	add	r1, r1, r0
175	sub	r1, r1, #1
176	/* Erratum ARM1136 371025, workaround #2 */
177	/* Erratum ARM1176 371367 */
178	mrs	r2, cpsr		/* save the CPSR */
179	cpsid	ifa			/* disable interrupts (irq,fiq,abort) */
180	mov	r3, #0
181	mcr	p15, 0, r3, c13, c0, 0	/* write FCSE (uTLB invalidate) */
182	mcr	p15, 0, r3, c7, c5, 4	/* flush prefetch buffer */
183	add	r3, pc, #0x24
184	mcr	p15, 0, r3, c7, c13, 1	/* prefetch I-cache line */
185	mcrr	p15, 0, r1, r0, c5	/* invalidate I-cache range */
186	msr	cpsr_cx, r2		/* local_irq_restore */
187	nop
188	nop
189	nop
190	nop
191	nop
192	nop
193	nop
194
195	mcrr	p15, 0, r1, r0, c14	/* clean and invalidate D cache range */
196	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
197	RET
198END(arm11x6_idcache_wbinv_range)
199
200/*
201 * Preload the cache before issuing the WFI by conditionally disabling the
202 * mcr intstructions the first time around the loop. Ensure the function is
203 * cacheline aligned.
204 */
205	.arch	armv6
206	.p2align 5
207
208ENTRY_NP(arm11x6_sleep)
209	mov	r0, #0
210	mov	r1, #2
2111:
212	subs	r1, #1
213	nop
214	mcreq	p15, 0, r0, c7, c10, 4		/* data sync barrier */
215	mcreq	p15, 0, r0, c7, c0, 4		/* wait for interrupt */
216	nop
217	nop
218	nop
219	bne	1b
220	RET
221END(arm11x6_sleep)
222
223