vmm_lapic.c revision 262350 
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/amd64/vmm/vmm_lapic.c 262350 2014-02-23 00:46:05Z jhb $
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/vmm_lapic.c 262350 2014-02-23 00:46:05Z jhb $");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/smp.h>
35
36#include <x86/specialreg.h>
37#include <x86/apicreg.h>
38
39#include <machine/vmm.h>
40#include "vmm_ipi.h"
41#include "vmm_ktr.h"
42#include "vmm_lapic.h"
43#include "vlapic.h"
44
45/*
46 * Some MSI message definitions
47 */
48#define	MSI_X86_ADDR_MASK	0xfff00000
49#define	MSI_X86_ADDR_BASE	0xfee00000
50#define	MSI_X86_ADDR_RH		0x00000008	/* Redirection Hint */
51#define	MSI_X86_ADDR_LOG	0x00000004	/* Destination Mode */
52
53int
54lapic_pending_intr(struct vm *vm, int cpu)
55{
56	struct vlapic *vlapic;
57
58	vlapic = vm_lapic(vm, cpu);
59
60	return (vlapic_pending_intr(vlapic));
61}
62
63void
64lapic_intr_accepted(struct vm *vm, int cpu, int vector)
65{
66	struct vlapic *vlapic;
67
68	vlapic = vm_lapic(vm, cpu);
69
70	vlapic_intr_accepted(vlapic, vector);
71}
72
73int
74lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
75{
76	struct vlapic *vlapic;
77
78	if (cpu < 0 || cpu >= VM_MAXCPU)
79		return (EINVAL);
80
81	if (vector < 32 || vector > 255)
82		return (EINVAL);
83
84	vlapic = vm_lapic(vm, cpu);
85	vlapic_set_intr_ready(vlapic, vector, level);
86
87	vcpu_notify_event(vm, cpu);
88
89	return (0);
90}
91
92int
93lapic_set_local_intr(struct vm *vm, int cpu, int vector)
94{
95	struct vlapic *vlapic;
96	cpuset_t dmask;
97	int error;
98
99	if (cpu < -1 || cpu >= VM_MAXCPU)
100		return (EINVAL);
101
102	if (cpu == -1)
103		dmask = vm_active_cpus(vm);
104	else
105		CPU_SETOF(cpu, &dmask);
106	error = 0;
107	while ((cpu = CPU_FFS(&dmask)) != 0) {
108		cpu--;
109		CPU_CLR(cpu, &dmask);
110		vlapic = vm_lapic(vm, cpu);
111		error = vlapic_trigger_lvt(vlapic, vector);
112		if (error)
113			break;
114	}
115
116	return (error);
117}
118
119int
120lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
121{
122	int delmode, vec;
123	uint32_t dest;
124	bool phys;
125
126	VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
127
128	if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) {
129		VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr);
130		return (-1);
131	}
132
133	/*
134	 * Extract the x86-specific fields from the MSI addr/msg
135	 * params according to the Intel Arch spec, Vol3 Ch 10.
136	 *
137	 * The PCI specification does not support level triggered
138	 * MSI/MSI-X so ignore trigger level in 'msg'.
139	 *
140	 * The 'dest' is interpreted as a logical APIC ID if both
141	 * the Redirection Hint and Destination Mode are '1' and
142	 * physical otherwise.
143	 */
144	dest = (addr >> 12) & 0xff;
145	phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
146	    (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
147	delmode = msg & APIC_DELMODE_MASK;
148	vec = msg & 0xff;
149
150	VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d",
151	    phys ? "physical" : "logical", dest, vec);
152
153	vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec);
154	return (0);
155}
156
157static boolean_t
158x2apic_msr(u_int msr)
159{
160	if (msr >= 0x800 && msr <= 0xBFF)
161		return (TRUE);
162	else
163		return (FALSE);
164}
165
166static u_int
167x2apic_msr_to_regoff(u_int msr)
168{
169
170	return ((msr - 0x800) << 4);
171}
172
173boolean_t
174lapic_msr(u_int msr)
175{
176
177	if (x2apic_msr(msr) || (msr == MSR_APICBASE))
178		return (TRUE);
179	else
180		return (FALSE);
181}
182
183int
184lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu)
185{
186	int error;
187	u_int offset;
188	struct vlapic *vlapic;
189
190	vlapic = vm_lapic(vm, cpu);
191
192	if (msr == MSR_APICBASE) {
193		*rval = vlapic_get_apicbase(vlapic);
194		error = 0;
195	} else {
196		offset = x2apic_msr_to_regoff(msr);
197		error = vlapic_read(vlapic, offset, rval, retu);
198	}
199
200	return (error);
201}
202
203int
204lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu)
205{
206	int error;
207	u_int offset;
208	struct vlapic *vlapic;
209
210	vlapic = vm_lapic(vm, cpu);
211
212	if (msr == MSR_APICBASE) {
213		vlapic_set_apicbase(vlapic, val);
214		error = 0;
215	} else {
216		offset = x2apic_msr_to_regoff(msr);
217		error = vlapic_write(vlapic, offset, val, retu);
218	}
219
220	return (error);
221}
222
223int
224lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
225		 void *arg)
226{
227	int error;
228	uint64_t off;
229	struct vlapic *vlapic;
230
231	off = gpa - DEFAULT_APIC_BASE;
232
233	/*
234	 * Memory mapped local apic accesses must be 4 bytes wide and
235	 * aligned on a 16-byte boundary.
236	 */
237	if (size != 4 || off & 0xf)
238		return (EINVAL);
239
240	vlapic = vm_lapic(vm, cpu);
241	error = vlapic_write(vlapic, off, wval, arg);
242	return (error);
243}
244
245int
246lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
247		void *arg)
248{
249	int error;
250	uint64_t off;
251	struct vlapic *vlapic;
252
253	off = gpa - DEFAULT_APIC_BASE;
254
255	/*
256	 * Memory mapped local apic accesses must be 4 bytes wide and
257	 * aligned on a 16-byte boundary.
258	 */
259	if (size != 4 || off & 0xf)
260		return (EINVAL);
261
262	vlapic = vm_lapic(vm, cpu);
263	error = vlapic_read(vlapic, off, rval, arg);
264	return (error);
265}
266